Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell comprises a semiconductor substrate, the first surface of the semiconductor substrate is provided with a first semiconductor layer, the first semiconductor layer is provided with isolation regions, and the isolation regions are arranged at intervals in the first direction and extend in the second direction; the passivation layer at least covers one side, deviating from the semiconductor substrate, of the first semiconductor layer and the isolation region; the passivation layer is provided with a plurality of groups of first holes; at least part of the first grid lines are electrically connected with the first semiconductor layer through a group of first holes, and the first grid lines are formed by base metal slurry; in the first direction, the distance between the hole edge close to the first edge and the hole edge close to the second edge in the first open holes in the same group is W1, the width of the first semiconductor layer is W2, the width of the first grid line is W3, W2 / W3 is larger than or equal to 2 and smaller than or equal to 50, and W3 / W1 is larger than or equal to 1.2 and smaller than or equal to 4.5. The light absorption and utilization rate is improved while the manufacturing cost of the solar cell is reduced.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the pn junction of the solar cell's semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, the photogenerated holes flow to the p region, and the photogenerated electrons flow to the n region. Once the circuit is connected, current is generated.

[0003] As the photovoltaic industry's market and production capacity continue to expand, demand for silver paste has surged, driving up prices and squeezing profit margins. Furthermore, existing solar cells have low light absorption and utilization rates, hindering their efficiency. Summary of the Invention

[0004] The purpose of this application is to provide a solar cell and a photovoltaic module to reduce the manufacturing cost of the solar cell while improving the light absorption and utilization rate.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell comprising:

[0007] A semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface having a plurality of first regions spaced apart along a first direction and extending along a second direction, and an isolation region between two adjacent first regions, the first semiconductor layer being disposed in the first region, the first direction being orthogonal to the second direction;

[0008] a passivation layer covering at least a side of the first semiconductor layer facing away from the semiconductor substrate and the isolation region; the passivation layer having a plurality of first openings exposing the first semiconductor layer;

[0009] a plurality of first gate lines, at least some of which are electrically connected to the first semiconductor layer through a group of first openings, the first gate lines being formed of a base metal paste; the first gate lines having opposite first and second edges along a first direction;

[0010] Along the first direction, the distance between the edge of the first opening near the first edge and the edge of the second opening near the second edge in the same group of first openings is W1, the width of the first semiconductor layer is W2, and the width of the first gate line is W3, 2≤W2 / W3≤50, and 1.2≤W3 / W1≤4.5. It should be noted that the width of the first semiconductor layer can be understood as the width of the first region adjacent to the isolation region; or the width of the first semiconductor layer adjacent to the isolation region.

[0011] Along the first direction, the distance between the edge of the hole close to the first edge and the edge of the hole close to the second edge in the first opening of the same group is W1, the width of the first semiconductor layer is W2, and the width of the first gate line is W3. Among them, if the width ratio of the first semiconductor layer to the first gate line is too large, the first gate line will be thinner and cannot timely guide out the carriers collected by the first semiconductor layer; if the width ratio of the first semiconductor layer to the first gate line is too small, the first gate line will be wider and severely shading, which will reduce the light absorption utilization rate and cause waste of the raw materials of the first gate line. In view of the above two situations, in this application, 2≤W2 / W3≤50, that is, the width ratio of the first semiconductor layer to the first gate line is set within a reasonable range of 2 to 50, which not only ensures better carrier transmission efficiency, but also reduces the shading of the first gate line and improves the light absorption utilization rate.

[0012] In addition, if the ratio of the width of the first gate line to the distance between the edge of the hole close to the first edge and the edge of the hole close to the second edge in the first opening of the same group is too large, the contact area between the first gate line and the first semiconductor layer will be too small, affecting the current transmission efficiency; if the ratio of the width of the first gate line to the distance between the edge of the hole close to the first edge and the edge of the hole close to the second edge in the first opening of the same group is too small, the area of the first opening is large, and the damage to the semiconductor substrate during the laser grooving process is large; in view of the above two situations, in this application, 1.2≤W3 / W1≤4.5, that is, the ratio of the width of the first gate line to the distance between the edge of the hole close to the first edge and the edge of the hole close to the second edge in the first opening of the same group is set within a reasonable range of 1.2~4.5, which not only ensures better carrier transmission efficiency, but also reduces damage to the semiconductor substrate during the laser grooving process.

[0013] The base metal slurry used in this application can be considered as a slurry with a base metal content greater than 50%, such as copper slurry, aluminum slurry, silver-clad copper, and other relatively inexpensive conductive metals, compared to the entire metal system solder, to reduce the manufacturing cost of the grid lines. Sintered or non-sintered slurries can be used, and the slurry layer can be sintered or dried in a reducing atmosphere or inert gas protection, or in air atmosphere depending on the slurry characteristics.

[0014] In some embodiments, when the first gate line is formed using a base metal paste, 2≤W2 / W3≤50 matches 1.2≤W3 / W1≤4.5, which can achieve higher current collection efficiency of the first gate line and ensure lower transmission resistance.

[0015] In some embodiments, the isolation region between any two adjacent first semiconductor layers includes at least one column of sub-isolation regions;

[0016] The sub-isolation regions are continuously or discontinuously arranged along the second direction; and / or, two adjacent columns of sub-isolation regions do not overlap or partially overlap.

[0017] In some embodiments, each group of first openings is distributed in at least one column, and each column includes a plurality of first openings spaced apart along the second direction; or, each group of first openings is a strip-shaped hole extending continuously along the second direction.

[0018] In some embodiments, the plurality of first openings in the same group do not overlap or partially overlap; and / or the first openings include circular holes, elliptical holes and / or polygonal holes.

[0019] In some embodiments, 50 μm≤W1≤120 μm; and / or, 300 μm≤W2≤600 μm; and / or, 4 μm≤W3≤200 μm; and / or, the height of the first gate line is h, 0.2≤h / W3≤2; and / or, the height of the first gate line is h, 0.5 μm≤h≤10 μm.

[0020] In some embodiments, along the first direction, a width W4 of the isolation region is 50 μm≤W4≤500 μm; and / or, along the first direction, a distance W5 between center lines of two adjacent first gate lines is 400 μm≤W5≤1000 μm.

[0021] In some embodiments, the isolation region is a polished surface; along the thickness direction of the semiconductor substrate, the distance between the surface of the passivation layer disposed on the first semiconductor layer and the surface facing away from the semiconductor substrate is D1, 0.1um≤D1≤5.5um; or,

[0022] The isolation region is a velvet surface, on which a plurality of pyramid-like or inverted pyramid-like structures are formed; along the thickness direction of the semiconductor substrate, the distance between the surface of the passivation layer disposed on the first semiconductor layer facing away from the semiconductor substrate and the surface of the portion of the passivation layer in the isolation region covering the top of the pyramid facing away from the semiconductor substrate is D2, 0.1um≤D2≤3.5um; the distance between the surface of the passivation layer disposed on the first semiconductor layer facing away from the semiconductor substrate and the surface of the portion of the passivation layer in the isolation region covering the bottom of the pyramid facing away from the semiconductor substrate is D3, 0.4um≤D3≤5um.

[0023] In some embodiments, along the second direction, the semiconductor substrate includes a third edge and a fourth edge disposed opposite to each other, and the distance between the hole edge closest to the third edge in the same group of the first openings and the third edge is d1, 1000 μm ≥ d1 ≥ 150 μm.

[0024] In some embodiments, the first gate line comprises copper powder and organic matter; the copper powder comprises at least flake particles and spherical particles; and / or,

[0025] The passivation layer has a heat-affected zone surrounding the first opening; and / or the heat-affected zone includes a plurality of holes and / or cracks, the holes and / or cracks are filled with a conductive material, and the conductive material is electrically connected to the first semiconductor layer.

[0026] In some embodiments, the solar cell further comprises a second semiconductor layer disposed on the second surface; the passivation layer further covers a side of the second semiconductor layer facing away from the semiconductor substrate; and the second semiconductor layer is provided with an isolation region. When the second semiconductor layer also has an isolation region, it may have any one or more of the same technical features as the isolation region on the first surface described above.

[0027] A photovoltaic module comprises a plurality of solar cells as described above and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, the interconnecting member is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell, wherein the polarity of the second grid line is opposite to that of the first grid line.

[0028] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0030] Figure 1 A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0031] Figure 2 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0032] Figure 3 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0033] Figure 4 A graph showing the relationship between the distance between the edge of the first opening near the first edge and the edge of the second opening near the second edge in the same group of first openings and the power generation efficiency of the battery under different conditions provided in this application;

[0034] Figure 5 A graph showing the relationship between the width of the isolation area and the power generation efficiency of the battery when the isolation area provided in this application is a polished surface;

[0035] Figure 6 A graph showing the relationship between the width of the isolation region and the power generation efficiency of the battery when the isolation region provided in this application is a velvet surface;

[0036] Figure 7 A top view of the first surface of a solar cell provided in an embodiment of the present application;

[0037] Figure 8 A top view of a first surface of a solar cell provided in another embodiment of the present application;

[0038] Figure 9 A top view of a first surface of a solar cell provided in another embodiment of the present application;

[0039] Figure 10 A schematic diagram of a first opening provided in an embodiment of the present application;

[0040] Figure 11 A partial schematic diagram of the area near the end of the first gate line provided in an embodiment of the present application.

[0041] Reference numerals:

[0042] 1-semiconductor substrate, 2-passivation layer, 2a-first opening, 2b-heat-affected zone, 3-first interface layer, 4-first semiconductor layer, 5-conductive barrier layer, 6-first gate line, 7-second gate line, 8-second semiconductor layer, 9-isolation region, 10-first region, 11-first main gate. DETAILED DESCRIPTION

[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0044] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0046] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0047] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0048] See also Figure 1 The solar cell provided in the embodiment of the present application includes a semiconductor substrate 1, a first semiconductor layer 4, a passivation layer 2, and a plurality of first gate lines 6. The semiconductor substrate 1 includes a first surface and a second surface that are opposite to each other along the thickness direction of the semiconductor substrate 1. The first surface can correspond to the backlight side of the solar cell, and the second surface can correspond to the light-facing side of the solar cell; alternatively, the first surface can correspond to the light-facing side of the solar cell, and the second surface can correspond to the backlight side of the solar cell.

[0049] The first surface has a plurality of first regions spaced apart along a first direction and extending along a second direction, and an isolation region located between two adjacent first regions, the first semiconductor layer is disposed in the first region, and the first direction and the second direction are orthogonal;

[0050] It can be understood that the first surface has a first semiconductor layer 4, and the first semiconductor layer 4 is provided with isolation regions 9. The isolation regions 9 are arranged at intervals along the first direction and extend along the second direction. The first semiconductor layer 4 can be strip-shaped, or the first semiconductor layer 4 can also be in a "F"-shaped pattern, with multiple strip-shaped first semiconductor layers 4 or "F"-shaped first semiconductor layers 4 arranged at intervals along the first direction. There is an isolation region 9 between two adjacent first semiconductor layers 4, that is, the first semiconductor layer 4 does not cover the isolation region 9. The first direction and the second direction are orthogonal, that is, the first direction is perpendicular to the second direction. The first direction can be one of the length and width directions of the semiconductor substrate 1, and the second direction can be the other of the length and width directions of the semiconductor substrate 1. The first semiconductor layer 4 can be formed additionally on the semiconductor substrate 1 through deposition technology, or can be formed within the semiconductor substrate 1 through diffusion, ion implantation, etc.

[0051] The passivation layer 2 covers at least the side of the first semiconductor layer 4 facing away from the semiconductor substrate 1 and the isolation region 9. Specifically, in the isolation region 9, the passivation layer 2 directly covers the semiconductor substrate 1. The passivation layer 2 can protect the surface of the cell and prevent water vapor or oxygen from penetrating into the interior of the cell, thereby avoiding the performance degradation of the cell due to oxidation or hydrolysis; and the provision of the passivation layer 2 can reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell. Figure 1 As shown, the passivation layer 2 can be a single layer structure; or, as shown Figure 2 and Figure 3 As shown, the passivation layer 2 can also be a multilayer structure. Specifically, the passivation layer 2 is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and an aluminum oxide layer, or a composite film stacked therefrom. For example, Figure 2 As shown, the passivation layer 2 may be a double-layer structure including an aluminum oxide layer and a silicon nitride layer, wherein the aluminum oxide layer is located on the side of the silicon nitride layer close to the semiconductor substrate 1. The passivation layer 2 has a plurality of first openings 2a exposing the first semiconductor layer 4.

[0052] The first gate line 6 extends along the second direction, that is, the length of the first gate line 6 is arranged along the second direction. The first gate line 6 is arranged on the passivation layer 2, and at least part of the first gate line 6 Each first gate line 6 is electrically connected to the first semiconductor layer 4 through a group of first openings 2a. Specifically, each first gate line 6 is electrically connected to the first semiconductor layer 4 through a group of first openings 2a. Specifically, a portion of the first gate line 6 is electrically connected to the first semiconductor layer 4 through the first openings 2a, so that the first gate lines 6 can be used to conduct carriers collected by the first semiconductor layer 4. The first gate lines 6 are formed from a base metal paste, which is a non-burn-through paste. The base metal paste can be considered to have a base metal content greater than 50%, such as a relatively inexpensive conductive metal such as copper paste, aluminum paste, or silver-clad copper. The first gate lines 6 can be formed using processes such as screen printing, electroplating, sputtering, or evaporation.

[0053] like Figure 1 As shown, the first gate line 6 has a first edge and a second edge relative to each other along the first direction. Along the first direction, the distance between the edge of the hole close to the first edge and the edge of the hole close to the second edge in the first opening 2a of the same group is W1. Along the first direction, the width of the first semiconductor layer 4 is W2, and the width of the first gate line 6 is W3. It should be noted that the width W2 of the first semiconductor layer can be understood as the width of the first area adjacent to the partition area; or the width of the first semiconductor layer adjacent to the partition area. Among them, if the ratio of the width of the first semiconductor layer 4 to the first gate line 6 is too large, the first gate line 6 will be thinner and the carriers collected by the first semiconductor layer 4 will not be able to be promptly extracted; if the ratio of the width of the first semiconductor layer 4 to the first gate line 6 is too small, the first gate line 6 will be wider and the light blocking will be serious, which will reduce the light absorption utilization rate and cause waste of the raw materials of the first gate line 6. In view of the above two situations, in this application, 2≤W2 / W3≤50, that is, the width ratio of the first semiconductor layer 4 and the first gate line 6 is set within a reasonable range of 2 to 50, which not only ensures better carrier transmission efficiency, but also reduces the shading of the first gate line 6 and improves the light absorption utilization rate.

[0054] In addition, if the ratio of the width of the first gate line 6 to the distance between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2a of the same group is too large, the contact area between the first gate line 6 and the first semiconductor layer 4 will be too small, affecting the current transmission efficiency; if the ratio of the width of the first gate line 6 to the distance between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2a of the same group is too small, the area of the first opening 2a is large, and the semiconductor substrate 1 is more damaged during the laser grooving process; in view of the above two situations, in this application, 1.2≤W3 / W1≤4.5, that is, the ratio of the width of the first gate line 6 to the distance between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2a of the same group is set within a reasonable range of 1.2~4.5, which not only ensures better carrier transmission efficiency, but also reduces the damage to the semiconductor substrate 1 during the laser grooving process.

[0055] The present application uses a base metal slurry, which can be considered a slurry with a base metal content greater than 50%, such as copper slurry, aluminum slurry, silver-clad copper, and other relatively inexpensive conductive metals, to reduce the manufacturing cost of the gate lines. When the first gate lines 6 are formed using a base metal slurry, 2≤W2 / W3≤50 matches 1.2≤W3 / W1≤4.5, that is, the ratio of the width of the first gate line 6 to the distance between the edge of the hole near the first edge and the edge of the hole near the second edge in the same group of first openings 2a matches the ratio of the width of the first semiconductor layer 4 to the first gate line 6, which can achieve higher efficiency in collecting current for the first gate line 6 and ensure lower transmission resistance.

[0056] For example, W2 / W3 may be 2, 5, 10, 15, 20, 25, 30, 35, 40, 45, or 50. W3 / W1 may be 1.2, 1.5, 1.8, 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, 3.8, 4, 4.2, or 4.5, etc.

[0057] In some embodiments, when the distance W1 between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2a of the same group is small, the contact resistance of the first gate line 6 is large, and both FF and current are low. When the distance W1 between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2a of the same group increases, the contact resistance of the first gate line 6 decreases while its metal composite (doping layer damage) and metal shading area increase. Because the first gate line 6 needs to completely cover the area of the first opening 2a, the contact area between the first gate line 6 and the first semiconductor layer 4 can be guaranteed to be within a reasonable range when 50μm≤W1≤120μm, while ensuring the current transmission efficiency and reducing the damage to the semiconductor substrate 1 during the grooving process. Figure 4 As shown, it shows the relationship between the distance W1 between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2a of the same group and the battery efficiency under the conditions of BSL (baseline, control group), the isolation area 9 being a polished surface, and the isolation area 9 being a velvet surface. Figure 4 It can be seen from the figure that when W1 is in the reasonable range of 15μm to 80μm, the battery efficiency is higher.

[0058] Illustratively, W1 may be 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 105 μm, 110 μm, 115 μm or 120 μm, etc.

[0059] In some embodiments, if the width of the first semiconductor layer 4 is too wide, it will block light, and the first semiconductor layer 4 will easily absorb light to generate parasitic current, thereby reducing the photoelectric conversion efficiency; if the width of the first semiconductor layer 4 is too narrow, the carrier collection and transmission efficiency will be reduced. Therefore, in this application, 300μm≤W2≤600μm, that is, the width W2 of the first semiconductor layer 4 is maintained in a reasonable range of 300μm to 600μm, so that the solar cell maintains a good photoelectric conversion efficiency and carrier collection and transmission efficiency. Exemplarily, W2 can be 300μm, 340μm, 380μm, 400μm, 440μm, 480μm, 500μm, 540μm, 580μm or 600μm, etc.

[0060] Considering that if the first gate line 6 is too wide, the shading area and light loss will increase, and the light absorption utilization rate will be reduced; if the first gate line 6 is too narrow, the transmission resistance of the first gate line 6 will increase, and the photoelectric conversion efficiency will be reduced. In view of the above two situations, in this technical solution, the width W3 of the first gate line 6 is set within a reasonable range of 4μm≤W3≤200μm to reduce the shading area and light loss, improve the light absorption utilization rate, reduce the transmission resistance of the first gate line 6, and improve the current transmission efficiency. Exemplarily, the width W3 of the first gate line 6 can be 4μm, 20μm, 50μm, 80μm, 100μm, 120μm, 150μm, 180μm or 200μm, etc.

[0061] In some embodiments, along the thickness direction of the semiconductor substrate 1, the height of the first gate line 6 is h; the width of the first gate line 6 is W3, 0.2≤h / W3≤2. When the aspect ratio of the first gate line 6 is less than 0.2, the width of the first gate line 6 needs to be wider, which will increase the light-shielding area of the first gate line 6 and reduce the light absorption utilization rate. At the same time, the area of the first opening 2a needs to be increased, and the damage to the semiconductor substrate 1 caused during the opening process will also increase. When the aspect ratio of the first gate line 6 is greater than 2, the height of the first gate line 6 needs to be higher, which makes it easy to break the gate during printing. Therefore, in order to balance the above two aspects, h / W3 in this application is 0.2~2 to reduce the light-shielding area and light loss, improve the light absorption utilization rate, reduce the damage to the semiconductor substrate 1, and reduce the risk of broken gates during printing. Exemplarily, h / W3 can be 0.2, 0.5, 0.8, 1, 1.2, 1.5, 1.8 or 2, etc.

[0062] In other embodiments, if the height of the first grid lines 6 is too high, the grid lines 6 may easily break during the printing process, affecting the product yield; if the height of the first grid lines 6 is too small, the width of the first grid lines 6 will need to be wider, which will increase the light-shielding area of the first grid lines 6 and reduce the light absorption efficiency. In view of the above two situations, in this technical solution, the height h of the first grid lines 6 is set within a reasonable range of 0.5μm ≥ h ≥ 10μm, reducing the light-shielding area and light loss while ensuring product yield.

[0063] For example, the height h of the first gate line 6 may be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0064] In some embodiments, if the width of the isolation region 9 is too small, less light will pass through the passivation layer 2 to the semiconductor substrate 1, resulting in a decrease in the number of photogenerated carriers generated on the semiconductor substrate 1; if the width of the isolation region 9 is too large, the width of the first semiconductor layer 4 will become narrower, affecting the carrier collection efficiency. Therefore, in this technical solution, if Figure 1As shown, along the first direction, the width W4 of the isolation region 9 is 50 μm ≤ W4 ≤ 500 μm, ensuring that more light can pass through the passivation layer 2 to irradiate the semiconductor substrate 1, and more photogenerated carriers are generated on the semiconductor substrate 1. At the same time, the first semiconductor layer 4 can also collect the carriers in time, so as to take into account both the battery power generation efficiency and the carrier collection efficiency. Figure 5 As shown, Figure 5 FIG. 1 is a graph showing the relationship between the width W4 of the isolation region 9 and the power generation efficiency of the battery when the isolation region 9 is a polished surface; Figure 6 As shown, Figure 6 When the isolation area 9 is a velvet surface, the relationship between the width W4 of the isolation area 9 and the battery power generation efficiency is shown in FIG. Figure 5 and Figure 6 It can be seen from the figure that when W4 is in the reasonable range of 50μm to 500μm, the solar cell can have a higher power generation efficiency.

[0065] For example, the width W4 of the isolation region 9 may be 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm.

[0066] In other embodiments, Figure 7 As shown, along the first direction, the distance between the center lines of two adjacent first gate lines 6 is W5, 400μm≤W5≤1000μm. In this technical solution, it is avoided that the distance between two adjacent first gate lines 6 is too large to reduce the carrier collection efficiency, and it is also avoided that the distance between two adjacent first gate lines 6 is too small to cause serious shading. Exemplarily, the distance W5 between the center lines of two adjacent first gate lines 6 can be 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, 700μm, 750μm, 800μm, 850μm, 900μm, 950μm or 1000μm.

[0067] In some embodiments, as Figure 2 As shown, the isolation region 9 can be a polished surface. Along the thickness direction of the semiconductor substrate 1, the distance between the surface of the passivation layer 2 disposed on the first semiconductor layer 4 facing away from the semiconductor substrate 1 and the surface of the passivation layer 2 in the isolation region 9 facing away from the semiconductor substrate 1 is D1, 0.1um≤D1≤5um. In this technical solution, D1 is roughly the thickness of the first semiconductor layer 4. Setting D1 within a reasonable range can ensure the thickness of the first semiconductor layer 4 while ensuring the absorbance of the isolation region 9. For example, D1 can be 0.1um, 0.2um, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm, etc.

[0068] In other embodiments, Figure 3 As shown, the isolation region 9 is a velvet surface, on which a plurality of pyramid-like or inverted pyramid-like structures are formed. This helps to increase the surface area of the isolation region 9, improve the light trapping effect of the isolation region 9, and allow more light to be refracted through the isolation region 9 into the semiconductor substrate 1 and utilized by the semiconductor substrate 1.

[0069] For example, the aforementioned quasi-pyramid can be a pyramid with a sharp top angle; or, the quasi-pyramid can be a quasi-pyramid with a rounded chamfered corner; or, the quasi-pyramid can be a quasi-pyramid with a flattened top angle. In this case, the quasi-pyramid can have at least the three aforementioned examples, which helps improve the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios. In addition, there is no need to strictly control the manufacturing precision to obtain a quasi-pyramid or quasi-inverted pyramid with a single morphology, which reduces the process difficulty and helps improve the yield of the solar cell.

[0070] like Figure 3 As shown, when the isolation region 9 is a velvet surface, along the thickness direction of the semiconductor substrate 1, the distance between the surface of the passivation layer 2 disposed on the first semiconductor layer 4 facing away from the semiconductor substrate 1 and the surface of the portion of the passivation layer 2 in the isolation region 9 covering the top of the pyramid facing away from the semiconductor substrate 1 is D2, 0.1um≤D2≤3um. In this technical solution, D2 is set within a reasonable range to prevent the pyramid from being too high above the first semiconductor layer 4, which is not conducive to processing and is easily damaged; at the same time, it is prevented from being too short, which affects the absorption rate of light. For example, D2 can be 0.1um, 0.2um, 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm or 3μm, etc.

[0071] Along the thickness direction of the semiconductor substrate 1, the distance between the surface of the passivation layer 2 disposed on the first semiconductor layer 4 away from the semiconductor substrate 1 and the surface of the portion of the passivation layer 2 covering the bottom of the pyramid in the isolation region 9 away from the semiconductor substrate 1 is D3, 0.4um≤D3≤5um. In this technical solution, taking into account both the light absorption rate and the pyramid-like processing technology, D3 is set within the isolation range, while ensuring the light absorption rate, so that the bottom of the pyramid is at a suitable depth. Exemplarily, D3 can be 0.4um, 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm, 3μm, 3.2μm, 3.5μm, 3.8μm, 4μm, 4.2μm, 4.5μm, 4.8μm or 5μm, etc.

[0072] In some embodiments, as Figure 7-Figure 9As shown, the isolation region 9 between any two adjacent first semiconductor layers 4 includes at least one column of sub-isolation regions 9. Each column of sub-isolation regions 9 extends along the second direction, for example, Figure 7 As shown, the isolation region 9 between any two adjacent first semiconductor layers 4 includes a column of sub-isolation regions 9; Figure 8 As shown, the isolation region 9 between any two adjacent first semiconductor layers 4 includes two columns of sub-isolation regions.

[0073] Specifically, the sub-isolation regions are arranged continuously or discontinuously along the second direction. In the case where the solar cell further includes a first main grid 11, the first grid lines 6 are thin grids, the first main grid 11 extends along the first direction and is electrically connected to a plurality of first grid lines 6, and the sub-isolation regions can be discontinuous or uninterrupted at the position of the first main grid 11. Between adjacent first main grids 11, such as Figure 7 As shown, the sub-isolation areas can be set continuously; or as shown Figure 9 As shown, the sub-isolation areas can be set discontinuously.

[0074] In some embodiments, two adjacent columns of sub-isolation regions do not overlap or partially overlap, that is, the two columns of sub-isolation regions between two adjacent first semiconductor layers 4 may overlap, or may overlap as shown in FIG. Figure 8 As shown, there is a gap between the two columns of sub-isolation regions. In this way, the isolation region 9 can be divided into multiple sub-isolation regions according to actual conditions to meet the light absorption rate requirements.

[0075] In other embodiments, Figure 10 As shown, the first openings 2a of the same group corresponding to the same first gate line 6 can be distributed in at least one column, and each column of first openings 2a is arranged along the second direction. Specifically, each column includes a plurality of first openings 2a spaced apart along the second direction extending direction. When each group of first openings 2a is provided with only one column, the plurality of first openings 2a of the same group can be arranged in sequence along the second direction; when a group of first openings 2a is provided in multiple columns, the plurality of first openings 2a of the same group can be distributed in multiple columns and each column of first openings 2a can be arranged in sequence along the second direction. For example, the plurality of first openings 2a can be distributed in two columns, three columns or more columns. In this way, the plurality of first openings 2a are distributed more evenly, and the positions where the first gate line 6 is electrically connected to the first semiconductor layer 4 are distributed more evenly, which is beneficial for the first gate line 6 to promptly derive the current from each position of the first semiconductor layer 4 to avoid local overheating.

[0076] When a group of first openings 2a are arranged in multiple rows, two adjacent rows of first openings 2a do not overlap or partially overlap, that is, two adjacent rows of first openings 2a may overlap or not overlap; along the second direction, two adjacent first openings 2a may overlap or not overlap, which can be determined according to actual conditions.

[0077] In other embodiments, the first openings 2a are strip-shaped holes extending continuously along the second direction. Specifically, each group of first openings 2a may include one strip-shaped hole extending along the second direction, or may include multiple strip-shaped holes arranged side by side and extending along the second direction. This arrangement increases the area of conductive contact between the first gate line 6 and the first semiconductor layer 4, thereby reducing the transmission resistance between the first gate line 6 and the first semiconductor layer 4.

[0078] Of course, the shape of the first opening 2a may include a circular hole, an elliptical hole and / or a polygonal hole, which is not limited here.

[0079] In some embodiments, along the second direction, the semiconductor substrate 1 includes a third edge and a fourth edge that are oppositely disposed, that is, the third edge and the fourth edge are arranged along the second direction, and both the third edge and the fourth edge intersect with the second direction. The distance between the hole edge closest to the third edge in the same group of first openings 2a and the third edge is d1; specifically, as Figure 11 As shown, when a group of first openings 2a includes multiple first openings 2a, the distance between the edge of the first opening 2a closest to the third edge and the third edge is d1. In this technical solution, 1000μm ≥ d1 ≥ 150μm. In this application, d1 is set within a reasonable range of 150μm to 1000μm. Sufficient distance is reserved between the first opening 2a and the third edge of the semiconductor substrate 1, which also ensures that all first openings 2a along the second direction are sufficiently distanced from the edge of the semiconductor substrate 1. This avoids opening holes in the passivation layer 2 in the thinner edge region of the first semiconductor layer 4, preventing the openings from causing damage and blackening of the first semiconductor layer 4, thereby improving the passivation effect of the thinner edge region of the first semiconductor layer 4. In addition, the distance between the first opening 2a and the third edge of the semiconductor substrate 1 is prevented from being too large, thereby avoiding the situation where carriers collected in the edge region of the first semiconductor layer 4 cannot be promptly discharged through the first gate line 6.

[0080] Illustratively, d1 may be 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, 800 μm, 850 μm, 900 μm, 950 μm, 1000 μm, etc.

[0081] In some embodiments, as Figure 11As shown, the passivation layer 2 has a heat-affected zone 2b surrounding the first opening 2a. Specifically, during the laser grooving process of the passivation layer 2, the area near the edge of the first opening 2a is not removed but is affected by the heat of the laser, which is referred to as the heat-affected zone 2b. This heat-affected zone 2b is formed around the first opening 2a. The shape of the first opening 2a can be circular, elliptical, rectangular, or other shapes. The surrounding shape of the heat-affected zone 2b also varies with the shape of the first opening 2a, and its annular shape can be circular, elliptical, rectangular, or the like.

[0082] In some embodiments, the width of the heat-affected zone 2b is D, 1 μm ≤ D ≤ 5 μm, so as to avoid the heat-affected zone 2b being too wide and reducing the passivation effect. For example, D can be 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0083] In some embodiments, during the laser drilling process, the laser energy at the edge is appropriately increased, for example, greater than 200 J / cm 2 , the passivation layer 2 material in the heat-affected zone 2b will be opened, and a plurality of holes and / or cracks will be formed. The purpose of such a setting is that if no holes and / or cracks are formed in the heat-affected zone 2b, the thermal damage to the first semiconductor layer 4 corresponding to the position of the heat-affected zone 2b cannot be repaired, and in this embodiment, the holes and / or cracks are filled with a conductive material, and the conductive material is electrically connected to the first semiconductor layer 4. With such a setting, the first gate line 6 can be electrically connected to the first semiconductor layer 4 through the first opening 2a while also being electrically connected to the first semiconductor layer 4 through the conductive material, and the first semiconductor layer 4 at the position corresponding to the holes and / or cracks is also a heat concentration area with greater damage (heat concentration areas are prone to holes and / or cracks), and the conductive material can repair the damage at this position.

[0084] In some embodiments, the first grid lines 6 are made of a copper paste material, and after curing, the first grid lines 6 include copper powder and an organic material. Copper has a reasonable electrical conductivity and is inexpensive. Therefore, the inclusion of copper powder in the first grid lines 6 in this technical solution reduces manufacturing costs compared to the prior art method of including only silver in the first grid lines 6. In addition, the organic material has good viscosity, and the particles contained in the copper powder can adhere to each other through the organic material. The organic material can also improve the adhesion between the first grid lines 6 and the first surface, preventing the first grid lines 6 from detaching from the first surface.

[0085] The copper powder at least includes flaky particles and spherical particles. The flaky particles are flat as a whole, and the edges of the flaky particles can be smooth edges, jagged edges or any irregular edges. The spherical particles can be spherical, ellipsoidal, quasi-spherical or quasi-ellipsoidal, etc. The contact area between the flaky particles and other conductive particles is large, which is conducive to reducing the contact resistance, while the contact area between the spherical particles and organic matter is large, which is conducive to the forming of the grid line. Based on this, in the present technical solution, the copper powder includes flaky particles and spherical particles at the same time, which can not only make the first grid line 6 have a suitable resistivity, but also facilitate the printing and forming of the first grid line 6.

[0086] Of course, the copper powder may also include one or more of linear particles, V-shaped particles, polygonal particles, and columnar particles. Specifically, the copper powder may include particles of any shape. Particles of these shapes have more contact points, which facilitates contact and conductivity between adjacent conductive particles, thereby ensuring that the first gate line 6 has a suitable resistivity.

[0087] In order to prevent the non-fire-through paste from damaging the passivation effect of the first semiconductor layer 4, as shown in FIG. Figure 1 As shown, a conductive barrier layer 5 is also provided in the present application, that is, the conductive barrier layer 5 is located between the semiconductor layer and the gate line. The function of the conductive barrier layer 5 is to separate the gate line and the semiconductor layer, thereby ensuring the passivation effect of the semiconductor layer while ensuring the conductive performance between the gate line and the semiconductor layer.

[0088] In actual application, the material of the semiconductor substrate 1 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0089] For example, the semiconductor substrate 1 can be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0090] The first semiconductor layer 4 may include doped polycrystalline silicon. Doped polycrystalline silicon layers have higher carrier transport properties. Therefore, when the first semiconductor layer 4 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which helps improve the photoelectric conversion efficiency of the solar cell. Of course, the first semiconductor layer 4 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0091] The solar cell provided herein also includes a second semiconductor layer 8. The second semiconductor layer 8 has a conductivity type opposite to that of the first semiconductor layer 4, so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent. The second semiconductor layer 8 is disposed on the second surface, and in this case, the solar cell is a bifacial cell. Specifically, the second semiconductor layer 8 can be disposed entirely or partially on the second surface. When the second semiconductor layer 8 is partially disposed on the second surface, the second semiconductor layer 8 can be arranged in strips or a "F"-like pattern at intervals on the second surface, with isolation regions between adjacent second semiconductor layers 8.

[0092] The second semiconductor layer 8 may include a doped layer or doped polysilicon in-situ doped on the semiconductor substrate 1 , or the second semiconductor layer 8 may be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0093] In some embodiments, a first interface layer 3 is provided between the first semiconductor layer 4 and the semiconductor substrate 1, and a second interface layer is provided between the second semiconductor layer 8 and the semiconductor substrate 1. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the region where the semiconductor layer is formed on the surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 3 can be set according to the material of the first semiconductor layer 4 and actual requirements, and the material and thickness of the second interface layer can be set according to the material of the second semiconductor layer 8 and actual requirements, and are not specifically limited here.

[0094] For example, the first semiconductor layer 4 may be a doped polysilicon layer, the first interface layer 3 may be a tunneling oxide layer, the second semiconductor layer 8 may be a doped polysilicon layer, and the second interface layer may be a tunneling oxide layer.

[0095] In some embodiments, as Figure 1 As shown, the passivation layer 2 also covers the side of the second semiconductor layer 8 facing away from the semiconductor substrate 1. The passivation layer 2 has multiple groups of second openings that expose the second semiconductor layer 8. The solar cell also includes second gridlines 7, which are disposed on the passivation layer 2. At least a portion of the second gridlines 7 is electrically connected to the second semiconductor layer 8 through a group of second openings. In other words, each second gridline 7 is electrically connected to the second semiconductor layer 8 through a group of second openings. That is, a portion of the second gridline 7 is electrically connected to the second semiconductor layer 8 through the second openings, so that the second gridlines 7 can be used to conduct carriers collected by the second semiconductor layer 8. The material, structure, and other characteristics of the second gridlines 7 can be referred to the description of the first gridlines and will not be repeated here.

[0096] The second gate line 7 has a fifth edge and a sixth edge relative to each other along the first direction. Along the first direction, the distance between the hole edge close to the fifth edge and the hole edge close to the sixth edge in the second openings of the same group is W6, 10μm≤W6≤150μm, to ensure that the contact area between the second gate line 7 and the second semiconductor layer 8 is within a reasonable range, ensuring current transmission efficiency while reducing damage to the semiconductor substrate 1 during the groove forming process. Exemplarily, W6 can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm or 150μm, etc.

[0097] In some embodiments, as Figure 3 and Figure 4 As shown, the second surface of the semiconductor substrate 1 can be a velvet surface with multiple pyramid-like structures formed thereon. When the second surface is a light-facing surface, this helps increase the surface area of the second surface, thereby improving the light trapping effect and light absorption rate of the second surface. Of course, the second surface can also be a polished surface.

[0098] The materials of the first semiconductor layer 4 and the second semiconductor layer 8 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs). In terms of conductivity type, the first semiconductor layer 4 can be an n-type doped layer, and the second semiconductor layer 8 can be a p-type doped layer; alternatively, the first semiconductor layer 4 can be a p-type doped layer, and the second semiconductor layer 8 can be an n-type doped layer.

[0099] For solar cells with busbars, the busbars include a first busbar 11 and / or a second busbar, with first busbar lines 6 and second busbar lines 7 both being thin busbars. First busbar 11 extends along a first direction and is electrically connected to a plurality of first busbar lines 6. Openings are provided below the thin busbars, while no openings are provided below the busbars. Alternatively, openings are provided only below the intersections of the busbars and thin busbars. Both of these configurations can save material while ensuring conductive contact.

[0100] An embodiment of the present invention further provides a method for manufacturing a solar cell. The method can be used to prepare the solar cell described in any of the above embodiments. The method for manufacturing a solar cell comprises the following steps:

[0101] S100: Providing a semiconductor substrate 1, wherein the semiconductor substrate 1 has a first surface and a second surface opposite to each other, wherein the first surface has a plurality of first regions 10 spaced apart along a first direction and extending along a second direction, and an isolation region 9 located between two adjacent first regions 10, wherein the first direction and the second direction intersect;

[0102] Prior to this step, in some embodiments, the semiconductor substrate 1 may be placed in a polishing and cleaning machine to remove the damaged layer of the semiconductor substrate 1 using a polishing liquid. Furthermore, in this step, the morphology of the first and second surfaces of the semiconductor substrate 1 after polishing and cleaning may be adjusted by controlling parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0103] S200: forming a first semiconductor layer 4 in the first region 10;

[0104] The first semiconductor layer 4 can be additionally formed on the first surface of the semiconductor substrate 1 by a deposition technique, or can be formed in the semiconductor substrate 1 by diffusion, ion implantation, or the like.

[0105] S300: forming a full-layer passivation layer 2 on the first surface, the passivation layer 2 covering the side of the first semiconductor layer 4 facing away from the semiconductor substrate 1 and the isolation region 9;

[0106] Specifically, the passivation layer 2 may be formed by deposition or the like. The material and structure of the passivation layer 2 may be referred to above and will not be described in detail here.

[0107] S400: opening a plurality of first openings 2a on the passivation layer 2 to expose the first semiconductor layer 4;

[0108] Specifically, a laser grooving process may be used to form a plurality of first openings 2a on the passivation layer 2. In some embodiments, after this step, the cell may be cleaned to remove dust particles generated during the grooving process.

[0109] S500: forming a plurality of first gate lines 6 on the passivation layer 2, wherein at least some of the first gate lines 6 are electrically connected to the first semiconductor layer 4 through a group of first openings 2a, and the first gate lines 6 are formed of a base metal paste;

[0110] The first gate lines 6 can be formed using processes such as screen printing, electroplating, sputtering, or evaporation. A relatively inexpensive conductive metal, such as copper paste, is added to a base metal paste to reduce gate line manufacturing costs. In some embodiments, after this step, the cell can be dried to facilitate rapid formation of the first gate lines 6.

[0111] The first gate line 6 has a first edge and a second edge relative to each other along a first direction. Along the first direction, the distance between the edge of the hole near the first edge and the edge of the hole near the second edge in the same group of first openings 2a is W1. The width of the first semiconductor layer 4 is W2, and the width of the first gate line 6 is W3. 2≤W2 / W3≤50, and 1.2≤W3 / W1≤4.5. When the first gate line 6 is formed using a non-burn-through paste, 2≤W2 / W3≤50 matches 1.2≤W3 / W1≤4.5. That is, the ratio of the width of the first gate line 6 to the distance between the edge of the hole near the first edge and the edge of the hole near the second edge in the same group of first openings 2a matches the ratio of the width of the first semiconductor layer 4 to the first gate line 6, thereby achieving more efficient current collection by the first gate line 6 and ensuring lower transmission resistance.

[0112] In some embodiments, S200 forms the first semiconductor layer 4 in the first region 10, including: forming an entire first semiconductor layer 4 on the first surface, etching away the first semiconductor layer 4 in the isolation region 9, and retaining the first semiconductor layer 4 in the first region 10. Specifically, laser etching can be used to remove the first semiconductor layer 4 in the isolation region 9, so that the first semiconductor layer 4 does not cover the isolation region 9.

[0113] In some embodiments, after forming the first semiconductor layer 4 in the first region 10 at S200 and before forming the entire passivation layer 2 on the first surface at S300, the solar cell manufacturing method further includes: S201 texturing the isolation region 9 on the first surface to form a velvet surface, wherein a plurality of pyramid-like structures are formed on the velvet surface. This helps to improve the light trapping effect of the isolation region 9, allowing more light to be refracted through the isolation region 9 into the semiconductor substrate 1 and utilized by the semiconductor substrate 1. The shape of the pyramid-like structures is described above and will not be further described here.

[0114] Alternatively, after forming the first semiconductor layer 4 in the first area 10 in S200 and before forming the entire passivation layer 2 on the first surface in S300, the manufacturing method of the solar cell also includes: polishing the isolation area 9 on the first surface in S202. This process is less difficult and helps improve production efficiency.

[0115] In some embodiments, before or after forming the first semiconductor layer 4 in the first region 10 at S200, the solar cell manufacturing method further includes: forming a second semiconductor layer 8 on the second surface, where the second semiconductor layer 8 has an opposite conductivity type to the first semiconductor layer 4. The second semiconductor layer 8 can be additionally formed on the second surface of the semiconductor substrate 1 using a deposition technique, or can be formed within the semiconductor substrate 1 by diffusion, ion implantation, or other methods. Furthermore, the material and structure of the second semiconductor layer 8 can be referred to above and will not be further elaborated here.

[0116] It should be noted that before forming the passivation layer 2, winding can be performed to remove the first semiconductor layer 4 on the side and the second surface. After the de-plating is completed, acid washing is performed to remove the chemical solution remaining on the battery cell.

[0117] In addition, the present application also provides a photovoltaic assembly, which includes a plurality of solar cells as provided in any of the above embodiments and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel. Specifically, the two adjacent solar cells are a first solar cell and a second solar cell, respectively, and the interconnecting member connects the first grid line 6 of the first solar cell and extends to connect to the second grid line 7 of the second solar cell. Similarly, the interconnecting member is analogous to form an interconnection of multiple solar cells. Compared with the prior art, the beneficial effects of the photovoltaic assembly provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, which will not be elaborated here.

[0118] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0119] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface having a plurality of first regions spaced apart along a first direction and extending along a second direction, and an isolation region between two adjacent first regions, the first semiconductor layer being disposed in the first region, the first direction being orthogonal to the second direction; a passivation layer, covering at least a side of the first semiconductor layer facing away from the semiconductor substrate and the isolation region; The passivation layer has a plurality of first openings exposing the first semiconductor layer; a plurality of first gate lines, at least some of which are electrically connected to the first semiconductor layer through a group of first openings, the first gate lines comprising a base metal paste; the first gate lines having opposite first and second edges along a first direction; Along the first direction, the distance between the hole edge close to the first edge and the hole edge close to the second edge in the same group of first openings is W1, the width of the first semiconductor layer is W2, and the width of the first gate line is W3, where 2≤W2 / W3≤50, 1.2≤W3 / W1≤4.

5.

2. The solar cell according to claim 1, wherein The isolation region between any adjacent first semiconductor layers includes at least one column of sub-isolation regions extending along the second direction; The sub-isolation regions are continuously or discontinuously arranged along the second direction; and / or, two adjacent columns of sub-isolation regions do not overlap or partially overlap.

3. The solar cell according to claim 1, wherein Each group of first openings is distributed in at least one column, and each column includes a plurality of first openings spaced apart along the second direction; or, each group of first openings is a strip-shaped hole extending continuously along the second direction.

4. The solar cell according to claim 1, wherein The plurality of first openings in the same group do not overlap or partially overlap; and / or the first openings include circular holes, elliptical holes and / or polygonal holes.

5. The solar cell according to claim 1, wherein 50μm≤W1≤120μm; and / or, 300μm≤W2≤600μm; and / or, 4μm≤W3≤200μm; and / or, the height of the first gate line is h, 0.2≤h / W3≤2; and / or, the height of the first gate line is h, 0.5μm≤h≤10μm.

6. The solar cell according to claim 1, wherein Along the first direction, the width W4 of the isolation region is 50 μm≤W4≤500 μm; And / or, along the first direction, a distance between center lines of two adjacent first gate lines is W5, 400 μm≤W5≤1000 μm.

7. The solar cell according to claim 1, wherein The isolation region is a polished surface; along the thickness direction of the semiconductor substrate, the distance between the surface of the passivation layer disposed on the first semiconductor layer facing away from the semiconductor substrate and the surface of the passivation layer in the isolation region facing away from the semiconductor substrate is D1, 0.1um≤D1≤5um; or, The isolation region is a velvet surface, on which a plurality of pyramid-like or inverted pyramid-like structures are formed; along the thickness direction of the semiconductor substrate, a distance D2 is defined between a surface of the passivation layer disposed on the first semiconductor layer facing away from the semiconductor substrate and a surface of a portion of the passivation layer in the isolation region covering the tops of the pyramids facing away from the semiconductor substrate, wherein 0.1 μm ≤ D2 ≤ 3 μm; A distance D3 is defined between a surface of the passivation layer on the first semiconductor layer facing away from the semiconductor substrate and a surface of a portion of the passivation layer in the isolation region covering the bottom of the pyramid facing away from the semiconductor substrate, and 0.4 um≤D3≤5 um.

8. The solar cell according to claim 1, wherein Along the second direction, the semiconductor substrate includes a third edge and a fourth edge opposite to each other. The distance between the edge of the hole closest to the third edge in the same group of the first openings and the third edge is d1, and 150μ≤d1≤1000μm.

9. The solar cell according to claim 1, wherein The first gate line comprises copper powder and organic matter; the copper powder comprises at least flake particles and spherical particles; and / or, The passivation layer has a heat-affected zone surrounding the first opening; and / or the heat-affected zone includes a plurality of holes and / or cracks, the holes and / or cracks are filled with a conductive material, and the conductive material is electrically connected to the first semiconductor layer.

10. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells according to any one of claims 1 to 9 and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, the interconnecting member is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell, and the polarity of the second grid line is opposite to that of the first grid line.

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