RTOS multi-task priority scheduling and real-time control method based on ARM

Abstract

The invention discloses a real time operating system (RTOS) multi-task priority scheduling and real-time control method based on advanced RISC machines (ARM), and relates to the technical field of embedded computing and control. Comprising the following steps: S1, time slice management setting: dividing CPU time according to a preset time period to obtain time slices; s2, performing task scheduling: setting each task according to a task control block, and performing context switching and priority arbitration through an OSScheduler () function; and S3, performing exception response: performing forced interruption and exception recovery operation through a set multi-stage exception classification mechanism. Through a three-level decision model and a partition response mechanism, it can be ensured that a high-priority task can be responded in time within strict time constraints, the hard real-time requirement is met, meanwhile, CPU time is divided through a fixed time slice, a counter is updated through timer interruption, and therefore the time deviation of task execution can be reduced, and the task execution efficiency is improved. And the certainty of the system is improved.

Description

Technical Field

[0001] The present invention relates to the field of embedded computing and control technology, in particular to an ARM-based RTOS multi-task priority scheduling and real-time control method. Background Art

[0002] Real-time systems (RTS) are computer systems that can respond to external events within strict time constraints. They are widely used in industrial control, aerospace, medical equipment, automotive electronics, and other fields. Furthermore, with the increasing complexity of embedded systems, traditional single-task or simple polling-based control methods are no longer able to meet the demands of multi-task parallel processing and high real-time performance.

[0003] At the same time, real-time operating systems (RTOS) emerged. Their core goal is to ensure that critical tasks are completed within a specified timeframe through multitasking scheduling algorithms and resource management mechanisms. Typical features of RTOS include deterministic response time, task priority scheduling, and resource preemption, making them the preferred platform for embedded real-time applications.

[0004] ARM processors, thanks to their low power consumption, high performance, and scalability, have become a mainstream architecture in the embedded system. For example, the STM32 series of microcontrollers, with its built-in interrupt controller (NVIC), timer module, and memory management unit (MMU), provides hardware support for RTOS implementation. Regarding hardware interrupt handling, ARM's interrupt priority mechanism directly maps to the RTOS's preemptive scheduling strategy, ensuring that high-priority tasks can quickly respond to external events. Regarding timers and scheduling, the timer module provides a precise time base for time slice rotation or dynamic priority adjustment, supporting RTOS periodic task scheduling. Regarding resource optimization, ARM's Thumb instruction set and low-power modes (such as those in the Cortex-M series) enable RTOSs to meet real-time requirements while reducing system energy consumption, making them suitable for battery-powered devices.

[0005] When traditional RTOS performs multi-station chip burning on the ARM architecture, the inherent interrupt response delay and priority arbitration time of the software scheduler will lead to serious timing deviation and nonlinear throughput degradation during multi-task parallel processing. This will not only increase the bit error rate of high-speed Flash programming by three orders of magnitude, but also force the production line to increase the number of stacked devices to meet production capacity requirements. Summary of the Invention

[0006] The purpose of the present invention is to provide an ARM-based RTOS multi-task priority scheduling and real-time control method to solve the problem of time deviation of task execution.

[0007] To achieve the above object, the present invention provides the following technical solution: an ARM-based RTOS multi-task priority scheduling and real-time control method, comprising:

[0008] S1: Time slice management settings: divide the CPU time into time slices according to the preset time period;

[0009] S2: Task scheduling: Set each task according to the task control block, and perform context switching and priority arbitration through the OSScheduler() function;

[0010] S3: Exception response: Forced interruption and exception recovery operations are performed through the set multi-level exception classification mechanism.

[0011] Furthermore, context switching and priority arbitration are performed through the OSScheduler() function, including:

[0012] S2.1: Create and configure tasks: Use the task control block to set each task and the corresponding task control block, and configure the priority parameters and status identifier of each task;

[0013] S2.2: Setting the scheduler: Setting the scheduler to a three-level decision model according to the time segment and the task control block;

[0014] S2.3: Context switch: Setting the status register and secure stack space of the task control block, and continuously storing the register group through the STMIA instruction, while performing context switch on the task according to the ARM EDM engine;

[0015] S2.4: Task selection: partition setting is performed according to the priority field of the task control block, and tasks corresponding to the task control block are selectively executed according to the response time corresponding to each partition.

[0016] Furthermore, the task control block is provided with a priority field, a status register, a time slice counter and a context storage area.

[0017] Furthermore, the scheduler includes basic scheduling, checking abnormal events and performing priority arbitration.

[0018] Furthermore, the scheduler is provided with a dual queue management strategy, and the dual queue management strategy includes a ready queue and a delay queue.

[0019] Furthermore, the delay queue manages waiting tasks through the OSDelayStart() function and updates the time count through the OSTimerUpdating() function.

[0020] Furthermore, the status register includes a core register, a CPSR register and a floating-point register.

[0021] Furthermore, the response time corresponding to each partition is different, and when the timer is interrupted, the fragment counter of the task is updated through the OSTimerUpdating() function.

[0022] Furthermore, the multi-level exception classification mechanism includes three levels: general, important and urgent, and the response times corresponding to the three levels gradually decrease.

[0023] Furthermore, the low-priority task is forcibly interrupted through the OSTaskTerminate() function, and the abnormal task is suspended through the OSWaitSignalEnd() function.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] First, the present invention uses a three-level decision-making model and a partitioned response mechanism to ensure that high-priority tasks can respond promptly within strict time constraints and meet hard real-time requirements. At the same time, by dividing CPU time into fixed time slices and updating counters through timer interrupts, the time deviation of task execution can be reduced, thereby improving the determinism of the system.

[0026] Second, the present invention uses ARM's EDM engine and STMIA instructions to continuously store register groups, and combines strategies such as shadow registers and on-demand floating-point register storage to reduce context switching overhead. At the same time, an independent security stack is allocated to each task control block, which not only avoids memory conflicts between tasks but also enhances system stability.

[0027] Third: The present invention supports dynamic suspension / resumption of tasks and optimizes resource utilization through the collaborative work of ready queues and delay queues. At the same time, through a multi-level exception classification mechanism, low-priority tasks are forcibly interrupted and abnormal tasks are suspended, thereby ensuring that critical events can be responded to quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a flow control diagram of the RTOS multi-task priority scheduling and real-time control method in the present invention. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0030] refer to Figure 1 This embodiment provides an ARM-based RTOS multi-task priority scheduling and real-time control method, which includes the following steps:

[0031] Step S1: Time slice management setting. That is, the CPU time is divided into time slices according to the preset time period, and the corresponding time slices are obtained, and the obtained time slices are used as the basic time units for task scheduling.

[0032] During the specific implementation, the preset time period is set to 5ms, that is, the CPU time is divided into fixed 5ms time segments. That is, in this embodiment, the 5ms time segment is used as the basic time unit for task scheduling.

[0033] Step S2: Perform task scheduling. That is, set each task according to the set task control block, and perform context switching and priority arbitration through the OSScheduler() function. The details are as follows:

[0034] Step S2.1: Create and configure tasks. That is, through the set task control block, each task is set to the corresponding task control block, and the priority parameters and status identifiers of each task are configured according to the set task control block.

[0035] In the present embodiment, a one-to-one correspondence is set between the task and the task control block of the corresponding setting, and simultaneously, each task control block is provided with a priority field, a status register, a time slice counter and a context storage area. Specifically, the priority field is set to a plurality of different levels, namely, according to the number of the task control blocks, a level of corresponding size is set, and according to the level size of the setting, the corresponding priority level is determined. Further, by a multi-bit flag bit, the status register is set, namely, according to the difference of the flag bit, the state corresponding to the task control block is determined, including but not limited to states such as running, hanging up, ready and waiting. Further, by the time slice counter, the time slice divided in step S1 is divided and recorded, that is, the time slice divided in step S1 is divided into the time slice of having been executed and the time slice of the remaining time. Further, by the context storage area, the state of the status register corresponding to the suspended task is stored.

[0036] In the specific implementation process, in this embodiment, a maximum of 32 task control blocks are set, that is, a maximum of 32 concurrent tasks can be run simultaneously. Specifically, the priority field set in this embodiment is 0-31 levels, and each level of priority field corresponds to a task control block.

[0037] Step S2.2: Set up the scheduler. Based on the time segments divided in step S1 and the task control blocks set in step S2.1, the scheduler is configured as a three-level decision-making model: basic scheduling, checking for exceptions, and performing priority arbitration. This means that at the end of each time segment, context switching and task selection can be performed using the OSScheduler() function.

[0038] Furthermore, the scheduler in this embodiment employs a dual-queue management strategy, consisting of a ready queue and a delay queue. Specifically, the ready queue groups tasks by priority, storing the task control blocks of the corresponding priority tasks. Tasks of the same priority are managed using a ring buffer. The delay queue manages waiting tasks via the OSDelayStart() function and collaboratively updates the corresponding time counter via the OSTimerUpdating() function.

[0039] Step S2.3: Context Switch. Based on the task control blocks set in step S2.1, the status registers in each task control block are set to core registers, CPSR registers, and floating-point registers. The core registers are set to shadow registers, the CPSR registers are used to store the current program state, and the floating-point registers are saved on demand. Each task control block is also assigned a secure stack space of a preset size.

[0040] Specifically, the register group is continuously stored through the STMIA instruction, and at the same time, according to the ARM EDM engine, the task context is switched by comparing the switching time with the preset switching time.

[0041] Step S2.4: Task selection. That is, according to the priority field corresponding to the task control block set in step S2.1, the priority field in this embodiment is partitioned by size, that is, levels 0-7 are the first interval, levels 8-23 are the second interval, and levels 24-31 are the third interval. At the same time, according to the divided intervals, the response time corresponding to each interval is set. Specifically, the response time of the first interval, the response time of the second interval, and the response time of the third interval are gradually increased. In other words, according to the set priority field size and the response time of the corresponding interval, the task corresponding to each task control block is selectively executed.

[0042] It is worth noting that during the task switching process, when the timing of the set timer is interrupted, the fragment counters of all tasks are updated by calling the OSTimerUpdating() function.

[0043] Step S3: Exception Response. This involves performing forced interruption and exception recovery operations based on a multi-level exception classification mechanism. Specifically, the multi-level exception classification mechanism in this embodiment is configured as a three-level exception response system, with three different levels: general, important, and urgent. Each level has a different response time, with the response times corresponding to the three levels decreasing in a progressively decreasing manner.

[0044] Furthermore, according to the level of the exception response system corresponding to the task, the low-priority task is forcibly interrupted through the OSTaskTerminate() function, and the corresponding exception task is suspended through the OSWaitSignalEnd() function, and then the normal scheduling process is returned.

[0045] Furthermore, during the forced interruption process, the scheduler of the current task is locked, and the key context content of the current task is saved. At the same time, the task control block status of the current task is set to "forced interruption", and the scheduler lock of the current task is released, that is, the current task is locked to execute the high-priority exception task.

[0046] Furthermore, during the exception recovery process, the register status, stack boundary and resource occupancy list of the task are verified and checked, and the corresponding exception task is suspended through the OSWaitSignalEnd() function, and then the normal scheduling process is returned.

[0047] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is limited by the accompanying embodiments and their equivalents.

Claims

1. An ARM-based RTOS multi-task priority scheduling and real-time control method, characterized in that: Includes: S1: Time slice management settings: divide the CPU time into time slices according to the preset time period; S2: Task scheduling: Set each task according to the task control block, and perform context switching and priority arbitration through the OSScheduler() function; S3: Exception response: Forced interruption and exception recovery operations are performed through the set multi-level exception classification mechanism.

2. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 1, characterized in that: Context switching and priority arbitration are performed through the OSScheduler() function, including: S2.1: Create and configure tasks: Use the task control block to set each task and the corresponding task control block, and configure the priority parameters and status identifier of each task; S2.2: Setting the scheduler: Setting the scheduler to a three-level decision model according to the time segment and the task control block; S2.3: Context switch: Setting the status register and secure stack space of the task control block, and continuously storing the register group through the STMIA instruction, while performing context switch on the task according to the ARM EDM engine; S2.4: Task selection: partition setting is performed according to the priority field of the task control block, and tasks corresponding to the task control block are selectively executed according to the response time corresponding to each partition.

3. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 2, characterized in that: The task control block is provided with a priority field, a status register, a time slice counter and a context storage area.

4. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 2, characterized in that: The scheduler includes basic scheduling, checking abnormal events and executing priority arbitration.

5. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 2 or 4, characterized in that: The scheduler is provided with a dual-queue management strategy, which includes a ready queue and a delay queue.

6. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 5, characterized in that: The delay queue manages the waiting tasks through the OSDelayStart() function and updates the time count through the OSTimerUpdating() function.

7. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 2, characterized in that: The status register includes a core register, a CPSR register and a floating point register.

8. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 2, characterized in that: The response time corresponding to each partition is different, and when the timer is interrupted, the fragment counter of the task is updated through the OSTimerUpdating() function.

9. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 1, characterized in that: The multi-level exception classification mechanism includes three levels: general, important and urgent, and the response times corresponding to the three levels gradually decrease.

10. The ARM-based RTOS multi-task priority scheduling and real-time control method according to claim 1, characterized in that: The low-priority task is forced to be interrupted through the OSTaskTerminate() function, and the abnormal task is suspended through the OSWaitSignalEnd() function.

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