Dynamic flow speed limiting method and device based on cache and delay update under multi-core condition

Abstract

The invention relates to the technical field of cloud computing networks, and discloses a multi-core dynamic flow rate limiting method and device based on cache and delay update, and the method comprises the steps: distributing local cache data for each CPU core; the local cache data comprises accumulated size and quantity of network packets cached in the current period, a flow rate limiting result of the previous period and a timestamp of global rate limiting operation of the previous period; performing threshold condition check on the network packets cached in the current period, and performing speed limiting processing on the accumulated size and the number of the network packets cached in the current period based on a threshold condition check result to obtain a flow speed limiting result in the current period; and performing speed limiting operation on the network packets cached in the current period based on the flow speed limiting result in the current period. According to the invention, the access frequency of global resources is reduced, the resource competition in a multi-core scene is reduced, and the processing performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of cloud computing network technology, and in particular to a dynamic traffic speed limiting method and device based on caching and delayed updating in a multi-core environment. Background Art

[0002] With the widespread use of multi-core processors, the challenge of traffic rate limiting has become increasingly complex. Related rate limiting mechanisms usually rely on global state management, which can easily lead to resource contention and performance bottlenecks in multi-core environments. Especially under high load conditions, multiple cores simultaneously accessing shared rate-limited resources can cause severe delays and degraded processing performance. Therefore, a new rate limiting method is urgently needed that can reduce contention between cores while maintaining network performance. Summary of the Invention

[0003] In view of this, the present invention provides a dynamic traffic rate limiting method and device based on cache and delayed update under multi-core conditions to solve the problem that under high load conditions, multiple cores simultaneously access shared rate-limited resources, which may cause serious delays and reduced processing performance.

[0004] In a first aspect, the present invention provides a dynamic traffic rate limiting method based on caching and delayed updating in a multi-core environment, the method comprising:

[0005] Allocate local cache data to each CPU core; the local cache data includes the cumulative size and number of cached network packets in the current cycle, the traffic rate limit results of the previous cycle, and the timestamp of the global rate limit operation in the previous cycle;

[0006] Perform a threshold condition check on the network packets cached in the current cycle, and based on the threshold condition check result, perform speed limit processing on the cumulative size and number of network packets cached in the current cycle to obtain the traffic speed limit result in the current cycle;

[0007] Based on the traffic speed limit results in the current period, the speed limit operation is performed on the network packets cached in the current period.

[0008] This embodiment provides a dynamic traffic speed limiting method based on caching and delayed updating in a multi-core environment. By allocating local cache data to each CPU core, storing the cumulative size and number of network packets cached in the current cycle, and continuing the traffic speed limiting result of the previous cycle, the cached data is used as the input for the next small amount of global speed limiting operations, delaying the time of global speed limiting, significantly reducing the frequent access to global speed limiting resources, and effectively reducing resource competition and lock contention problems in a multi-core environment. Only when it is checked that the network packets stored in the local cache data meet the set threshold, the cumulative size and number of network packets cached in the current cycle are speed limited to update the traffic speed limiting result for subsequent fast forwarding. The threshold-based delayed update mechanism reduces the frequent locking operations of global resources, thereby avoiding the global competition bottleneck problem and greatly improving the processing performance.

[0009] In an optional embodiment, a threshold condition check is performed on the network packets cached in the current period, and based on the threshold condition check result, a rate limit process is performed on the cumulative size and number of network packets cached in the current period, to obtain a traffic rate limit result in the current period, including:

[0010] Set time interval threshold and maximum network packet size threshold;

[0011] Compare the difference between the timestamp of the network packets cached in the current cycle and the timestamp of the global rate limit operation in the previous cycle with the time interval threshold;

[0012] If the difference between the timestamp of the network packets cached in the current period and the timestamp of the global rate limit operation in the previous period is less than the time interval threshold, the size of the network packets cached in the current period is compared with the maximum network packet size threshold;

[0013] If the size of the cached network packets in the current cycle is less than the maximum network packet size threshold, the traffic speed limit result of the previous cycle will be used as the traffic speed limit result of the current cycle;

[0014] Alternatively, if the size of the network packets cached in the current period is greater than the maximum network packet size threshold, a global speed limit operation is performed on the cumulative size and number of network packets cached in the current period to obtain the traffic speed limit result of the current period.

[0015] This embodiment provides a dynamic traffic speed limiting method based on caching and delayed update in multi-core. Only when the network packets cached in the current period meet the time interval threshold and the maximum network packet size threshold, will the global speed limiting operation be performed on the cumulative size and number of network packets cached in the current period. The above threshold-based delayed update mechanism reduces the frequent locking operations of global resources, thereby avoiding the global competition bottleneck problem and greatly improving the system's processing performance.

[0016] In an optional embodiment, if the size of the network packets cached in the current period is less than the maximum network packet size threshold, the traffic rate limit result of the previous period is used as the traffic rate limit result of the current period, including:

[0017] If the size of the cached network packets in the current period is less than the maximum network packet size threshold, the cumulative size and number of network packets in the current period are accumulated and updated, and the traffic speed limit result of the previous period is used as the traffic speed limit result of the current period.

[0018] This embodiment provides a dynamic traffic speed limiting method based on caching and delayed update in multi-core mode, which uses the traffic speed limiting result of the previous cycle in the local cache data as the traffic speed limiting result of the current cycle, realizes the rapid forwarding processing of network packets, reduces the frequent access to global speed limiting resources, and improves processing performance.

[0019] In an optional embodiment, if the size of the network packets cached in the current period is greater than the maximum network packet size threshold, a global rate limit operation is performed on the cumulative size of the network packets cached in the current period and the number of network packets, and a traffic rate limit result for the current period is obtained, including:

[0020] If the size of the network packets cached in the current period is greater than the maximum network packet size threshold, the global Token Bucket speed limit operation is locked and executed to obtain the traffic speed limit result of the current period. The traffic speed limit result of the previous period is updated as the traffic speed limit result of the current period, and the cumulative size and number of network packets cached in the current period are cleared.

[0021] This embodiment provides a dynamic traffic speed limiting method based on caching and delayed update in multi-core. Only when it is detected that the size of the cached network packet in the current cycle is greater than the maximum network packet size threshold, a locking operation will be performed to update the global speed limit Token Bucket, save the traffic speed limiting result of the current cycle, and use it for subsequent fast forwarding, thereby reducing the frequency of access to global resources, and reducing competition and delay.

[0022] In an optional implementation, setting the time interval threshold and the maximum network packet size threshold includes:

[0023] Obtain actual CPU operation data and dynamically adjust the time interval threshold and maximum network packet size threshold based on the actual CPU operation data.

[0024] This embodiment provides a dynamic traffic speed limiting method based on caching and delayed updates in a multi-core environment. It dynamically adjusts the time interval threshold and the maximum network packet size threshold according to the changes in the network load, performance, and accuracy requirements in the actual CPU operation data. This achieves dynamic adjustment of the cycle and timing of the speed limiting operation, further improves the speed limiting accuracy and performance adaptability, and improves the overall throughput and processing performance while meeting the accuracy requirements of different load scenarios.

[0025] In an optional implementation, the rate limiting operation is performed on the network packets cached in the current period based on the traffic rate limiting result in the current period, including:

[0026] Based on the traffic speed limit result in the current period, the network packets cached in the current period are discarded or received at a limited speed.

[0027] In a second aspect, the present invention provides a dynamic traffic rate limiting device based on caching and delayed updating in a multi-core environment, the device comprising:

[0028] The allocation module is used to allocate local cache data to each CPU core. The local cache data includes the cumulative size and number of network packets cached in the current cycle, the traffic rate limit results of the previous cycle, and the timestamp of the global rate limit operation in the previous cycle.

[0029] The inspection module is used to perform a threshold condition check on the network packets cached in the current cycle, and based on the threshold condition check result, perform speed limit processing on the cumulative size and number of network packets cached in the current cycle to obtain the traffic speed limit result in the current cycle;

[0030] The rate limiting module is used to perform rate limiting operations on the network packets cached in the current period based on the traffic rate limiting results in the current period.

[0031] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the computer instructions to thereby execute the dynamic traffic speed limiting method based on cache and delayed update in a multi-core environment of the above-mentioned first aspect or any corresponding embodiment thereof.

[0032] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the dynamic traffic speed limiting method based on caching and delayed updating in a multi-core environment according to the first aspect or any corresponding embodiment thereof.

[0033] In a fifth aspect, the present invention provides a computer program product comprising computer instructions, which are used to enable a computer to execute the dynamic traffic rate limiting method based on caching and delayed updating in a multi-core environment according to the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 This is a flow chart of a dynamic traffic rate limiting method based on caching and delayed updating in a multi-core environment according to an embodiment of the present invention;

[0036] Figure 2 1 is a flow chart of another method for dynamic traffic rate limiting based on caching and delayed updating in a multi-core environment according to an embodiment of the present invention;

[0037] Figure 3 1 is a flow chart of another method for dynamic traffic rate limiting based on caching and delayed updating in a multi-core environment according to an embodiment of the present invention;

[0038] Figure 4 1 is a flow chart of another method for dynamic traffic rate limiting based on caching and delayed updating in a multi-core environment according to an embodiment of the present invention;

[0039] Figure 5 This is a structural block diagram of a dynamic traffic rate limiting device based on caching and delayed updating in a multi-core environment according to an embodiment of the present invention;

[0040] Figure 6 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0042] An embodiment of the present invention provides a dynamic traffic speed limiting method based on caching and delayed updating under multi-core. It should be noted that the dynamic traffic speed limiting method based on caching and delayed updating under multi-core provided by the embodiment of the present invention can be executed by a dynamic traffic speed limiting device based on caching and delayed updating under multi-core. The dynamic traffic speed limiting device based on caching and delayed updating under multi-core can be implemented as part or all of an electronic device through software, hardware, or a combination of software and hardware, wherein the electronic device can be a server or a terminal, wherein the server in the embodiment of the present application can be a single server or a server cluster composed of multiple servers, and the terminal in the embodiment of the present application can be a smart phone, a personal computer, a tablet computer, a wearable device, an intelligent robot, and other intelligent hardware devices. In the following method embodiments, the execution subject is an electronic device as an example for explanation.

[0043] An embodiment of the present invention provides a dynamic traffic speed limiting method based on cache and delayed update under multi-core conditions. By allocating a local cache to each core, storing the size and number of network packets passing through, continuing the global speed limiting result of the previous cycle, and delaying the global speed limiting update, a small amount of global speed limiting operations are performed only when the time threshold is exceeded, thereby reducing the frequency of access to global resources, reducing competition and delay; at the same time, by dynamically adjusting the cycle and timing of the speed limiting operation, the speed limiting accuracy and performance adaptability are improved, and the simplicity of the system architecture is maintained; the embodiment of the present invention effectively solves the problems of high delay and degradation of processing performance of traffic speed limiting caused by multi-core resource competition, enhances adaptability to dynamic traffic environments, and maintains the simplicity of the system architecture, which not only significantly improves network traffic processing performance, but also reduces implementation complexity and potential error risks.

[0044] According to an embodiment of the present invention, an embodiment of a dynamic traffic rate limiting method based on cache and delay update in a multi-core environment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0045] In this embodiment, a dynamic traffic speed limiting method based on caching and delayed updating in a multi-core environment is provided, which can be used in the above-mentioned electronic devices. Figure 1 is a flow chart of a dynamic traffic rate limiting method based on caching and delayed updating in a multi-core environment according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0046] Step S101, allocating local cache data to each CPU core; the local cache data includes the cumulative size and number of network packets cached in the current cycle, the traffic speed limit result of the previous cycle, and the timestamp of the global speed limit operation of the previous cycle.

[0047] Specifically, each CPU core is allocated a local cache to store the cumulative size and number of network packets cached in the current cycle, the traffic speed limit result (color) of the previous cycle, and the timestamp of the global speed limit operation in the previous cycle. The timestamp can be obtained using the TSC (Time Stamp Counter), ensuring that each core can process the speed limit operation without locking, and caching data for the next global speed limit cycle to guide the global speed limit evaluation of the next cycle.

[0048] Furthermore, the local cache data stores a plurality of network packets to be processed in the current cycle.

[0049] Step S102: perform a threshold condition check on the network packets cached in the current cycle, and based on the threshold condition check result, perform speed limiting processing on the cumulative size and number of network packets cached in the current cycle to obtain the traffic speed limiting result in the current cycle.

[0050] Specifically, when a large packet is encountered or a predetermined CPU cycle is reached (such as using CPU TSC), a global speed limit operation is triggered, otherwise fast forwarding is performed; wherein, the global speed limit operation is: the cumulative size and number of network packets cached in the current cycle recorded in the local cache data are accelerated global speed limit operations are performed, and then the cumulative size and number of network packets cached in the current cycle in the local cache data are cleared for re-accumulation in the next cycle, and the speed limit result is cached and the timestamp TSC is updated; fast forwarding is: continuing the cache result of the previous cycle recorded in the local cache data, and cumulatively updating the cumulative size and number of network packets cached in the current cycle in the cache, for delaying the global speed limit for the next cycle. This stage improves processing performance, reduces the number of global speed limit operations, and optimizes forwarding efficiency.

[0051] Step S103: performing a rate limiting operation on the network packets cached in the current period based on the traffic rate limiting result in the current period.

[0052] Specifically, based on the traffic speed limiting result in the current period, a speed limiting discarding operation or a receiving operation is performed on the network packets cached in the current period.

[0053] Furthermore, based on the speed limit color in the traffic speed limit result in the current cycle, it is decided to discard (red) or forward (green) the packet, and the network traffic control after speed limit is executed.

[0054] This embodiment provides a dynamic traffic speed limiting method based on caching and delayed updating in a multi-core environment. By allocating local cache data to each CPU core, storing the cumulative size and number of network packets cached in the current cycle, and continuing the traffic speed limiting result of the previous cycle, the cached data is used as the input for the next small amount of global speed limiting operations, delaying the time of global speed limiting, significantly reducing the frequent access to global speed limiting resources, and effectively reducing resource competition and lock contention problems in a multi-core environment. Only when it is checked that the network packets stored in the local cache data meet the set threshold, the cumulative size and number of network packets cached in the current cycle are speed limited to update the traffic speed limiting result for subsequent fast forwarding. The threshold-based delayed update mechanism reduces the frequent locking operations of global resources, thereby avoiding the global competition bottleneck problem and greatly improving the processing performance.

[0055] In this embodiment, a dynamic traffic speed limiting method based on caching and delayed updating in a multi-core environment is provided, which can be used in the above-mentioned electronic devices. Figure 2 is a flow chart of a dynamic traffic rate limiting method based on caching and delayed updating in a multi-core environment according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0056] Step S201: Allocate local cache data to each CPU core; the local cache data includes the cumulative size and number of network packets cached in the current cycle, the traffic speed limit result of the previous cycle, and the timestamp of the global speed limit operation of the previous cycle. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0057] Step S202: perform a threshold condition check on the network packets cached in the current cycle, and based on the threshold condition check result, perform speed limiting processing on the cumulative size and number of network packets cached in the current cycle to obtain the traffic speed limiting result in the current cycle.

[0058] Specifically, the above step S202 includes:

[0059] Step S2021: Set a time interval threshold and a maximum network packet size threshold.

[0060] Specifically, actual CPU operation data is obtained, and the time interval threshold and the maximum network packet size threshold are dynamically adjusted based on the actual CPU operation data.

[0061] Furthermore, according to the actual CPU operation data, namely the CPU frequency, number of concurrent cores, bandwidth limit value and required speed limit accuracy, set the appropriate time interval threshold and maximum network packet size threshold; according to the actual environment (CPU frequency, number of concurrent cores, speed limit bandwidth value, speed limit accuracy, etc.), adjust the condition thresholds: time interval and maximum network packet size. According to the actual operation data, the time interval is 5000TSC, which has a better effect.

[0062] Furthermore, a rough evaluation is performed on the set time interval threshold and maximum network packet size threshold. The evaluation method includes: calculating the bandwidth in an extreme manner, that is, using PPS (packets per second, used to measure the number of data packets transmitted per unit time in a network device or system) as the forwarding performance of the bandwidth. Assuming that the CPU frequency is 3GHz (gigahertz) and the single-core processing performance of the speed-limiting software is 6Mpps (megabits per second), the average TSC of each packet is calculated to be 500TSC / Packet, and each packet is an average of 1500Byte (bytes); when the rough error is set to 15KB (kilobytes), the interval time TSC should be set to 15KB / 1.5KB*500TSC=5000TSC, and the actual evaluation also needs to be combined with the number of concurrent cores; based on actual experience, the interval time of 5000TSC is better.

[0063] Step S2022: Compare the difference between the timestamp corresponding to the network packet cached in the current period and the timestamp of the global rate limiting operation in the previous period with the time interval threshold.

[0064] Step S2023: If the difference between the timestamp corresponding to the network packet cached in the current cycle and the timestamp of the global rate limit operation in the previous cycle is less than the time interval threshold, the size of the network packet cached in the current cycle is compared with the maximum network packet size threshold.

[0065] Specifically, when processing a network packet on each CPU core, it first checks the difference between the timestamp corresponding to the network packet cached in the current cycle and the timestamp of the global speed limit operation in the previous cycle recorded in the cache to determine whether it is within the set time interval threshold, and checks whether the size of the current network packet exceeds the maximum network packet size threshold.

[0066] Step S2024: If the size of the network packets cached in the current cycle is smaller than the maximum network packet size threshold, the traffic speed limit result of the previous cycle is used as the traffic speed limit result of the current cycle.

[0067] Specifically, if the size of the cached network packets in the current cycle is less than the maximum network packet size threshold, the cumulative size of the network packets and the number of network packets in the current cycle are cumulatively updated, and the traffic speed limit result of the previous cycle is used as the traffic speed limit result of the current cycle.

[0068] Furthermore, if the network packets cached in the current cycle meet the threshold check, the cumulative size of the network packets packets_size and the number of network packets packets_count are accumulated and updated, updated to the local cache data, and the traffic speed limit result last_color of the previous cycle is used as the speed limit calculation result of the current cycle for fast forwarding.

[0069] Step S2025: If the size of the network packets cached in the current period is greater than the maximum network packet size threshold, a global speed limit operation is performed on the cumulative size and number of network packets cached in the current period to obtain the traffic speed limit result of the current period.

[0070] Specifically, if the size of the cached network packets in the current period is greater than the maximum network packet size threshold, the global Token Bucket speed limit operation is locked and executed to obtain the traffic speed limit result of the current period, and the traffic speed limit result of the previous period is updated to the traffic speed limit result of the current period, and the cumulative size of the cached network packets and the number of network packets in the current period are cleared.

[0071] Furthermore, the cumulative size and number of cached network packets in the local cache data since the last global speed limit operation are locked to execute the global Token Bucket speed limit operation, and the speed limit result is saved in the cache to guide subsequent fast forwarding. The cumulative size and number of cached network packets in the current cycle are cleared, and the timestamp of the global speed limit operation in the previous cycle is updated.

[0072] Furthermore, the specific steps for locking and executing the global Token Bucket speed limit operation include: defining the token bucket data structure: creating a data structure to represent the token bucket, including fields such as the bucket capacity (capacity), the current number of tokens (tokens), the token generation rate (rate), and the last update time (lastUpdateTime); initializing the token bucket parameters: setting the initial capacity of the bucket and the token generation rate; creating a lock object: using the lock mechanism provided by the programming language, creating a mutex lock object to protect concurrent access to the token bucket; acquiring the lock: acquiring the lock before performing any operation on the token bucket; updating the token number: calculating the time from the last update time (i.e., the previous cycle) to the current time (i.e., the current cycle) The number of tokens that should be generated within the interval is calculated based on the token generation rate and time interval, and then the newly generated tokens are added to the current tokens, but make sure that it does not exceed the capacity of the bucket, and update the last update time to the current time; Check the number of tokens: Check whether the current number of tokens in the token bucket is sufficient. If the number of tokens is greater than or equal to 1, it means that there are enough tokens to send network data packets, and take a token from the token bucket. Then, the lock is released to allow other threads or processes to access the token bucket; Handling insufficient tokens: If the number of tokens is less than 1, it means that there are insufficient tokens and related operations cannot be performed. At this time, it can be handled according to specific business needs, such as putting the task in a queue to wait, or directly returning an error message to the caller.

[0073] Step S203: Based on the traffic speed limit result in the current period, the network packets cached in the current period are speed-limited. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0074] This embodiment provides a dynamic traffic speed limiting method based on caching and delayed update in multi-core. Only when the network packets cached in the current period meet the time interval threshold and the maximum network packet size threshold, will the global speed limiting operation be performed on the cumulative size and number of network packets cached in the current period. The above threshold-based delayed update mechanism reduces the frequent locking operations of global resources, thereby avoiding the global competition bottleneck problem and greatly improving the system's processing performance.

[0075] The following describes the specific steps of a dynamic traffic rate limiting method based on caching and delayed updating in a multi-core environment through a specific embodiment.

[0076] Example 1:

[0077] like Figure 3 As shown, the specific steps of a dynamic traffic rate limiting method based on cache and delayed update in a multi-core environment include:

[0078] 1) Design the cache structure of the speed limit meter (a tool or mechanism used to measure and monitor speed limit-related indicators):

[0079]

[0080] like Figure 4 As shown, local cache data is allocated to each CPU core (i.e., Core0-CoreN). The contents of the cache structure of the speed limit meter include: last_color: the traffic speed limit result of the previous cycle; packets_count: the number of network packets cached in the current cycle; packets_size: the total size of the network packets cached in the current cycle; last_do_time (or last_update_time): the timestamp of the global display in the previous cycle; the cache structure is aligned to 64 bytes to ensure efficient access and writing, and reduce performance loss caused by data competition.

[0081] 2) Set the meter threshold:

[0082]

[0083] Each meter contains two key thresholds: interval_tsc: the time period threshold for global rate limiting operations; max_pkt_size: the cached packet size exceeds this value, which triggers global rate limiting. These two thresholds can be dynamically adjusted through the configuration channel to adapt to different traffic patterns, performance requirements, and accuracy requirements.

[0084] 3) Threshold Check and Speed Limit Processing: When performing a threshold check on each processed network packet, the local cache data corresponding to the corresponding CPU core is searched, and a threshold check is performed on the network packet to determine whether a global speed limit operation is required:

[0085]

[0086] 4) If Figure 4 As shown, the steps for obtaining the speed limit result include:

[0087] 4.1) Fast forwarding when thresholds are met: The size and number of network packets cached in the current cycle are accumulated into the cache, and the speed limit results of the previous cycle are continued:

[0088] meter->cache[cache_id].packets_size+=pkt_size;

[0089] meter->cache[cache_id].packets_count+=pkt_cnt;

[0090] current_color=meter->cache[cache_id].last_color;

[0091] 4.2) Global rate limit operation when the threshold is not met: Accumulate the size and number of network packets cached in the current cycle to the global rate limit token bucket, and update last_color to the current rate limit result; update last_tsc and clear the cache counter to prepare for the next cycle.

[0092] current_tsc = now_tsc();

[0093] current_color=do_global_meter_handle(meter->cache[cache_id].packets_size+pkt_size,meter->cache[cache_id].packets_count+pkt_cnt);

[0094] meter->cache[cache_id].packets_size=0;

[0095] meter->cache[cache_id].packets_count=0;

[0096] meter->cache[cache_id].last_tsc=current_tsc;

[0097] meter->cache[cache_id].last_color=current_color;

[0098] 5) According to the above speed limit result, perform corresponding reception or discarding, speed limit operation: According to the speed limit result in the above step 4, perform corresponding reception or discarding operations on the network packet to achieve speed limit.

[0099] In the above-mentioned embodiment 1, the system reduces the frequency of access to global resources, reduces resource competition in multi-core scenarios, and improves processing performance. The stress test under quad-core concurrency shows that the forwarding performance is improved by 560%, while the speed limit bandwidth remains unchanged, demonstrating a significant optimization effect. The above-mentioned method is suitable for high-concurrency network processing environments and has high feasibility and flexibility.

[0100] Specifically, the dynamic traffic rate limiting method based on caching and delayed updates in multi-core environments has the following advantages:

[0101] 1) In a multi-core scenario, batch rate limit updates based on local cache:

[0102] By allocating a local cache to each processing core, storing the size and number of network packets, and continuing the global speed limit results of the previous cycle, the cached data is used as the input for the next small amount of global speed limit operations, which delays the time of global speed limit, significantly reduces the frequent access to global speed limit resources, and effectively reduces resource competition and lock contention problems in a multi-core environment; compared with global state management, the present invention achieves more efficient speed limit control through local cache, which is particularly suitable for high-concurrency network fields; in addition, compared with the technology of each core pre-applying for a part of tokens from the global speed limit token bucket as a local cache token bucket, the technology of caching the size and number of packets has simpler, more efficient and more effective token consumption, avoiding the problem of token waste caused by idle cores pre-applying for tokens and reduced speed limit accuracy.

[0103] 2) Delayed update mechanism:

[0104] Only when the data in the core local cache meets the set threshold (interval time, packet size) will the locking operation be performed, and the cached short-term historical data (packet size, number) will be subject to global Token Bucket speed limit processing. The above threshold-based delayed update mechanism reduces the frequent locking operations of global resources, thereby avoiding the global competition bottleneck problem and greatly improving system performance. Compared with the real-time speed limit update method, the delayed speed limit update mechanism not only improves the overall throughput of the system, but also effectively reduces the system processing delay and significantly enhances the data packet forwarding performance.

[0105] 3) Dynamically adjust the cycle and timing of speed limit operations:

[0106] By introducing a dynamic threshold adjustment mechanism, the cycle and timing of rate limiting operations can be dynamically adjusted according to changes in network load, performance, and accuracy requirements. This provides greater flexibility and adaptability, making it suitable for different load scenarios. While meeting accuracy requirements, it also improves overall throughput and processing performance.

[0107] This embodiment also provides a dynamic traffic rate limiting device based on caching and delayed updating in a multi-core environment. The device is used to implement the above-mentioned embodiments and preferred embodiments, and the details that have been described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0108] This embodiment provides a dynamic flow rate limiting device based on cache and delayed update in a multi-core environment. Figure 5Shown, including:

[0109] Allocation module 501 is used to allocate local cache data to each CPU core; the local cache data includes the cumulative size and number of network packets cached in the current cycle, the traffic speed limit result of the previous cycle, and the timestamp of the global speed limit operation in the previous cycle;

[0110] The checking module 502 is configured to perform a threshold condition check on the network packets cached in the current period, and based on the threshold condition check result, perform a rate limiting process on the cumulative size and number of network packets cached in the current period, thereby obtaining a traffic rate limiting result for the current period;

[0111] The speed limiting module 503 is configured to perform a speed limiting operation on the network packets cached in the current period based on the traffic speed limiting result in the current period.

[0112] In some optional implementations, the inspection module 502 includes:

[0113] A setting unit, used to set a time interval threshold and a maximum network packet size threshold;

[0114] A first comparing unit is configured to compare a difference between a timestamp corresponding to a network packet cached in a current cycle and a timestamp of a global rate limiting operation in a previous cycle with a time interval threshold;

[0115] a second comparing unit, configured to compare the size of the network packets cached in the current period with a maximum network packet size threshold if a difference between a timestamp corresponding to the network packets cached in the current period and a timestamp of the global rate limit operation in the previous period is less than a time interval threshold;

[0116] a determination unit, configured to use the traffic speed limit result of the previous cycle as the traffic speed limit result of the current cycle if the size of the network packets cached in the current cycle is less than the maximum network packet size threshold;

[0117] The global speed limit operation unit is used to perform a global speed limit operation on the cumulative size and number of network packets cached in the current period if the size of the network packets cached in the current period is greater than the maximum network packet size threshold, so as to obtain the traffic speed limit result of the current period.

[0118] In some optional embodiments, the determination unit is specifically used to accumulate and update the cumulative size of network packets and the number of network packets in the current period if the size of the network packets cached in the current period is less than the maximum network packet size threshold, and use the traffic speed limit result of the previous period as the traffic speed limit result of the current period.

[0119] In some optional embodiments, the global speed limit operation unit is specifically used to lock and execute the global Token Bucket speed limit operation if the size of the network packets cached in the current period is greater than the maximum network packet size threshold, obtain the traffic speed limit result of the current period, and update the traffic speed limit result of the previous period to the traffic speed limit result of the current period, and clear the cumulative size of the network packets cached in the current period and the number of network packets.

[0120] In some optional implementations, the setting unit is specifically configured to obtain actual CPU operation data, and dynamically adjust the time interval threshold and the maximum network packet size threshold based on the actual CPU operation data.

[0121] In some optional implementations, the rate limiting module 503 is specifically configured to perform a rate limiting discarding operation or a receiving operation on the network packets cached in the current period based on the traffic rate limiting result in the current period.

[0122] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0123] In this embodiment, a dynamic traffic rate limiting device based on cache and delayed update in a multi-core environment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0124] The embodiment of the present invention also provides a computer device having the above Figure 5 A dynamic traffic rate limiting device based on cache and delayed update in a multi-core environment is shown.

[0125] See also Figure 6 , Figure 6 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 6As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of a GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0126] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0127] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0128] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0129] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0130] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 6 The bus connection is taken as an example.

[0131] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0132] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0133] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0134] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A dynamic traffic rate limiting method based on cache and delayed update in multi-core, characterized in that: The method comprises: Allocate local cache data to each CPU core; the local cache data includes the cumulative size and number of network packets cached in the current cycle, the traffic speed limit results of the previous cycle, and the timestamp of the global speed limit operation in the previous cycle; Performing a threshold condition check on the network packets cached in the current period, and based on the threshold condition check result, performing speed limiting processing on the cumulative size and number of network packets cached in the current period, to obtain a traffic speed limiting result in the current period; A rate limiting operation is performed on the network packets cached in the current period based on the traffic rate limiting result in the current period.

2. The method according to claim 1, characterized in that The threshold condition check is performed on the network packets cached in the current period, and the cumulative size and number of network packets cached in the current period are speed-limited based on the threshold condition check result to obtain the traffic speed limit result in the current period, including: Set time interval threshold and maximum network packet size threshold; Compare the difference between the timestamp corresponding to the network packet cached in the current period and the timestamp of the global rate limit operation in the previous period with the time interval threshold; If the difference between the timestamp corresponding to the network packet cached in the current period and the timestamp of the global speed limit operation in the previous period is less than the time interval threshold, then comparing the size of the network packet cached in the current period with the maximum network packet size threshold; If the size of the network packets cached in the current period is less than the maximum network packet size threshold, the flow rate limit result of the previous period is used as the flow rate limit result of the current period; Alternatively, if the size of the network packets cached in the current period is greater than the maximum network packet size threshold, a global speed limit operation is performed on the cumulative size and number of network packets cached in the current period to obtain the traffic speed limit result of the current period.

3. The method according to claim 2, characterized in that If the size of the network packets cached in the current period is less than the maximum network packet size threshold, the flow rate limit result of the previous period is used as the flow rate limit result of the current period, including: If the size of the network packets cached in the current period is less than the maximum network packet size threshold, the cumulative size of the network packets and the number of network packets in the current period are cumulatively updated, and the traffic speed limit result of the previous period is used as the traffic speed limit result of the current period.

4. The method according to claim 2, characterized in that If the size of the network packets cached in the current period is greater than the maximum network packet size threshold, a global rate limit operation is performed on the cumulative size of the network packets cached in the current period and the number of network packets, to obtain a traffic rate limit result for the current period, including: If the size of the network packets cached in the current period is greater than the maximum network packet size threshold, the global Token Bucket speed limit operation is locked and executed to obtain the traffic speed limit result of the current period, and the traffic speed limit result of the previous period is updated to the traffic speed limit result of the current period, and the cumulative size of the network packets cached in the current period and the number of network packets are cleared.

5. The method according to claim 2, characterized in that The setting of the time interval threshold and the maximum network packet size threshold includes: Acquire actual CPU operation data, and dynamically adjust the time interval threshold and the maximum network packet size threshold based on the actual CPU operation data.

6. The method according to claim 1, characterized in that The performing a rate limiting operation on the network packets cached in the current period based on the traffic rate limiting result in the current period includes: Based on the traffic speed limit result in the current period, a speed limit discarding operation or a receiving operation is performed on the network packets cached in the current period.

7. A dynamic traffic rate limiting device based on cache and delayed update in multi-core, characterized in that: The device comprises: An allocation module is used to allocate local cache data to each CPU core; the local cache data includes the cumulative size and number of network packets cached in the current cycle, the traffic speed limit result of the previous cycle, and the timestamp of the global speed limit operation in the previous cycle; An inspection module is used to perform a threshold condition check on the network packets cached in the current period, and based on the threshold condition check result, perform speed limit processing on the cumulative size and number of network packets cached in the current period to obtain a traffic speed limit result in the current period; The speed limiting module is used to perform a speed limiting operation on the network packets cached in the current period based on the traffic speed limiting result in the current period.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the dynamic traffic speed limiting method based on cache and delayed update in a multi-core environment as described in any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the dynamic traffic speed limiting method based on cache and delayed update in a multi-core environment according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the dynamic traffic speed limiting method based on cache and delayed update in a multi-core environment according to any one of claims 1 to 6.

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