A heterogeneously integrated fast recovery response high power limiter and its preparation method

Abstract

The present invention discloses a heterogeneously integrated fast-recovery response high-power limiter and a preparation method thereof, belonging to the field of radio frequency / microwave circuit protection. The device sequentially comprises an input port, a first limiter unit, an impedance matching and rectification bias network, a second limiter unit, and an output port. The first limiter unit adopts a Si-based PIN diode for carrying a high-power input signal. The impedance matching and rectification bias network comprises a 1 / 4 wavelength impedance transformation line, a GaN-based Schottky diode, and an LRC series-parallel network for quickly triggering the front-stage PIN diode to conduct. The second limiter unit comprises a GaAs-based PIN diode for further absorbing the residual high-power energy leaked from the front stage, thereby improving the final isolation of the limiter. The present invention can significantly improve the limiting response speed and recovery time performance, reduce the limiting threshold, improve the protection sensitivity, improve the high-power processing capability, enhance the reliability, improve the device integration, and reduce the packaging complexity and volume.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency / microwave circuit protection, and in particular relates to a heterogeneously integrated fast recovery response type high power limiter and a preparation method thereof. Background Art

[0002] A limiter is a protective nonlinear device widely used in RF front-end circuits. It is primarily used to suppress input power that exceeds the system's allowable range, preventing subsequent circuit components (such as low-noise amplifiers) from being damaged by overvoltage. High-power limiters must simultaneously meet requirements such as high power handling capability, low turn-on voltage, fast response time, and rapid recovery. In traditional structures, PIN diodes are the primary device for implementing the limiting function. PIN diodes based on silicon (Si) or gallium arsenide (GaAs) are particularly popular, as they are widely used in limiting applications at varying power levels. Currently, due to technological development challenges, gallium nitride (GaN) PIN diodes are not available worldwide. Schottky barrier diodes (SBDs) are rarely used in RF applications and are a relatively new technology.

[0003] In existing technologies, a series-parallel structure of Si-based PIN diodes and GaAs-based PIN diodes is often used to balance power handling capacity and response speed. Si PIN diodes offer excellent high-power handling performance, but their response and recovery times are typically in the microsecond (μs) range, resulting in a slow response. GaAs PIN diodes, on the other hand, have faster response and recovery times, reaching hundreds of nanoseconds (ns), but their power handling capacity is lower (less than 50W). While combining these two diodes offers a certain balance between speed and power, they present the following three issues:

[0004] 1. High threshold voltage and limiting level: The turn-on voltage of the two PIN diodes is generally high (usually around 0.7V), resulting in almost no response of the entire limiter to small signal inputs. The limiting start point is high (up to 15dBm), making it difficult to meet the low threshold protection requirements (for example, systems below 10dBm) of sensitive RF receiving systems.

[0005] 2. Uncertainty in the startup process: Since GaAs PIN diodes are turned on earlier than Si PIN diodes, their limiting process behaves as "reflection first, clamping later". Overshoot leakage easily occurs before Si PIN diodes enter the conductivity modulation state, resulting in spike output, which reduces the limiter's suppression effect on high-power pulses. Figure 6 Indicated by the red line;

[0006] 3. The recovery time is long and it is difficult to meet the requirements of high-repetition-rate pulse systems: Even if the GaAs PIN has a faster recovery speed, the entire limiter is still limited by the recovery characteristics of the Si PIN, making it difficult to recover in time when continuously subjected to high-power pulses in a short period of time. There is a problem of minority carrier response accumulation, and it is generally unable to exceed the hundreds of nanoseconds level.

[0007] To alleviate the above problems, some public solutions attempt to introduce Schottky barrier diodes (SBDs) as auxiliary rectifying elements, enabling them to perform rapid rectification output in the front stage, generating a bias to control the conduction of the main limiting diode. GaAs-based SBDs are typically used in this type of structure, which have a low turn-on voltage and fast response speed, which helps to improve the triggering speed of the entire limiter. However, due to the extremely low power handling capacity of GaAs SBDs, it is often necessary to direct a portion of the power in the main path to the SBD branch through a power coupler for rectification to prevent it from directly bearing high-power pulses. Although this method improves the limiting response speed to a certain extent, it also introduces the following defects:

[0008] 1. Additional power distribution structures (such as couplers) increase loss and area, which is not conducive to the miniaturization and integration design of the limiter;

[0009] 2. The bias control link relies on precise design, resulting in low accuracy of the limiter start point, and unstable control characteristics, especially in wide frequency bands.

[0010] 3. The overall response speed is still limited by the hysteresis characteristics of the Si PIN diode in the main limiting path, making it difficult to meet the extreme requirement of a response time of <100ns.

[0011] In summary, existing limiter solutions generally suffer from long response times, high limiting levels, slow recovery, and complex structures. In particular, they struggle to balance high power, fast recovery, and low-threshold response. Therefore, a new limiter with a novel structure, reasonable configuration, fast response, and high power handling capabilities is urgently needed to meet the application requirements of next-generation RF communications and electronic countermeasures systems. Summary of the Invention

[0012] In response to the problems of existing limiters such as slow response speed, high limiting threshold, and difficulty in balancing power handling capability and recovery capability, the present invention proposes a heterogeneously integrated fast recovery response high power limiter and a preparation method, which solves the shortcomings of the existing technology and thus achieves the unification of fast response, low threshold, high power tolerance and fast recovery characteristics.

[0013] In order to achieve the above-mentioned object of the invention, the present invention adopts the following technical solutions:

[0014] A heterogeneously integrated fast recovery response high power limiter comprises an input port, a first limiter unit, an impedance matching and rectification bias network, a second limiter unit and an output port in sequence;

[0015] The input port is used to receive an external radio frequency signal or a high-power pulse signal;

[0016] The first limiting unit uses a Si-based PIN diode D1 to carry the high-power input signal;

[0017] The impedance matching and rectification bias network includes a 1 / 4 wavelength impedance transformation line Z1, a GaN-based Schottky diode D2 and an LRC series-parallel network, which is used to quickly trigger the front-stage PIN diode to turn on;

[0018] The second limiting unit includes GaAs-based PIN diodes D3 to D6, which are used to further absorb the remaining high-power energy leaked from the previous stage and improve the final isolation of the limiter;

[0019] The output port is connected to a subsequent radio frequency receiving or amplifying circuit.

[0020] Furthermore, a DC blocking capacitor C1 and an impedance matching structure Z0 are connected in series between the input port and the first limiter unit. Z0 is connected to the anode of the Si-based PIN diode D1, and the cathode of D1 is grounded.

[0021] Furthermore, a DC blocking capacitor C2 is provided between the impedance matching and rectification bias network and the second amplitude limiting unit;

[0022] The LRC series-parallel network includes a capacitor C, a resistor R and an inductor L, the first ends of C and R are connected to the first end of L, the second ends of C and R are grounded, the cathode of the GaN-based Schottky diode D2 is connected to the first end of L, the anode of D2 is grounded, the second end of L is connected to the 1 / 4 wavelength impedance transformation line Z1 and the first end of C2, and the second end of Z1 is connected to the anode of D1.

[0023] Furthermore, the second limiting unit also includes a 1 / 4 wavelength impedance transformation line Z2, the anodes of the GaAs-based PIN diodes D3 and D5, and the cathodes of D4 and D6 are grounded, the cathode of D3 and the anode of D4 are connected to the first end of Z2 and the second end of C2, and the cathode of D5 and the anode of D6 are connected to the second end of Z2 and the output port.

[0024] Furthermore, the Si-based PIN diode D1 is selected as MA4L401-134, with a size of 0.4mm×0.4mm, a turn-on voltage of 0.8V@10mA, a thermal resistance of 16°C / W, a reverse breakdown voltage higher than 250V, an on-resistance of 1.2Ω, and can provide an isolation of more than 8dB;

[0025] The GaN-based Schottky diode D2 is selected as FCR080, with a reverse breakdown voltage of 120V, an on-resistance of 2.5Ω, and a turn-on voltage of 0.45V;

[0026] The GaAs-based PIN diodes D3 to D6 are microwave monolithic integrated circuits.

[0027] Furthermore, when receiving a high-power RF input signal, the limiter is first in the low-power range, the signal amplitude is small, D1~D6 are all in the cut-off state, and the signal is directly transmitted to the subsequent stage;

[0028] Next, when the limiter is in the medium power range, the input signal voltage exceeds the turn-on voltage of GaN-based Schottky diode D2. D2 is turned on first, generating a DC rectifier output, which is biased to the anode of Si-based PIN diode D1 through the LRC series-parallel network, triggering D1 to turn on early.

[0029] Then, when the limiter is in the high-power range, D1 enters a conductivity modulation state, exhibiting extremely low dynamic resistance. Most of the input power is reflected or absorbed at this stage. Simultaneously, the quarter-wavelength conversion line design aligns the reflected wave peak with the phase at D1, accelerating conduction. If any residual power still leaks to the subsequent stage, the GaAs-based PIN diode performs the final limiting.

[0030] Finally, the limiter is in the recovery stage after the signal disappears. The recovery time of the GaAs-based PIN diode is hundreds of nanoseconds, and the GaN-based Schottky diode recovers instantaneously. The recovery time of the entire limiter is controlled within <20ns.

[0031] A method for preparing a heterogeneously integrated fast-recovery high-power limiter comprises the following steps: first, a substrate is provided on a metal region. The substrate is an AlN ceramic substrate, and metal traces are electroplated on its surface to form a surface metal layer with a thickness greater than 4 μm. Second, three heterogeneous chips are fixed to corresponding metal regions using different welding methods. The heterogeneous chips include a Si-based PIN diode, a GaN-based Schottky diode, and a GaAs-based PIN diode. The tops of all the chips are then interconnected with the upper traces via gold wire leads to form a functional series path. The inductor L is a gold-wire wound inductor, the resistor R and the capacitor C are small devices in 0201 packages, and the DC blocking capacitors C1 and C2 are flat surface-mount capacitors bonded to the surface metal. The interconnections are achieved via 50 μm-diameter gold wires using wedge bonding, spot welding, or ball bonding. Finally, the cathodes or circuit return paths of each device are connected to the underlying metal region through vertical openings to improve RF electrical performance and heat dissipation efficiency. The overall dimensions are 7.7 mm × 4 mm.

[0032] Furthermore, the Si-based PIN diode and the GaAs-based PIN diode are eutectic-welded to a molybdenum-copper alloy gasket below, and the whole is soldered to the metal area. The GaN-based Schottky diode is installed in the center of the AlN ceramic substrate by pasting or soldering with nano-silver paste, and is connected to the RC circuit by gold wire bonding.

[0033] Beneficial technical effects brought about by the present invention:

[0034] 1. Significantly improve the limiting response speed and recovery time performance;

[0035] This invention uses a GaN-based Schottky diode (SBD) as the pre-rectifier control unit. This diode exhibits an extremely low turn-on voltage (approximately 0.45V) and sub-nanosecond switching response. It can immediately conduct at the initial stage of the RF pulse, providing a DC bias to trigger the Si-based PIN diode to quickly enter a conductive state. Compared to traditional limiting structures based on Si or GaAs PIN diodes, this invention achieves an overall response time of less than 20ns, significantly superior to traditional Si PIN structures (typically in the microsecond range) and GaAs PIN structures (in the hundreds of nanoseconds).

[0036] 2. Reduce the limiting threshold and improve protection sensitivity;

[0037] This invention leverages the low turn-on characteristics of GaN SBDs and their synergy with the LRC bias network to bias the Si PIN diode into conduction at lower input power, effectively lowering the limiter's threshold. Experiments have shown that the limiting threshold of the proposed structure can be reduced to approximately 5–8 dBm, significantly lower than the 15 dBm or higher threshold of existing Si / GaAs PIN series structures. This makes it suitable for receiver systems with high sensitivity requirements.

[0038] 3. Improve high power handling capability and enhance reliability;

[0039] This invention utilizes a Si PIN diode as the primary limiting element in the front-end. This diode possesses excellent high-power handling capabilities, capable of handling loads in the hundreds of watts range. A subsequent GaAs PIN diode absorbs Si PIN leakage energy, improving overall output isolation. Structurally, through impedance transformation and reflected wave matching, the Si PIN diode can rapidly turn on when reflected wave peaks overlap, preventing spike leakage at the input. This structure offers enhanced robustness in high-repetition-rate, high-power pulse environments.

[0040] 4. Improve device integration and reduce packaging complexity and volume;

[0041] This invention utilizes an AlN ceramic + double-layer metal interconnect structure platform to achieve co-basic integration of three heterogeneous devices: Si, GaN, and GaAs, on a single substrate. The devices are interconnected via gold wires and grounded vias, simplifying the peripheral bias and power distribution network. This design is more compact than traditional designs that incorporate couplers and discrete bias sources. The overall limiter measures just 7.7mm x 4.0mm, significantly smaller than traditional surface-mount limiter modules (typically >15mm x 10mm).

[0042] 5. Improve production consistency and process compatibility;

[0043] All chips in this invention are fabricated using standard mounting and soldering processes, making them compatible with existing RF power module assembly platforms. Furthermore, the AlN substrate offers excellent thermal conductivity (>170W / m·K) and RF performance, helping to improve product yield and thermal stability, while avoiding operating point shifts caused by thermal mismatch or electrical performance drift.

[0044] 6. Simplify usage and improve project feasibility;

[0045] The limiter provided by the present invention has an integrated, passive, dual-port structure. Its installation method is compatible with conventional SMA ports or microstrip welding. It does not require additional bias or control circuits and is easy to embed directly in system-level modules, improving the convenience of on-site use and maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a schematic diagram of the device configuration in the present invention.

[0047] Figure 2 This is a circuit structure diagram of a heterogeneous integrated limiter in the present invention.

[0048] Figure 3 This is a top view of the heterogeneous integrated limiter in the present invention.

[0049] Figure 4 It is a side view of the heterogeneous integrated limiter in the present invention.

[0050] Figure 5 This is a comparison chart of the limiting characteristics of the limiter in the present invention and the performance of the traditional structure.

[0051] Figure 6 Schematic diagram of the recovery time of the limiter of the present invention.

[0052] Figure 7 Schematic diagram of the response time of the limiter of the present invention. DETAILED DESCRIPTION

[0053] The specific implementation of the present invention will be further described below with reference to specific embodiments:

[0054] A heterogeneously integrated fast recovery response high power limiter, such as Figure 1 As shown, a limiting structure consisting of a Si-based PIN diode, a GaN-based Schottky diode (SBD), and a GaAs-based PIN diode is employed in sequence. Through rigorous electrical connection design (first stage: Si-based PIN diode, with high power handling capability, responsible for the main limiting task; second stage: GaN-based Schottky diode, serving as a low-threshold fast rectifier; third stage: GaAs-based PIN diode; this order cannot be reversed, with the peak power handled by the Si PIN), the turn-on sequence is ensured to be GaN SBD → Si PIN → GaAs PIN (this is due to the different thresholds or turn-on voltages of the three diodes: typically 0.8V for the Si PIN, 0.45V for the GaN SBD, and 0.7V for the GaAs PIN). This allows for rapid rectification of high-power input signals, pre-biasing the main limiting diode, significantly improving the triggering speed and suppression capability of the limiter. Furthermore, a quarter-wavelength impedance transformation line and a parallel LRC network are introduced between the GaN SBD and Si PIN to further optimize conduction efficiency and bias path, while also ensuring broadband response.

[0055] In addition, to achieve miniaturization and electrothermal stability of the device, the present invention adopts a double-layer structure based on AlN ceramic and metal interconnection layer to realize the integrated packaging of the above-mentioned heterogeneous material devices, thereby improving the high-frequency adaptability and batch manufacturing capability of the limiter from a structural level.

[0056] like Figure 2 As shown, the limiter includes an input port, a first limiter unit, an impedance matching and rectification bias network, a second limiter unit and an output port in sequence;

[0057] The input port is used to receive external radio frequency signals or high-power pulse signals;

[0058] The first limiting unit uses a Si-based PIN diode D1, which is used to carry the main limiting task, that is, to carry high-power input signals. It has the strongest power handling capability and is the main power clamping path in the limiter. The selected model is MA4L401-134, which has a size of 0.4mm×0.4mm, a turn-on voltage of 0.8V@10mA, a thermal resistance of 16℃ / W, a reverse breakdown voltage greater than 250V, and an on-resistance of 1.2Ω, which can provide more than 8dB of isolation.

[0059] The impedance matching and rectification bias network is used to quickly trigger the front-stage PIN diode to conduct. It consists of the following three parts:

[0060] Quarter-wavelength impedance transformation line Z1: Since the GaN SBD has the lowest threshold and is the first to turn on, the quarter-wavelength impedance transformation line allows the reflected power to reach its peak at the Si PIN when the SBD turns on, prompting the preceding Si PIN to enter the on state earlier. In addition, C1 and C2 are DC-blocking capacitors that force the current rectified by the GaN SBD to be directly introduced into the Si PIN diode.

[0061] GaN-based Schottky diode D2: Its cathode is connected to the main signal path and is used to achieve low-voltage fast rectification function; the turn-on voltage is 0.45V, it turns on before the PIN diode, and can provide DC bias in the initial response stage; the selected model is Fengcheng Technology's FCR080, with a reverse breakdown voltage of 120V and an on-resistance of 2.5Ω.

[0062] The LRC series-parallel network, connected in parallel to the GaN SBD, consists of an inductor L, a resistor R, and a capacitor C. The inductor L prevents low-power signals from leaking to ground. The resistor R and the capacitor C together form the time constant τ = R × C of the rectifier output channel, which is used to control the bias holding time and ensure that the bias remains valid during the high-frequency signal cycle.

[0063] The second limiting unit includes GaAs-based PIN diodes D3 to D6, which are used to further reflect and absorb the remaining high-power energy leaked from the previous stage, thereby improving the final isolation of the limiter. Generally, for the sake of miniaturization, an adapted type of GaAs PIN diode limiter microwave monolithic integrated circuit (MMIC) is selected. For wide bandwidth considerations, D3 to D6 generally form a π-type structure together with a quarter-wavelength variation line. The tube selection is basically the same (this limiter is a common limiter on the market. The focus is on selecting a microwave monolithic integrated circuit for miniaturization, with a size of 2mm 2 within);

[0064] The output port is connected to a subsequent RF receiving or amplifying circuit.

[0065] Specifically, a DC blocking capacitor C1 and a characteristic impedance matching structure Z0 are connected in series between the input port and the first limiter unit. Z0 is connected to the anode of the Si-based PIN diode D1, and the cathode of D1 is grounded.

[0066] Specifically, a DC blocking capacitor C2 is further provided between the impedance matching and rectification bias network and the second amplitude limiting unit;

[0067] The LRC series-parallel network includes a capacitor C, a resistor R and an inductor L. The first ends of C and R are connected to the first end of L1, and the second ends of C and R are grounded. The cathode of the GaN-based Schottky diode D2 is connected to the first end of L, the anode of D2 is grounded, the second end of L is connected to the 1 / 4 wavelength impedance transformation line Z1 and the first end of C2, and the second end of Z1 is connected to the anode of D1.

[0068] Specifically, the second limiting unit also includes a 1 / 4 wavelength impedance transformation line Z2, the anodes of the GaAs-based PIN diodes D3 and D5, and the cathodes of D4 and D6 are grounded, the cathode of D3 and the anode of D4 are connected to the first end of Z2 and the second end of C2, and the cathode of D5 and the anode of D6 are connected to the second end of Z2 and the output port.

[0069] Specifically, when receiving a high-power RF input signal, the limiter is first in the low-power range, the signal amplitude is small, D1~D6 are all in the cut-off state, and the signal is directly transmitted to the subsequent stage;

[0070] Next, when the limiter is in the medium power range, the input signal voltage exceeds the turn-on voltage of GaN-based Schottky diode D2 (about 0.45V). D2 is turned on first, generating a DC rectifier output, which is biased to the anode of Si-based PIN diode D1 through the LRC network, triggering D1 to turn on early.

[0071] Then, when the limiter is in the high-power range, D1 enters a conductance modulation state, exhibiting extremely low dynamic resistance. Most of the input power is reflected or absorbed during this phase. Simultaneously, the quarter-wavelength conversion line design aligns the reflected wave peak with the position of D1, accelerating conduction. If any residual power still leaks to the subsequent stage, the GaAs-based PIN diode performs the final limiting.

[0072] Finally, the limiter is in the recovery stage after the signal disappears. The recovery time of the GaAs-based PIN diode is hundreds of nanoseconds, and the GaN-based Schottky diode recovers instantaneously. The recovery time of the overall limiter is controlled within <20ns, which is much faster than traditional Si PIN or GaAs PIN limiters.

[0073] A method for preparing a heterogeneously integrated fast recovery response high power limiter, such as Figure 3 and Figure 4 As shown, a substrate is first set on the metal area. The substrate is an AlN ceramic substrate with metal traces attached to its surface to form a surface metal. The thickness of the surface metal is greater than 4μm. Holes are opened in some positions of the surface metal and the substrate. Figure 3As shown, a vertical grounding structure is formed; secondly, three heterogeneous chips are fixed to the corresponding metal area by different welding methods. The heterogeneous chips include Si-based PIN diodes, GaN-based Schottky diodes and GaAs-based PIN diodes; then the tops of all chips are interconnected with the upper wiring through gold wire leads to form a functional series path. The inductor L uses a gold wire winding inductor, the resistor R and the capacitor C use small devices in 0201 package, and the DC blocking capacitors C1 and C2 use flat surface-mount capacitors bonded to the surface metal. They are bonded and interconnected by 50μm diameter gold wires using wedge welding, spot welding or ball welding; finally, the cathode or circuit return path of each device is connected to the metal area below through a vertical opening to improve RF electrical performance and heat dissipation efficiency;

[0074] The symmetrical structure and clear heat diffusion path make it suitable for high-power pulse operation. The overall size is 7.7mm×4mm.

[0075] Specifically, the Si-based PIN diode and the GaAs-based PIN diode are eutectic-welded with a molybdenum-copper alloy (MoCu) gasket underneath, and the entire device is soldered to the metal area. The GaN-based Schottky diode is installed in the center of the AlN substrate using nano-silver paste or soldering. Since GaN is a planar device, it is not necessary to open holes in the AlN and it is connected to the RC circuit by gold wire bonding.

[0076] Through the above structural design, the limiter of the present invention has the following technical advantages:

[0077] The response time is significantly shortened, and the overall recovery time is less than 20ns;

[0078] The limiter start-up voltage is reduced, and the SBD start-up voltage is only about 0.45V;

[0079] The output suppression capability is enhanced, the limiting curve is smoother, and there is no peak overshoot;

[0080] Improved wideband adaptability avoids the failure of traditional SBD solutions to respond at low frequencies;

[0081] The device has high integration and compact structure, which is conducive to the application of large-scale array systems.

[0082] like Figure 5 As shown in the figure, it can be seen that the red curve is the limiting characteristic curve of the general SI PIN and GaAs PIN limiters, which have problems with peak leakage and high start-up threshold. The blue curve is the present invention. Due to the presence of SBD and rectifier bias network, the Si PIN turns on quickly to achieve fast response, which not only reduces the turn-on threshold but also avoids the peak leakage phenomenon. At the same time, the SiPIN enters the conductivity modulation state faster, reflects and absorbs higher power, and reduces the overall limiting level. Figure 6 and Figure 7As shown, the response time and recovery time of the limiter of the present invention are both less than 20ns.

[0083] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A heterogeneously integrated fast recovery response high power limiter, characterized in that: It includes an input port, a first limiting unit, an impedance matching and rectification bias network, a second limiting unit and an output port in sequence; The input port is used to receive an external radio frequency signal or a high-power pulse signal; The first limiting unit uses a Si-based PIN diode D1 to carry the high-power input signal; The impedance matching and rectification bias network includes a 1 / 4 wavelength impedance transformation line Z1, a GaN-based Schottky diode D2 and an LRC series-parallel network, which is used to quickly trigger the front-stage PIN diode to turn on; The second limiting unit includes GaAs-based PIN diodes D3 to D6, which are used to further reflect and absorb the remaining high-power energy leaked from the previous stage, thereby improving the final isolation of the limiter; The output port is connected to a subsequent radio frequency receiving or amplifying circuit; A DC blocking capacitor C1 and an impedance matching structure Z0 are connected in series between the input port and the first amplitude limiting unit. Z0 is connected to the anode of the Si-based PIN diode D1, and the cathode of D1 is grounded. A DC blocking capacitor C2 is further provided between the impedance matching and rectification bias network and the second amplitude limiting unit; The LRC series-parallel network includes a capacitor C, a resistor R, and an inductor L, wherein the first ends of C and R are connected to the first end of L, the second ends of C and R are grounded, the cathode of the GaN-based Schottky diode D2 is connected to the first end of L, the anode of D2 is grounded, the second end of L is connected to the 1 / 4 wavelength impedance transformation line Z1 and the first end of C2, and the second end of Z1 is connected to the anode of D1; The second limiting unit also includes a 1 / 4 wavelength impedance transformation line Z2, the anodes of the GaAs-based PIN diodes D3 and D5, and the cathodes of D4 and D6 are grounded, the cathode of D3 and the anode of D4 are connected to the first end of Z2 and the second end of C2, and the cathode of D5 and the anode of D6 are connected to the second end of Z2 and the output port.

2. The heterogeneously integrated fast recovery response high power limiter according to claim 1, characterized in that: The Si-based PIN diode D1 is MA4L401-134, with a size of 0.4mm×0.4mm, a turn-on voltage of 0.8V@10mA, a thermal resistance of 16°C / W, a reverse breakdown voltage higher than 250V, an on-resistance of 1.2Ω, and can provide an isolation of more than 8dB. The GaN-based Schottky diode D2 is selected as FCR080, with a reverse breakdown voltage of 120V, an on-resistance of 2.5Ω, and a turn-on voltage of 0.45V; The GaAs-based PIN diodes D3 to D6 are microwave monolithic integrated circuits.

3. The heterogeneously integrated fast recovery response high power limiter according to claim 1, characterized in that: When receiving a high-power RF input signal, the limiter is first in the low-power range, D1~D6 are all in the cut-off state, and the signal is directly transmitted to the subsequent stage; Next, when the limiter is in the medium power range, the input signal voltage exceeds the turn-on voltage of GaN-based Schottky diode D2. D2 is turned on first, generating a DC rectifier output, which is biased to the anode of Si-based PIN diode D1 through the LRC series-parallel network, triggering D1 to turn on early. Then, when the limiter is in the high-power range, D1 enters the conductivity modulation state, exhibiting extremely low dynamic resistance. Most of the input power is reflected or absorbed in this stage. At the same time, due to the 1 / 4 wavelength conversion line design, the reflected wave peak is aligned with the phase at D1, accelerating the conduction. If there is still residual power leaking to the subsequent stage, the GaAs-based PIN diode will complete the final limiting; Finally, the limiter is in the recovery stage after the signal disappears. The recovery time of the GaAs-based PIN diode is hundreds of nanoseconds, and the GaN-based Schottky diode recovers instantaneously. The recovery time of the entire limiter is controlled within <20ns.

4. A method for preparing a heterogeneously integrated fast recovery response high power limiter according to any one of claims 1 to 3, characterized in that: First, a substrate is set on the metal area. The substrate is an AlN ceramic substrate with metal traces electroplated on its surface to form a surface metal layer with a thickness greater than 4μm. Secondly, three heterogeneous chips are fixed to the corresponding metal area through different welding methods. The heterogeneous chips include Si-based PIN diodes, GaN-based Schottky diodes, and GaAs-based PIN diodes. Then, the tops of all chips are interconnected with the upper traces through gold wire leads to form a functional series path. The inductor L is a gold wire wound inductor, the resistor R and the capacitor C are small devices in 0201 package, and the DC blocking capacitors C1 and C2 are flat surface-mount capacitors bonded to the surface metal. They are bonded and interconnected by 50μm diameter gold wire using wedge welding, spot welding, or ball welding. Finally, the cathode or circuit return path of each device is connected to the metal area below through vertical openings to improve RF electrical performance and heat dissipation efficiency. The overall size is 7.7mm×4mm.

5. The method for preparing a heterogeneously integrated fast recovery response high power limiter according to claim 4, characterized in that: The Si-based PIN diode and the GaAs-based PIN diode are eutectic-welded to a molybdenum-copper alloy gasket below, and the whole is soldered to the metal area. The GaN-based Schottky diode is installed in the center of the AlN ceramic substrate by pasting with nano-silver paste or soldering, and is connected to the RC circuit by gold wire bonding.

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