Process layer management and display method supporting multi-chip stacking design

Abstract

A process layer management and display method supporting multi-chip stacking design comprises the following steps: analyzing a layout file, generating a process layer list and a core particle list of all core particles, and distributing a corresponding shadow layer for each core particle; the shadow layer comprises a layer number and a layer name of the process layer, and a definition for controlling visible, selectable and color display of the core particles or the process layer; searching all core particles containing corresponding process layers from the core particle list and the process layer list according to input layer numbers and layer names, and performing highlight display; when the editing area is switched, the process layer of the target core particle is set to be in an active state in the process layer list; and storing the editing operation data of the process layer in the current active state into an independent layout file. An independent shadow layer is bound for each core particle, and the number and the name of the original process layer are reused, so that the correct editing behavior is ensured; the core particles and all process layers in the core particles are managed and displayed through coarse and fine granularity, so that the management and display problems of cross layers among different processes are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of 3D integrated circuit electronic design automation (EDA), and in particular to a process layer management and display method supporting multi-chip stacking design. Background Art

[0002] As the multi-chip stacking design process advances, multiple processes are nested within a single layout. The top-level layout that supports these multiple processes is called the top design. The modules containing chips from different processes within the top design are called die. These die are generally process-free and are primarily used for chip placement, verification, and simulation. The die in a top design typically originates from different processes. During the design process, it's necessary to view the placement and connection relationships between different regions and layers of the die in large quantities, requiring precise control over the display of each process layer. However, existing single-process layer management methods no longer meet the requirements for viewing complex multi-process layouts. The reasons are as follows: Layers across different processes overlap, making single-process layer management methods unable to precisely locate a specific layer within a specific process; overlapping layers share a single management solution, preventing personalized display control; and there's a lack of coarse-grained control over all process layers within a given die. Summary of the Invention

[0003] In order to solve the defects of the prior art, the purpose of the present invention is to provide a process layer management and display method that supports multi-chip stacking design, realizes personalized management of process layers in multi-chip stacking design, and supports process layer display and editing of multiple process layouts.

[0004] To achieve the above objectives, the present invention provides a process layer management and display method supporting multi-chip stacking design, including: Parse the layout file, generate a process layer list and a core particle list for all core particles, and assign a corresponding shadow layer to each core particle; the shadow layer includes the layer number and layer name of the process layer, as well as the definition of controlling the visibility, selectability, and color display of the core particle or process layer; According to the input layer number and layer name, all core particles containing the corresponding process layer are retrieved from the core particle list and the process layer list and highlighted; When switching the editing area, the process layer of the target core particle is set to active in the process layer list; and the editing operation data of the process layer in the current active state is saved in an independent layout file.

[0005] Furthermore, it also includes: providing a multi-process module, which is used to pop up a multi-process mode selection dialog box when the layout is opened, and allocate a corresponding shadow layer to each core particle.

[0006] Furthermore, it also includes: providing a process layer selection tool, which is used to manage and display the core particle list and the process layer list; in the process layer selection tool, according to the input layer number and layer name, all core particles containing the corresponding process layer are retrieved and highlighted.

[0007] Furthermore, in the top-level unit or module, each device instance is treated as a core particle, and an independent set of shadow layers is assigned to each device instance regardless of whether the device instance comes from the same layout; the layer number and layer name of each device instance in the shadow layer are the same as the layer number and layer name defined in the process file.

[0008] Furthermore, it also includes: Read the default color data from the process file and store it in the display editor; According to the colors configured by the user for the same process layer of different core particles in the display editor, the corresponding color matching data is saved in real time to the key-value database.

[0009] Furthermore, when a visible and / or optional state of a process layer is checked in the process layer list, only the state of the process layer of the current core particle is updated; When the visible and / or optional status of a core particle is checked in the core particle list, the status of all process layers of the corresponding core particle is updated in batches, and the status change in the core particle list will trigger the synchronous update of the corresponding row in the process layer list.

[0010] Furthermore, the step of retrieving and highlighting all core particles containing the corresponding process layer from the core particle list and the process layer list based on the input layer number and layer name also includes: performing combined screening based on the layer number and layer name of the process layer, and the device instance name to locate the target process layer.

[0011] Furthermore, when switching the editing area, the step of setting the process layer of the target core particle to an active state in the process layer list also includes: setting the process layer of the target core particle to the top, the font to the first set color, and the editable state in the process layer list, and setting the process layers of other core particles to the second set color and the disabled state.

[0012] To achieve the above-mentioned purpose, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein the processor is used to execute the computer program stored in the memory to implement the process layer management and display method supporting multi-chip stacking design as described above.

[0013] To achieve the above objectives, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the process layer management and display method supporting multi-chip stacking design as described above.

[0014] The process layer management and display method supporting multi-chip stacking design provided by the present invention has the following beneficial effects compared with the prior art: By binding an independent shadow layer to each core particle and reusing the original process layer number and name, correct editing behavior is guaranteed; by managing and displaying core particles and all process layers within the core particles at a coarse and fine granularity, the management and display issues of cross-layers between different processes are solved, making process layer management in multi-process scenarios more convenient; supporting quick search and personalized display, and significantly improving the efficiency of browsing and editing.

[0015] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 A flow chart of a process layer management and display method supporting multi-chip stacking design according to an embodiment of the present invention; Figure 2 An operation interface for opening a multi-process layout according to an embodiment of the present invention; Figure 3 is a schematic diagram of a shadow layer structure according to an embodiment of the present invention; Figure 4 An operation interface for a process layer selection tool for multiple processes according to an embodiment of the present invention; Figure 5 A display editor operation interface for multiple processes according to an embodiment of the present invention; Figure 6 Schematic diagram of the effect of checking DI1E_CMOS_CT according to an embodiment of the present invention; Figure 7 Schematic diagram of the effect of deselecting DIE1_CMOS_CT according to an embodiment of the present invention; Figure 8 is a schematic diagram of search results according to an embodiment of the present invention; Figure 9 An operation interface for modifying a color scheme according to an embodiment of the present invention; Figure 10 A schematic diagram of a process layer selection tool interface and layout effect according to an embodiment of the present invention; Figure 11 Schematic diagram of switching editing areas and editing operation effects according to an embodiment of the present invention; Figure 12 FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0018] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0019] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0020] It should be understood that the terms "first," "second," and the like may be mentioned in the present invention only to distinguish different data or units, and are not intended to limit the order or interdependence of the functions performed by these data or units. These terms are used solely to distinguish one feature from another. For example, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature, without departing from the scope of the exemplary embodiments.

[0021] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative and non-restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more." "Plurality" should be understood as two or more.

[0022] Figure 1 The following is a flowchart of a process layer management and display method for supporting multi-chip stacking design according to an embodiment of the present invention. Figure 1 The embodiments of the present invention are described in detail.

[0023] First, in step 101 , the multi-process module is enabled.

[0024] In the embodiment of the present invention, a multi-tech module (hereinafter referred to as MT) is added to provide an opening mode for manually setting the layout, such as Figure 2 As shown, when the layout is opened, the MT mode selection dialog box pops up, in which you can select the opening mode of the layout, for example, select Layout with MT (open the layout in MT mode). The multi-process module is used to assign an independent Shadow Layer to each core particle (instance, abbreviated as Inst) during initialization. The shadow layer inherits the layer number and layer name of the original process layer, and is mainly used to control the display status and display color of each device instance. When editing a device instance, you need to pay attention to the specific connection layer of other device instances connected to it, because these two device instances may come from the same process. By shielding the non-connected layers of other device instances, you can reduce display data and improve editing efficiency. In the shadow layer, other settings such as the display control (Visible Ctrl), selection control (Selectable Ctrl), color scheme (Packet) of each core particle can be defined separately, that is, the shadow layer of each core particle includes the layer number and layer name of its process layer, as well as the definition of the visible state, optional state, and color display of the core particle and process layer, thereby providing differentiated display control between core particles. For example, the shadow layer structure of the core particle is as follows Figure 3 , Tech Layer is the process layer, Die1 Shadow Layer is the shadow layer of the first core particle including the process layer, and Die2 Shadow Layer is the shadow layer of the second core particle including the process layer.

[0025] In this embodiment of the present invention, in the top-level cell or module of the hierarchy, each device instance is a corelet. Regardless of whether the device instance originates from the same layout, a set of shadow layers is assigned to it. The shadow layer's layer number and name match those defined in the process (Tech) file to ensure correct editing behavior.

[0026] In step 102 , the layout file is parsed to generate a layer table and a die table for all die, and a corresponding shadow layer is assigned to each die.

[0027] In an embodiment of the present invention, a process layer selection tool is provided, which is used to manage and display the core particle list and the process layer list. For example, when the process layer selection tool (Layer Select Window, LSW for short) is started and the layout is opened in MT mode, the process layer selection tool displays the names of all core particles and the process layer information (including layer number and layer name) used by each core particle in a fine-grained manner (high degree of data refinement). The core particle name is marked with the instance name (device instance name), such as Figure 4 At the same time, the core particle information needs to be displayed separately, such as Figure 4 The upper part is used to display and select the status of all process layers of the coarse-grained (low data refinement) control core particles, realizing the status linkage between the process layers and core particles.

[0028] In the embodiment of the present invention, when the visible and / or optional status of any process layer is checked in the process layer list, only the status of the process layer of the current core particle is updated; when the visible and / or optional status of any core particle is checked in the core particle list, the status of all process layers of the corresponding core particle is updated in batches, and the status change in the core particle list will trigger the synchronous update of the corresponding row in the process layer list. Figure 4 , by selecting the process layer list ( Figure 4 The S (optional) and V (visible) of a row in the lower middle part of the diagram control the display and selectable status of the process layer of the chip corresponding to the row in the layout; by selecting the chip list ( Figure 4 The S and V in a row in the upper middle part of the diagram control the display and selectable status of all process layers of the core particles corresponding to the row in the layout.

[0029] In an embodiment of the present invention, the following steps are also included: reading the default color matching data from the process file and storing it in the display editor; according to the colors configured by the user for the same process layer of different core particles in the display editor, the corresponding color matching data is saved in real time to the key-value database, thereby realizing dynamic color matching management and editing authority isolation in display and editing control. The color schemes (Packets) of each process layer of different core particles can be configured through the display editor (Display Resource Editor, hereinafter referred to as DRE) without affecting the colors of the corresponding process layers of other core particles. DRE mainly provides a process layer viewing and editing interface, which also displays the core particle information and process layer information of multiple processes, and can quickly locate the required process layer for easy operation, such as Figure 5 .

[0030] In step 103 , according to the process layer number and / or name input in the process layer selection tool, all core particles containing the corresponding process layer are retrieved from the core particle list and the process layer list and highlighted.

[0031] In an embodiment of the present invention, combined filtering based on the layer number and layer name of the process layer, as well as the device instance name, is supported to quickly locate the target process layer. The process layer selection tool supports search and filtering functions for multiple process layers. It can search by layer number and layer name to retrieve and filter all core particles with that process layer. Combined with the device instance name in the search results, it can quickly filter and locate the specified process layer of the specified core particle. Based on this function, all process layers of the core particle can also be filtered out, and the status of the process layers can be modified in batches.

[0032] In step 104 , when switching the editing area, the process layer of the target core particle is set to active in the process layer list; and the editing operation data of the process layer in the current active state is saved in an independent layout file.

[0033] In an embodiment of the present invention, when a user switches editing regions, the process layer of the target core is set to the top of the process layer list, with the font color set to the first setting and editable active state, while the process layers of other cores are set to the second setting color and disabled in an inactive state. Editing operations only affect the core in the current active state, and the operation data is saved in the corresponding independent layout file. The first setting color should be darker than the second setting color to intuitively display the process layer information of active and inactive cores.

[0034] In an embodiment of the present invention, a dynamic synchronization function is provided between the multi-process module and the process layer selection tool. When the multi-process module dynamically creates or deletes a core particle, the process layer of the corresponding core particle in the process layer selection tool is synchronously created or deleted. When switching editing areas, for example, switching from the Die1 editing area to the Die2 editing area, the process layer of the edited core particle in the process layer list is displayed in black font, which is selectable and fixed to the top. The process layer of other non-editable core particles is displayed in gray font and is not selectable. At the same time, the display format of the editable unit in the core particle list is different from that of other non-editable core particles.

[0035] The process layer management and display method provided by the present invention supports multi-chip stacking design. By binding an independent shadow layer to each core particle and reusing the original process layer number and name, correct editing behavior is ensured. By managing and displaying the core particles and all process layers within the core particles at a coarse and fine granularity, the management and display problems of cross-layers between different processes are perfectly solved. The process layer management in multi-process scenarios is made more convenient. Quick search and personalized display are supported. The efficiency of review and editing is improved. By hiding unnecessary core particle information, designers can focus more on the units that need to be reviewed and edited.

[0036] The effects of the present invention will be further illustrated below through a specific case.

[0037] For example, first, in an EDA design tool, when you right-click to open the layout, a selection box pops up, and you select Layout With MT (such as Figure 2 ), open the specified multi-process layout. This layout has three die: Die1_CMOS_CT, DIE2_SOI_SW, DIE3_GaAs_HBT. Use the layout tool to enter DIE2_SOI_SW for editing, such as Figure 6 , the right side is the layout interface, where the upper left is DIE2_SOI_SW, the upper right is DIE3_GaAs_HBT, and the bottom is Die1_CMOS_CT; Open the Layer Selection Tool (LSW), such as Figure 6 ,At this time, DIE2_SOC_SW in the core particle list turns blue, and the process layer of DIE2_SOC_SW in the process layer list below is highlighted (black), which can be selected and edited. The process layers of other core particles are set to gray and cannot be selected; By checking or unchecking V and S in the chip list in the process layer selection tool, you can control whether the corresponding chip can be displayed in the layout. For example, if you uncheck V in DIE1_CMOS_CT, all process layers of the chip will not be displayed. Figure 6 and Figure 7 ; In the process layer selection tool, search for process layer M5 in the Search bar. The process layers DIE2_SOC_SW and DIE3_GaAs_HBT are selected from the process layer list. However, only M5 of DIE2_SOC_SW is highlighted, while M5 of DIE3_GaAs_HBT is grayed out. Figure 8 ; Start the display editor (DRE), modify the display scheme of the process layer M5 of DIE3_GaAs_HBT in Packets and apply it (Apply), such as Figure 9 ; After the color scheme of the process layer M5 of DIE3_GaAs_HBT is modified, the color of M5 of DIE3_GaAs_HBT in the process layer selection tool and the layout is modified accordingly, such as Figure 10 ; Switch to DIE3_GaAs_HBT for editing and insert a path (Path) of process layer M1, such as Figure 11 , drawing means drawing. As can be seen from the figure, the editing operation only affects the currently active core particle DIE3_GaAs_HBT.

[0038] In an embodiment of the present invention, an electronic device is further provided. Figure 12 FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Figure 12As shown, the electronic device of the present invention includes a processor 1201 and a memory 1202, wherein: The memory 1202 stores a computer program. When the computer program is read and executed by the processor 1201 , the computer program executes the steps in the embodiment of the process layer management and display method supporting multi-chip stacking design as described above.

[0039] In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps in the embodiment of the process layer management and display method supporting multi-chip stacking design as described above when running.

[0040] In this embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0041] Those skilled in the art will understand that the foregoing descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will be able to modify the technical solutions described in the foregoing embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A process layer management and display method supporting multi-chip stacking design, characterized in that: include: Parse the layout file, generate a process layer list and a core particle list for all core particles, and assign a corresponding shadow layer to each core particle; the shadow layer includes the layer number and layer name of the process layer, as well as the definition of controlling the visibility, selectability, and color display of the core particle or process layer; According to the input layer number and layer name, all core particles containing the corresponding process layer are retrieved from the core particle list and the process layer list and highlighted; When switching the editing area, the process layer of the target core particle is set to active in the process layer list; Save the editing operation data of the currently active process layer to a separate layout file.

2. The process layer management and display method supporting multi-chip stacking design according to claim 1, characterized in that: Also includes: A multi-process module is provided, which is used to pop up a multi-process mode selection dialog box when the layout is opened and allocate a corresponding shadow layer to each core particle.

3. The process layer management and display method supporting multi-chip stacking design according to claim 1, characterized in that: Also includes: Providing a process layer selection tool, wherein the process layer selection tool is used to manage and display the core particle list and the process layer list; In the process layer selection tool, according to the input layer number and layer name, all core particles containing the corresponding process layer are retrieved and highlighted.

4. The process layer management and display method supporting multi-chip stacking design according to claim 1, characterized in that: In the top-level unit or module, each device instance is treated as a core particle. Regardless of whether each device instance comes from the same layout, an independent set of shadow layers is assigned to it; the layer number and layer name of each device instance in the shadow layer are the same as the layer number and layer name defined in the process file.

5. The process layer management and display method supporting multi-chip stacking design according to claim 1, characterized in that: Also includes: Read the default color data from the process file and store it in the display editor; According to the colors configured by the user for the same process layer of different core particles in the display editor, the corresponding color matching data is saved in real time to the key-value database.

6. The process layer management and display method supporting multi-chip stacking design according to claim 1, characterized in that: When a visible and / or optional state of a process layer is checked in the process layer list, only the state of the process layer of the current core particle is updated; When the visible and / or optional status of a core particle is checked in the core particle list, the status of all process layers of the corresponding core particle is updated in batches, and the status change in the core particle list will trigger the synchronous update of the corresponding row in the process layer list.

7. The process layer management and display method supporting multi-chip stacking design according to claim 1, characterized in that: The step of retrieving and highlighting all core particles containing the corresponding process layer from the core particle list and the process layer list based on the input layer number and layer name also includes: performing combined screening based on the layer number and layer name of the process layer and the device instance name to locate the target process layer.

8. The process layer management and display method supporting multi-chip stacking design according to claim 1, characterized in that: When switching the editing area, the step of setting the process layer of the target core particle to the active state in the process layer list also includes: setting the process layer of the target core particle to the top, the font to the first set color, and the editable state in the process layer list, and setting the process layers of other core particles to the second set color and the disabled state.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor is used to execute the computer program stored in the memory to implement the process layer management and display method supporting multi-chip stacking design as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, which is loaded and executed by a processor to implement the process layer management and display method supporting multi-chip stacking design as described in any one of claims 1 to 8.

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