Chip reset circuit, server and mobile terminal

Abstract

The invention discloses a chip reset circuit, a server and a mobile terminal, relates to the technical field of chip reset, and provides the chip reset circuit aiming at the problem that the reset of a CPU (Central Processing Unit) chip excessively depends on a CPLD (Complex Programmable Logic Device) chip at present. And a power-on ready signal is output to a backward stage through the time delay module. The post-stage reset control circuit can control whether to reset the CPU chip according to whether the reset trigger signal is received. Otherwise, a reset control signal is output all the time to prohibit the CPU chip from being started, so that the reset control requirement and the power-on time sequence management requirement of the CPU chip are met at the same time. And the circuit is completely realized by a hardware circuit and does not need to depend on complex devices such as a CPLD (Complex Programmable Logic Device), so that the reliability and the stability of the reset control of the CPU chip are greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip reset, and in particular to a chip reset circuit, a server and a mobile terminal. Background Art

[0002] Servers typically utilize multiple chips to implement their functions. When a server experiences issues like overheating, overvoltage, or software errors, the entire server system must be reset to restore normal operation. The most critical part of a server reset is resetting the central processing unit (CPU), the chip responsible for server operation. Furthermore, the CPU requires the server system to be fully powered on before it can function properly, necessitating strict control of the server system's power-up sequence.

[0003] Currently, servers typically use Complex Programmable Logic Devices (CPLDs) to control the power-on and power-off sequencing within the server system and reset the CPU chip. After the server system is fully powered on, the CPLD chip outputs a reset signal to the CPU chip's reset pin when needed, effectively resetting the CPU. However, this reset solution relies heavily on the CPLD chip. If the CPLD chip fails or malfunctions, it cannot properly reset the CPU chip, resulting in poor reliability.

[0004] Therefore, technicians in this field are in urgent need of a chip reset circuit to solve the problem of excessive dependence of the current common server reset solution on the CPLD chip, thereby improving the reliability of reset control. Summary of the Invention

[0005] The purpose of the present invention is to provide a chip reset circuit, a server and a mobile terminal to solve the current problem of over-reliance on CPLD chips when controlling the reset of a CPU chip.

[0006] In order to solve the above technical problems, the present invention provides a chip reset circuit, comprising: a logic AND module, a delay module and a reset control module;

[0007] The first input terminal of the logic AND module is connected to a first power supply, and the second input terminal of the logic AND module is connected to a second power supply; wherein the first power supply is the power supply for the chip reset circuit in the system; and the second power supply is the power supply that is located before the power-on timing sequence of the chip reset circuit in the power-on timing sequence of the system;

[0008] The output end of the logic and module is connected to the input end of the delay module, and the output end of the delay module is connected to the first input end of the reset control module; the delay module is used to output a power-on ready signal to the first input end of the reset control module after a delay when the input end receives the high-level signal output by the logic and module;

[0009] The second input end of the reset control module is connected to the reset trigger source and is used to receive the reset trigger signal output by the reset trigger source; the output end of the reset control module is connected to the reset end of the central processing unit chip; the reset control module is used to output a reset control signal to reset the central processing unit chip when the power-on ready signal is not received, and when the power-on ready signal and the reset trigger signal are received.

[0010] In a possible embodiment, the number of reset trigger sources is N, where N is a positive integer and greater than 2; the reset control module includes: N+1 input terminals;

[0011] Wherein, one input terminal of the reset control module is connected to the output terminal of the delay module, and the remaining N input terminals are respectively connected to the N reset trigger sources;

[0012] The reset control module is further configured to output the reset control signal when the power-on ready signal is not received, or when the power-on ready signal and the reset trigger signal output by any reset trigger source are received.

[0013] In a possible embodiment, the reset control signal and the reset trigger signal are low-level signals, and the power-on ready signal is a high-level signal;

[0014] The reset control module is a multi-input AND network composed of N AND gates;

[0015] The multi-input AND network outputs a high-level signal only when all input terminals are connected to high-level signals, and outputs a low-level signal otherwise.

[0016] In a possible embodiment, in the multi-input AND network:

[0017] The first input of the first AND gate is connected to the power-on ready signal; the output of the nth AND gate is connected to the first input of the n+1th AND gate, where n is a positive integer and n is less than N; the second input of each AND gate is respectively connected to the reset trigger signal output by different reset trigger sources; the output of the Nth AND gate serves as the output of the multi-input AND network.

[0018] In a possible embodiment, the reset trigger source includes: a socket strip;

[0019] Wherein, any one end of the socket strip is connected to the reset control module and is connected to the first power supply through a pull-up circuit; the other end of the socket strip is grounded.

[0020] In a possible embodiment, the reset trigger source includes: a reset button;

[0021] Wherein, a first end of the reset button is connected to the reset control module and is connected to the first power supply through a pull-up circuit; a second end of the reset button is grounded.

[0022] In a possible embodiment, the reset trigger source includes: a complex programmable logic device chip;

[0023] The output end of the complex programmable logic device chip is connected to the reset control module for outputting the reset trigger signal.

[0024] In order to solve the above technical problems, the present invention further provides a server, comprising the chip reset circuit as described above.

[0025] In a possible embodiment, the reset trigger source includes: a socket strip, a reset button, a complex programmable logic device chip, and a baseboard management controller chip.

[0026] In order to solve the above technical problem, the present invention further provides a mobile terminal, comprising the chip reset circuit as described above.

[0027] In a possible embodiment, the reset trigger source includes: a socket strip, a reset button, a complex programmable logic device chip, and a power management chip.

[0028] The present invention provides a chip reset circuit that uses a logic AND module to determine whether both a first power supply and a second power supply have been successfully powered on. The first power supply is used to power the chip reset circuit. The chip reset circuit can function properly only when the first power supply is operating. The second power supply is the power supply that powers up before the chip reset circuit in the system's (e.g., server system) power-up sequence. In server systems, the circuit used to reset the CPU chip is typically located at the last stage in the power-up sequence to ensure that effective control of the CPU chip reset occurs only after the server system is fully powered on. Therefore, only when both the first and second power supplies are operating (i.e., outputting a high level) does the logic AND module output a high-level signal to the delay module, indicating that the chip reset circuit has met the power-up sequence. Furthermore, after a delay, the delay module outputs a formal power-on-ready signal, indicating that the chip reset circuit has completed the power-up sequence and can implement reset control. Subsequently, the reset control module receives the reset trigger signal output by the reset trigger source and the power-on-ready signal output by the delay module. If the reset control module does not receive a power-on ready signal, it indicates that the chip reset circuit has not yet completed powering on. By default, it outputs a reset trigger signal to reset the CPU chip to prevent it from starting. If the reset control module receives a power-on ready signal, it assumes that the server has completed powering on. It then determines whether to reset the CPU chip based on whether it receives a reset trigger signal from the reset trigger source, completing normal CPU chip reset control.

[0029] From the above, it can be seen that this circuit can realize reset control of controlled objects such as CPU chips under the premise of meeting power-on timing control. The entire process is implemented by a simple hardware circuit without the participation of the CPLD chip, which is more reliable. It is not easy for the CPU chip to fail to reset or even malfunction due to damage or abnormality of complex devices such as the CPLD chip, thereby better ensuring the stability and reliability of the server system.

[0030] The server and mobile terminal provided by the present invention correspond to the above chip reset circuit and have the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 A schematic diagram of the structure of a chip reset solution provided by an embodiment of the present invention;

[0033] Figure 2A schematic structural diagram of a chip reset circuit provided by an embodiment of the present invention;

[0034] Figure 3 A circuit schematic diagram of a chip reset circuit provided by an embodiment of the present invention;

[0035] Figure 4 A structural diagram of a multi-input and network provided by an embodiment of the present invention;

[0036] Figure 5 Another structural diagram of multiple inputs and networks provided by an embodiment of the present invention;

[0037] Figure 6 A circuit schematic diagram of another chip reset circuit provided by an embodiment of the present invention;

[0038] Figure 7 A timing diagram of the first and second stages of a CPU chip reset process provided by an embodiment of the present invention;

[0039] Figure 8 A timing diagram of the third stage of a CPU chip reset process provided by an embodiment of the present invention;

[0040] Figure 9 A timing diagram of the fourth stage of a CPU chip reset process provided by an embodiment of the present invention;

[0041] Figure 10 A timing diagram of the fifth stage of a CPU chip reset process provided by an embodiment of the present invention;

[0042] Among them, 11 is a logic AND module, 12 is a delay module, 13 is a reset control module, and 20 is a reset trigger source. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] The core of the present invention is to provide a chip reset circuit, a server and a mobile terminal.

[0045] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0046] In a server system, the central processing unit (CPU) chip needs to wait until the entire server system is fully powered on before it can work properly. At the same time, only after the CPU chip is working properly, there is a need to reset the CPU chip to solve occasional problems during the operation of the CPU chip. Figure 1 As shown in the figure, the power-on and power-off sequencing and CPU chip reset control in a server are typically controlled by a Complex Programmable Logic Device (CPLD). The CPLD ensures that the CPU chip's power-on and power-off sequencing meets the server system's power-on and power-off sequencing requirements. It also provides reset control when the server system is operating normally, outputting a reset signal (CPU chips and other chips are generally reset by a low-level signal) to the CPU chip's reset terminal to reset the CPU.

[0047] However, it's easy to see that this reset control solution relies entirely on the CPLD chip. As a device with a complex structure and functionality, the CPLD chip is prone to malfunction or even damage in actual use. Therefore, the reliability of the current CPU chip reset solution, which relies entirely on the CPLD chip, needs to be further improved.

[0048] In order to solve the above problems, the present invention provides a chip reset circuit, such as Figure 2 As shown, it includes: a logic AND module 11, a delay module 12 and a reset control module 13.

[0049] The first input end of the logic AND module 11 is connected to the first power supply, and the second input end of the logic AND module 11 is connected to the second power supply; wherein, the first power supply is the power supply for the chip reset circuit in the system; the second power supply is the power supply that is located before the power-on sequence of the chip reset circuit in the system's power-on sequence.

[0050] The output end of the logic AND module 11 is connected to the input end of the delay module 12, and the output end of the delay module 12 is connected to the first input end of the reset control module 13; the delay module 12 is used to output a power-on ready signal to the first input end of the reset control module 13 after a delay when the input end receives a high-level signal output by the logic AND module 11.

[0051] The second input end of the reset control module 13 is connected to the reset trigger source 20 for receiving the reset trigger signal output by the reset trigger source 20; the output end of the reset control module 13 is connected to the reset end of the central processing unit chip; the reset control module 13 is used to output a reset control signal to reset the central processing unit chip when it does not receive a power-on ready signal, and when it receives a power-on ready signal and a reset trigger signal.

[0052] It should be noted that the above-mentioned logic AND module 11 is also a module for realizing the “logic AND” function, such as Figure 3 As shown, logical AND module 11 can be implemented using a device with a logical AND function, such as an AND gate. In circuit design, a high level is generally considered a logical "1" and a low level is considered a logical "0." This corresponds to the first and second power supplies. Specifically, when both power supplies are outputting, logical AND module 11 receives a logical "1," and when both power supplies are not outputting, logical AND module 11 receives a logical "0." The output logic of logical AND module 11 or the AND gate is shown in Table 1 below.

[0053] Table 1 AND gate truth table

[0054]

[0055] As can be seen, only when both the first and second power supplies are outputting (i.e., both outputting a logic "1") does the logic AND module 11 output a high-level signal, allowing the delay module 12 to output a power-on-ready signal after a certain delay. It should be noted that the power-on-ready signal can be of any form, as long as it can be recognized by the subsequent reset control circuit. In one possible implementation, the power-on-ready signal can be a high-level or low-level signal, with the specific high-level or low-level signal determined based on the specific implementation and output logic of the delay module 12 and reset control module 13.

[0056] The delay module 12 can be implemented by a Schmitt trigger, a delay circuit, etc. Figure 3 In the illustrated example of a possible chip reset circuit structure, the delay module 12 is implemented by a Schmitt trigger. The delay duration of the delay module 12 should be determined based on the power-on timing requirements of the chip reset circuit in actual scenarios, and this embodiment does not impose any limitation thereto.

[0057] But it should be noted that if Figure 3 The delay module 12 shown uses an inverted Schmitt trigger, that is, when the input terminal X is connected to a high level, the output terminal Y outputs a low level, and when the input terminal X is connected to a low level, the output terminal outputs a high level. Therefore, it is necessary to add an inverting module before or after the inverted Schmitt trigger to meet the logic requirements of the previous and subsequent stages. The inverting module can be connected through an inverter or a Figure 3The switch NM1 shown is implemented, and this embodiment does not limit this. However, if the delay module 12 uses a positive Schmitt trigger, that is, the level logic of the input terminal X and the output terminal Y are the same, then there is no need to add an inversion module.

[0058] Next, let's consider the reset control module 13. As described above, the output logic of the reset control module 13 controls the CPU chip reset when it doesn't receive the power-on-ready signal, regardless of whether it receives the reset trigger signal. However, when it receives the power-on-ready signal, it controls whether the CPU is reset based on whether the reset trigger signal has been received. Therefore, the specific implementation of the reset control module 13 depends on the specific implementations of the power-on-ready signal, the reset trigger signal, and the reset control signal.

[0059] Exemplarily, when the aforementioned power-on-ready signal is high and the reset trigger signal and reset control signal are low, the reset control module 13 can be a logic gate circuit composed of an AND gate. When there is only one reset trigger source 20, only one AND gate is required to implement the reset control module 13, with the power-on-ready signal and the reset trigger signal connected to the two inputs of the AND gate, respectively. When the power-on-ready signal is not received (i.e., one input is connected to a logic "0"), the AND gate will inevitably output a logic "0," regardless of whether the other input is connected to a logic "0" or a logic "1," thereby outputting the reset control signal to reset the CPU chip. Similarly, when the power-on-ready signal is received (i.e., one input is connected to a logic "1"), the output of the AND gate is dependent on the signal connected to the other input. If the other input is connected to the reset trigger signal (i.e., a logic "0"), the AND gate also outputs a logic "0," otherwise it outputs a logic "1."

[0060] Similarly, when the high and low level correspondences of the power-on ready signal, the reset trigger signal, and the reset control signal are completely opposite, the reset control module 13 can also be implemented using an OR gate. Furthermore, when the power-on ready signal, the reset trigger signal, and the reset control signal use signal forms other than high and low levels, the reset control module 13 also needs to adapt. Since other signal forms are too numerous to enumerate, they are not described in detail in this embodiment.

[0061] Furthermore, regarding the aforementioned first and second power supplies, the first power supply needs to be determined based on the power supply requirements of the various components in the chip reset circuit. Any power supply that meets the voltage levels required by the components in the chip reset circuit can be selected from the server system. Although this embodiment does not restrict the specific implementation of the various components in the chip reset circuit, it is readily apparent that the currently common delay module 12 often requires a power supply to achieve its delay function. Therefore, the selection of the first power supply can be determined based on the power supply requirements of the delay module 12. The second power supply is determined based on the power-on sequence requirements of the chip reset circuit in the actual system. The second power supply is selected as the power supply that precedes the chip reset circuit in the system power-on sequence to ensure that the chip reset circuit powers on according to the expected power-on sequence. It should be noted that in typical server system applications, the CPU chip reset control system (i.e., this circuit) is generally located at the last stage of the entire system power-on sequence.

[0062] The reset trigger source 20 described above can be any device capable of responding to a reset request in practical applications. For example, a CPLD chip in a conventional server system, which is used in related art to implement reset control for the CPU chip, can selectively output a specific signal based on the actual reset requirement. Furthermore, other chips can be used as the reset trigger source 20 to implement a soft reset, or a hardware circuit or structure can be used as the reset trigger source 20 to implement a hard reset, etc., which are not limited in this embodiment.

[0063] Furthermore, if the CPU chip has multiple reset terminals, this circuit can be used to achieve unified reset control of multiple reset terminals. Figure 3 As shown, assuming that the CPU chip has four different reset terminals RST2, RST3, RST4, and RST5, unified reset management can be achieved by connecting these four reset terminals to the output terminal of this circuit.

[0064] As can be seen from the above, the chip reset circuit provided by the present invention performs logical AND processing on the first power supply for the chip reset circuit and the second power supply located at the previous level of the chip reset circuit in the system power-on sequence. Only when both power supplies have completed normal power-on output will the power-on ready signal be output to the subsequent stage through the delay module 12. The delay processing delay made by the delay module 12 is used to meet the needs of the power-on interval of each level in the power-on sequence. Only when the power-on sequence is met, the reset control circuit of the subsequent stage can control whether to reset the CPU chip based on whether the reset trigger signal is received. Otherwise, the reset control signal is always output to prohibit the CPU chip from starting, thereby meeting the power-on sequence management requirements for the CPU chip. In addition, after the power-on sequence is met, the reset control module 13 can decide whether to control the reset of the CPU chip based on whether the reset trigger signal output by the reset trigger source 20 is received, thereby achieving effective and reliable reset control.

[0065] This circuit can realize reset control of controlled objects such as CPU chips under the premise of meeting power-on timing control. The entire process is realized by a simple hardware circuit without the participation of CPLD chips, which is more reliable. It is not easy for the CPU chip to fail to reset or even malfunction due to damage or abnormality of complex devices such as CPLD chips, thus better ensuring the stability and reliability of the server system.

[0066] On the other hand, in the above embodiment, there is no restriction on the number of reset trigger sources 20. The chip reset circuit provided by the present invention can also support reset control based on multiple different reset trigger sources 20. Specifically, this embodiment provides a corresponding implementation scheme:

[0067] There are N reset trigger sources 20 , where N is a positive integer and greater than 2. The reset control module 13 includes N+1 input terminals.

[0068] One input end of the reset control module 13 is connected to the output end of the delay module 12 , and the remaining N input ends are connected to N reset trigger sources 20 respectively.

[0069] The reset control module 13 is further configured to output a reset control signal when no power-on ready signal is received, or when both the power-on ready signal and a reset trigger signal output by any reset trigger source 20 are received.

[0070] In this embodiment, the reset control module 13 includes N+1 input terminals to receive a power-on ready signal and N reset trigger signals output by N reset trigger sources 20. Any reset trigger signal output by any reset trigger source 20 can serve as a condition for the reset control module 13 to control the CPU chip reset.

[0071] This embodiment introduces multiple reset trigger sources 20 to ensure the reliability and stability of the reset trigger control of the CPU chip through more and more comprehensive reset trigger sources 20, thereby further ensuring the stable operation of the CPU chip in the server system.

[0072] Specifically, when the reset trigger signal is low, if the N reset trigger signals are treated as a logical AND, the output logic of the reset control module 13 is essentially unchanged. Specifically, only when all reset trigger sources 20 fail to output a reset trigger signal (all output a logical "1") does the reset control module 13 fail to receive a reset trigger signal (i.e., multiple logical "1s" still produce a logical "1" after logical AND processing). However, when any reset trigger source 20 outputs a reset trigger signal (i.e., any reset trigger source 20 outputs a logical "0"), the reset control module 13 receives a reset trigger signal (i.e., as long as there is a logical "0," the final output of the logical AND processing is always a logical "0").

[0073] Based on the above, it can be known that the functional requirements of the reset control module 13 can be met by introducing a multi-input and network structure in which the number of input terminals can adapt to the number of reset trigger sources 20. This embodiment provides a possible implementation scheme, such as Figure 3 As shown:

[0074] The reset control signal and reset trigger signal are low-level signals, and the power-on ready signal is a high-level signal.

[0075] The reset control module 13 is a multi-input AND network composed of N AND gates, wherein the multi-input AND network outputs a high-level signal only when all input terminals are connected to high-level signals, and outputs a low-level signal otherwise.

[0076] But it should be noted that if Figure 3 The multi-input AND network structure shown is only one possible way of connecting AND gates. This embodiment provides a corresponding implementation scheme based on this. Figure 3 As shown, in multiple input networks:

[0077] The first input of the first AND gate is connected to the power-on ready signal; the output of the nth AND gate is connected to the first input of the n+1th AND gate, where n is a positive integer and n is less than N; the second input of each AND gate is respectively connected to the reset trigger signal output by a different reset trigger source 20; the output of the Nth AND gate serves as the output of the multi-input AND network.

[0078] That is, in this embodiment, the AND gates are connected by Figure 4The connection method shown is cascaded. Except that the first input terminal of the first-level AND gate is used to access the power-on ready signal, the first input terminal of each level of AND gate is connected to the output terminal of the previous level AND gate. In addition, the second input terminal of each level of AND gate is used to connect to a reset trigger source 20 for receiving a reset trigger signal. The output terminal of the last level of AND gate serves as the output terminal of the entire multi-input AND network and outputs the final reset control signal. The entire multi-input AND network provided in this embodiment constitutes a logical AND network containing N+1 inputs. It outputs logic "1" only when all N+1 inputs are logic "1", otherwise it outputs logic "0", which can meet the needs of the reset control module 13 in the above embodiment.

[0079] In another possible embodiment, the connection relationship between each AND gate in the multi-input AND network can also be as follows: Figure 5 The structure shown in FIG. Based on the last-stage AND gate (i.e., the output of this AND gate serves as the output of the reset control module 13), an AND gate is added before the AND gate for each additional reset trigger signal required. Each AND gate includes at most two AND gates connected to it from the previous stage. This structure also satisfies the output logic requirement of outputting a logic "1" only when all N+1 inputs are logic "1" and outputting a logic "0" otherwise, thus meeting the requirements for the reset control module 13 in the above embodiment.

[0080] In addition, N AND gates can be connected in other ways to form a multi-input AND network with N+1 input terminals, and this embodiment does not impose any restrictions on this. As long as the multi-input AND network consists of N+1 AND gates, and the number of AND gate input terminals not connected to the output terminals of other AND gates is N+1, it can meet the output logic requirement of outputting a logic "1" only when all N+1 inputs are logic "1" and outputting a logic "0" otherwise, thereby meeting the requirements of the reset control module 13 in the above embodiment.

[0081] As can be seen from the above embodiments, the present invention provides a solution for implementing the reset control module 13 using AND gates, and provides multiple different implementations of the reset control module 13 based on the number of reset trigger sources 20. Each solution is implemented using a simple hardware network consisting of multiple AND gates, eliminating the need for any complex control components, further improving the reliability of CPU chip reset control.

[0082] On the other hand, in the above embodiment, there is no limitation on the specific nature of the reset trigger source 20. In one possible embodiment, the CPLD chip originally used for resetting the CPU chip can be used as a possible reset trigger source 20. In this case, this embodiment provides a corresponding implementation scheme, such as Figure 3 As shown, the reset trigger source 20 includes: a complex programmable logic device chip;

[0083] The output end of the complex programmable logic device chip is connected to the reset control module 13 for outputting a reset trigger signal.

[0084] Since the CPLD chip is used to control the reset of the CPU chip in the related art, there is no need to make complex modifications to the original CPLD chip and it can be used as the reset trigger source 20 in this circuit, which is easy to implement.

[0085] In addition, the reset implemented by using complex control devices such as CPLD chips is a soft reset solution, that is, the reset trigger signal is sent through software methods. Figure 6 As shown, this function can also be implemented by other chips besides the CPLD chip. The specific chip to be used can be determined based on the system in which the reset circuit of this chip is actually applied, and which chips have the reset control function or can add the reset control function.

[0086] On the other hand, in addition to the soft reset solution implemented by the chip and software method, this embodiment also provides a hard reset solution implemented by a hardware circuit or device, such as Figure 3 As shown, the reset trigger source 20 includes: a socket SW1.

[0087] Among them, either end of the socket SW1 (such as Figure 3 Pin 2 in the socket SW1 is connected to the reset control module 13 and is connected to the first power supply VDD through a pull-up circuit; the remaining terminals of the socket SW1 (such as Figure 3 Pins 1 and 3 in the circuit are grounded.

[0088] Combine Figure 3 It is not difficult to see that when the socket SW1 is vacant, the socket terminals are suspended (mainly because pin 2 is not connected to other pins). At this time, pin 2 will be pulled to a high level by the pull-up circuit, which is equivalent to the input terminal of the corresponding reset control module 13 receiving a high-level signal, and will not trigger the reset of the CPU chip. When the socket SW1 is closed, the socket terminals are connected to each other. Figure 3 Pin 2 of SW1 is connected to pins 1 and 3, and pin 2 is equivalent to ground. At this time, even if there is a pull-up circuit, the input end of the corresponding reset control module 13 will be pulled down to a low level due to grounding. At this time, it is equivalent to outputting a low-level signal as a reset trigger signal, which can trigger the reset of the CPU chip.

[0089] In addition, this embodiment also provides another possible hard reset solution, such as Figure 3 As shown, the reset trigger source 20 includes: a reset button Reset Button.

[0090] A first end of the reset button Reset Button is connected to the reset control module 13 and is connected to the first power supply VDD through a pull-up circuit; a second end of the reset button Reset Button is grounded.

[0091] Similar to the aforementioned power strip, the first terminal of the reset button in this embodiment, connected to the reset control module 13, also outputs a high voltage by default via a pull-up circuit. To reset the device, the reset button can be pressed, connecting its first and second terminals. This grounds the first terminal, pulling the terminal voltage down to a low level and effectively outputting a reset trigger signal to reset the CPU chip.

[0092] It should be noted that the various reset schemes provided in the above embodiments, whether soft or hard, do not conflict with each other and can be implemented simultaneously. By increasing the number of AND gates in the reset control module 13 accordingly based on the number of reset trigger sources 20 introduced, redundant reset control logic based on multiple reset trigger sources 20 can be implemented, further improving the reliability of the CPU chip reset control.

[0093] Furthermore, in order to better illustrate the principle of the chip reset circuit provided by the present invention, this embodiment combines the above embodiments and Figure 3 A chip reset circuit is shown in the figure, and the whole working process of the chip reset circuit is explained in more detail:

[0094] 1. The first stage: when the system is powered on;

[0095] At this point, pin A of AND gate AND1 defaults to a high level (because if the first power supply, VDD, is depleted, subsequent circuits like the Schmitt trigger and pull-up circuit will not function properly, and the reset control function will be impossible. Therefore, it is assumed here that the system power-up sequence has progressed at least until the first power supply, VDD, is powered on). Pin B of AND gate AND1 defaults to a low level (i.e., the second power supply is not powered on). The high level of pin A and the low level of pin B are logically ANDed by AND gate AND1, outputting a low signal from pin C. Pin C is connected to the base of NMOS transistor NM1 through resistor R2, disconnecting NM1 and turning Schmitt trigger pin X high. At this point, pin 2 of power strip SW1 is not connected to pins 1 or 3, so pin D of AND gate AND2 is low. Since the ResetButton is not pressed, pin E of AND gate AND2 is high. The low level of pin D and the high level of pin E are logically ANDed by AND gate AND2, outputting a low signal from pin F. At this time, the CPLD chip has not yet completed power-on and started normal operation, and the default output is high level, that is, the pin H of the AND gate AND3 is high level. The low level signal of pin G and the high level signal of pin H are ANDed through the AND gate AND3, and a low level signal is output from pin I. The CPU chip is reset and cannot start. The timing diagram of the above process is shown in the figure below. Figure 7 shown.

[0096] 2. The second stage: system power-on is completed;

[0097] After the second power supply voltage reaches the system requirement value and is output stably, the PWRGD pin of the second power supply outputs a high level signal to the AND gate AND1 pin B. Figure 7 It can be seen that at this time, the signal at pin B changes from low level to high level, and the pin A of AND gate AND1 is connected to the first power supply VDD through resistor R1, and the pin A of AND gate AND1 continues to input high level. Therefore, the high level of pin A and the high level signal of pin B are ANDed through the AND gate AND1, and a high level signal is output from pin C. Figure 4 It can be seen from the figure that the signal of pin C changes from low level to high level. After that, pin C is connected to the base of NMOS tube NM1 through resistor R2, controlling NM1 to close, and the pin X of Schmitt trigger changes from high level to low level input. After the Schmitt trigger is delayed, the signal output by pin Y changes from low level to high level. At this time, pin 2 of socket SW1 is not connected to pin 1 or pin 3, and the input signal of pin D of AND gate AND2 changes from low level to high level. Since pin E of AND gate AND2 is connected to the power supply VDD with pull-up resistor R4, the reset button Reset Button is not pressed at this time, and pin E of AND gate AND2 continues to input high level. Therefore, the high level signals of pin D and pin E are ANDed through the AND gate AND2 to output a high level signal from pin F, and the timing is shown in FIG. Figure 7It can be seen that the signal at pin F changes from low level to high level, and the input signal at pin G of AND gate AND3 changes from low level to high level. Although pin H of AND gate AND3 is connected to the CPLD chip, the CPLD chip does not send a reset signal through the RST1 pin. Since pin H of AND gate AND3 is connected to the pull-up resistor R5 to the power supply VDD, pin H of AND gate AND3 inputs a high level. The high level signals of pin G and pin H are ANDed through the AND logic of AND gate AND3 to output a high level signal from pin I. Pin I is connected to the RST2, RST3, RST4, and RST5 pins of the CPU chip to reset the CPU. After the CPU is reset, the system starts to work normally. The timing diagram of the above process is shown as follows. Figure 7 shown.

[0098] 3. The third stage: The system runs abnormally and the CPU chip is reset through the socket strip;

[0099] The specific reset trigger action is: connect pin 2 of the power strip SW1 to pin 1 or pin 3 for a few seconds and then disconnect it. The specific time that SW1 pin 2 is pulled low is determined by the system reset requirements.

[0100] When pin 2 of the socket SW1 is connected to pin 1 or pin 3, the input signal of pin D of AND gate AND2 changes from high level to low level. For the timing diagram, see Figure 8 Since the AND2 pin E is connected to the power supply VDD by the pull-up resistor R4, the reset button Reset Button is not pressed at this time, and the AND2 pin E continues to input a high level. The low level signal of pin D and the high level signal of pin E are ANDed through the AND2 logic and output a low level signal from pin F. Figure 8 It can be seen that the signal at pin F changes from high to low, and the input signal at pin G of AND gate AND3 changes from high to low. Although pin H of AND gate AND3 is connected to the CPLD chip, no reset trigger signal is being sent through the CPLD chip at this time. Because pin H of AND gate AND3 is connected to power supply VDD via pull-up resistor R5, the input to pin H of AND gate AND3 is high. The low level at pin G and the high level at pin H are combined through the AND logic of AND gate AND3, and a low level signal is output from pin I.

[0101] When SW1 pin 2 is pulled to a low level for a few seconds and then disconnected, the input signal of AND2 pin D changes from a low level to a high level. The timing can be seen in Figure 8 Since the AND gate AND2 pin E is connected to the first power supply VDD by the pull-up resistor R4, the reset button is not pressed at this time, and the AND gate AND2 pin E continues to input a high level. The high level signals of pin D and pin E are ANDed through the AND gate AND2, and a high level signal is output from pin F. Figure 8It can be seen that the signal at pin F changes from low level to high level, and the input signal at pin G of AND gate AND3 changes from low level to high level. The CPLD chip connected to pin H of AND gate AND3 does not send a reset trigger signal. Since pin H of AND gate AND3 is connected to the pull-up resistor R5 to the power supply VDD, pin H of AND gate AND3 inputs a high level. The high level signals of pin G and pin H are ANDed through the AND logic of AND gate AND3 to output a high level signal from pin I. Pin I is connected to the RST2, RST3, RST4, and RST5 pins of the CPU chip, the CPU is reset, and the system starts to work normally. The timing diagram of the above process is shown in the figure. Figure 8 shown.

[0102] 4. The fourth stage: The system runs abnormally, and the CPU chip is reset by pressing the reset button;

[0103] The specific reset trigger action is: press and hold the reset button for a few seconds and then lift it.

[0104] When the reset button is pressed, the AND2 pin E changes from high level to low level. The specific low level maintenance time is determined by the system reset requirements. For the timing diagram, see Figure 9 The high level signal of pin D and the low level signal of pin E are combined with the logic of AND gate AND2 to output a low level signal from pin F. Figure 9 As can be seen in the figure, the signal at pin F changes from high to low, so the input signal at pin G of AND gate AND3 changes from high to low. Although pin H of AND gate AND3 is connected to the CPLD chip, no reset trigger signal is sent through the CPLD chip at this time. Because pin H of AND gate AND3 is connected to the first power supply VDD via pull-up resistor R5, the input to pin H of AND gate AND3 is high. The low level at pin G and the high level at pin H are combined through the AND logic of AND gate AND3, resulting in a low level signal output from pin I, resetting the CPU chip.

[0105] When the Reset Button is pressed for a few seconds and then released, the input signal of the AND2 pin E changes from low level to high level. For the timing diagram, see Figure 9 The high level signal of pin D and the high level signal of pin E are processed by AND gate AND2 to output a high level signal from pin F. Figure 9It can be seen that the signal at pin F changes from low level to high level, and the input signal at pin G of AND gate AND3 changes from low level to high level. Pin H of AND gate AND3 is connected to the pull-up resistor R5 to the power supply VDD, and pin H of AND gate AND3 inputs a high level. The high level signals at pin G and pin H are ANDed through the AND logic of AND gate AND3 to output a high level signal from pin I. Pin I is connected to the RST2, RST3, RST4, and RST5 pins of the CPU chip. The CPU chip is powered on again, completing the complete CPU chip reset process, and the system starts to work normally. The timing diagram of the above process is shown in the figure. Figure 9 shown.

[0106] 5. The fifth stage: The system runs abnormally, and the CPU chip is reset through the CPLD chip;

[0107] The specific reset trigger action is: the RST1 pin of the CPLD chip sends a low-level signal for a few seconds and then sends a high-level signal.

[0108] When the RST1 pin of the CPLD chip sends a low-level signal, the AND3 pin H of the AND gate changes from a high level to a low level. The specific low-level maintenance time is determined by the system reset requirements. For the timing diagram, see Figure 10 The high level signal of pin G and the low level signal of pin H are combined through the AND gate AND3 to output a low level signal from pin I. The RST1 pin of the CPLD chip sends a low level signal for a few seconds and then sends a high level signal. After sending the high level signal, the input signal of the AND gate AND3 pin H changes from low level to high level. For the timing diagram, see Figure 10 The high level signals of pin G and pin H are combined through the AND gate AND3 to output a high level signal from pin I. Pin I is connected to the RST2, RST3, RST4, and RST5 pins of the CPU chip, and the CPU is reset, and the system starts to work normally. The timing diagram of the above process is shown in the figure below. Figure 10 shown.

[0109] As can be seen from the first and second stages above, the chip reset circuit provided by the present invention can achieve accurate power-on and power-off timing management of the CPU chip without relying on the CPLD chip. Furthermore, based on the third to fifth stages, it can be seen that the chip reset circuit provided by the present invention can achieve effective reset control of the CPU chip through the CPLD chip or other reset trigger source, thus eliminating the dependence on the CPLD chip and improving the reliability of the normal operation and reset control of the CPU chip.

[0110] In the above embodiments, a chip reset circuit is described in detail. A typical application scenario of the chip reset circuit is to reset the CPU chip in a server system. Therefore, the present application also provides a corresponding embodiment of a server, which includes: a chip reset circuit as described in any of the above embodiments.

[0111] Since the server portion embodiment corresponds to the circuit portion embodiment, the server portion embodiment can be found in the circuit portion embodiment description and will not be repeated here. However, it should be noted that when a chip other than the CPLD chip is selected as the reset trigger source for the soft reset, this embodiment provides a possible implementation plan for selecting the reset trigger source in the server:

[0112] Reset trigger sources include: socket strips, reset buttons, complex programmable logic device chips, and baseboard management controller chips.

[0113] The baseboard management controller (BMC) chip is a key module for intelligent server monitoring, remote control, and operational optimization. It monitors and determines whether the CPU chip is operating normally. Therefore, if a CPU chip malfunctions, the BMC detects this and uses it as a reset trigger to reset the CPU chip through the chip reset circuit. This eliminates the need for new equipment to trigger the CPU chip reset, and eliminates the need for major changes to the BMC's existing logic. The BMC simply outputs a reset trigger signal to the chip reset circuit when it detects a CPU chip malfunction.

[0114] In addition, this embodiment also provides a corresponding embodiment of a mobile terminal, which includes a chip reset circuit as described in any of the above embodiments. Since the embodiments of the mobile terminal portion correspond to the embodiments of the circuit portion, the embodiments of the mobile terminal portion refer to the description of the embodiments of the circuit portion and are not further described here. However, it should be noted that when a chip other than the CPLD chip is selected as the reset trigger source for the soft reset, this embodiment provides a possible implementation plan for selecting the reset trigger source in the mobile terminal:

[0115] Reset trigger sources include: socket strips, reset buttons, complex programmable logic device chips, and power management chips.

[0116] Similar to the above-mentioned embodiment of the server part, since mobile terminals such as mobile phones are generally not equipped with high-performance operation and maintenance management chips such as BMC chips. Therefore, for the mobile terminal scenario, other soft reset chips except CPLD chips can be implemented through power management chips. Most current mobile terminals are equipped with power management chips, which are used to monitor and manage the power supply and operation status of various devices in the mobile terminal. Based on this, the same reset logic as the above-mentioned BMC chip can be implemented, that is, when the CPU chip operates abnormally, a reset trigger signal is output to the chip reset circuit to control the reset of the CPU chip. This implementation scheme also does not introduce additional control devices, and can realize the function without making too many improvements to the software program of the power management chip, and is easy to implement.

[0117] The above is a detailed introduction to a chip reset circuit, a server and a mobile terminal provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0118] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A chip reset circuit, characterized in that: include: Logic AND module, delay module and reset control module; The first input terminal of the logic AND module is connected to a first power supply, and the second input terminal of the logic AND module is connected to a second power supply; wherein the first power supply is the power supply for the chip reset circuit in the system; and the second power supply is the power supply that is located before the power-on timing sequence of the chip reset circuit in the power-on timing sequence of the system; The output end of the logic and module is connected to the input end of the delay module, and the output end of the delay module is connected to the first input end of the reset control module; the delay module is used to output a power-on ready signal to the first input end of the reset control module after a delay when the input end receives the high-level signal output by the logic and module; The second input terminal of the reset control module is connected to the reset trigger source, and is used to receive the reset trigger signal output by the reset trigger source; The output end of the reset control module is connected to the reset end of the central processing unit chip; the reset control module is used to output a reset control signal to reset the central processing unit chip when the power-on ready signal is not received, and when the power-on ready signal and the reset trigger signal are received.

2. The chip reset circuit according to claim 1, characterized in that: There are N reset trigger sources, where N is a positive integer and greater than 2; The reset control module includes: N+1 input terminals; Wherein, one input terminal of the reset control module is connected to the output terminal of the delay module, and the remaining N input terminals are respectively connected to the N reset trigger sources; The reset control module is further configured to output the reset control signal when the power-on ready signal is not received, or when the power-on ready signal and the reset trigger signal output by any reset trigger source are received.

3. The chip reset circuit according to claim 2, characterized in that: The reset control signal and the reset trigger signal are low level signals, and the power-on ready signal is a high level signal; The reset control module is a multi-input AND network composed of N AND gates; The multi-input AND network outputs a high-level signal only when all input terminals are connected to high-level signals, and outputs a low-level signal otherwise.

4. The chip reset circuit according to claim 3, characterized in that: In the multi-input network: The first input of the first AND gate is connected to the power-on ready signal; the output of the nth AND gate is connected to the first input of the n+1th AND gate, where n is a positive integer and n is less than N; the second input of each AND gate is respectively connected to the reset trigger signal output by different reset trigger sources; the output of the Nth AND gate serves as the output of the multi-input AND network.

5. The chip reset circuit according to claim 3, characterized in that: The reset trigger source includes: a socket strip; Wherein, any one end of the socket strip is connected to the reset control module and is connected to the first power supply through a pull-up circuit; the other end of the socket strip is grounded.

6. The chip reset circuit according to claim 3, characterized in that: The reset trigger source includes: a reset button; Wherein, a first end of the reset button is connected to the reset control module and is connected to the first power supply through a pull-up circuit; a second end of the reset button is grounded.

7. The chip reset circuit according to claim 3, characterized in that: The reset trigger source includes: a complex programmable logic device chip; The output end of the complex programmable logic device chip is connected to the reset control module for outputting the reset trigger signal.

8. A server, characterized in that: The chip reset circuit comprises the chip reset circuit according to any one of claims 1 to 7.

9. The server according to claim 8, wherein: Reset trigger sources include: socket strips, reset buttons, complex programmable logic device chips, and baseboard management controller chips.

10. A mobile terminal, characterized in that: The chip reset circuit comprises the chip reset circuit according to any one of claims 1 to 7.

11. The mobile terminal according to claim 10, wherein: Reset trigger sources include: socket strips, reset buttons, complex programmable logic device chips, and power management chips.

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