Processor performance optimization method and device, electronic equipment and storage medium

Abstract

The invention discloses a processor performance optimization method and device, electronic equipment and a storage medium, and can solve the problems that the performance of a processor cannot be analyzed from multiple angles, and the performance of the processor cannot be accurately and effectively optimized. Acquiring real-time operation data of the target processor, wherein the real-time operation data comprises hardware sensing information, software sensing information and load information; multi-dimensional feature extraction is carried out on the operation data to obtain target load features, and the target load features comprise a cache miss rate and / or a branch prediction error rate; determining an optimization strategy corresponding to the target load feature according to the target load feature and a target performance optimization strategy model; the target performance optimization strategy model is obtained through model training in advance; and performing performance optimization on the target processor through the optimization strategy so as to reduce the cache miss rate and / or the branch prediction error rate.

Description

Technical Field

[0001] The present application relates to the field of processor optimization technology, and in particular to a method, device, electronic device, and storage medium for optimizing processor performance. Background Art

[0002] Traditional processor performance optimization relies mostly on manual experience to preset parameters for optimization, which has poor adaptability in scenarios with dynamically changing loads. In addition, most traditional solutions only focus on the impact of PMC events on performance and are unable to analyze processor performance from multiple angles, making it impossible to accurately and effectively optimize processor performance. Summary of the Invention

[0003] The present application provides a processor performance optimization method, device, electronic device and storage medium to at least solve the problem of being unable to analyze processor performance from multiple angles and unable to accurately and effectively optimize processor performance.

[0004] The present application provides a processor performance optimization method, comprising: obtaining real-time operating data of a target processor, the real-time operating data including hardware perception information, software perception information, and load information; Perform multi-dimensional feature extraction on the running data to obtain target load features, which include: cache miss rate and / or branch prediction error rate; Determine the optimization strategy corresponding to the target load characteristics based on the target load characteristics and the target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training; The target processor is optimized for performance through optimization strategies to reduce cache miss rate and / or branch prediction error rate.

[0005] The present application also provides a processor performance optimization device, comprising: an acquisition module, configured to acquire real-time operating data of a target processor, the real-time operating data including hardware perception information, software perception information, and load information; A processing module is used to extract multi-dimensional features from the operating data to obtain target load features, where the target load features include: cache miss rate and / or branch prediction error rate; The processing module is further configured to determine an optimization strategy corresponding to the target load characteristics based on the target load characteristics and the target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training; The processing module is further configured to optimize the performance of the target processor through an optimization strategy, so as to reduce a cache miss rate and / or a branch prediction error rate.

[0006] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned processor performance optimization methods when executing the computer program.

[0007] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned processor performance optimization methods are implemented.

[0008] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned processor performance optimization methods when executed by a processor.

[0009] Through this application, the real-time operation data of the target processor is obtained, and the real-time operation data includes hardware perception information, software perception information and load information; multi-dimensional feature extraction is performed on the operation data to obtain the target load characteristics, and the target load characteristics include: cache miss rate and / or branch prediction error rate; based on the target load characteristics and the target performance optimization strategy model, the optimization strategy corresponding to the target load characteristics is determined; the target performance optimization strategy model is obtained in advance through model training; the performance of the target processor is optimized through the optimization strategy to reduce the cache miss rate and / or branch prediction error rate. In this solution, the operation data of the processor is first obtained from multiple angles, and then the multi-dimensional features are extracted and input into the pre-trained model. In this way, the optimization strategy that best matches the current load operation scenario can be obtained, thereby effectively improving the processor optimization effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 A process for optimizing processor performance provided in this application embodiment Figure 1 ; Figure 2 A process for optimizing processor performance provided in this application embodiment Figure 2 ; Figure 3 A structural diagram of a processor performance optimization device provided in an embodiment of the present application; Figure 4 A structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0013] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0014] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being more preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0015] Traditional methods rely on manual experience to preset compilation parameters (such as -march / -mtune in the GNU Compiler Collection (GCC) that supports multiple languages ​​and cross-platforms), which cannot adapt to changes in dynamic load characteristics. Existing tools (such as perf / Likwid) only collect limited power and platform management controller (PMC) events, and lack the correlation analysis between instruction stream micro-features and system-level behavior. Existing solutions focus more on improving the number of instructions per second (IPS) cycles, ignoring the balance of multiple objectives such as power consumption, temperature, and tail latency. Optimization solutions based on offline analysis take several hours to generate reports and cannot meet real-time tuning requirements. Therefore, it is necessary to address the performance loss caused by hardware resource contention, compilation parameter mismatch, and rigid runtime policies when the processor runs compute-intensive loads such as SPEC CPU.

[0016] In order to solve all or part of the above technical problems, the embodiments of the present application provide a processor performance optimization method, device, electronic device and storage medium, which obtain the real-time operation data of the target processor, and the real-time operation data includes hardware perception information, software perception information and load information; perform multi-dimensional feature extraction on the operation data to obtain the target load characteristics, and the target load characteristics include: cache miss rate and / or branch prediction error rate; determine the optimization strategy corresponding to the target load characteristics according to the target load characteristics and the target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training; optimize the performance of the target processor through the optimization strategy to reduce the cache miss rate and / or branch prediction error rate. In this solution, the operation data of the processor is first obtained from multiple angles, and then the multi-dimensional features are extracted and input into the pre-trained model, so that the optimization strategy that best matches the current load operation scenario can be obtained, thereby effectively improving the processor optimization effect.

[0017] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] like Figure 1 As shown, Figure 1 A flowchart of a method for optimizing processor performance provided in an embodiment of the present application, the method may include the following steps: 101. Obtain real-time operating data of the target processor.

[0019] In an embodiment of the present application, the target processor is a processor that requires performance monitoring and performance optimization. The real-time operation data can specifically include hardware perception information, software perception information and load information. The real-time operation data can specifically constitute a three-dimensional perception matrix.

[0020] In some embodiments, the hardware perception information may specifically include: an event set and an instruction stream quantity heat map. Specifically, preset events may be collected at a preset sampling frequency to obtain an event set; and an instruction stream quantity heat map may be collected through instruction stream sampling technology.

[0021] It should be noted that Intel PT instruction stream sampling technology can be used to deeply mine CPU PMC events at a preset sampling frequency (for example, every 10ms). These events include the triggering of the CPU L1 data cache prefetch (L1D_PREFETCH_TRIGGER) and the execution stall cycles CYCLE_ACTIVITY.STALLS_LDM_PENDING caused by memory load instructions waiting for data. Furthermore, Intel PT (ProcessorTrace) instruction stream sampling technology can be used to capture IPC heat maps at a preset sampling frequency (for example, every 10ms). These IPC heat maps can specifically describe the resource usage of various CPU caches and loads.

[0022] In some embodiments, the software perception information may specifically include: compiler optimization tags and kernel behavior information. Specifically, the system operation file may be parsed to obtain the compiler optimization tags; and the processor operation process may be monitored to obtain the kernel behavior information.

[0023] It's important to note that compiler optimization flags can be dynamically parsed from ELF binary files. ELF is a standard binary file format widely used in Unix-like systems (such as Linux, FreeBSD, and Android) for storing executable programs, object files, shared libraries, and core dump files. This means that the CPU automatically generates and continuously updates these ELF binary files during execution. Compiler optimization flags can be read directly from the ELF binary file, for example, using __attribute__((optimize("O3"))). These compiler optimization flags can be tailored to different compilation priorities and workloads, such as prioritizing energy efficiency, performance, or security redundancy. Furthermore, eBPF can be used to dynamically load and securely execute sandboxed programs to track kernel behavior in real time, including scheduling latency and memory allocation patterns. It also allows for network filtering and performance analysis of kernel behavior. eBPF (extended Berkeley Packet Filter) is a revolutionary technology in the Linux kernel that allows users to run custom programs securely and efficiently in the kernel without modifying kernel code or loading kernel modules.

[0024] In some embodiments, the load information may specifically include: instruction mix variance and cache distribution characteristics. Specifically, the distribution of multiple types of instructions may be calculated to obtain instruction mix variance; and a cache access matrix may be constructed to obtain cache distribution characteristics.

[0025] It should be noted that the IMF technique for analyzing program instruction execution characteristics focuses on the dynamic distribution of different instruction types (such as AVX512 vector instructions, branch instructions, and memory access instructions). The sliding window variance of the instruction type ratio is calculated, thereby obtaining the instruction mixture variance. During CPU operation, many instructions flow simultaneously. To calculate the distribution and dynamic flow of various instruction types, a preset window can be used to slide and calculate the instruction dynamic distribution variance. Furthermore, an L3 cache access pattern matrix can be constructed to identify the cache access patterns of the program during operation, thereby identifying spatial distribution and temporal locality characteristics.

[0026] In some embodiments, the operating data of the target processor may also include other parameters, which are not specifically limited in the embodiments of the present application.

[0027] 102. Perform multi-dimensional feature extraction on the operating data to obtain target load features.

[0028] In an embodiment of the present application, after obtaining the operating data of the target processor, it is necessary to analyze the operating data. In order to improve the comprehensiveness of the processor characteristics, the operating characteristics can be extracted from multiple dimensions to obtain target load characteristics, which include at least: cache miss rate and / or branch prediction error rate.

[0029] It should be noted that the cache miss rate can be used to describe the error rate when the CPU pre-reads data in the cache. That is, when the CPU is running, there are continuous load updates. In order to improve data processing efficiency, the data that may need to be called can be pre-read before the load and placed in the cache. If the load does need to use the pre-read data, then the pre-read is considered correct; if the load does not need to use the pre-read data, then it is considered a pre-read error. The number of pre-read errors is recorded, and the cache miss rate is calculated based on the total number of pre-reads. The cache miss rate can be used to monitor L1 / L2 cache efficiency. A high miss rate requires triggering prefetching or NUMA rebinding. Specifically, it can be combined with the "unit operation cache pre-read error miss count (MPO)" to identify whether the current stage is memory-intensive. The number of misses corresponding to memory-intensive stages is higher, and the corresponding cache miss rate is also higher.

[0030] It should be noted that during CPU operation, multiple processes and instructions may be running simultaneously. Therefore, when data is called, it must flow to the corresponding process or instruction. Each process or instruction can be considered a branch. If the data flow is directed to an incorrect branch, the process or instruction execution may fail. Therefore, the number of branch prediction errors for the data can be counted, and then combined with the total number of branch predictions to calculate the branch prediction error rate. The branch prediction error rate can affect the efficiency of the instruction pipeline. A high error rate requires adjusting the CPU frequency or instruction mix. Frequency adjustment can alleviate pipeline stalls caused by prediction errors.

[0031] It should be noted that the above cache miss rate and / or branch prediction error rate can be calculated by performing feature extraction on the running data.

[0032] In some embodiments, the target load characteristics may also include IPC and instruction mix variance; IPC (instructions per cycle) can reflect the CPU computing efficiency, a high value indicates a computationally intensive stage, and a low value may encounter a memory bottleneck or branch prediction error. Specifically, the IPC value can be obtained through periodic sampling (such as 3 seconds / time) of the Linux kernel tool perf; Instruction Mix Variance quantifies the volatility of the distribution of instruction types (such as integer / floating point / vector instructions), and a high variance indicates that the execution strategy needs to be dynamically adjusted.

[0033] 103. According to the target load characteristics and the target performance optimization strategy model, determine the optimization strategy corresponding to the target load characteristics.

[0034] In an embodiment of the present application, the target performance optimization strategy model is obtained in advance through model training, and the target load characteristics are input into the target performance optimization strategy model to obtain an optimization strategy corresponding to the target load characteristics output by the target performance optimization strategy model. This optimization strategy can be considered to be the strategy with the best performance optimization effect for the target processor in the current scenario.

[0035] 104. Optimize the performance of the target processor through an optimization strategy to reduce a cache miss rate and / or a branch prediction error rate.

[0036] In an embodiment of the present application, after the optimization strategy is determined, the optimization strategy can be executed on the target processor to optimize the performance of the target processor through the optimization strategy, thereby reducing the cache miss rate and / or branch prediction error rate and achieving the effect of performance optimization.

[0037] In an embodiment of the present application, real-time operating data of a target processor is obtained, and the real-time operating data includes hardware perception information, software perception information, and load information; multi-dimensional feature extraction is performed on the operating data to obtain target load features, and the target load features include: cache miss rate and / or branch prediction error rate; based on the target load features and the target performance optimization strategy model, an optimization strategy corresponding to the target load features is determined; the target performance optimization strategy model is obtained in advance through model training; the performance of the target processor is optimized through the optimization strategy to reduce the cache miss rate and / or branch prediction error rate. In this solution, the operating data of the processor is first obtained from multiple angles, and then the multi-dimensional features are extracted and input into the pre-trained model. In this way, the optimization strategy that best matches the current load operating scenario can be obtained, thereby effectively improving the processor optimization effect.

[0038] like Figure 2 As shown, Figure 2 Another flowchart of a method for optimizing processor performance provided in an embodiment of the present application, the method may include the following steps: 201. Obtain real-time operating data of the target processor.

[0039] In the embodiment of the present application, for the description of step 201, please refer to the detailed description of step 101 in the above embodiment, and the embodiment of the present application will not be repeated.

[0040] 202. Feature extraction of running data is performed through a time series convolutional network to obtain time series features.

[0041] In an embodiment of the present application, when extracting features from operating data, it can be done through a neural network model, which can integrate multiple neural network modules, including: Temporal Convolutional Network (TCN), Graph Attention Network (GAT) and Cross Attention layer, etc., through the above-mentioned neural network modules to extract features from operating data from multiple dimensions.

[0042] It should be noted that the time series convolutional network can be mainly used to extract time series features. Therefore, the time series features of the running data can be extracted through the time series convolutional network to obtain time series features.

[0043] Among them, the Temporal Convolutional Network (TCN) is a deep learning model based on the Convolutional Neural Network (CNN) architecture. It is optimized for processing sequential data and achieves efficient time series modeling through causal and dilated convolutions. It has demonstrated superior performance compared to traditional Recurrent Neural Networks (RNNs) in multiple fields. TCN transforms the two-dimensional convolution of traditional CNNs into one-dimensional convolutions, directly operating on time series data. Its core concept is to extract local temporal features by sliding the convolution kernel along the time axis, and to expand the receptive field by stacking layers to capture long-term dependencies. Unlike RNNs, TCNs do not require recursive computation and naturally support parallel training, significantly improving computational efficiency.

[0044] In some embodiments, this can be specifically implemented through the code: self.temporal_conv = TemporalConvNet(input_dim=512), where input_dim=512 indicates that the feature dimension of the input running data is 512.

[0045] In some embodiments, the neural network model may be initialized before feature extraction, which can be achieved through code: class WorkloadClassifier(nn.Module); def __init__(self); """Initialize the neural network model"""; super().__init__().

[0046] 203. Convert the timing features into a graph structure to obtain a program control flow graph.

[0047] In an embodiment of the present application, after obtaining the timing features of the operating data, the graph features can also be extracted. The graph features are reflected by the program control flow graph, so the timing features can be converted into a graph structure to obtain the program control flow graph.

[0048] In some embodiments, converting timing features into a graph structure (such as a program control flow graph (CFG)) requires analyzing the control flow logic in the program and abstracting structures such as basic blocks, branches, and loops into nodes and edges in the graph. A program control flow graph (CFG) includes the concepts of nodes and edges. A node can represent a basic block (a set of instructions executed sequentially with a unique entry and exit (no jumps except the last instruction). Edges can represent control flow transfers (such as branches, jumps, function calls, etc.). Edges include directed edges and special edges. Directed edges indicate the direction of control flow (such as if-else and loops), while special edges include exception handling and function returns.

[0049] The steps of converting timing features into a graph structure may include: extracting basic blocks, constructing control flow edges, and processing special structures. Extracting basic blocks includes: based on the intermediate representation of the program (such as assembly, LLVM IR, source code), identifying continuous instruction sequences until encountering a jump instruction (such as jmp, br), a conditional branch (such as if, switch), or a function call. The last instruction of each basic block determines the subsequent control flow (such as goto target or next instruction). Constructing control flow edges includes: sequential flow, branch flow, loop flow, and function call. Sequential flow refers to when the last instruction of basic block A does not jump, and the edge A → next basic block is added; branch flow refers to conditional branches (such as if (cond) goto L1; else goto L2;): edges A → L1 and A → L2 are added; loop flow refers to loop headers (such as while conditions) that may be pointed to by multiple basic blocks (back edges); explicit calls in function calls include adding call → function entry and function return → post-call instructions. Implicit control flow (such as exceptions) requires additional processing. Handling special structures includes: identifying back edges (edges pointing from the loop body to the loop head) and marking loop structures; unreachable code: deleting basic blocks without predecessors (unless they are entry points); multiple exits: terminating control flow such as return or exit.

[0050] 204. Feature extraction of program control flow graph is performed through graph attention network to obtain graph features.

[0051] In an embodiment of the present application, after obtaining the program control flow graph, the graph features in the program control flow graph can be extracted. Here, a graph attention network can be used to extract features of the program control flow graph to obtain graph features.

[0052] Among them, the graph attention network is a graph neural network model based on the attention mechanism. It aims to capture complex dependencies in graph-structured data by dynamically calculating the attention weights between nodes. It is suitable for tasks such as node classification, link prediction, image segmentation, and recommendation systems. The core idea of ​​GAT is to calculate the attention coefficient at each node to determine the importance between the node and its neighboring nodes. This attention mechanism enables the model to assign different weights to the relationships between different nodes, thereby better capturing the local structure and global information in the graph data. The GAT model usually consists of multiple attention heads, each of which can learn different attention weights, and finally aggregate the outputs of multiple heads. This multi-head attention mechanism helps to improve the representation and generalization capabilities of the model.

[0053] In some embodiments, this can be specifically implemented through the code: self.gnn = GAT(in_features=64, hidden_features=128), indicating that the input feature dimension is 64 and the hidden layer feature dimension is 128.

[0054] 205. The time series features and graph features are fused through the cross attention mechanism to obtain the target load features.

[0055] In an embodiment of the present application, after obtaining the time series features and the graph features, the time series features and the graph features can be fused, which can be achieved through a cross-attention mechanism, so that the target load features are obtained after fusion.

[0056] Among them, the cross-attention mechanism is a variant of the attention mechanism, mainly used to model the interactive relationship between two different sequences or features. It is widely used in natural language processing (NLP), computer vision (CV), and multimodal tasks, and can dynamically capture the dependencies between different inputs. Compared with self-attention, which processes the relationship between elements within a single sequence (such as the encoder in the Transformer), cross-attention can process the relationship between two different sequences (such as combining the encoder output with the current decoder state in the Transformer decoder). The goal of the cross-attention mechanism is to highlight the relevant parts of the two sequences and suppress the irrelevant parts through dynamic weight allocation. You can first prepare the input and obtain sequence A (such as encoder output): shape is (L_A, d_model); sequence B (such as the current state of the decoder): shape is (L_B, d_model); then you can use linear transformation to map the input to the query (Q), key (K), value (V) space: then perform attention weight calculation, calculate the similarity (dot product or scaled dot product) between the query (Q) and the key (K), and obtain the weight matrix α, shape is (L_B, L_A); finally, perform weighted summation, multiply the weight matrix α by the value (V) to get the output.

[0057] In some embodiments, this can be specifically implemented through code: self.fusion_layer = CrossAttention(embed_dim=256); def forward(self, pmc_data, cfg_graph).

[0058] In summary, feature extraction is performed on the operating data to obtain the target load feature, which can be specifically expressed as follows: # Extract time series features; time_feat = self.temporal_conv(pmc_data); # Extract graph structure features; graph_feat = self.gnn(cfg_graph); # Fuse time series and graph features and return the result; return self.fusion_layer(time_feat, graph_feat).

[0059] In an embodiment of the present application, a neural network module is used to extract the timing features and graph features of the operating data respectively, and then fuse them. This allows the operating features of the target processor to be mined from multiple angles, and can better ensure the matching degree of the optimization strategy.

[0060] 206. Obtain running sample data of the sample processor.

[0061] In an embodiment of the present application, in the process of training the target performance optimization strategy model, a large amount of sample data can be obtained first, that is, the running sample data of the sample processor can be obtained. The running sample data can be similar to the running data, including: hardware perception information, software perception information and load information, etc. Here, the sample processor can be a processor that can operate normally. The sample processor can run in various actual scenarios, so that the target performance optimization strategy model obtained by operation has a strong generalization ability.

[0062] 207. The preset model is trained by running sample data to obtain the target performance optimization strategy model.

[0063] In an embodiment of the present application, after obtaining the running sample data, model training can be performed. The preset model is trained by running the sample data, and the model obtained after the training is completed is the target performance optimization strategy model.

[0064] In an embodiment of the present application, pre-training the model with sample operation data can improve the accuracy of the target performance optimization strategy model, and enable the model to conform to multiple scenarios and multiple types of processors, thereby improving generalization capabilities and optimization strategy decision-making capabilities.

[0065] In some embodiments, a preset model is trained by running sample data to obtain a target performance optimization strategy model, which may specifically include: training a preset model by running sample data to obtain a target performance optimization strategy model, which may specifically include: extracting features from the running sample data to obtain target load sample features; optimizing the performance of the sample processor respectively through multiple preset optimization strategies, and recording the sample performance evaluation value of the sample processor corresponding to each optimization strategy; determining the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy; training the preset model through the target load sample features and the sample optimization strategy to obtain a target performance optimization strategy model.

[0066] It should be noted that, since the model will perform feature extraction on the operating data during actual application, and input the features into the target performance optimization strategy model to obtain the output results, the feature extraction can be performed on the operating sample data first to obtain the target load sample features. The process of feature extraction on the operating sample data here is the same as the process of feature extraction on the operating data mentioned above, and will not be repeated here.

[0067] After obtaining the target load sample characteristics including the cache miss rate and / or branch prediction error rate, the sample processor performance can be optimized through multiple optimization strategies, and the sample optimization strategy with the best performance optimization effect on the current sample processor can be selected. The preset model is trained according to the target load sample characteristics and the sample optimization strategy to obtain the target performance optimization strategy model.

[0068] It should be noted that the optimization strategy may include: adjusting CPU frequency (0.1 GHz step), rebinding NUMA nodes, injecting pre-read instructions, adjusting L2 pre-fetch distance and other strategies, and setting different parameter values ​​in each strategy can also be considered as different optimization strategies. After the performance of the sample processor is optimized through multiple optimization strategies, the optimization effect can be evaluated by the sample performance evaluation value. The sample performance evaluation value can be understood as a reward function. The reward function is related to the change in processor speed, power consumption and instruction delay time, and can be specifically expressed by the following formula:

[0069] in, is the sample performance evaluation value, is the processor speed change, is the power consumption change, is the change amount of instruction delay duration, , and are weight values respectively. These weight values can be set and adjusted by oneself. For example: can be related to the current IPC and the target SLA, can be related to the PUE of the computer room and the real-time electricity price, etc.

[0070] In some embodiments, when the target load characteristics can include IPC, cache miss rate, branch prediction error rate, and instruction mix variance, the target load characteristics are optimized by adjusting strategies such as CPU frequency (0.1GHz step), re-binding NUMA nodes, injecting prefetch instructions, and adjusting the L2 prefetch distance. During the optimization process, the numerical value of the sample performance evaluation value is also continuously increasing until it is higher than a certain threshold and gradually stabilizes.

[0071] In the embodiments of the present application, during the model training process, the sample performance evaluation values of each optimization strategy are calculated. The higher the sample performance evaluation value, the better the optimization effect of the processor. Therefore, by using the sample performance evaluation value to select the optimal optimization strategy for model training, the output accuracy of the target performance optimization strategy model and the effectiveness of the target processor performance optimization can be ensured to the greatest extent.

[0072] In some embodiments, the optimization strategy with the highest sample performance evaluation value is determined as the sample optimization strategy. Specifically, it can include: determining the optimization strategy with the highest sample performance evaluation value and the power consumption index not exceeding the preset thermodynamic constraint as the sample optimization strategy.

[0073] When evaluating the performance of the processor, it is also necessary to introduce thermodynamic constraints, that is, there are also certain constraint conditions for thermodynamic parameters such as the temperature and power consumption of the processor. Specifically, the thermodynamic constraint Tjmax = f(Power, CFD heat dissipation coefficient) can be defined, and the CFD heat dissipation coefficient can be a fixed coefficient value. Specifically, Power * CFD heat dissipation coefficient < MaxTJunction, where Power can be understood as the real-time power consumption value, and MaxTJunction can be understood as the maximum power consumption value corresponding to the maximum temperature value. That is to say, during the optimization process of the processor, the maximum power consumption cannot exceed the maximum power consumption value corresponding to the maximum temperature value.

[0074] In the embodiments of the present application, during the model training process, thermodynamic constraints are also considered, that is, when continuously improving the performance of the processor, the numerical values of the thermodynamic parameters are also controlled not to be too high, effectively ensuring the operation safety of the target processor and also improving the output accuracy of the target performance optimization strategy model.

[0075] In some embodiments, the performance of the sample processor is optimized respectively through multiple preset optimization strategies, and the sample performance evaluation value of the sample processor corresponding to each optimization strategy is recorded. Specifically, it may include: optimizing the performance of the sample processor respectively through multiple preset optimization strategies, adjusting the data of each optimization strategy through a nonlinear optimizer, and recording the sample performance evaluation value of the sample processor corresponding to each optimization strategy.

[0076] It should be noted that in the process of optimizing the performance of the sample processor, the specific data of the optimization strategy can also be adjusted by itself. This can be achieved through a nonlinear optimizer that uses an improved multi-objective Bayesian optimization (MOBO) algorithm and a kernel function to adapt to the non-smooth parameter space.

[0077] The Multi-Objective Bayesian Optimization (MOBO) algorithm is an intelligent algorithm for solving multi-objective optimization problems. It combines the Bayesian optimization framework with multi-objective optimization strategies. It can efficiently find a set of Pareto-optimal solutions that balance multiple objectives, even when the objective functions are complex and evaluation is expensive. Bayesian optimization constructs a probabilistic surrogate model of the objective function (such as a Gaussian process) and combines it with acquisition functions (such as expected improvement and upper confidence bounds) to balance exploration and exploitation, gradually approaching the global optimal solution. Its core concept is to use historical observations to update the understanding of the objective function and avoid unnecessary sampling. In multi-objective scenarios, the objective function is expanded from a single value to a vector (e.g., simultaneously optimizing accuracy, computational efficiency, and energy consumption). MOBO addresses trade-offs between objectives rather than a single optimal solution. Its goal is to find a set of Pareto-optimal solutions through iterative sampling—that is, solutions where any objective cannot be improved without compromising other objectives. Through the Pareto frontier and acquisition function, MOBO explicitly addresses trade-offs between objectives, avoiding the subjectivity of manually setting weights and providing more comprehensive optimization results.

[0078] In some embodiments, this can be specifically implemented through code: function [optimal_params] = MOBO_optimize(); bayesopt(@ObjectiveFunction, ParameterSpace; 'AcquisitionFunction','EI'; 'Constraints',constraint; 'KernelFunction','matern52'); End.

[0079] In an embodiment of the present application, by introducing a nonlinear optimizer to perform optimization strategy adjustment, and using an improved MOBO algorithm and kernel function to adapt to the non-smooth parameter space, the data adjustment of the optimization strategy can be made smoother without affecting the normal operation of the processor.

[0080] 208. Determine an optimization strategy corresponding to the target load characteristics based on the target load characteristics and the target performance optimization strategy model.

[0081] 209. Optimize the performance of the target processor through optimization strategies.

[0082] In the embodiment of the present application, for the description of steps 208 to 209, please refer to the detailed description of steps 103 to 104 in the above embodiment, which will not be repeated in the embodiment of the present application.

[0083] 210. Obtain performance evaluation parameters of the target processor in real time.

[0084] In an embodiment of the present application, in the process of optimizing the performance of the target processor through an optimization strategy, the performance evaluation parameters of the target processor can also be detected to determine whether the current optimization strategy is effective. The performance evaluation parameters may include at least: power consumption parameters, computing speed parameters and delay parameters, that is, the current power consumption value, computing speed and delay duration.

[0085] 211. Determine a performance evaluation score of the target processor based on the performance evaluation parameters.

[0086] In the embodiment of the present application, the performance evaluation score here can be understood as the reward function mentioned above, that is:

[0087] in, is the sample performance evaluation value, is the processor speed change, is the power consumption change, is the change in instruction delay time, 、 and are weight values, In other words, the performance evaluation parameters can be collected, and the changes in the performance evaluation parameters can be calculated over a period of time, and then brought into the above reward function to obtain the performance evaluation score R.

[0088] 212. If the performance evaluation score is higher than the preset score, the optimization strategy is determined to be a valid strategy, and the performance of the target processor is continuously optimized through the optimization strategy.

[0089] In an embodiment of the present application, during the process of optimizing the performance of the target processor, theoretically, the performance evaluation score will gradually increase. The higher the performance evaluation score, the better the performance of the target processor. Therefore, a preset score can be set in advance, and the performance evaluation score can be compared with the preset score. If the performance evaluation score is higher than the preset score, it means that the current optimization strategy is effective for the target processor, and then the performance of the target processor can be optimized through the optimization strategy.

[0090] In an embodiment of the present application, during the optimization process of the target processor, the calculated performance evaluation score can be used to determine whether the current optimization strategy is suitable and whether there is a performance optimization effect. This can detect the accuracy of the model output and make corresponding decisions in a timely manner.

[0091] In some embodiments, when obtaining the operating parameters of the target processor, the preset sampling frequency for collecting preset events can be dynamically adjusted, and the preset sampling frequency can be related to the IPC and thermodynamic constraints. If the IPC change is greater than a preset ratio (for example, 5%), then the preset sampling frequency can be 1kHz; if the temperature is greater than the difference between the thermodynamic constraint value and 10°C (i.e., temperature > thermodynamic constraint value - 10°C), then the Turbo frequency reduction detection mode is started; if the IPC change is less than or equal to the preset ratio, and the temperature is less than or equal to the difference between the thermodynamic constraint value and 10°C, then the 200Hz baseline sampling is maintained.

[0092] In some embodiments, during the entire performance optimization process of the target processor, a real-time feedback control loop can be constructed, which is to continuously adjust the optimization strategy through real-time operating parameters, and then evaluate the optimization performance through performance evaluation scores to adjust the optimization strategy again.

[0093] In some embodiments, metadata tags (such as llvm.loop.unroll.disable) are inserted during the compilation phase to describe the cache hit rate; and when L1 cache contention is detected during runtime, optimized code is regenerated through JIT, and runtime characteristics are fed back to the compiler's machine learning optimizer (ML-guided Compiler) to retrain the model.

[0094] In some embodiments, when a high-density floating-point operation event is detected during the startup phase of 503.bwaves_r, the AVX-512 frequency adjustment strategy is activated to avoid frequency reduction due to overheating; and the __builtin_prefetch instruction template is inserted to prefetch the interval adaptively to the data step size.

[0095] In some embodiments, when an L2 cache miss rate > 15% occurs, the L2 prefetcher is adjusted via MSR 0x1A4 (bits 54:55 are set to '10' to enable enhanced mode); and the process core binding policy is dynamically modified to migrate memory-intensive threads to near-memory NUMA nodes.

[0096] In some embodiments, when an instruction mix variance sudden increase (IMF_σ>0.25) is detected, real-time analysis of the control flow graph is triggered to identify hot loop bodies; and a JIT compiler is called to generate SIMD optimized code (using VPMASKMOV instruction).

[0097] In some embodiments, when a policy switching event occurs within 10 ms, the Uncore frequency is adjusted through a WRMSR instruction; and the C-state policy is updated to limit the deepest sleep state to C3.

[0098] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0099] like Figure 3 As shown, an embodiment of the present application further provides a processor performance optimization device, which may include: An acquisition module 301 is configured to acquire real-time operating data of a target processor, where the real-time operating data includes hardware perception information, software perception information, and load information. The processing module 302 is configured to extract multi-dimensional features from the operation data to obtain target load features, where the target load features include: cache miss rate and / or branch prediction error rate; The processing module 302 is further configured to determine an optimization strategy corresponding to the target load characteristics based on the target load characteristics and the target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training; The processing module 302 is further configured to optimize the performance of the target processor through an optimization strategy, so as to reduce a cache miss rate and / or a branch prediction error rate.

[0100] In some embodiments, the acquisition module 301 is further configured to acquire performance evaluation parameters of the target processor in real time, the performance evaluation parameters including at least: power consumption parameters, operation speed parameters, and delay parameters; The processing module 302 is further configured to determine a performance evaluation score of the target processor based on the performance evaluation parameters; The processing module 302 is further configured to determine that the optimization strategy is a valid strategy if the performance evaluation score is higher than a preset score, and to continue to optimize the performance of the target processor using the optimization strategy.

[0101] In some embodiments, the acquisition module 301 is further configured to acquire running sample data of the sample processor; The processing module 302 is further used to train the preset model by running sample data to obtain a target performance optimization strategy model.

[0102] In some embodiments, the processing module 302 is specifically configured to extract features from the running sample data to obtain target load sample features; The processing module 302 is specifically configured to optimize the performance of the sample processors using a plurality of preset optimization strategies, and record the sample performance evaluation value of the sample processor corresponding to each optimization strategy; The processing module 302 is specifically configured to determine the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy; The processing module 302 is specifically used to train the preset model through the target load sample characteristics and the sample optimization strategy to obtain the target performance optimization strategy model.

[0103] In some embodiments, the processing module 302 is specifically configured to determine, as the sample optimization strategy, an optimization strategy with the highest sample performance evaluation value and a power consumption index that does not exceed a preset thermodynamic constraint.

[0104] In some embodiments, the processing module 302 is specifically configured to optimize the performance of the sample processor using multiple preset optimization strategies, adjust the data of each optimization strategy using a nonlinear optimizer, and record the sample performance evaluation value of the sample processor corresponding to each optimization strategy.

[0105] In some embodiments, the processing module 302 is specifically configured to extract features from the operating data using a temporal convolutional network to obtain temporal features; The processing module 302 is specifically configured to convert the timing features into a graph structure to obtain a program control flow graph; Processing module 302 is specifically used to extract features from the program control flow graph through a graph attention network to obtain graph features; The processing module 302 is specifically used to fuse the time series features and the graph features through the cross attention mechanism to obtain the target load features.

[0106] In the embodiments of the present application, the description of the features in the embodiments corresponding to the processor performance optimization device can refer to the relevant description of the embodiments corresponding to the processor performance optimization method, and will not be repeated here.

[0107] like Figure 4As shown, an embodiment of the present application further provides an electronic device, including a memory 401 and a processor 402, wherein the memory 401 stores a computer program, and the processor 402 is configured to run the computer program to execute the steps in any of the above-mentioned processor performance optimization method embodiments.

[0108] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned processor performance optimization method embodiments when running.

[0109] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0110] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned processor performance optimization method embodiments are implemented.

[0111] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned processor performance optimization method embodiments are implemented.

[0112] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0113] The above is a detailed introduction to the process monitoring of a storage system provided by this application. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand the method and core ideas of this application. It should be pointed out that, for those skilled in the art, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A method for optimizing processor performance, characterized in that: The method comprises: Acquiring real-time operating data of a target processor, wherein the real-time operating data includes hardware perception information, software perception information, and load information; Performing multi-dimensional feature extraction on the operating data to obtain target load features, the target load features including: cache miss rate and / or branch prediction error rate; Determining an optimization strategy corresponding to the target load characteristics according to the target load characteristics and the target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training; The target processor is performance optimized by using the optimization strategy to reduce a cache miss rate and / or a branch prediction error rate.

2. The method according to claim 1, characterized in that After optimizing the performance of the target processor using the optimization strategy, the method further includes: Acquiring performance evaluation parameters of the target processor in real time, wherein the performance evaluation parameters include at least: power consumption parameters, operation speed parameters, and delay parameters; Determining a performance evaluation score of the target processor according to the performance evaluation parameters; If the performance evaluation score is higher than a preset score, the optimization strategy is determined to be a valid strategy, and the performance of the target processor is continuously optimized using the optimization strategy.

3. The method according to claim 1, characterized in that Before determining the optimization strategy of the target processor according to the target load characteristics and the target performance optimization strategy model, the method further includes: Obtaining running sample data of the sample processor; The preset model is trained using the running sample data to obtain the target performance optimization strategy model.

4. The method according to claim 3, characterized in that The step of training a preset model using the running sample data to obtain the target performance optimization strategy model includes: Performing feature extraction on the running sample data to obtain target load sample features; Optimizing the performance of the sample processors using a plurality of preset optimization strategies, and recording the sample performance evaluation value of the sample processors corresponding to each optimization strategy; Determine the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy; The preset model is trained using the target load sample characteristics and the sample optimization strategy to obtain the target performance optimization strategy model.

5. The method according to claim 4, characterized in that Determining the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy includes: The optimization strategy with the highest sample performance evaluation value and a power consumption index not exceeding a preset thermodynamic constraint is determined as the sample optimization strategy.

6. The method according to claim 4, characterized in that The performing performance optimization on the sample processors respectively by using a plurality of preset optimization strategies, and recording the sample performance evaluation value of the sample processor corresponding to each optimization strategy, includes: The performance of the sample processor is optimized respectively by using a plurality of preset optimization strategies, the data of each optimization strategy is adjusted by a nonlinear optimizer, and the sample performance evaluation value of the sample processor corresponding to each optimization strategy is recorded.

7. The method according to claim 1, characterized in that The performing multi-dimensional feature extraction on the operating data to obtain target load features includes: Extracting features from the operating data using a temporal convolutional network to obtain temporal features; Converting the timing features into a graph structure to obtain a program control flow graph; Extract features from the program control flow graph through a graph attention network to obtain graph features; The time series features and the graph features are fused through a cross-attention mechanism to obtain the target load features.

8. A processor performance optimization device, characterized in that: The device comprises: An acquisition module is used to acquire real-time operation data of the target processor, wherein the real-time operation data includes hardware perception information, software perception information and load information; a processing module, configured to perform multi-dimensional feature extraction on the operation data to obtain target load features, wherein the target load features include: a cache miss rate and / or a branch prediction error rate; The processing module is further configured to determine an optimization strategy corresponding to the target load characteristics based on the target load characteristics and a target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training; The processing module is further configured to optimize the performance of the target processor using the optimization strategy, so as to reduce a cache miss rate and / or a branch prediction error rate.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the processor performance optimization method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the processor performance optimization method according to any one of claims 1 to 7 are implemented.

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