Chip pin multiplexing control circuit, control method thereof and chip

Abstract

The invention provides a chip pin multiplexing control circuit and a control method thereof, and a chip, the circuit comprises a multiplexing terminal, a chip power supply terminal, a power-on reset controller, a pin signal detector, a voltage detector and a debugging controller, the multiplexing terminal is used for receiving a general function signal and a debugging function signal; the power-on reset controller is used for sending a first enabling control signal to the pin signal detector during power-on; the pin signal detector is used for obtaining an input signal of the multiplexing terminal when enabling is confirmed according to the first enabling control signal, and sending the first control signal to the debugging controller; the voltage detector is used for detecting a voltage signal of a chip power supply terminal and sending a second control signal to the debugging controller; the debugging controller is used for confirming whether to enter a debugging mode according to the first control signal and the second control signal. By applying the chip pin multiplexing control circuit provided by the invention, the waste of chip pin resources can be reduced, and accurate identification of the debugging request signal is ensured.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip pin multiplexing control circuit, a control method for a chip pin multiplexing control circuit using the chip pin multiplexing control circuit, and a chip using the chip pin multiplexing control circuit. Background Art

[0002] In today's chip design and application fields, the rational utilization of chip pin resources and the effective control of debugging functions have always been important issues of great concern. As chip functions become increasingly complex and diverse, the demand for chip pins continues to increase. However, the limitations of chip package size prevent the number of pins from increasing indefinitely, resulting in an increasing shortage of pin resources.

[0003] In traditional chip designs, debug request pins and standard function pins are often independent of each other. While this design approach ensures the stability and independence of debug and standard functions to a certain extent, it significantly wastes valuable pin resources. For example, in some miniaturized chip products, due to the limited number of pins, in order to retain independent debug request pins, some standard functions must be sacrificed, or more complex and expensive packaging must be used to increase the pin count, which undoubtedly increases chip design and production costs.

[0004] Furthermore, during debugging, accurately distinguishing whether a signal applied to a pin is a debug request or a functional communication signal is a challenge. Traditional detection methods are often inaccurate and prone to misjudgment, leading to confusion during the debugging process, impacting debugging efficiency and the proper functioning of the chip. For example, in complex communication environments, fluctuations in the functional communication signal might be misinterpreted as a debug request signal, causing the chip to enter debug mode and disrupting normal communication functions.

[0005] In summary, the existing chip pin design and debugging function control methods have many shortcomings, such as waste of pin resources, inflexible debugging function control, and inaccurate signal detection. A new technical solution is urgently needed to solve these problems. Summary of the Invention

[0006] A first object of the present invention is to provide a control method for a chip pin multiplexing control circuit that reduces chip pin resource waste and ensures accurate recognition of debug request signals.

[0007] A second object of the present invention is to provide a control method for a chip pin multiplexing control circuit that reduces chip pin resource waste and ensures accurate recognition of debug request signals.

[0008] A third object of the present invention is to provide a chip that reduces chip pin resource waste and ensures accurate recognition of debug request signals.

[0009] In order to achieve the above-mentioned first purpose, the chip pin multiplexing control circuit provided by the present invention includes a multiplexing terminal, a chip power terminal, a power-on reset controller, a pin signal detector, a voltage detector and a debug controller, the multiplexing terminal is used to receive general function signals and debug function signals; the power-on reset controller is used to send a first enable control signal to the pin signal detector within a preset time after power-on to control the pin signal detector to be enabled; the pin signal detector is used to obtain the input signal of the multiplexing terminal when enabled, and send the first control signal to the debug controller when the input signal meets the preset debug request signal; the voltage detector is used to detect the voltage signal of the chip power terminal, and send the second control signal to the debug controller when the voltage signal is greater than the preset voltage; the debug controller is used to enter the debug mode when the first control signal and the second control signal are obtained at the same time.

[0010] As can be seen from the above scheme, the chip pin multiplexing control circuit of the present invention can simultaneously receive general function signals and debug function signals by setting a multiplexing terminal. Without increasing the number of chip pins, the same pin can be used as both a debug request function and a normal function pin in normal working mode, which greatly improves the pin utilization rate. At the same time, by setting a pin signal detector to obtain the input signal of the multiplexing terminal and setting a voltage detector to detect the voltage signal of the chip power terminal, it can be used to control whether the debug controller enters the debug mode. Since the signal and voltage in the debug function mode are different from the signal and voltage in the general function mode, this dual judgment mechanism can be used to effectively avoid the occurrence of misjudgment, ensuring the accurate recognition of the debug request signal and the stable operation of the normal function of the chip.

[0011] In a further solution, the chip pin multiplexing control circuit also includes a memory, which is used to store debugging function configuration information, and the debugging function configuration information includes allowing debugging information or turning off debugging information; the debugging controller is also used to obtain the debugging function configuration information, and confirm whether to enter the debugging function based on the debugging function configuration information, the first control signal and the second control signal.

[0012] This shows that in many application scenarios where debugging is not required, the debug request pin and its associated debug detection circuitry remain active. This not only consumes additional power and increases chip power consumption, but can also falsely trigger the debug function due to external interference and other factors, causing the chip to malfunction. Therefore, by obtaining debug function configuration information, it is possible to confirm whether debugging is allowed in the current scenario. In different application scenarios, the debug function can be flexibly and efficiently controlled according to actual needs. In application scenarios where debugging is not required, users can completely disable the debug request detection function, thereby reducing chip power consumption and improving system stability.

[0013] In a further solution, the memory further stores a data valid flag and a data valid flag complement. When the data valid flag is equal to the inverse of the data valid flag complement, the debugging function configuration information is valid.

[0014] As can be seen, by storing the data valid flag and the data valid flag's complement, the debug function configuration only takes effect when the data valid flag is equal to the inverted complement of the data valid flag, ensuring the accuracy of the configuration information. This measure also prevents the random number stored in the memory after manufacturing from being exactly equal to the debug function disabled configuration, preventing the chip from entering the first programming operation.

[0015] In a further solution, the power-on reset controller is further configured to send a second enable control signal to the voltage detector within a preset time period after power-on to control the voltage detector to be enabled.

[0016] It can be seen from this that sending the second enable control signal to the voltage detector within the preset time after power-on can facilitate controlling the working time of the voltage detector and save energy consumption.

[0017] In order to achieve the above-mentioned second purpose, the control method of the chip pin multiplexing control circuit provided by the present invention includes: within a preset time period after power-on, the power-on reset controller sends a first enable control signal to the pin signal detector to control the pin signal detector to be enabled; the pin signal detector obtains the input signal of the multiplexing terminal when enabled, and when the input signal meets the preset debugging request signal, sends the first control signal to the debugging controller; the voltage detector obtains the voltage signal of the chip power terminal, and when the voltage signal is greater than the preset voltage, sends the second control signal to the debugging controller; when the debugging controller obtains the first control signal and the second control signal at the same time, it enters the debugging mode.

[0018] As can be seen from the above scheme, in the control method of the chip pin multiplexing control circuit of the present invention, the power-on reset controller sends a first enable control signal to the pin signal detector after power-on to control its enable, ensuring that the pin signal detector performs signal detection at the appropriate time, and improving the accuracy of debugging request signal recognition. At the same time, the debugging controller must obtain the first control signal and the second control signal at the same time before entering the debugging mode. The first control signal is issued by the pin signal detector when the input signal meets the preset debugging request signal, and the second control signal is issued by the voltage detector when the voltage signal is greater than the preset voltage. This multi-condition judgment method significantly reduces the possibility of false triggering of the debugging mode, ensuring that the debugging mode is entered only when specific conditions are met, thereby accurately identifying the debugging request signal and ensuring the stable operation of the normal functions of the chip.

[0019] In a further solution, when the number of flips of the input signal is greater than a preset number, the preset debugging request signal is satisfied.

[0020] As can be seen, using the number of toggle cycles of the input signal as the basis for determining whether a preset debug request signal is met gives the debug request signal a unique characteristic. Compared to determining a single signal level or a simple signal pattern, the toggle cycle is more discriminative and significantly reduces the possibility of false triggering of the debug mode by external interference signals.

[0021] In a further solution, the chip pin multiplexing control circuit also includes a memory, which is used to store debugging function configuration information, and the debugging function configuration information includes allowing debugging information or turning off debugging information; the method also includes: the debugging controller obtains the debugging function configuration information, and when the debugging function configuration information includes allowing debugging information, and when the first control signal and the second control signal are obtained at the same time, enters the debugging mode.

[0022] As can be seen, the debug controller obtains debug function configuration information and, when the configuration information includes debugging permission information, combines the first control signal and the second control signal to determine whether to enter debug mode. This adds an important basis for determining the debug request signal, making the determination more accurate and reliable. Debug mode is only entered when the configuration information allows debugging, the pin signal detector detects a signal that meets the requirements, and the power supply voltage is normal. This effectively avoids misjudgments and inadvertent entries into debug mode, and improves the accuracy of debug request signal recognition.

[0023] In a further solution, the memory further stores a data valid flag and a data valid flag complement; the method further comprises: when the debug controller confirms that the data valid flag is equal to the inverted complement of the data valid flag, it considers that the debug information is valid.

[0024] As can be seen, by storing the data valid flag and the data valid flag's complement, the debug function configuration only takes effect when the data valid flag is equal to the inverted complement of the data valid flag, ensuring the accuracy of the configuration information. This measure also prevents the random number stored in the memory after manufacturing from being exactly equal to the debug function disabled configuration, preventing the chip from entering the first programming operation.

[0025] In a further solution, after the power-on step, the method further includes: if the input signal obtained within a preset time period does not meet the preset debugging request signal, the power-on reset controller controls the pin signal detector and the voltage detector to be turned off.

[0026] As can be seen, once it is determined that no debug request has been received within the preset time, the pin signal detector and voltage detector are turned off, and the system can quickly switch to normal operation mode, reducing unnecessary waiting time and improving system response speed. This in turn reduces chip power consumption and improves system stability.

[0027] In order to achieve the third object of the present invention, the chip of the present invention includes a chip pin multiplexing control circuit, and the chip pin multiplexing control circuit applies the above-mentioned chip pin multiplexing control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a circuit principle block diagram of a chip embodiment of the present invention.

[0029] Figure 2 It is a flow chart of an embodiment of a control method of a chip pin multiplexing control circuit of the present invention.

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0031] Chip Example:

[0032] like Figure 1As shown, in this embodiment, the chip includes a chip pin multiplexing control circuit. The chip pin multiplexing control circuit includes a multiplexing terminal SDA, a chip power terminal VDD, a power-on reset controller 1, a pin signal detector 2, a voltage detector 3, and a debug controller 4. The multiplexing terminal SDA is used to receive general function signals and debug function signals. The general function signal is determined by the general function required by the multiplexing terminal SDA. The power-on reset controller 1 is used to send a first enable control signal to the pin signal detector 2 and a second enable control signal to the voltage detector 3 within a preset duration after power-on, thereby enabling the pin signal detectors 2 and 3. The preset duration can be pre-set based on experimental data, for example, 1ms. The pin signal detector 2 is used to obtain the input signal from the multiplexing terminal SDA when enabled, and to send a first control signal to the debug controller 4 when the input signal meets a preset debug request signal. The voltage detector 3 is used to detect the voltage signal from the chip power terminal VDD and to send a second control signal to the debug controller 4 when the voltage signal exceeds a preset voltage. The debug controller 4 is used to confirm entry into debug mode upon receiving both the first and second control signals.

[0033] In a preferred embodiment, the power-on reset controller 1 can be set with a timer. After power-on, the power-on reset controller 1 sends a first enable control signal to the pin signal detector 2 and a second enable control signal to the voltage detector 3, and starts the timer at the same time. After the timer overflows the preset time, the power-on reset controller 1 turns off the pin signal detector 2 and the voltage detector 3.

[0034] In this embodiment, the chip pin multiplexing control circuit also includes a memory 5, which is used to store debugging function configuration information. The debugging function configuration information includes information for allowing debugging or disabling debugging. The debugging controller 4 is also used to obtain the debugging function configuration information and confirm whether to enter the debugging function based on the debugging function configuration information, the first control signal, and the second control signal. In many application scenarios where the debugging function is not required, the debugging request pin and its related debugging detection circuit are still in a working state, which not only consumes additional power and increases the power consumption of the chip, but may also mistakenly trigger the debugging function due to factors such as external interference, causing abnormal chip operation. Therefore, by obtaining the debugging function configuration information, it is possible to confirm whether debugging is allowed in the current scenario, and flexibly and efficiently control the debugging function according to actual needs. In application scenarios where the debugging function is not required, the user can completely turn off the debugging request detection function, thereby reducing the power consumption of the chip and improving the stability of the system.

[0035] Memory 5 also stores a data valid flag and its complement. When the data valid flag equals the inverse of the data valid flag's complement, the debug function configuration information becomes valid. The data valid flag and its complement can be set as needed. For example, the data valid flag can be 0x66 and the data valid flag's complement can be 0x99. By storing the data valid flag and its complement, the debug function configuration only takes effect when the data valid flag equals the inverse of the data valid flag's complement, ensuring the accuracy of the configuration information. This measure also prevents the random number in memory 5 after manufacturing from being exactly equal to the debug function disable configuration, preventing the chip from entering the first programming operation.

[0036] In order to better illustrate the present invention, a control method of a chip pin multiplexing control circuit is described below.

[0037] See also Figure 2 In this embodiment, the control method for the chip pin multiplexing control circuit, when in operation, first executes step S1. Within a preset time period after power-on, the power-on reset controller 1 sends a first enable control signal to the pin signal detector 2 and a second enable control signal to the voltage detector 3 to enable the pin signal detector 2 and the voltage detector 3. After the chip is powered on, the power-on reset controller 1 operates and sends the first enable control signal to the pin signal detector 2 to enable the pin signal detector 2. At the same time, it sends the second enable control signal to the voltage detector 3 to enable the voltage detector 3.

[0038] After the pin signal detector 2 is enabled, step S2 is executed, in which the pin signal detector 2 obtains the input signal of the multiplex terminal SDA. In order to confirm the type of the signal input by the multiplex terminal SDA, the pin signal detector 2 needs to obtain the input signal of the multiplex terminal SDA.

[0039] After obtaining the input signal of the multiplexed terminal SDA, step S3 is executed to determine whether the input signal meets the preset debugging request signal. The preset debugging request signal can be set accordingly according to the debugging function. In this embodiment, when the number of flips of the input signal is greater than the preset number, the preset debugging request signal is met. The preset number can be pre-set based on experimental data. Using the number of flips of the input signal as the basis for judging whether the preset debugging request signal is met gives the debugging request signal a unique feature. Compared with a single signal level or a simple signal mode judgment, the judgment of the number of flips is more recognizable, which greatly reduces the possibility of external interference signals falsely triggering the debugging mode.

[0040] If the input signal does not meet the preset debug request signal, step S10 is executed, and the power-on reset controller 1 controls the pin signal detector 2 and voltage detector 3 to be turned off. Once it is determined that no debug request has been received within the preset time period, the pin signal detector 2 and voltage detector 3 are turned off, and the system can quickly switch to the general function mode, reducing unnecessary waiting time and improving the system's response speed. At the same time, the detection circuit related to entering the debug mode is turned off, thereby reducing the chip's power consumption and improving the system's stability. The general function mode can be set as needed. After entering the general function mode, the system identifies the input signal based on the general function mode and performs the corresponding operation.

[0041] When the input signal satisfies the preset debugging request signal, step S4 is executed to send a first control signal to the debugging controller 4. If the input signal satisfies the preset debugging request signal, it means that the input signal can be preliminarily considered to be a debugging request signal. Therefore, the first control signal can be sent to the debugging controller 4 for further determination.

[0042] After voltage detector 3 is enabled, step S5 is executed, where voltage detector 3 obtains the voltage signal of chip power supply terminal VDD. Because the signal and voltage in debug mode differ from those in general mode, to avoid false positives and improve the accuracy of debug mode entry detection, it is necessary to combine the input signal of pin signal detector 2 with the voltage signal of chip power supply terminal VDD to make a judgment.

[0043] After obtaining the voltage signal of the chip power supply terminal VDD, step S6 is executed to determine whether the voltage signal is greater than a preset voltage. The preset voltage can be determined based on the voltages corresponding to the debug function mode and the general function mode. For example, if the voltage corresponding to the debug function mode is 5V and the voltage corresponding to the general function mode is 3.3V, the detection threshold of the voltage detector 3 is selected to be a voltage value between 3.3V and 5V that is easily distinguishable, such as a voltage value between 4V and 5V.

[0044] If the voltage signal is less than or equal to the preset voltage, step S10 is executed, and the power-on reset controller 1 controls the pin signal detector 2 and voltage detector 3 to be turned off. If the voltage signal is less than or equal to the preset voltage, it means that the voltage does not meet the debugging function requirements. Therefore, the power-on reset controller 1 controls the pin signal detector 2 and voltage detector 3 to be turned off, and the system enters the general function mode.

[0045] When the voltage signal is greater than the preset voltage, step S7 is executed to send a second control signal to the debugging controller 4. If the voltage signal is greater than the preset voltage, it means that the voltage meets the debugging function requirements and the debugging mode can be entered. Therefore, the second control signal is sent to the debugging controller 4 for further determination.

[0046] After sending the second control signal to debug controller 4, step S8 is executed to determine whether the debug function configuration information includes debugging permission information. To ensure more accurate and reliable judgment of the conditions for entering debug mode, debug controller 4 retrieves the debug function configuration information from memory 5 to confirm whether debugging permission information exists. For example, if the debugging permission information stored in memory 5 is 0xA5, when debug controller 4 retrieves this information, it confirms that the debug function configuration information includes debugging permission information.

[0047] In this embodiment, when the debug controller 4 retrieves the debug function configuration information from the memory 5, it also retrieves the data valid flag and the data valid flag complement stored in the memory 5. When the debug controller 4 confirms that the data valid flag is equal to the inverse of the data valid flag complement, it deems the debug information valid. By storing the data valid flag and the data valid flag complement, the debug function disable configuration only takes effect when the data valid flag is equal to the inverse of the data valid flag complement, thus ensuring the accuracy of the configuration information. This measure also prevents the random number in the memory 5 after manufacturing from being exactly equal to the debug function disable configuration, preventing the chip from entering the first programming operation.

[0048] If the debugging function configuration information does not include debugging permission information, step S10 is executed, and the power-on reset controller 1 controls the pin signal detector 2 and the voltage detector 3 to be turned off. If the debugging function configuration information does not include debugging permission information, it means that debugging is not allowed. Therefore, the power-on reset controller 1 can control the pin signal detector 2 and the voltage detector 3 to be turned off, and the system enters the general function mode.

[0049] If the debug function configuration information includes debugging permission, step S9 is executed to enter debug mode. If the debug function configuration information includes debugging permission and the first control signal and the second control signal are simultaneously received, debug mode can be entered. Therefore, debug controller 4 will take control of other modules within the chip and perform various debugging actions. For example, it can pause the operation of certain functional modules within the chip and read or modify the values ​​of specific registers to facilitate developers in troubleshooting chip operation.

[0050] Debug controller 4 obtains debug function configuration information and, if the configuration information includes debugging permission information, combines the first control signal and the second control signal to determine whether to enter debug mode. This adds an important basis for determining the debug request signal, making the determination more accurate and reliable. Debug mode is entered only when the configuration information allows debugging, the pin signal detector 2 detects a signal that meets the requirements, and the power supply voltage meets the debug function voltage. This effectively avoids misjudgments and inadvertent entries into debug mode, and improves the accuracy of debug request signal recognition.

[0051] As can be seen from the above, the chip pin multiplexing control circuit of the present invention, by providing a multiplexing terminal SDA, can simultaneously receive general function signals and debug function signals. Without increasing the number of chip pins, the same pin can perform both debug request functions and be used as a normal function pin in normal operation mode, greatly improving pin utilization. Furthermore, by providing a pin signal detector 2 to obtain the input signal of the multiplexing terminal SDA and a voltage detector 3 to detect the voltage signal of the chip power supply terminal VDD, it can be used to control whether the debug controller 4 enters debug mode. Because the signal and voltage in debug mode are different from those in general function mode, this dual judgment mechanism can effectively avoid the occurrence of misjudgments, ensuring accurate recognition of debug request signals and stable operation of normal chip functions. Furthermore, in the control method of the chip pin multiplexing control circuit of the present invention, the power-on reset controller 1 sends a first enable control signal to the pin signal detector 2 after power-on to control its enablement, ensuring that the pin signal detector 2 performs signal detection at the appropriate time, thereby improving the accuracy of debug request signal recognition. Furthermore, the debug controller 4 must simultaneously receive the first control signal and the second control signal to enter debug mode. The first control signal is issued by pin signal detector 2 when the input signal meets the preset debug request signal, and the second control signal is issued by voltage detector 3 when the voltage signal exceeds the preset voltage. This multi-condition judgment method significantly reduces the possibility of false triggering of debug mode, ensuring that debug mode is entered only when specific conditions are met, thereby accurately identifying debug request signals and ensuring the stable operation of normal chip functions.

[0052] It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept also fall within the scope of protection of the present invention.

Claims

1. A chip pin multiplexing control circuit, characterized in that: It includes a multiplexing terminal, a chip power terminal, a power-on reset controller, a pin signal detector, a voltage detector and a debug controller. The multiplexing terminal is used to receive general function signals and debug function signals; The power-on reset controller is used to send a first enable control signal to the pin signal detector within a preset time period after power-on to control the pin signal detector to be enabled; The pin signal detector is used to obtain the input signal of the multiplexing terminal when enabled, and send a first control signal to the debugging controller when the input signal meets the preset debugging request signal; The voltage detector is used to detect the voltage signal of the chip power terminal and send a second control signal to the debug controller when the voltage signal is greater than a preset voltage; The debugging controller is configured to enter a debugging mode when the first control signal and the second control signal are obtained simultaneously.

2. The chip pin multiplexing control circuit according to claim 1, characterized in that: The chip pin multiplexing control circuit further includes a memory, wherein the memory is used to store debugging function configuration information, wherein the debugging function configuration information includes enabling debugging information or disabling debugging information; The debugging controller is further configured to obtain the debugging function configuration information, and determine whether to enter the debugging function according to the debugging function configuration information, the first control signal, and the second control signal.

3. The chip pin multiplexing control circuit according to claim 2, characterized in that: The memory further stores a data valid flag and a data valid flag complement. When the data valid flag is equal to the inverse of the data valid flag complement, the debugging function configuration information is valid.

4. The chip pin multiplexing control circuit according to any one of claims 1 to 3, characterized in that: The power-on reset controller is further configured to send a second enable control signal to the voltage detector within the preset time period after power-on to control the voltage detector to be enabled.

5. A control method for a chip pin multiplexing control circuit, applied to a chip pin multiplexing control circuit, characterized in that: The chip pin multiplexing control circuit includes a multiplexing terminal, a chip power terminal, a power-on reset controller, a pin signal detector, a voltage detector and a debug controller, wherein the multiplexing terminal is used to receive a general function signal and a debug function signal; The method comprises: Within a preset time period after power-on, the power-on reset controller sends a first enable control signal to the pin signal detector to control the pin signal detector to be enabled; The pin signal detector acquires the input signal of the multiplexing terminal when enabled, and sends a first control signal to the debugging controller when the input signal meets a preset debugging request signal; The voltage detector acquires a voltage signal of the chip power terminal, and sends a second control signal to the debug controller when the voltage signal is greater than a preset voltage; The debugging controller enters a debugging mode when simultaneously acquiring the first control signal and the second control signal.

6. The control method of the chip pin multiplexing control circuit according to claim 5, characterized in that: When the number of flips of the input signal is greater than a preset number, the preset debugging request signal is satisfied.

7. The control method of the chip pin multiplexing control circuit according to claim 5 or 6, characterized in that: The chip pin multiplexing control circuit further includes a memory, wherein the memory is used to store debugging function configuration information, wherein the debugging function configuration information includes enabling debugging information or disabling debugging information; The method further comprises: The debugging controller obtains the debugging function configuration information, and enters a debugging mode when the debugging function configuration information includes the debugging permission information and the first control signal and the second control signal are obtained at the same time.

8. The control method of the chip pin multiplexing control circuit according to claim 7, characterized in that: The memory also stores a data valid flag and a data valid flag complement; The method further comprises: When the debug controller confirms that the data valid flag is equal to the inverse of the complement of the data valid flag, it is considered that the debug permission information is valid.

9. The control method of the chip pin multiplexing control circuit according to claim 5 or 6, characterized in that: After the power-on step, it also includes: If the input signal obtained within a preset time period does not meet the preset debugging request signal, the power-on reset controller controls the pin signal detector and the voltage detector to be turned off.

10. A chip, comprising a chip pin multiplexing control circuit, characterized in that: The chip pin multiplexing control circuit applies the chip pin multiplexing control circuit according to any one of claims 1 to 4.

Images