Semiconductor module packaging structure and semiconductor module packaging method

Abstract

The invention provides a semiconductor module packaging structure and a semiconductor module packaging method. The semiconductor module packaging structure comprises a first substrate, a second substrate and a metal shell, the first substrate comprises a first surface and a second surface which are opposite to each other, the second substrate comprises a third surface and a fourth surface which are opposite to each other, the fourth surface is recessed towards the third surface to form a groove, and the non-recessed part of the fourth surface is electrically connected with the first surface. The structure that the first substrate and the second substrate are directly interconnected replaces a traditional copper column interconnection structure, and the problems that in the prior art, a longitudinally-stacked semiconductor packaging structure is low in reliability, high in parasitic parameter and high in thermal resistance are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor module packaging structure and a semiconductor module packaging method. Background Art

[0002] Existing vertical stacking semiconductor packaging technology significantly improves device density and performance by vertically integrating multiple layers of chips or wafers, becoming a key technology in the fields of power modules, high-performance computing and memory.

[0003] As one of the mainstream interconnect structures in vertically stacked semiconductor packages, copper pillars are widely used in advanced packaging scenarios requiring high-density, high-reliability interconnects. However, when the thermal expansion coefficients of copper pillars and the substrate material do not match, they become less stable and susceptible to damage. This not only reduces the reliability of vertically stacked semiconductor packaging structures but also poses the risk of elevated parasitic parameters. Furthermore, the limitations of the copper pillars' inherent thermal conduction paths or interfacial thermal resistance issues can adversely affect heat dissipation efficiency. Summary of the Invention

[0004] In response to the deficiencies in the prior art, the present invention provides a semiconductor module packaging structure and a semiconductor module packaging method, which solve the problems in the prior art of low reliability of the longitudinally stacked semiconductor packaging structure and the risks of high parasitic parameters and high thermal resistance.

[0005] According to an embodiment of the present invention, a first aspect provides a semiconductor module packaging structure, including: A first substrate comprising a first surface and a second surface opposite to each other, wherein the first surface is provided with first bonding fingers; a second substrate comprising a third surface and a fourth surface opposite to each other, the fourth surface being recessed toward the third surface to form a groove, the unrecessed portion of the fourth surface being electrically connected to the first surface to form a front-to-back connected cavity, the third surface being provided with a second bonding finger; wherein the fourth surface is adjacent to the first surface, and the third surface is distal to the first surface; a metal housing having a cavity for accommodating the first substrate and the second substrate, the first substrate being mounted within the cavity, the second surface being in contact with the bottom of the metal housing, two opposing side walls of the metal housing each having an external pin, the second bonding finger being further connected to the external pin via a bonding wire; and the other two opposing side walls of the metal housing facing the front-to-back connected cavity; The first substrate is used to set a target unit that implements the same function in the target semiconductor module, and the second substrate is used to set a target unit that implements another same function in the target semiconductor module, wherein the target unit set on the first surface is electrically connected to the first bonding finger through a bonding wire, and the target unit set on the third surface is electrically connected to the second bonding finger through a bonding wire.

[0006] A second aspect provides a semiconductor module packaging method, using the semiconductor module packaging structure described above, comprising: Decomposing the target semiconductor module into modules to obtain a target unit that realizes one identical function and a target unit that realizes another identical function; A target unit realizing one identical function is arranged on a first substrate, and a target unit realizing another identical function is arranged on a second substrate.

[0007] Compared with the prior art, the present invention has the following beneficial effects: a new second substrate structure is proposed, wherein the non-recessed portion of the fourth surface of the second substrate is electrically connected to the first surface of the first substrate. This structure in which the first substrate and the second substrate are directly interconnected replaces the traditional copper pillar interconnection structure, and there is no need to consider the thermal expansion coefficients between multiple materials, thereby improving the reliability of the semiconductor module packaging structure. At the same time, a structure is formed in which the first substrate and the second substrate are interconnected and stacked longitudinally with the metal shell, which greatly improves the integration density. The target units that implement the same function in the target semiconductor module are arranged on the same substrate, and the functional division is clearer, which facilitates effectiveness testing and debugging. In addition, this three-dimensional, multi-faceted, cavity-containing structure can achieve gradient heat dissipation, reduce module thermal resistance, and effectively reduce parasitic parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a semiconductor module packaging structure according to an embodiment of the present invention; Figure 2 is a schematic diagram of a semiconductor module packaging structure according to an embodiment of the present invention; Figure 3 is a schematic diagram of a semiconductor module packaging structure according to an embodiment of the present invention; Figure 4 is a schematic diagram of a semiconductor module packaging structure according to an embodiment of the present invention; Figure 5 Schematic diagram of the implementation process of the semiconductor module packaging method according to an embodiment of the present invention; Figure 6 A layout diagram of a GaN power module on a first surface of a first substrate according to an embodiment of the present invention; Figure 7 Schematic diagram of the layout of the GaN power module on the third surface of the second substrate according to an embodiment of the present invention; Figure 8 FIG. 4 is a layout diagram of a GaN power module on the fourth surface of the second substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0010] like Figure 1 As shown, an embodiment of the present invention provides a semiconductor module packaging structure, including a first substrate 10, a second substrate 20 and a metal shell 30, wherein the first substrate 10 includes a first surface m1 and a second surface m2 opposite to each other, and the first surface m1 is provided with a first bonding finger 11; the second substrate 20 includes a third surface m3 and a fourth surface m4 opposite to each other, the fourth surface m4 is recessed toward the third surface m3 to form a groove 40, and the non-recessed portion m41 of the fourth surface m4 is electrically connected to the first surface m1 to form a cavity connected front to back, and the third surface m3 is provided with a second bonding finger 21; the metal shell 30 has a cavity for accommodating the first substrate 10 and the second substrate 20, the first substrate 10 is installed in the cavity, and the second surface m2 is in contact with the bottom 31 of the metal shell 30, and two opposite side walls of the metal shell 30, such as the side wall 32 and the side wall 33, are respectively provided with an external pin 34, and the second bonding finger 21 on the second substrate 20 is also connected to the external pin 34 through a bonding wire; the other two opposite side walls of the metal shell 30 ( Figure 1 (not shown) is facing the cavity connected front and back.

[0011] The detailed working process of the embodiment of the present invention is as follows: when the target semiconductor module is packaged by the above-mentioned semiconductor module packaging structure, the target units with the same function in the target semiconductor module are arranged on the first substrate 10 or the second substrate 20. Since the second surface is in contact with the bottom 31 of the metal shell 30, the target units with the same function in the target semiconductor module can be arranged on the first surface, the third surface and the fourth surface, or on the first surface and the third surface. The target unit 51 arranged on the first surface m1 is electrically connected to the first bonding finger 11 through a bonding wire, and the target unit 52 arranged on the third surface m3 is electrically connected to the second bonding finger 21 through a bonding wire, thereby constructing an electrical interconnection path between the internal circuit of the module and the external system.

[0012] The embodiment of the present invention proposes a new structure for the second substrate 20, wherein the non-recessed portion m41 of the fourth surface m4 in the second substrate 20 is electrically connected to the first surface m1 in the first substrate 10. This structure in which the first substrate 10 and the second substrate 20 are directly interconnected replaces the traditional copper pillar interconnection structure, eliminating the need to consider the thermal expansion coefficients between multiple materials, thereby improving the reliability of the semiconductor module packaging structure. At the same time, a structure is formed in which the first substrate 10 and the second substrate 20 are interconnected and stacked vertically with the metal housing 30, greatly improving the integration density. Furthermore, the target units that implement the same function in the target semiconductor module are arranged on the same substrate, resulting in a clearer functional division and easier effectiveness testing and debugging. Furthermore, this three-dimensional, multi-faceted, cavity-containing structure can achieve gradient heat dissipation, reduce module thermal resistance, and effectively reduce parasitic parameters.

[0013] like Figure 1 As shown, a target unit that performs the same function, such as target unit 51, is disposed on the first surface m1. A target unit that performs another function, such as target unit 52, is disposed on both the third surface m3 and the fourth surface m4, and is disposed in a recessed portion of the fourth surface m4. In a preferred implementation, the target unit that performs the other function is disposed in the recessed portion of the fourth surface and the third surface, further improving the integration density to 200%.

[0014] See also Figure 1 , the fourth surface m4 of the second substrate 20 is recessed toward the third surface m3 to form a groove 40. In one implementation, as Figure 1 As shown, the shape of the groove 40 is rectangular. In practical applications, when manufacturing the second substrate 20, a portion of the groove can be hollowed out by milling to form a Figure 1 The left vertical sidewall 41 and right vertical sidewall 42 of the rectangular groove 40 are shown. The groove 40 is rectangular in shape, and the upper and lower cross-sectional dimensions of the left and right vertical sidewalls 41 and 42 are identical. This provides a more reliable structure for the interconnected first and second substrates 10 and 20, and for longitudinally stacking the metal housing 30, thereby resisting adverse effects such as cyclic stress and thermomechanical fatigue. It is understood that the upper ends of the left and right vertical sidewalls are located closer to the second substrate 20, while the lower ends of the left and right vertical sidewalls are located closer to the first substrate 10.

[0015] In another implementation, Figure 2 As shown, the shape of the groove 40 is trapezoidal. In practical applications, when manufacturing the second substrate 20, a part of the groove can be hollowed out by milling to form a groove. Figure 2The left trapezoidal side wall 41' and the right trapezoidal side wall 42' are based on the trapezoidal groove 40. The groove 40 is trapezoidal in shape, so the left side wall is the left trapezoidal side wall 41', and the right side wall is the right trapezoidal side wall 42'. The upper and lower ends of the left side wall have different cross-sectional sizes, and the upper and lower ends of the right side wall have different cross-sectional sizes. This makes the structure of the first substrate 10 and the second substrate 20 interconnected and stacked vertically with the metal housing 30 more stable. It can be understood that the upper end of the left trapezoidal side wall 41' and the right trapezoidal side wall 42' is the end close to the second substrate 20, and the lower end of the left trapezoidal side wall 41' and the right trapezoidal side wall 42' is the end close to the first substrate 10, and according to the remaining layout area of ​​the first substrate 10 and the second substrate 20, the cross-sectional size of the upper end of the left trapezoidal side wall and the right trapezoidal side wall can be selected to be greater than the cross-sectional size of the lower end of the left trapezoidal side wall and the right trapezoidal side wall, or the cross-sectional size of the upper end of the left trapezoidal side wall and the right trapezoidal side wall can be selected to be less than the cross-sectional size of the lower end of the left trapezoidal side wall and the right trapezoidal side wall.

[0016] See also Figure 1 and Figure 2 , shows an implementation structure of a metal housing 30 in a semiconductor module packaging structure. The bottom 31 of the metal housing 30 further includes an extension 35. The extension 35 is formed by connecting the bottom 31 of the metal housing 30 with two opposing sidewalls of the metal housing 30, such as sidewalls 32 and 33, and extending away from the two opposing sidewalls by a predetermined length. This allows for rapid heat dissipation by utilizing the large metal area of ​​the bottom 31 of the metal housing 30. In a preferred implementation, target units can be ranked by heat dissipation requirement, such that the target units with the highest heat dissipation requirement are positioned on the first surface m1. The target units with the highest heat dissipation requirement, the first substrate 10, and the bottom 31 of the metal housing 30 then form a gradient heat dissipation design, maximizing heat dissipation structurally. Exemplarily, ranking the heat dissipation requirement of the target units includes calculating the heat dissipation requirement based on the power processing capacity and operating power consumption of the target units. The calculation results are used to quantify the heat dissipation requirement of each target unit, thereby determining whether the heat dissipation requirement of a target unit implementing the same function is higher than that of another target unit implementing the same function based on the calculation results.

[0017] See also Figures 1 to 3 , the detailed structure of the metal shell 30 in the semiconductor module packaging structure is described. Figure 1 and Figure 2 As shown, a detailed structure further includes a metal cover plate 36, which is sealed to the top of the metal shell 30 by parallel seam welding, so as to adapt to high-frequency application scenarios. Figure 3 As shown in a detailed structure, a surface of the extension portion 35 close to the outer pin 34 is provided with a package pin 61 and a mounting hole 62. Figure 3 As shown in a detailed structure, the external pin 34 includes a connection portion located in the inner cavity of the metal shell 30 and a heat dissipation portion exposed from the inner cavity of the metal shell 30. Figure 3 It is also shown that the portion of the external pin 34 in the inner cavity of the metal shell 30 is a bonding finger structure. Figure 3 In FIG. 1 , A is a schematic diagram of the positions of the interconnected first substrate 10 and the second substrate 20 in the inner cavity of the metal shell 30 , projected on the bottom 31 of the metal shell 30 .

[0018] It is understandable that if Figures 1 to 3 As shown, the metal cover plate 36 , the extension portion 35 and the external pins 34 can be simultaneously implemented in the metal housing 30 of the semiconductor module packaging structure.

[0019] In one embodiment, the electrical connection method of the semiconductor module packaging structure is further defined. The solder used to attach the target unit to the first and second substrates 10 and 20, the solder used to bond the second surface m2 to the bottom 31 of the metal housing 30, and the solder used to electrically connect the unrecessed portion m41 of the fourth surface m4 to the first surface m1 are all different. For example, the solder used to attach the target unit to the first and second substrates 10 and 20 is solder paste. Based on this, the target unit is mounted to the first and second substrates 10 and 20 by applying solder paste and reflowing. The solder used to bond the second surface m2 to the bottom 31 of the metal housing 30 is a gold-tin solder sheet. Based on this, the first substrate 10 is mounted within the inner cavity of the metal housing via the gold-tin solder sheet. The solder used to electrically connect the unrecessed portion m41 of the fourth surface m4 to the first surface m1 is another solder paste with better electrical connection performance. Based on this, applying solder paste to the unrecessed portion m41 of the fourth surface m4 achieves vertical interconnection between the first and second substrates 10 and 20.

[0020] Another embodiment of the present invention further provides a semiconductor module packaging structure, based on Figure 1 The three-dimensional, multi-faceted, cavity-containing semiconductor packaging structure shown continues to optimize and realize the three-dimensional, multi-faceted, multi-cavity semiconductor packaging structure, thereby achieving a higher integration density, and is not limited to the integration density of 200% mentioned in the above embodiment.

[0021] like Figure 4 As shown, another embodiment of the present invention provides a semiconductor module packaging structure, comprising a plurality of second substrates, and the structure of the first substrate is the same as Figures 1 to 3The same as shown, a target unit for realizing the same function, such as target unit 51, 51 is arranged on the first surface m(1), and the second surface m(2) is attached to the bottom 31 of the metal shell 30. Other structures are not described here. Among them, the first second substrate 20(1) includes a third surface m(3) and a fourth surface m(4) opposite to each other, the fourth surface m(4) is recessed toward the third surface m(3) to form a groove 40(1), the non-recessed portion m(41) of the fourth surface m(4) is electrically connected to the first surface m(1), and the third surface m(3) is provided with a second bonding finger 21(1); another target unit for realizing the same function, such as target unit 52, 52 is arranged on the third surface m(3) and the fourth surface m(4). The n+1th second substrate 20(n+1) includes an n+4th surface m(n+4) and an n+5th surface m(n+5) facing each other. The n+4th surface m(n+4) is provided with an n+2th functional chip and an n+2th bonding finger 21(n+1). The n+2th functional chip is electrically connected to an n+2th bonding finger 21(n+1) through a bonding wire. The n+5th surface m(n+5) is recessed toward the n+4th surface m(n+4) to form a After the n+5th surface is recessed, the unrecessed portion m(k1), k=(n+5), of the n+5th surface m(n+5) is electrically connected to the n+2th surface m(n+2). The recessed portion of the n+5th surface m(n+5) is provided with the n+2th peripheral resistor and capacitor. The n+5th surface m(n+5) is adjacent to the n+2th surface m(n+2), and the n+4th surface m(n+4) is away from the n+2th surface m(n+2). N is a positive integer greater than or equal to 1, n+1≤N, and the N second substrates are all used to provide target units implementing the same function in the target semiconductor module.

[0022] It should be noted that, structurally, if only one second substrate is included, the second bonding finger of the first second substrate is still connected to the external pin 34 through a bonding wire. If at least two second substrates are included, the second bonding finger of the first second substrate is not connected to the external pin 34 through a bonding wire, but the bonding finger of the last second substrate is connected to the external pin 34 through a bonding wire. Figure 4 In the example, the last bonding finger of the second substrate is connected to the external lead 34 through a bonding wire.

[0023] In specific applications, the target semiconductor module usually integrates multiple chips with complementary functions, so the target semiconductor module may include target units that implement multiple functions. In this case, the above-mentioned Figure 4 The semiconductor module packaging structure shown in FIG. 1 is a semiconductor module packaging structure, and on the first substrate and the second substrate, the first substrate is used to set a target unit of one function, and Figures 1 to 3The same as shown, and the N second substrates are all used to set target units that implement the same function in the target semiconductor module. Among them, the N second substrates are all used to set target units that implement the same function in the target semiconductor module means that: the first second substrate is used to set a target unit that implements another function, and the second second substrate and the remaining multiple second substrates can be the same as the first second substrate and used to set a target unit that implements another function, or can be different from the first second substrate and used to set a target unit that implements another function or multiple functions, which is not limited in the embodiments of the present invention.

[0024] In a preferred implementation, the two opposing surfaces of the second substrate are interconnected through pre-set vias. Exemplarily, if only one second substrate is included, the third surface and the fourth surface of the second substrate are interconnected through pre-set vias. If multiple second substrates are included, the two opposing surfaces of each second substrate, such as the n+4th surface and the n+5th surface, are interconnected through pre-set vias. The pre-set vias refer to the number and positions of the vias designed in advance based on the target units to be set on the second substrate. It is understandable that when multiple second substrates are included, the number and positions of the pre-set vias on each second substrate are different, and are not limited here.

[0025] In a preferred implementation, target units that achieve the same function are disposed on the recessed portion of each (n+5)th surface and each (n+4)th surface. That is, in a preferred solution, target units are disposed on both opposing surfaces of each second substrate, rather than on only one surface of the second substrate.

[0026] For ease of understanding, Figure 4 , the mark of the second second substrate is shown in , that is, n=1, and the target unit on the second second substrate has the third same function, so the target unit on the second second substrate is recorded as target unit 53. Figure 4 In the second substrate 20 (2), the second substrate 20 (2) includes a fifth surface m (5) and a sixth surface m (6) facing each other, and the fifth surface m (5) is provided with a third functional chip ( Figure 4 The third functional chip is electrically connected to the third bonding finger 21(2) through a bonding wire. The sixth surface m(6) is recessed toward the fifth surface m(5) to form a groove 40(2). After the sixth surface is recessed, the non-recessed portion m(61) of the sixth surface m(6) is electrically connected to the third surface m(3). The recessed portion of the sixth surface m(6) is provided with a third peripheral resistor and capacitor ( Figure 4 denoted as target unit 53); wherein, the 6th surface m(6) is adjacent to the 3rd surface m(3), and the 5th surface m(5) is far away from the 3rd surface m(3).

[0027] It is understandable that Figure 4 The semiconductor module packaging structure shown is also applicable to the shape of the groove 40 shown in the above embodiment, the target unit setting method shown in the above embodiment, the bottom 31 structure of the metal shell 30, the sealing method of the metal cover 36 shown in the above embodiment, and the electrical connection method shown in the above embodiment.

[0028] The target unit setting method refers to setting the target unit with the highest heat dissipation requirement level on the first surface. Figure 4 The semiconductor module packaging structure shown is applicable to the above-mentioned target unit setting method. Adjustments are made based on the functions implemented by the target units, not limited to two types. At this time, the heat dissipation requirement level is sorted, which exemplarily includes: quantifying the heat dissipation requirements of the target units that implement each function based on the power processing capability of the target units and their own working power consumption, and sorting the heat dissipation requirements of the target units that implement the a1 function, the heat dissipation requirements of the target units that implement the a2 function, ..., the heat dissipation requirements of the target units that implement the ab functions, etc., to obtain the target unit that implements the ax (x∈b) function with the highest heat dissipation requirement level.

[0029] like Figure 5 As shown, another embodiment of the present invention further provides a semiconductor module packaging method, using the semiconductor module packaging structure shown in the above embodiment, the method includes but is not limited to the following steps: S501, modularize and decompose the target semiconductor module to obtain a target unit that realizes one same function and a target unit that realizes another same function; S502 , disposing a target unit that realizes one identical function on a first substrate, and disposing a target unit that realizes another identical function on a second substrate.

[0030] In a preferred implementation, an embodiment of the present invention further ranks target units that implement the same function and target units that implement another same function according to their heat dissipation requirement levels, and classifies each target unit according to its device characteristics. Thus, in step S501, the target unit that implements the same function includes a first function chip and a first peripheral resistor and capacitor device, and the target unit that implements another same function includes a second function chip and a second peripheral resistor and capacitor device. Step S502 is implemented as follows: the first function chip and the first peripheral resistor and capacitor device are disposed on the first surface of the first substrate, and the first function chip is electrically connected to a first bonding finger via a bonding wire; the second function chip is disposed on the third surface of the second substrate and electrically connected to a second bonding finger via a bonding wire, and the second peripheral resistor and capacitor device is disposed in a recessed portion of the fourth surface of the second substrate. This further improves integration density, and in practical applications, the integration density can reach 200%.

[0031] The target units that implement the same function and the target units that implement another same function are sorted according to their heat dissipation requirement levels, including: calculating the heat dissipation requirement based on the power processing capacity and operating power consumption of the target units, and using the calculation results to quantify the heat dissipation requirement of each target unit, thereby determining whether the heat dissipation requirement level of the target unit that implements the same function is higher than the heat dissipation requirement level of the target unit that implements the same function. Each target unit is classified according to device characteristics, including: classifying all devices included in any target unit according to the device characteristic of whether they are used to implement the function of resistors or capacitors, thereby classifying all devices included in the target unit that implements the same function as a first functional chip and a first peripheral resistor and capacitor device; and classifying all devices included in the target unit that implements the same function as a second functional chip and a second peripheral resistor and capacitor device.

[0032] It should be noted that when using Figures 1 to 3 The semiconductor module packaging structure shown in the figure indicates that the target semiconductor module mainly includes target units that realize two functions. The results of modular decomposition, sorting by heat dissipation requirement level, and classification by device characteristics are shown above. Figure 4 The semiconductor module packaging structure shown in the figure indicates that the target semiconductor module may include target units that implement multiple functions. After modular decomposition of the target semiconductor module, target units that implement function a1, target units that implement function a2, ..., target units that implement function ab can be obtained. Figure 4The semiconductor module packaging structure of the plurality of second substrates shown is packaged, and the N second substrates are all used to set the target units that realize the same function in the target semiconductor module. The second substrates are all used to set the target units that realize the same function in the target semiconductor module, which means: the first second substrate is used to set the target unit with another function, the second second substrate and the remaining plurality of second substrates can be the same as the first second substrate and used to set the target unit with another function, or can be different from the first second substrate and used to set the target unit with another function or multiple functions. The embodiment of the present invention does not limit it. When using Figure 4 The semiconductor module packaging structure shown in the figure sorts the target units for realizing the a1 function, the target units for realizing the a2 function, ..., and the target units for realizing the ab functions according to the heat dissipation requirement level, including: quantifying the heat dissipation requirements of the target units for realizing each function according to the power processing capability of the target units and their own working power consumption, sorting the heat dissipation requirements of the target units for realizing the a1 function, the heat dissipation requirements of the target units for realizing the a2 function, ..., and the heat dissipation requirements of the target units for realizing the ab functions, etc., to obtain the target unit for realizing the ax(x∈b) function with the highest heat dissipation requirement level. When using Figure 4 The semiconductor module packaging structure shown in the figure classifies the target unit for implementing the a1 function, the target unit for implementing the a2 function, ..., and the target unit for implementing the ab function according to device characteristics, including: classifying all devices included in the target unit for implementing the a1 function as a first functional chip and a first peripheral resistor and capacitor device; classifying all devices included in the target unit for implementing the a2 function as a second functional chip and a second peripheral resistor and capacitor device; ..., classifying all devices included in the target unit for implementing the ab function as a bth functional chip and a bth peripheral resistor and capacitor device.

[0033] The embodiments of the present invention exemplarily illustrate several target semiconductor modules, including but not limited to a power module, a sensor module, a power management module, and a wireless communication module, to illustrate the above-mentioned semiconductor module packaging method.

[0034] First, the core functional chips of the power module include a driver chip and a power chip; the core functional chips of the sensor module include a sensor chip and a signal processing chip; the core functional chips of the power management module include a power management chip and a battery management chip; and the core functional chips of the wireless communication module include a radio frequency chip and a baseband chip. When the target semiconductor module is packaged according to the above packaging method, the target units obtained after modular decomposition include at least target units based on two core functional chips. For example, after modular decomposition of the power module, a target unit including a driver chip and its peripheral resistor-capacitor components and a target unit including a power chip and its peripheral resistor-capacitor components can be obtained; after modular decomposition of the sensor module, a target unit including a sensor chip and its peripheral resistor-capacitor components and a target unit including a signal processing chip and its peripheral resistor-capacitor components can be obtained; after modular decomposition of the power management module, a target unit including a power management chip and its peripheral resistor-capacitor components and a target unit including a battery management chip and its peripheral resistor-capacitor components can be obtained; after modular decomposition of the wireless communication module, a target unit including a radio frequency chip and its peripheral resistor-capacitor components and a target unit including a baseband chip and its peripheral resistor-capacitor components can be obtained.

[0035] Secondly, in an embodiment of the present invention, the first functional chip and the first peripheral resistor and capacitor component are arranged on the first surface of the first substrate, indicating that after modular decomposition of the target semiconductor module, the target unit including the first functional chip and the first peripheral resistor and capacitor component has the highest heat dissipation requirement level. Therefore, in a specific application, before the first functional chip and the first peripheral resistor and capacitor component are arranged on the first surface of the first substrate, it also includes: sorting the target units that realize the same function and the target units that realize another same function according to the heat dissipation requirement level to obtain a first target unit including the first functional chip and the first peripheral resistor and capacitor component, and a second target unit including the second functional chip and the second peripheral resistor and capacitor component, wherein the first target unit has the highest heat dissipation requirement level, so that the first functional chip and the first peripheral resistor and capacitor component are on the first surface. Exemplarily, for the power module, the heat dissipation requirement of the power chip is greater than that of the driver module, then the first functional chip and the first peripheral resistor-capacitor component in the above steps correspond to the power chip and its peripheral resistor-capacitor component respectively, that is, the target unit for realizing the same function is the target unit including the power chip and its peripheral resistor-capacitor component, and the power chip is the first functional chip, and its peripheral resistor-capacitor component is the first peripheral resistor-capacitor component; the second functional chip and the second peripheral resistor-capacitor component in the above steps correspond to the driver chip and its peripheral resistor-capacitor component respectively, that is, the target unit for realizing another same function is the target unit including the driver chip and its peripheral resistor-capacitor component, and the driver chip is the second functional chip, and its peripheral resistor-capacitor component is the second peripheral resistor-capacitor component; and then the power chip and its peripheral resistor-capacitor component are arranged on the first surface. For the sensor module, the signal processing chip has a greater heat dissipation requirement than the sensor chip. The first functional chip and the first peripheral resistor-capacitor device in the above steps correspond to the signal processing chip and its peripheral components, respectively. That is, the target unit for achieving the same function is the target unit including the signal processing chip and its peripheral resistor-capacitor device, and the signal processing chip is the first functional chip, and its peripheral components are the first peripheral resistor-capacitor device. The second functional chip and the second peripheral resistor-capacitor device in the above steps correspond to the sensor chip and its peripheral resistor-capacitor device, respectively. That is, the target unit for achieving another identical function is the target unit including the sensor chip and its peripheral resistor-capacitor device, and the sensor chip is the second functional chip, and its peripheral resistor-capacitor device is the second peripheral resistor-capacitor device. Furthermore, the signal processing chip and its peripheral resistor-capacitor device are disposed on the first surface. Similarly, for the power management module and the wireless communication module, the power management chip of the power management module has a greater heat dissipation requirement than the battery management chip, and therefore the power management chip is disposed on the first surface as the first functional chip. The RF chip of the wireless communication module has a greater heat dissipation requirement than the baseband chip, and therefore the RF chip is disposed on the first surface as the first functional chip. Other similar contents are not repeated here.

[0036] Finally, for the case where the target semiconductor module includes target units that realize multiple functions, the above-mentioned power module is used to illustrate the actual application scenario of the industrial robot. In this actual application scenario, the number of target units based on the driver chip usually corresponds to the number of joint axes of the industrial robot, which is responsible for the specific control of each joint axis. Therefore, the power module includes target units that realize two functions, such as a target unit that realizes the power supply function and a target unit that realizes the motor drive function. Among them, the target unit that realizes the motor drive function includes multiple target units according to the different joint axes, such as a target unit that realizes the specific control of joint axis 1, a target unit that realizes the specific control of joint axis 2, a target unit that realizes the specific control of joint axis 3, etc. At this time, a structure of multiple second substrates is applicable. For example, in the final packaging structure, a first functional chip (power chip) and a first peripheral resistor-capacitor device are disposed on the first surface of the first substrate. Target units disposed on the first and remaining second substrates perform the same functions as the first and second substrates. The first and second substrates are provided with target units for specifically controlling joint axis 1. Specifically, the second functional chip (the driver chip for driving joint axis 1) is disposed on the third surface of the first second substrate, the second peripheral resistor-capacitor device is disposed on the fourth surface of the first second substrate, the third functional chip (the driver chip for driving joint axis 2) is disposed on the fifth surface of the second second substrate, and the third peripheral resistor-capacitor device is disposed on the sixth surface of the second second substrate. The remaining components are not further described. For another example, in the actual application scenario of a sensor module in an industrial robot, for automatic welding, a sensor module in the industrial robot typically uses multiple sensor chips to improve weld positioning accuracy and stable welding quality. In this actual application scenario, these sensors include at least a laser tracking sensor, an infrared temperature sensor, and an arc sensor. Therefore, this sensor module in the industrial robot includes target units that perform four functions, such as a target unit for weld positioning, a target unit for temperature monitoring, and a target unit for current and voltage control.Exemplarily, in the final packaging structure, a first functional chip (signal processing chip) and a first peripheral resistor and capacitor device are disposed on the first surface of the first substrate. Target units disposed on the second and remaining second substrates perform different functions than those of the first second substrate. For example, the first second substrate may be provided with a target unit for weld positioning, specifically, a second functional chip (laser tracking sensor chip) disposed on the third surface of the first second substrate, and a second peripheral resistor and capacitor device disposed on the fourth surface of the first second substrate. The second second substrate may be provided with a target unit for temperature monitoring, specifically, a third functional chip (infrared temperature sensor chip) disposed on the fifth surface of the second second substrate, and a third peripheral resistor and capacitor device disposed on the sixth surface of the second second substrate. Furthermore, a third second substrate may be provided with a target unit for current and voltage control, specifically, a fourth functional chip (arc sensor chip) disposed on the seventh surface of the third second substrate, and a third peripheral resistor and capacitor device disposed on the eighth surface of the third second substrate. It can be seen that for practical application scenarios involving target units that perform two functions or multiple functions, the above-described structure is preferably used. Figure 4 The three-dimensional, multi-faceted, multi-cavity semiconductor packaging structure shown is packaged.

[0037] In an embodiment of the present invention, the power module may be a GaN power module, a SiC power module, or a Ga2O3 power module. GaN power modules, in particular, have the characteristics of high frequency, high efficiency, and high power density. Compared with traditional silicon-based devices, they can achieve higher breakdown electric fields and temperature resistance. At the same time, their electron mobility and saturation velocity are significantly better than silicon, and they can operate at high frequencies in the MHz range, reducing switching losses by more than 50%, and significantly reducing the size of passive components to achieve system-level miniaturization. In addition, the GaN power module's near-zero reverse recovery charge and low on-resistance characteristics further improve the energy efficiency performance in medium and low voltage scenarios (such as fast charging and on-board power supplies), with an efficiency of more than 95%.

[0038] In specific applications, for GaN power modules, the first and second substrates are made of AlN ceramic. AlN ceramic has high thermal conductivity and a thermal expansion coefficient that closely matches that of GaN chips, making it suitable for high-frequency applications. Therefore, embodiments of the present invention are particularly useful for optimizing the packaging structure of GaN power modules. They also optimize substrate material selection based on the GaN power module's packaging structure. Combined with the GaN power module's high-temperature resistance (e.g., >200°C) and low drive power consumption, they can provide more compact and efficient solutions for 5G communications, new energy vehicles, and renewable energy.

[0039] In one embodiment, for a GaN power module, an embodiment of the present invention provides a better circuit structure implementation, including a primary drive circuit, a pulse width modulation control circuit, a synchronous rectification drive circuit, and a half-bridge current doubler synchronous rectification main power circuit, wherein the half-bridge current doubler synchronous rectification main power circuit includes a power chip and its peripheral resistor and capacitor components. Therefore, according to the semiconductor module packaging method provided by an embodiment of the present invention, the power chip and its peripheral resistor and capacitor components included in the half-bridge current doubler synchronous rectification main power circuit are arranged on the first surface of the first substrate, and the primary drive circuit, the pulse width modulation control circuit, and the synchronous rectification drive circuit belong to the drive chip and its peripheral resistor and capacitor components. Therefore, according to the semiconductor module packaging method provided by an embodiment of the present invention, the primary drive circuit is arranged on the third surface of the second substrate, and the pulse width modulation control circuit and the synchronous rectification drive circuit are arranged on the fourth surface of the second substrate, that is, the recessed portion of the fourth surface.

[0040] In actual application, the circuit structure of the GaN power module mentioned above includes 128 components including resistors, capacitors, diodes, transistors, transformers, chips, and electrical connectors. The product has an input voltage of 70-120V, an output voltage of 5V, an output current of 24A, and a power of 120W. Figure 3 The position shown in A in the figure determines the layout area range of 55.0mm*36.6mm. Figure 3 Within the layout area shown, the first substrate and the second substrate are designed to package the GaN power module. Figure 6 As shown, the first substrate 10 is used to set the power chip and its peripheral resistor and capacitor components included in the half-bridge current doubler synchronous rectification main power circuit, wherein T1 and T3 are transformers in the half-bridge current doubler synchronous rectification main power circuit, DX, CX, RX are peripheral passive components, VMX, QX are transistors, and X represents the serial number of each peripheral resistor and capacitor component. Figure 7 and Figure 8 As shown, the second substrate 20 is used to set the primary side drive circuit, pulse width modulation control circuit, synchronous rectification drive circuit, and the driver chip and its peripheral resistor and capacitor components. The chip and the corresponding resistor and capacitor components around it are placed as concentrated as possible in the perspective direction, and low parasitic interconnection between the chip and the substrate is achieved through vias. Figure 7 In the figure, the third surface m3 of the second substrate 20 is provided with a primary drive circuit, a pulse width modulation control circuit, and a synchronous rectification drive circuit, wherein T2 represents a transformer, U1, U2, U3, and U4 represent chip parts in the above circuits, and D10 represents a diode; Figure 8 In the figure, the fourth surface m4 of the second substrate 20 is provided with peripheral resistor-capacitor components of the primary drive circuit, peripheral resistor-capacitor components of the pulse width modulation control circuit, and peripheral resistor-capacitor components of the synchronous rectification drive circuit, including CX and RX, where X represents the serial number of each peripheral resistor-capacitor component.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A semiconductor module packaging structure, characterized in that: include: A first substrate comprising a first surface and a second surface opposite to each other, wherein the first surface is provided with first bonding fingers; a second substrate comprising a third surface and a fourth surface opposite to each other, the fourth surface being recessed toward the third surface to form a groove, the unrecessed portion of the fourth surface being electrically connected to the first surface to form a front-to-back connected cavity, the third surface being provided with a second bonding finger; wherein the fourth surface is adjacent to the first surface, and the third surface is distal to the first surface; a metal housing having a cavity for accommodating the first substrate and the second substrate, the first substrate being mounted within the cavity, the second surface being in contact with the bottom of the metal housing, two opposing side walls of the metal housing each having an external pin, the second bonding finger being further connected to the external pin via a bonding wire; and the other two opposing side walls of the metal housing facing the front-to-back connected cavity; The first substrate is used to set a target unit that implements the same function in the target semiconductor module, and the second substrate is used to set a target unit that implements another same function in the target semiconductor module, wherein the target unit set on the first surface is electrically connected to the first bonding finger through a bonding wire, and the target unit set on the third surface is electrically connected to the second bonding finger through a bonding wire.

2. The semiconductor module packaging structure according to claim 1, wherein: The target unit realizing another same function is provided on the concave portion of the fourth surface and the third surface.

3. The semiconductor module packaging structure according to claim 1, wherein: The N second substrates are each used to set target units implementing the same function in a target semiconductor module; The first second substrate comprises a third surface and a fourth surface opposite to each other, the fourth surface is recessed toward the third surface to form a groove, the non-recessed portion of the fourth surface is electrically connected to the first surface, and the third surface is provided with a second bonding finger; The n+1th second substrate includes an n+4th surface and an n+5th surface facing each other, the n+4th surface being provided with an n+2th functional chip and an n+2th bonding finger, the n+2th functional chip being electrically connected to one of the n+2th bonding fingers via a bonding wire, the n+5th surface being recessed toward the n+4th surface to form a groove, and the unrecessed portion of the n+5th surface being electrically connected to the n+2th surface to form a cavity communicating front to back; the n+5th surface being adjacent to the n+2th surface, the n+4th surface being away from the n+2th surface, N being a positive integer greater than or equal to 1, and n+1≤N; If only one second substrate is included, the second bonding finger of the first second substrate is connected to the external pin via a bonding wire; if at least two second substrates are included, the bonding finger of the last second substrate is connected to the external pin via a bonding wire.

4. The semiconductor module packaging structure according to claim 3, wherein: Two opposite surfaces of the second substrate are interconnected through pre-set via holes.

5. The semiconductor module packaging structure according to claim 4, wherein: The target units realizing the same function are arranged on two opposite surfaces of each second substrate.

6. The semiconductor module packaging structure according to claim 2 or 5, characterized in that: The shape of the groove is rectangular or trapezoidal.

7. The semiconductor module packaging structure according to claim 2 or 5, characterized in that: The bottom of the metal shell further includes an extension portion, which is formed by connecting the bottom of the metal shell with two opposite side walls of the metal shell provided with external pins and continuing to extend away from the two opposite side walls by a preset length.

8. The semiconductor module packaging structure according to claim 7, wherein: The target unit with the highest heat dissipation requirement level is arranged on the first surface.

9. The semiconductor module packaging structure according to claim 7, wherein: The invention also comprises a metal cover plate, which is sealed to the top of the metal shell by parallel seam welding.

10. The semiconductor module packaging structure according to claim 7, wherein: A packaging pin and a mounting hole are provided on a surface of the extension portion close to the outer pin.

11. The semiconductor module packaging structure according to claim 7, wherein: The external pin includes a connecting portion located in the inner cavity of the metal shell, and a heat dissipation portion exposed from the inner cavity of the metal shell.

12. The semiconductor module packaging structure according to claim 2 or 5, characterized in that: The solders for setting the target unit on the first substrate and the second substrate, the solder for bonding the second surface to the bottom of the metal housing, and the solder for electrically connecting the non-recessed portion of the fourth surface to the first surface are all different.

13. A semiconductor module packaging method, characterized in that: The semiconductor module packaging structure according to any one of claims 1 to 12 comprises: Decomposing the target semiconductor module into modules to obtain a target unit that realizes one identical function and a target unit that realizes another identical function; A target unit realizing one identical function is arranged on a first substrate, and a target unit realizing another identical function is arranged on a second substrate.

14. The semiconductor module packaging method according to claim 13, wherein: Target units that implement a same function and target units that implement another same function are sorted according to heat dissipation requirement levels, and each target unit is classified according to device characteristics to obtain a first target unit including a first function chip and a first peripheral resistor and capacitor device, and a second target unit including a second function chip and a second peripheral resistor and capacitor device; The first functional chip and the first peripheral resistor and capacitor component are arranged on the first surface of the first substrate, and the first functional chip is electrically connected to a first bonding finger through a bonding wire; the second functional chip is arranged on the third surface of the second substrate and is electrically connected to a second bonding finger through a bonding wire, and the second peripheral resistor and capacitor component is arranged in a recessed portion of the fourth surface of the second substrate.

15. The semiconductor module packaging method according to claim 13 or 14, wherein: The target semiconductor module includes a power module, a sensor module, a power management module, and a wireless communication module.

16. The semiconductor module packaging method according to claim 15, wherein: The power module includes any one of a GaN power module, a SiC power module, and a Ga2O3 power module; for the GaN power module, the first substrate and the second substrate are made of AlN ceramics.

17. The semiconductor module packaging method according to claim 15, wherein: The power module includes a primary side drive circuit, a pulse width modulation control circuit, a synchronous rectification drive circuit, and a half-bridge current doubling synchronous rectification main power circuit; Among them, the half-bridge current-doubling synchronous rectification main power circuit is arranged on the first surface, the primary side drive circuit, the pulse width modulation control circuit, and the synchronous rectification drive circuit are arranged on the third surface, and the peripheral resistor-capacitor components of the primary side drive circuit, the peripheral resistor-capacitor components of the pulse width modulation control circuit, and the peripheral resistor-capacitor components of the synchronous rectification drive circuit are arranged on the fourth surface.

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