Controllable frequency detectors, phase-locked loops, and communication equipment

Abstract

The present application relates to the technical field of frequency synthesizers and discloses a controllable phase frequency detector, a phase-locked loop (PLL), and a communication device. The controllable phase frequency detector includes a phase detection core circuit, a switching power supply circuit, a clock selection circuit, and a control circuit. The clock selection circuit selects a reference clock signal and a feedback clock signal and outputs a gated clock signal based on an input clock selection signal. After its enable signal becomes valid, the control circuit controls the switching power supply circuit to conduct in response to the first valid clock edge of the gated clock signal, thereby powering the phase detection core circuit. The control circuit can start at a controllable preset initial phase, and its initial output state depends only on the setting of the clock selection signal and is independent of the actual phase relationship of the input clock when powered on. When used in a phase-locked loop, it can effectively shorten the lock time and avoid the risk of overvoltage in the charge pump due to long-term charging, thereby improving the performance and reliability of the phase-locked loop.

Description

Technical Field

[0001] The present application relates to the technical field of frequency synthesizers, and in particular to a phase-locked loop (PLL) and a phase-frequency detector therein. Background Art

[0002] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of this application.

[0003] A phase-locked loop (PLL) is a circuit widely used in modern communications and electronic systems. Its core function is to use an external reference clock input to generate a high-quality output clock signal that is precisely synchronized in both frequency and phase. A typical PLL circuit consists of a phase-frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a divider (DIV) in the feedback loop.

[0004] The phase-frequency detector (PFD) plays a key role in the operation of a phase-locked loop (PLL). Its function is to compare the frequency and phase differences between a reference clock signal and the voltage-controlled oscillator's output signal, divided by a frequency divider (the feedback clock signal). Based on the comparison results, the PFD generates two control signals, commonly referred to as "UP" (up) and "DN" (down), to drive the subsequent charge pump. The charge pump charges or discharges according to the UP / DN signals. The output current pulses are smoothed by a loop filter to form a stable control voltage. This control voltage is ultimately applied to the voltage-controlled oscillator to adjust the frequency of its output clock until the frequency and phase of the feedback clock are precisely aligned with the reference clock. At this point, the PLL is said to be "locked."

[0005] However, during the initial startup phase of a phase-locked loop (PLL), the phase relationship between the reference clock and the feedback clock is completely uncertain because the VCO frequency has not yet stabilized. This uncertainty results in an uncertain state for the initial UP / DN signals output by the PFD. This presents two major problems: First, the uncertain initial state can cause the charge pump to generate a long, continuous charge or discharge pulse during startup, prolonging the time required for the entire PLL to reach a stable lock state, thereby increasing the lock time. Second, in some high-performance PLL designs, the charge pump and its subsequent circuitry may operate at a higher supply voltage domain to achieve a wider tuning range and better noise performance. In this case, prolonged continuous charging can cause the charge pump output node voltage to rise abnormally, resulting in an overvoltage condition. This can damage not only the charge pump itself but also subsequent circuits such as the loop filter and VCO.

[0006] To address this issue, several solutions have been proposed. For example, one approach involves adding an additional fast-lock control unit to the phase-locked loop (PLL). This control unit generates a synchronous reset signal using a reference clock and a PLL enable signal, and uses this signal to trigger the frequency divider to start operating. The goal is to control the initial phase relationship between the two input signals of the PFD by synchronizing the start-up timing of the frequency divider, thereby indirectly controlling the PFD output and accelerating locking.

[0007] While the above-mentioned prior art solutions attempt to address the problem to some extent, they also have inherent drawbacks. First, they require the addition of additional circuit modules to the existing phase-locked loop (PLL) structure, increasing chip area and design complexity. Second, this solution places special requirements on the circuit's operating timing. It requires the frequency divider to be enabled after the PFD begins operating. However, in many designs, the frequency divider may be reused with modules such as counters and needs to be enabled early after the PLL is enabled, resulting in timing conflicts. Furthermore, the frequency divider is typically composed of multiple cascaded frequency division units, and the synchronization reset signal introduces a long delay during its transmission to the final output of the frequency divider. This delay can cause the synchronization scheme to fail. Finally, even if edge synchronization of the input clock is achieved, this solution cannot fully guarantee a fixed initial phase for the PFD output. This is because at startup, the VCO frequency may be higher or lower than the target frequency, causing the feedback clock frequency to be correspondingly higher or lower than the reference clock. Synchronizing the clock edges alone cannot resolve the phase ambiguity caused by this frequency difference.

[0008] Therefore, this field urgently needs a new technical solution to reliably control the frequency detector and phase detector to output a certain initial phase when the phase-locked loop is started, regardless of the initial phase relationship of its input clock, thereby effectively solving the problems of long locking time and circuit overvoltage. Summary of the Invention

[0009] The purpose of this application is to provide a controllable phase frequency detector, phase-locked loop and communication equipment, which can still control the phase frequency detector circuit structure of its output initial phase when the phase relationship of the phase frequency detector input clock is uncertain, thereby solving the problems of long phase-locked loop locking time and overvoltage.

[0010] The present application discloses a controllable frequency and phase detector, comprising:

[0011] a phase detection core circuit configured to generate an output signal related to a phase difference between a reference clock signal and a feedback clock signal;

[0012] a switching power supply circuit, configured to provide or cut off power supply to the phase detection core circuit;

[0013] a clock selection circuit, having two input terminals connected to the reference clock signal and the feedback clock signal, respectively, and configured to select one of the reference clock signal and the feedback clock signal and output a gated clock signal according to an input clock selection signal; and

[0014] A control circuit has an input end connected to an enable signal and the selection clock signal, and an output end controlling the switching power supply circuit; the control circuit is configured to, after the enable signal is valid, control the switching power supply circuit to be turned on in response to the first valid clock edge of the selection clock signal to supply power to the phase detection core circuit, thereby starting the phase detection core circuit in a controllable preset initial phase state.

[0015] In a preferred embodiment, the control circuit includes a first D flip-flop, wherein a clock input terminal of the first D flip-flop is connected to the strobe clock signal, a data input terminal of the first D flip-flop is connected to the enable signal, and the first D flip-flop has a first output terminal and a second output terminal that are mutually inverted;

[0016] The switching power supply circuit includes a first switch and a second switch, wherein the first switch is controlled by the first output terminal to connect the power supply voltage to the power supply terminal of the phase detection core circuit, and the second switch is controlled by the second output terminal to ground the power supply terminal of the phase detection core circuit.

[0017] In a preferred example, the clock selection circuit is a multiplexer.

[0018] In a preferred embodiment, the output signal of the phase detection core circuit includes a first output signal and a second output signal;

[0019] The phase detection core circuit includes:

[0020] a second D flip-flop, wherein a clock input terminal thereof is connected to the reference clock signal, a data input terminal thereof is connected to a power supply voltage, and a data output terminal thereof generates the first output signal;

[0021] a third D flip-flop, whose clock input terminal is connected to the feedback clock signal, whose data input terminal is connected to the power supply voltage, and whose data output terminal generates the second output signal; and

[0022] A reset logic circuit, whose two input terminals are respectively connected to the data inverting output terminals of the second D flip-flop and the third D flip-flop, is used to generate a common reset signal when the first output signal and the second output signal are both at a high level, and apply the common reset signal to the reset terminals of the second D flip-flop and the third D flip-flop.

[0023] In a preferred embodiment, when the clock selection signal selects the reference clock signal as the gate clock signal, the phase detection core circuit first generates the first output signal after being started;

[0024] When the clock selection signal selects the feedback clock signal as the gate clock signal, the phase detection core circuit first generates the second output signal after being started.

[0025] In a preferred example, the reset logic circuit is a NOR gate.

[0026] The present application also discloses a phase-locked loop, comprising:

[0027] The controllable phase frequency detector as described above is configured to receive a reference clock signal and a feedback clock signal and generate an output signal related to a phase difference between the reference clock signal and the feedback clock signal;

[0028] a charge pump, an input terminal of which is connected to the output terminal of the controllable phase frequency detector and configured to generate a current pulse according to the output signal;

[0029] a loop filter having an input terminal connected to an output terminal of the charge pump and configured to smooth the current pulses to generate a control voltage;

[0030] a voltage controlled oscillator, an input terminal of which is connected to an output terminal of the loop filter, and configured to generate an output clock signal according to the control voltage; and

[0031] The frequency divider, whose input terminal is connected to the output terminal of the voltage controlled oscillator, is configured to divide the output clock signal to generate the feedback clock signal, and provide the feedback clock signal to the input terminal of the controllable phase frequency detector.

[0032] In a preferred embodiment, the output signal of the controllable phase frequency detector includes an UP signal for controlling the charging of the charge pump and a DN signal for controlling the discharging of the charge pump;

[0033] In the controllable phase and frequency detector, the reference clock signal is configured to trigger the UP signal;

[0034] The clock selection circuit of the controllable phase and frequency detector is configured to select the reference clock signal as the gated clock signal according to the clock selection signal.

[0035] In a preferred embodiment, the output signal of the controllable phase frequency detector includes an UP signal for controlling the charging of the charge pump and a DN signal for controlling the discharging of the charge pump;

[0036] In the controllable phase and frequency detector, the feedback clock signal is configured to trigger the UP signal;

[0037] The clock selection circuit of the controllable phase and frequency detector is configured to select the feedback clock signal as the gated clock signal according to the clock selection signal.

[0038] The present application also discloses a communication device, comprising the phase-locked loop according to the above description.

[0039] In an embodiment of the present application, a combination circuit consisting of a clock selection circuit, a control circuit, and a switching power supply circuit is provided. Upon receiving an enable signal, the control circuit in this combination circuit, in response to the first valid edge of the reference clock or feedback clock selected by the clock selection circuit, turns on the switching power supply circuit, thereby powering the phase detection core circuit. This solves the problem of uncertain initial output phase of the phase frequency detector (PFD) in the prior art. Regardless of the actual phase relationship between the input reference clock and the feedback clock, this circuit structure ensures that the phase detection core circuit starts up in a preset, deterministic initial state. This controllable startup method avoids the prolonged charging or discharging of the charge pump (CP) during the initial startup of the phase-locked loop (PLL), significantly shortening the PLL lock time and effectively preventing overvoltage damage to the charge pump and subsequent circuitry caused by prolonged charging, thereby improving the performance and reliability of the entire circuit.

[0040] Furthermore, by employing a first D-type flip-flop as the control circuit and using a first switch and a second switch to form a switching power supply circuit, where the D-type flip-flop's clock terminal is connected to the strobe clock, its data terminal is connected to the enable signal, and its two inverting output terminals (Q and QB) respectively control the two switches, a specific, efficient, and reliable circuit implementation can be provided. This structure utilizes the D-type flip-flop to precisely latch the enable signal on the active edge of the strobe clock and drive the switch to explicitly connect the power supply terminal of the phase detection core circuit to the power supply voltage or ground, ensuring precise power on and preventing the power supply terminal from floating indefinitely.

[0041] Furthermore, by integrating the controllable PFD into a complete phase-locked loop (PLL), the PFD's technical advantages can be extended to the entire PLL system. Ultimately, the PLL's lock time is shortened, operational reliability is enhanced, and the overall performance of the PLL is improved.

[0042] Furthermore, by selecting the clock that triggers the UP signal in the phase-locked loop as the gate clock for starting the PFD, it is ensured that when the phase-locked loop starts, it will output a narrow-pulse-width UP signal and a wide-pulse-width DN signal. This specific configuration can minimize the initial charging time of the subsequent high-voltage charge pump, accurately solving the overvoltage problem that may be caused by prolonged charging, and greatly improving circuit safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 1 is a schematic diagram of a controllable frequency and phase detector circuit according to an embodiment of the present application;

[0044] Figure 2 yes Figure 1 Schematic diagram of the circuit's VPSW changing with pfd_en and clock signals;

[0045] Figure 3 yes Figure 1 Schematic diagram of the waveform of the frequency and phase detector when clk_sel selects clk_ref and the phase of clk_ref lags behind clk_div in the circuit;

[0046] Figure 4 yes Figure 1 Schematic diagram of the waveform of the frequency and phase detector when clk_sel selects clk_ref and the phase of clk_ref leads clk_div in the circuit;

[0047] Figure 5 yes Figure 1 Schematic diagram of the waveform of the frequency and phase detector when clk_sel selects clk_div and the phase of clk_ref leads clk_div in the circuit;

[0048] Figure 6 yes Figure 1 Schematic diagram of the waveform of the frequency and phase detector when clk_sel selects clk_div and the phase of clk_ref lags behind clk_div;

[0049] Figure 7 is a schematic diagram of a controllable frequency and phase detector circuit according to another embodiment of the present application;

[0050] Figure 8 This is another implementation of a phase detection core circuit in a controllable phase frequency detector according to an embodiment of the present application;

[0051] Figure 9 This is another implementation of a phase detection core circuit in a controllable phase frequency detector according to an embodiment of the present application;

[0052] Figure 10 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present application;

[0053] Figure 11 It is the simulation waveform of the frequency detector and charge pump in the existing phase-locked loop;

[0054] Figure 12 This is a simulation waveform of a phase frequency detector and a charge pump in a phase-locked loop according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0056] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0057] The first embodiment of the present application relates to a controllable frequency and phase detector, Figure 1 A specific embodiment of the controllable frequency phase detector is shown. The controllable frequency phase detector includes:

[0058] The phase detection core circuit is configured to generate an output signal related to the phase difference between the reference clock signal and the feedback clock signal. Figure 1In this embodiment, the phase detection core circuit includes D flip-flops dff2 and dff3, and a NOR gate nor. The power supply terminals of D flip-flops dff2, dff3, and nor are all VPSW, or in other words, VPSW serves as the power supply terminal for the entire phase detection core circuit. The clock input ck of D flip-flop dff2 is connected to the reference clock signal clk_ref, the data input D of dff2 is connected to the power supply voltage VDD, and the data output Q of dff2 outputs an UP signal. The clock input ck of D flip-flop dff3 is connected to the feedback clock signal clk_div, the data input D of dff3 is connected to the power supply voltage VDD, and the data output Q of dff3 outputs a DN signal. The nor gate nor implements a reset logic circuit. Its two inputs are connected to the inverting data outputs QB of D flip-flops dff2 and dff3, respectively (QB is the opposite of Q). When both UP and DN are high, a common reset signal is generated and applied to the reset terminals reset of D flip-flops dff2 and dff3.

[0059] The switching power supply circuit is configured to provide or cut off the power supply to the phase detection core circuit. Figure 1 In this embodiment, the switching power supply circuit includes two switching devices (a first switch s1 and a second switch s2). The first switch s1 is controlled by the first output terminal Q of the D-type flip-flop dff1. When Q is high, the power supply voltage VDD is connected to the power supply terminal VPSW of the phase detection core circuit. The second switch s1 is controlled by the second output terminal QB (opposite to Q) of the D-type flip-flop dff1. When QB is high, the power supply terminal VPSW of the phase detection core circuit is connected to ground. Preferably, s1 and s2 can be implemented using MOS transistors. However, other known electronic switching devices can also be used.

[0060] The clock selection circuit has two input terminals connected to the reference clock signal and the feedback clock signal, respectively, and is configured to select one of the reference clock signal and the feedback clock signal to output a gated clock signal according to the input clock selection signal. Figure 1 In the embodiment, the clock selection circuit is implemented by a multiplexer mux, the two inputs of the mux are the reference clock signal clk_ref and the feedback clock signal clk_div, the selection end of the mux is the clock selection signal clk_sel, and the output of the mux is the selection clock signal clk_s.

[0061] A control circuit has an input connected to an enable signal and a strobe clock signal, and an output controlling the switching power supply circuit. The control circuit is configured to, after the enable signal is asserted and in response to the first valid clock edge of the strobe clock signal, control the switching power supply circuit to conduct to supply power to the phase detection core circuit, thereby starting the phase detection core circuit in a controllable, preset initial phase state.

[0062] exist Figure 1 In an embodiment of the present invention, the control circuit includes a D flip-flop dff1, a clock input terminal CK of the D flip-flop dff1 is connected to the selection clock signal output by the mux, a data input terminal D of the D flip-flop dff1 is connected to the enable signal pfd_en, and the D flip-flop dff1 has a first output terminal Q and a second output terminal QB that are inverted to each other.

[0063] exist Figure 1 In the embodiment, when the clock selection signal clk_sel selects the reference clock signal clk_ref as the gate clock signal clk_s, the phase detection core circuit is enabled and first generates the DN signal. When the clock selection signal clk_sel selects the feedback clock signal clk_div as the gate clock signal clk_s, the phase detection core circuit is enabled and first generates the UP signal.

[0064] The following details Figure 1 Working principle of the embodiment circuit.

[0065] like Figure 2 As shown in the figure, when pfd_en changes from low level to high level, VPSW does not change to high level immediately, but will only become high level after the CK signal of dff1 changes from low level to high level, so that dff2, dff3 and nor will start working.

[0066] Assume that clk_sel selects clk_ref connected to the CK terminal of dff1. When pfd_en jumps from low level to high level, clk_ref phase lags behind clk_div (the definition of clock overdue in this application is that after pfd_en rises, whichever clock has the rising edge first is considered to be the leading clock). The waveform of the frequency detector is as follows: Figure 3 shown.

[0067] Assume that clk_sel selects clk_ref connected to the CK terminal of dff1. When pfd_en jumps from low level to high level, clk_ref phase leads clk_div, the waveform of the frequency detector is as follows: Figure 4 shown.

[0068] Assume that clk_sel selects clk_div and connects to the CK terminal of dff1. When pfd_en jumps from low level to high level, clk_ref phase leads clk_div, the waveform of the frequency detector is as follows: Figure 5 shown.

[0069] Assume that clk_sel selects clk_div and connects to the CK terminal of dff1. When pfd_en jumps from low level to high level, clk_ref phase lags behind clk_div. The waveform of the frequency detector is as follows: Figure 6 shown.

[0070] from Figures 3 to 6 From these four waveforms, we can conclude that Figure 1 The phase frequency detector of the circuit structure shown, regardless of the initial phase relationship between its input clocks clk_ref and clk_div when pfd_en is enabled, its output is solely dependent on which clock, connected to the CK of dff1, is selected by clk_sel. When clk_div is selected as the CK signal of dff1, the initial phase of the phase frequency detector output is necessarily a wide-pulse-width UP signal and a narrow-pulse-width DN signal; when clk_ref is selected as the CK signal of dff1, the initial phase of the phase frequency detector output is necessarily a wide-pulse-width DN signal and a narrow-pulse-width UP signal. Therefore, simply by setting the appropriate clk_sel signal to select the clock used by the CK of dff1, the initial phase of the phase frequency detector output can be controlled. The narrow pulse width and wide pulse width mentioned in this application are relative. For example, if the pulse width of the DN signal is wider than that of the UP signal, it is referred to as a wide-pulse-width DN signal and a narrow-pulse-width UP signal, and vice versa.

[0071] In another embodiment, Figure 7 As shown, the CK terminal of D flip-flop dff2 can also be connected to the feedback clock signal clk_div, and the CK terminal of D flip-flop dff3 can be connected to the reference clock signal clk_ref. In this case, when the clock selection signal clk_sel selects the reference clock signal clk_ref as the gate clock signal clk_s, the phase detection core circuit is activated and first generates the UP signal. When the clock selection signal clk_sel selects the feedback clock signal clk_div as the gate clock signal clk_s, the phase detection core circuit is activated and first generates the DN signal.

[0072] The phase detection core circuit in the controllable frequency detector can also be implemented in other ways. For example, Figure 8 and Figure 9 Two alternatives of phase detection core circuits are shown respectively.

[0073] Figure 8The core phase detection circuit consists of an input section, two latches, reset logic, and an output section. The input section includes two inputs: the reference clock clk_ref and the divided feedback clock clk_div. Each input signal is first connected to a two-input NAND gate connected together. This NAND gate acts as an inverter, inverting the input clock signal. The main body of the circuit consists of two symmetrical RS latches (or flip-flops), each composed of two cross-coupled NAND gates. The upper latch is controlled by the clk_ref signal to generate a state related to the UP signal. The lower latch is controlled by the clk_div signal to generate a state related to the DN signal. The reset logic consists of a NAND gate located in the center of the circuit. Its two inputs are connected to the outputs of the upper and lower latches, respectively. The output of this NAND gate is an internal reset signal. When both the UP and DN signals are active (high), this gate generates a reset signal, resetting both latches to their initial states. The output section has two outputs: UP and DN. Each output signal is generated by a NAND gate.

[0074] Figure 9 The core phase detection circuit consists of two D flip-flops and an AND gate. For the upper D flip-flop, its clock (CLK) is connected to clk_ref, its data input (D) is constantly connected to a high voltage (VDD), and its output (Q) is the UP signal. For the lower D flip-flop, its clock (CLK) is connected to clk_div, its data input (D) is also constantly connected to a high voltage (VDD), and its output (Q) is the DN signal. Both the UP and DN output signals serve as inputs to the AND gate. The AND gate's output is connected to the reset terminals (Reset) of both the upper and lower D flip-flops.

[0075] Figure 8 and Figure 9 Each active component has a power supply terminal for obtaining power, and all power supply terminals are controlled by the VPSW output by the switching power supply circuit.

[0076] The second embodiment of the present application relates to a phase-locked loop, such as Figure 10 As shown, the phase-locked loop includes:

[0077] The first embodiment discloses a controllable phase frequency detector (PFD) configured to receive an external reference clock signal (clk_ref) and a feedback clock signal (clk_div) from a frequency divider, and generate an output signal related to the phase difference between the reference clock signal and the feedback clock signal. The output signal includes an UP signal for controlling the charging of a charge pump and a DN signal for controlling the discharging of the charge pump. Specifically, the charge pump charges when the UP signal is high, and discharges when the DN signal is high. A clock selection signal (clk_sel) is input as a control signal to the controllable phase frequency detector to select one of the reference clock signal (clk_ref) and the feedback clock signal (clk_div) as a reference for the initial phase of the controllable phase frequency detector.

[0078] The charge pump, whose input terminal is connected to the output terminal of the controllable phase frequency detector, is configured to generate current pulses according to the output signal.

[0079] The loop filter, whose input is connected to the output of the charge pump, is configured to smooth the current pulses to generate the control voltage.

[0080] The voltage controlled oscillator, whose input terminal is connected to the output terminal of the loop filter, is configured to generate an output clock signal according to a control voltage.

[0081] The frequency divider has an input terminal connected to the output terminal of the voltage controlled oscillator and is configured to divide the output clock signal to generate a feedback clock signal, and provide the feedback clock signal to the input terminal of the controllable phase frequency detector.

[0082] Optionally, in one embodiment, the controllable frequency detector is Figure 1 The reference clock signal clk_ref is configured to trigger the UP signal. The clock selection circuit of the controllable phase frequency detector is configured to select the reference clock signal clk_ref as the gate clock signal clk_s according to the clock selection signal clk_sel.

[0083] Optionally, in another embodiment, the controllable frequency detector is Figure 7 The feedback clock signal clk_div is configured to trigger the UP signal. The clock selection circuit of the controllable phase frequency detector is configured to select the feedback clock signal clk_div as the gate clock signal clk_s according to the clock selection signal clk_sel.

[0084] By setting the clock selection signal clk_sel, the clock signal used to trigger the UP signal between the reference clock signal clk_ref and the feedback clock signal clk_div is selected to control the timing of power supply to the phase detection core circuit. The initial UP signal output by the phase frequency detector can be controlled to be a narrow pulse width, thereby reducing the charging time of the subsequent charge pump, thereby ensuring that the high-voltage charge pump will not have an overvoltage problem due to too long charging time.

[0085] Figure 11 This is the traditional frequency detector-charge pump simulation waveform. When clk_ref is ahead of clk_div, UP is a wide pulse width. At this time, the output voltage of the charge pump will be charged to a very high level (see Figure 11 ), leading to overpressure risk.

[0086] Figure 12 This is a simulation waveform of the phase frequency detector-charge pump in the phase-locked loop of an embodiment of the present application. When clk_ref is ahead of clk_div, UP is a narrow pulse width. At this time, the output voltage of the charge pump will not be charged high (see Figure 12 The lower curve in the figure avoids the risk of overpressure.

[0087] The third embodiment of the present application relates to a communication device, which includes the phase-locked loop disclosed in the second embodiment. The phase-locked loop disclosed in the second embodiment of the present application has a controllable initial phase, a shorter lock time, and higher operating reliability, and is particularly capable of avoiding the risk of overvoltage in high-voltage charge pumps. It can be widely used in various modern communication devices. The communication device can be a mobile communication terminal and base station, a wireless local area network (WLAN) and short-range communication device (such as a Wi-Fi router, access point, Bluetooth device, wearable device, etc.), a high-speed data transceiver (such as an Ethernet transceiver used in data centers, servers, network switches, and optical communication modules, etc.), or a satellite communication and navigation device (such as a satellite TV receiver and a GPS receiver, etc.).

[0088] It should be noted that, in this application, relational terms such as first and second are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. Without further restriction, an element defined by the phrase "comprising a" does not exclude the presence of other identical elements in the process, method, article, or device comprising the element. In this application, if it is mentioned that an action is performed according to a certain element, it means that the action is performed at least according to that element, including two situations: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "multiple," and "multiple" include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0089] This specification includes combinations of the various embodiments described herein. Separate references to an embodiment (e.g., "one embodiment," "some embodiments," or "preferred embodiment") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as such or clear to one skilled in the art. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0090] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the contents of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A controllable frequency and phase detector, characterized in that: include: a phase detection core circuit configured to generate an output signal related to a phase difference between a reference clock signal and a feedback clock signal; a switching power supply circuit, configured to provide or cut off power supply to the phase detection core circuit; a clock selection circuit, wherein two input terminals of the clock selection circuit are connected to the reference clock signal and the feedback clock signal respectively, and the clock selection circuit is configured to select one of the reference clock signal and the feedback clock signal and output a gated clock signal according to the input clock selection signal; as well as a control circuit, wherein an input end of the control circuit is connected to an enable signal and the gate clock signal, and an output end of the control circuit controls the switching power supply circuit; The control circuit is configured to, after the enable signal is valid, control the switching power supply circuit to turn on in response to the first valid clock edge of the selection clock signal to supply power to the phase detection core circuit, thereby starting the phase detection core circuit in a controllable preset initial phase state.

2. The controllable phase frequency detector according to claim 1, characterized in that: The control circuit includes a first D flip-flop, wherein a clock input terminal of the first D flip-flop is connected to the strobe clock signal, a data input terminal of the first D flip-flop is connected to the enable signal, and the first D flip-flop has a first output terminal and a second output terminal that are mutually inverted; The switching power supply circuit includes a first switch and a second switch, wherein the first switch is controlled by the first output terminal to connect the power supply voltage to the power supply terminal of the phase detection core circuit, and the second switch is controlled by the second output terminal to ground the power supply terminal of the phase detection core circuit.

3. The controllable phase frequency detector according to claim 2, characterized in that: The clock selection circuit is a multiplexer.

4. The controllable phase frequency detector according to any one of claims 1 to 3, characterized in that: The output signal of the phase detection core circuit includes a first output signal and a second output signal; The phase detection core circuit includes: a second D flip-flop, wherein a clock input terminal thereof is connected to the reference clock signal, a data input terminal thereof is connected to a power supply voltage, and a data output terminal thereof generates the first output signal; a third D flip-flop, whose clock input terminal is connected to the feedback clock signal, whose data input terminal is connected to the power supply voltage, and whose data output terminal generates the second output signal; and A reset logic circuit, whose two input terminals are respectively connected to the data inverting output terminals of the second D flip-flop and the third D flip-flop, is used to generate a common reset signal when the first output signal and the second output signal are both at a high level, and apply the common reset signal to the reset terminals of the second D flip-flop and the third D flip-flop.

5. The controllable phase frequency detector according to claim 4, characterized in that: When the clock selection signal selects the reference clock signal as the gate clock signal, the phase detection core circuit is activated and first generates the first output signal; When the clock selection signal selects the feedback clock signal as the gate clock signal, the phase detection core circuit first generates the second output signal after being started.

6. The controllable phase frequency detector according to claim 4, characterized in that: The reset logic circuit is a NOR gate.

7. A phase-locked loop, characterized in that: include: The controllable phase frequency detector according to any one of claims 1 to 6, configured to receive a reference clock signal and a feedback clock signal, and generate an output signal related to a phase difference between the reference clock signal and the feedback clock signal; a charge pump, an input terminal of which is connected to the output terminal of the controllable phase frequency detector and configured to generate a current pulse according to the output signal; a loop filter having an input terminal connected to an output terminal of the charge pump and configured to smooth the current pulses to generate a control voltage; a voltage-controlled oscillator, an input terminal of which is connected to the output terminal of the loop filter and configured to generate an output clock signal according to the control voltage; as well as The frequency divider, whose input terminal is connected to the output terminal of the voltage controlled oscillator, is configured to divide the output clock signal to generate the feedback clock signal, and provide the feedback clock signal to the input terminal of the controllable phase frequency detector.

8. The phase-locked loop according to claim 7, wherein: The output signal of the controllable phase frequency detector includes an UP signal for controlling the charging of the charge pump and a DN signal for controlling the discharging of the charge pump; In the controllable phase and frequency detector, the reference clock signal is configured to trigger the UP signal; The clock selection circuit of the controllable phase and frequency detector is configured to select the reference clock signal as the gated clock signal according to the clock selection signal.

9. The phase-locked loop according to claim 7, wherein: The output signal of the controllable phase frequency detector includes an UP signal for controlling the charging of the charge pump and a DN signal for controlling the discharging of the charge pump; In the controllable phase and frequency detector, the feedback clock signal is configured to trigger the UP signal; The clock selection circuit of the controllable phase and frequency detector is configured to select the feedback clock signal as the gated clock signal according to the clock selection signal.

10. A communication device, characterized in that: Comprising a phase-locked loop according to any one of claims 7-9.

Images