A multi-network port dynamic redundancy switching method and system for an ARM host

Abstract

The application relates to the technical field of data processing, and discloses a multi-network-port dynamic redundancy switching method and system for an ARM host controller. The method comprises the following steps: collecting network states by an ARM host controller hardware counter to construct a four-dimensional vector, decoupling and distributing dimensions by using a heterogeneous multi-core architecture, predicting the state of each dimension by using a NEON instruction set parallel Kalman filtering algorithm, obtaining a comprehensive prediction result and a confidence interval by a covariance cross-fusion mechanism, and realizing predictive network interface switching based on a dynamic event triggering mechanism of the confidence interval. The application solves the technical problems of long switching delay, poor judgment accuracy and lack of predictive switching capability in the existing multi-network-port redundancy switching method of the ARM host controller.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method and system for dynamic redundant switching of multiple network ports for an ARM main controller. Background Art

[0002] Prior art multi-port redundant switching methods for ARM controllers primarily employ a passive response switching strategy based on threshold detection. These strategies periodically monitor the connectivity of network interfaces. Upon detecting a failure or performance degradation on the primary network interface, the controller initiates a switching process to redirect network traffic to the backup interface. Traditional solutions typically use simple ping tests or heartbeat detection mechanisms to determine network status, employing fixed switching thresholds and single-dimensional network quality assessment methods. Switching decisions are based on a snapshot of the current network status, and the switching process relies on software-level routing table modifications and application-layer connection reestablishment.

[0003] However, existing technologies have significant technical flaws. First, there is the significant issue of switching delay. Traditional passive response methods require waiting for a network failure to actually occur before initiating the switching process, resulting in the switching process typically taking several to tens of seconds to complete. This is unable to meet the requirements of application scenarios with high real-time requirements, such as industrial control. Secondly, the switching judgment accuracy is insufficient. Simple ping tests or heartbeat detection mechanisms are easily affected by instantaneous network fluctuations and lead to misjudgments. They lack the ability to comprehensively evaluate and predict trends in multiple dimensions of network quality, leading to unnecessary switching or delayed switching timing. In addition, existing solutions lack in-depth optimization of the hardware characteristics of ARM processors, fail to fully utilize the advantages of ARM's multi-core architecture and NEON instruction set for parallel processing, and have limited overall processing efficiency and response speed.

[0004] The fundamental problem with existing technologies is the lack of predictive switching capabilities and intelligent decision-making mechanisms, making it impossible to make advance judgments and prepare for network failures. Therefore, key technical challenges remain, including how to build a proactive switching method based on network status prediction, how to leverage the ARM multi-core architecture for efficient parallel network status analysis, and how to establish an accurate multi-dimensional network quality assessment and fusion mechanism. Furthermore, because network status prediction involves complex time series data analysis and multi-dimensional information fusion, traditional single-core serial processing methods face bottlenecks in computational efficiency and real-time performance. There is an urgent need to design parallel prediction algorithms optimized specifically for the ARM architecture, while also establishing dynamic event triggering mechanisms to achieve a fundamental shift from passive response to active prediction. Summary of the Invention

[0005] The present application provides a multi-network port dynamic redundant switching method and system for an ARM main controller, which is used to solve the problems of prolonged switching time, poor judgment accuracy and lack of predictive switching capability in the existing multi-network port redundant switching method of the ARM main controller.

[0006] In the first aspect, the present application provides a dynamic redundant switching method for multiple network ports of an ARM main controller, and the dynamic redundant switching method for multiple network ports of an ARM main controller includes: collecting and processing real-time status parameters of each network interface through the hardware counter of the ARM main controller to obtain a four-dimensional network state vector including network delay time, packet loss rate, bandwidth utilization and network jitter value; performing dimension decoupling and distribution processing on the four-dimensional network state vector according to the heterogeneous multi-core architecture characteristics of the ARM processor to obtain independent processing cores corresponding to the four network state dimensions; performing predictive calculation processing on each independent processing core through the parallel Kalman filtering algorithm of the ARM NEON instruction set to obtain a state prediction value and prediction error covariance of each dimension; performing optimal weighted fusion processing on the state prediction value and prediction error covariance of each dimension according to the covariance cross-fusion mechanism to obtain a fused four-dimensional network state prediction result and a comprehensive confidence interval; performing predictive switching decision processing on the network interface through a dynamic event trigger mechanism based on the comprehensive confidence interval to obtain a network interface switching instruction and execute a traffic redirection operation.

[0007] In a second aspect, the present application provides a multi-network port dynamic redundant switching system for an ARM main controller, the multi-network port dynamic redundant switching system for an ARM main controller comprising:

[0008] The acquisition module is used to collect and process the real-time status parameters of each network interface through the hardware counter of the ARM main controller, and obtain a four-dimensional network state vector including network delay time, packet loss rate, bandwidth utilization and network jitter value;

[0009] A decoupling module is used to perform dimension decoupling and distribution processing on the four-dimensional network state vector according to the heterogeneous multi-core architecture characteristics of the ARM processor, thereby obtaining independent processing cores corresponding to the four network state dimensions;

[0010] The prediction module is used to perform prediction calculations on each independent processing core using the parallel Kalman filter algorithm of the ARM NEON instruction set to obtain the state prediction value and prediction error covariance of each dimension;

[0011] The fusion module is used to perform optimal weighted fusion processing on the state prediction value and prediction error covariance of each dimension according to the covariance cross fusion mechanism to obtain the fused four-dimensional network state prediction result and comprehensive confidence interval;

[0012] The switching module is used to perform predictive switching decision processing on the network interface through a dynamic event triggering mechanism based on the comprehensive confidence interval, obtain a network interface switching instruction and perform a traffic redirection operation.

[0013] In a third aspect, a multi-network port dynamic redundant switching device for an ARM main controller is provided, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the multi-network port dynamic redundant switching device for the ARM main controller executes the above-mentioned multi-network port dynamic redundant switching method for the ARM main controller.

[0014] In a fourth aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium. When the computer-readable storage medium is run on a computer, the computer executes the above-mentioned multi-network port dynamic redundant switching method for an ARM main controller.

[0015] The technical solution provided in this application uses the hardware counters of the ARM main controller to collect and process real-time status parameters of each network interface to obtain a four-dimensional network state vector. Compared with traditional single-dimensional network monitoring methods, it can comprehensively capture key performance indicators such as network delay time, packet loss rate, bandwidth utilization, and network jitter value, providing a complete data foundation for subsequent predictive analysis. Based on the heterogeneous multi-core architecture characteristics of the ARM processor, the four-dimensional network state vector is dimensionally decoupled and distributed, fully leveraging the computing advantages of the high-performance Cortex-A78 core and the high-efficiency Cortex-A55 core to achieve parallel processing of network state analysis, significantly improving computing efficiency and response speed. The parallel Kalman filter algorithm of the ARM NEON instruction set is used to perform predictive calculations on each independent processing core, converting traditional scalar operations into vectorized parallel operations. The single prediction calculation time is controlled within 50 microseconds, which is 16 times more efficient than traditional methods. At the same time, the recursive nature of the Kalman filter algorithm can accurately predict future network states based on historical data and current measurements, solving the fundamental problem of lack of predictive ability in existing technologies.

[0016] Based on the covariance cross-fusion mechanism, the state prediction values ​​and prediction error covariances of each dimension are optimally weighted and fused. The mathematical optimality of the fusion result is ensured by the information theory principle of optimal weight allocation. The fused four-dimensional network state prediction results and comprehensive confidence intervals provide a quantitative uncertainty assessment for switching decisions, avoiding the problem of false switching caused by fixed threshold judgments in traditional methods. Based on the comprehensive confidence interval, a dynamic event triggering mechanism is used to make predictive switching decisions for network interfaces. When the probability of performance degradation of the primary network interface within the next 500 milliseconds exceeds 80%, the switching preparation process is initiated in advance, achieving a fundamental shift from passive response to active prediction. The entire switching process, from triggering to completion, is controlled within 50 milliseconds, reducing latency by over 90% compared to traditional passive switching methods. Especially in application areas such as smart manufacturing and industrial control that have extremely high requirements for network real-time performance, the parallel Kalman filter algorithm of the ARM NEON instruction set can fully utilize the SIMD computing capabilities of the ARM processor, and simultaneously process the prediction calculations of multiple network status dimensions through vectorized operations, while the covariance cross-fusion mechanism ensures the optimal integration of multi-dimensional information. The synergistic effect of these algorithmic features enables the network redundancy switching system to complete complex status prediction and decision-making within milliseconds, meeting the strict timing requirements of real-time control of production lines and equipment collaborative operations, and effectively avoiding the risk of production downtime and data loss due to network interruptions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a schematic diagram of an embodiment of a method for dynamic redundant switching of multiple network ports of an ARM main controller in an embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of an embodiment of a multi-network port dynamic redundant switching system for an ARM main controller in an embodiment of the present application;

[0020] Figure 3 This is a schematic block diagram of the structure of a multi-network port dynamic redundant switching device for an ARM main controller in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The embodiments of the present application provide a multi-network port dynamic redundant switching method and system for an ARM main controller. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] For ease of understanding, the specific process of the embodiment of the present application is described below. Figure 1 In one embodiment of the present application, a method for dynamic redundant switching of multiple network ports of an ARM main controller includes:

[0023] Step S101: Real-time state parameter collection and processing of each network interface is performed through the hardware counter of the ARM main controller to obtain a four-dimensional network state vector including network delay time, packet loss rate, bandwidth utilization and network jitter value;

[0024] Step S102: Decouple and distribute the four-dimensional network state vector according to the heterogeneous multi-core architecture characteristics of the ARM processor to obtain independent processing cores corresponding to the four network state dimensions;

[0025] Step S103: Perform prediction calculations on each independent processing core using the parallel Kalman filter algorithm of the ARM NEON instruction set to obtain a state prediction value and prediction error covariance for each dimension;

[0026] Step S104: performing optimal weighted fusion processing on the state prediction value and prediction error covariance of each dimension according to the covariance cross fusion mechanism to obtain the fused four-dimensional network state prediction result and comprehensive confidence interval;

[0027] Step S105: Based on the comprehensive confidence interval, a predictive switching decision is made on the network interface through a dynamic event triggering mechanism to obtain a network interface switching instruction and execute a traffic redirection operation.

[0028] It is understandable that the execution subject of this application can be a multi-network port dynamic redundant switching system for an ARM main controller, or a terminal or a server, which is not limited here. The embodiment of this application is described by taking a server as the execution subject as an example.

[0029] Specifically, the ARM main controller uses its built-in hardware performance monitoring unit to collect network status data. The network delay time is obtained by sending an ICMP echo request message to the gateway and calculating the round-trip time. Assuming that the sending time is T1 and the receiving time is T2, the delay time is T2 minus T1. The data packet loss rate is calculated by the ratio of the sending packet counter and the receiving confirmation packet counter counted by the network interface driver layer. If 1,000 data packets are sent and 980 confirmation packets are received, the packet loss rate is 2%. The bandwidth utilization is calculated by reading the byte counter of the network interface and dividing it by the nominal bandwidth of the interface. When the gigabit network port transmits 500MB of data in 1 second, the utilization rate is 40%. The network jitter value is calculated by the standard deviation of ten consecutive delay measurements, and these four values ​​are assembled into a four-dimensional vector.

[0030] The ARM controller recognizes its Cortex-A78 high-performance cores and Cortex-A55 high-efficiency core configuration. The four-dimensional network state vector is decomposed, with latency and bandwidth utilization allocated to the computationally powerful A78 cores, while packet loss and jitter are allocated to the power-optimized A55 cores. Each core is allocated 1KB of dedicated cache space in shared memory, with 64-byte cache line alignment ensuring efficient data access. A cache-coherent interconnect ensures inter-core data synchronization latency within 1 microsecond.

[0031] A parallel Kalman filter algorithm optimized with the ARM NEON instruction set is used. Each core initializes a one-dimensional Kalman filter, setting the initial state value, covariance matrix, process noise variance, and measurement noise variance. For the latency dimension, the initial state value is set to 10ms, the covariance is set to 1.0, the process noise variance is set to 0.1, and the measurement noise variance is set to 0.5. The NEON instruction set's four-element floating-point data type converts scalar operations into vector operations, allowing the state prediction equation and covariance prediction to be executed simultaneously. The prediction results are atomically written to each core's dedicated memory area using ARM exclusive access instructions to ensure data consistency.

[0032] Perform covariance cross-fusion processing. The ARM main controller core reads the prediction data for four dimensions, including the state prediction value and the prediction error covariance. The covariance cross-fusion mechanism calculates the optimal fusion weight for each dimension, with the weight ratio determined based on the inverse relationship between the prediction error covariances of each dimension. Assuming the covariance of the delay dimension is 0.8 and the covariance of the packet loss rate dimension is 0.3, the packet loss rate dimension has a higher weight in the fusion. A weighted summation calculation produces the fused four-dimensional network state prediction result, and the comprehensive prediction error covariance is calculated simultaneously. Based on the normal distribution characteristics of the fused covariance, a confidence interval is calculated to quantify the credibility of the prediction result.

[0033] Predictive switching decisions are made based on comprehensive confidence intervals. A dynamic event triggering mechanism calculates the probability of performance degradation on the primary network interface within the next 500 milliseconds. When the probability of the predicted delay exceeding 100ms reaches 80%, pre-switching preparation is triggered. The ARM master controller performs a rapid quality assessment on the backup network interface, checking the physical connection status, IP address configuration, and routing table reachability. After the assessment passes, pre-switching preparation operations are performed, including establishing a TCP connection preheat on the backup interface, preloading the DNS cache, and synchronizing the application layer session state. When the actual measurement value of the primary network interface confirms that it has reached the switching threshold, the ARM master controller modifies the Linux kernel routing table and redirects data traffic to the backup interface. The entire switching process is completed within 50 milliseconds.

[0034] In a specific embodiment, the process of executing step S101 may specifically include the following steps:

[0035] Create a network status monitoring module in the Linux kernel space of the ARM main controller, read and process the hardware counter data of each network interface, and obtain the original network statistics;

[0036] Based on the ICMP echo request message, the round-trip time measurement is performed on the gateway device to obtain the network delay time;

[0037] The packet loss rate is obtained by calculating the ratio of the number of packets sent and the number of received confirmation packets of the network interface to the packet loss statistics.

[0038] The bandwidth utilization is calculated by dividing the value of the network interface traffic statistics counter by the nominal bandwidth of the interface.

[0039] The standard deviation of ten consecutive delay measurement values ​​is calculated to obtain the network jitter value, and the network delay time, packet loss rate, bandwidth utilization and network jitter value are assembled into a four-dimensional network state vector.

[0040] Specifically, the network status monitoring module of the ARM master is created in the Linux kernel space, which directly accesses the hardware counter data structure of the network interface driver layer. The hardware counter is a statistical register built-in the network interface chip, which records the raw statistical information such as the number of sent bytes, the number of received bytes, the number of sent packets, the number of received packets, etc. The monitoring module obtains these counter values by reading the network interface statistical files under the proc file system or calling the netlink socket interface, and stores the read raw data in the kernel memory buffer. When measuring the delay by ICMP echo request message, the ARM master creates a raw socket through the socket programming interface, constructs an ICMP Echo Request packet and records the sending timestamp. After the packet is sent to the gateway device, the gateway automatically returns an ICMP Echo Reply response packet, and the ARM master records the receiving timestamp when receiving the response packet. The network delay time is equal to the difference between the receiving timestamp and the sending timestamp, which includes the transmission time of the packet in the network and the processing time of the gateway device. To ensure the accuracy of the measurement, the ARM master continuously sends multiple ICMP packets and calculates the average delay value as the current network delay time.

[0041] The packet loss rate calculation is based on the sending packet counter and the received acknowledgement packet counter values in the network interface hardware counter. The sending packet counter records the number of all data packets sent by the network interface, and the received acknowledgement packet counter records the number of received TCP ACK acknowledgement packets or other protocol acknowledgement responses. The packet loss rate calculation formula is one minus the ratio of the number of received acknowledgement packets divided by the number of sent packets. When the number of sent packets is greater than the number of received acknowledgement packets, it indicates that there is a data packet loss phenomenon. The ARM master reads the current values of these two counters every fixed time interval, and obtains the packet loss rate in the time period by calculating the incremental value between adjacent two readings. The bandwidth utilization rate calculation obtains the transmission byte number by reading the traffic statistical counter of the network interface, which records the total number of bytes transmitted through the network interface in a specific time window. The ARM master obtains the nominal bandwidth value of the network interface, which is the theoretical transmission rate of the network interface. The nominal bandwidth of the Ethernet interface is 10 Mbps, 100 Mbps or 1000 Mbps. The bandwidth utilization rate is equal to the actual transmission byte number multiplied by 8 to convert to bit number, then divided by the nominal bandwidth and divided by the time window length. The calculation result represents the current bandwidth usage degree of the network interface.

[0042] The network jitter value calculation needs ten continuous delay measurement values as input data, and the jitter reflects the change degree of network delay. The ARM master stores the ten continuous ICMP delay measurement results in an array, calculates the arithmetic mean of the ten values as the average delay. The standard deviation calculation process includes calculating the difference between each delay value and the average value, summing the squared difference, dividing by the sample size minus 1 to obtain the variance, and finally taking the square root of the variance to obtain the standard deviation, i.e. the network jitter value. The larger the jitter value, the more intense the network delay fluctuation, and the more unstable the network quality.

[0043] The four-dimensional network state vector assembly process arranges the network delay time, packet loss rate, bandwidth utilization rate and network jitter value in order to form a vector data structure. The ARM master allocates continuous storage space in the memory to store the four values, each value occupying 4 bytes of floating point number format, and the total length of the vector is 16 bytes. The vector data structure facilitates subsequent dimension decoupling allocation processing and parallel computing operation, and each dimension data is quickly accessed and modified through the index position.

[0044] For example, the ARM master monitoring module first reads the hardware counters of the Ethernet interface, obtains the current value of the sending packet counter as 50000, the receiving acknowledgment packet counter as 49000, and the flow counter displays that 480MB data has been transmitted. The monitoring module sends an ICMP packet to the gateway, records the high-precision timestamp of the sending time, records the receiving time timestamp when the reply packet is received, and the delay value is obtained by subtracting the two timestamps. Ten continuous delay measurements respectively obtain the results of 12ms, 15ms, 11ms, 14ms, 13ms, 16ms, 12ms, 15ms, 14ms, and 13ms, the average value is 13.5ms, the difference between each measurement value and the average value is -1.5, 1.5, -2.5, 0.5, -0.5, 2.5, -1.5, 1.5, 0.5, and -0.5, the sum of the squared differences is 22.5, the variance is 2.5, and the standard deviation, i.e. the jitter value, is 1.58ms. The packet loss rate calculation obtains 50000 minus 49000 divided by 50000 equal to 0.02, and the bandwidth utilization rate calculation obtains 480MB multiplied by 8 divided by 1000Mbps divided by 1 second equal to 0.384. The ARM master assembles the delay time 13.5ms, the packet loss rate 0.02, the bandwidth utilization rate 0.384, and the jitter value 1.58ms into a four-dimensional vector [13.5, 0.02, 0.384, 1.58] and stores it in the memory.

[0045] In a specific embodiment, the process of performing step S102 can specifically include the following steps:

[0046] Identify the core type configuration of the processor at the multi-core management layer of the ARM main controller, classify the high-performance Cortex-A78 core and the high-efficiency Cortex-A55 core, and obtain the heterogeneous core resource distribution;

[0047] The network delay time and bandwidth utilization in the four-dimensional network state vector are allocated to the high-performance Cortex-A78 core for processing and binding, thereby obtaining independent processing cores in the delay dimension and independent processing cores in the bandwidth dimension.

[0048] The packet loss rate and network jitter value in the four-dimensional network state vector are assigned to the high-efficiency Cortex-A55 core for processing and binding, resulting in independent processing cores for the packet loss rate dimension and independent processing cores for the jitter dimension.

[0049] In the shared memory area of ​​the ARM main controller, 1KB of dedicated cache space is allocated to each independent processing core for memory alignment, resulting in a core-specific storage area aligned with 64-byte cache lines;

[0050] The inter-core communication interface configuration of each independent processing core is processed through ARM's cache coherent interconnection, and an inter-core data synchronization mechanism with a delay controlled within 1 microsecond is obtained.

[0051] Specifically, the ARM master controller's multi-core management layer identifies the type and configuration information of each core by reading the processor's MIDR and MPIDR registers. The MIDR register stores processor identification information, including the core architecture type and version number, while the MPIDR register records the multi-processor affinity identifier, indicating the location of each core in the cluster. The multi-core management layer parses these register values ​​to distinguish the distribution of high-performance Cortex-A78 cores and energy-efficient Cortex-A55 cores, and stores the identification results in the core topology data structure. The heterogeneous core resource distribution data structure records each core's type identification, core number, cluster to which it belongs, and frequency range, forming a complete mapping table of the processor cores.

[0052] The four-dimensional network state vector is allocated based on a matching principle between computational complexity and core characteristics. Calculating network latency and bandwidth utilization involves floating-point operations and statistical analysis, requiring significant computational power, and is therefore assigned to the high-performance Cortex-A78 core. Calculating packet loss rate and network jitter is relatively simple, primarily involving basic arithmetic and logical analysis, making it suitable for processing on the energy-efficient Cortex-A55 core. The ARM controller binds specific processing tasks to specific core types by setting CPU affinity masks. An independent processing core for the latency dimension is dedicated to latency-related Kalman filter calculations, while an independent processing core for the bandwidth dimension handles bandwidth utilization prediction and analysis. Independent processing cores for packet loss rate and jitter perform data processing tasks for their respective dimensions on the A55 core. Dedicated cache space in shared memory areas is allocated by calling the mmap system call to allocate contiguous memory blocks in physical memory. Each independent processing core is allocated 1KB (1024 bytes) of dedicated space. Memory alignment ensures that the starting address of each cache space is an integer multiple of 64 bytes. Since the cache line size of ARM processors is 64 bytes, aligned memory accesses avoid cross-cache line reads and writes. The core-specific storage area is divided into a state data area, a covariance data area, a historical data area, and a prediction result area according to data type. The memory layout of each area follows the 64-byte alignment principle. Memory alignment is performed by calculating the modulo operation of the memory address with 64. If the modulo operation result is not zero, the address is adjusted upward to the next 64-byte boundary.

[0053] The cache coherent interconnect configuration uses ARM's AMBA protocol to synchronize data between independent processing cores. The AMBA protocol includes the AXI bus interface and the ACE extension, which specifically handles cache coherence issues between multiple cores. When a core modifies data in shared memory, the cache coherent interconnect automatically sends an invalidation signal to other cores to ensure that all cores see the latest version of the data. The inter-core communication interface configuration includes setting bus arbitration priority, configuring cache policies, and establishing data transmission channels. Each core has an independent AXI master interface connected to the shared memory controller. The data synchronization mechanism's delay control is achieved by optimizing the bus clock frequency and reducing the arbitration wait time to ensure that the inter-core data transmission delay remains within 1 microsecond.

[0054] In a specific embodiment, the process of executing step S103 may specifically include the following steps:

[0055] Initialization parameter configuration processing is performed on the one-dimensional Kalman filter on each independent processing core to obtain a filter parameter set including an initial state value, an initial covariance matrix, a process noise variance, and a measurement noise variance;

[0056] The state prediction equation of the Kalman filter is vectorized and processed based on the four-element floating-point data type of the ARM NEON instruction set to obtain the one-step predicted state value of each dimension;

[0057] The covariance prediction matrix operation is parallelized and multiplied by NEON parallel multiplication instructions to obtain the one-step prediction error covariance of each dimension;

[0058] The prediction results of each independent processing core are written into the core dedicated storage area for atomic storage processing to obtain dimensional prediction data including the prediction state value and prediction error covariance;

[0059] The ARM-based memory prefetch instruction performs memory prefetching on the historical data of the next computing cycle, obtains the network status historical data preloaded into the first-level cache, and outputs the state prediction value and prediction error covariance of each dimension.

[0060] Specifically, the initialization parameters of the one-dimensional Kalman filter for each independent processing core are configured with different values ​​based on the characteristics of the network state dimension. The initial state value in the delay dimension is set to the average of historical delay measurements. The initial covariance matrix reflects the uncertainty of the initial state estimate, with larger values ​​indicating greater uncertainty. The process noise variance describes the randomness of network delay variations over time. The process noise variance in the bandwidth dimension is typically larger than that in the delay dimension because bandwidth fluctuates more frequently. The measurement noise variance reflects the accuracy limitations of the measurement equipment. The noise variance of ICMP delay measurements is related to the complexity of the network path. The filter parameter set is stored in a dedicated memory area on each core and includes key data structures such as the state vector, covariance matrix, noise parameters, and gain coefficients. The ARM NEON instruction set's four-element floating-point data type allows a single processor instruction to operate on four 32-bit floating-point numbers simultaneously. The Kalman filter's state prediction equation involves matrix multiplication and vector addition operations. The state prediction calculation multiplies the current state estimate by the state transition matrix and adds the control input. The NEON instruction set converts these scalar operations into vector operations to process multiple data elements simultaneously. The one-step predicted state values ​​for each dimension are generated synchronously through vectorized computation. The latency and bandwidth dimensions are computed in parallel on the A78 core, while the packet loss rate and jitter dimensions are processed in parallel on the A55 core. During the vectorized computation, NEON registers are simultaneously loaded with four state values ​​and four transfer coefficients, completing a calculation that would otherwise require four separate operations with a single multiply-add instruction.

[0061] NEON parallel multiplication instructions simultaneously load multiple elements of the covariance matrix into NEON registers when processing covariance prediction matrix operations. Covariance prediction calculations involve complex operations such as matrix transposition, matrix multiplication, and matrix addition. Traditional scalar calculations require element-by-element matrix operations. The NEON instruction set packages the covariance matrix into vector data by row or column, using vector multiplication instructions to simultaneously calculate the product of multiple matrix elements. The covariance of the one-step prediction error in each dimension is obtained through parallel multiplication operations, and the calculation results reflect the degree of uncertainty in the predicted state. The diagonal elements of the covariance matrix represent the variance of each state component, while the off-diagonal elements represent the covariance relationship between different state components.

[0062] When each independent processing core writes the prediction results to the core-dedicated storage area, ARM's atomic store instructions are used to ensure data integrity. Atomic store instructions include paired operations of exclusive load and exclusive store. The exclusive load instruction locks the target memory address and marks it as exclusive access state. The prediction state value and prediction error covariance are encapsulated into a data packet according to a predefined data structure format. The data packet contains fields such as timestamp, dimension identifier, and prediction value. The exclusive store instruction checks the exclusive state of the memory address and only performs the write operation if the exclusive state has not been destroyed by other cores. The storage operation of the dimension prediction data includes three atomic steps: state check, data write, and state clear, to ensure that there will be no race conditions when the data is accessed concurrently by multiple cores.

[0063] ARM's memory prefetch instructions preload historical data needed for the next cycle into the processor cache while the current computation cycle is executing. Memory prefetching predicts the data address required for the next computation based on the access pattern of network state data. The prefetch instruction moves the data at the specified address from main memory to the first-level cache. Historical network state data consists of measured and predicted values ​​from several past time windows, stored in chronological order in a circular buffer. Data preloaded into the first-level cache avoids cache miss delays during the next access. The Kalman filter algorithm requires historical state values ​​and historical covariance values ​​for recursive calculations. The state prediction value and prediction error covariance for each dimension serve as the output of the current computation cycle and simultaneously become the input data for the next computation cycle.

[0064] For example, the independent processing core for the latency dimension reads the initial state value and covariance matrix from a dedicated memory area. The initial state value is set based on the latency measurement at the previous moment, and the covariance matrix reflects the confidence level in the current state estimate. The NEON instruction set vectorizes the multiplication operations in the state prediction equation, simultaneously calculating the product of the state value and the state transition coefficient, as well as the product of the covariance matrix and the transition matrix. During the covariance prediction process, NEON parallel multiplication instructions simultaneously process multiple elements of the covariance matrix, allowing matrix operations that would otherwise require multiple cycles to be completed in a single pass through vectorized instructions. The prediction results are written to the core's dedicated memory area using exclusive store instructions. The storage process includes address calculation, exclusive locking, data writing, and lock release. Memory prefetch instructions preload the state and measurement values ​​required for the next computation cycle into the L1 cache based on the address pattern of historical data. This ensures that the data is ready when the next computation begins, avoiding memory access delays.

[0065] In a specific embodiment, the step of writing the prediction results of each independent processing core into the core-specific storage area for atomic storage processing may specifically include the following steps:

[0066] Perform memory address calculation on the prediction result data on each independent processing core to obtain the target write address of the core dedicated storage area;

[0067] Based on the ARM exclusive access instruction, the core dedicated storage area is exclusively locked to obtain exclusive access rights;

[0068] The state prediction value and the prediction error covariance are encapsulated in a 64-byte aligned format to obtain a dimension prediction data packet;

[0069] The dimension prediction data packet is atomically written using ARM exclusive storage instructions to obtain the prediction result data that has been persistently stored.

[0070] Based on the ARM memory barrier instruction, the write operation is synchronously confirmed, the write completion flag is obtained and the exclusive access right is released, and the dimensional prediction data including the predicted state value and the prediction error covariance is output.

[0071] Specifically, when each independent processing core calculates the memory address of the prediction result data, it determines the storage location based on the core identifier and data type. The memory address calculation includes two steps: base offset calculation and alignment adjustment. The base offset is obtained by multiplying the core number by the size of the storage space allocated to each core. The 1KB storage space allocated to each core forms a continuous address segment in the shared memory. The address calculation algorithm uses the core identifier as the index value, multiplies it by the offset of 1024 bytes, and adds it to the starting base address of the shared memory to obtain the starting address of the core-specific storage area. The target write address also needs to take into account the offset of the data type. The state prediction value and the prediction error covariance occupy different positions in the storage area. The specific write offset address is calculated by the data type identifier.

[0072] ARM exclusive access instructions use the LDREX and STREX instruction pairs to implement atomic access control when locking core-specific memory areas. Exclusive access instructions operate on the ARM processor's exclusive monitor hardware unit, which tracks the exclusive access status of each processor core to a specific memory address. The LDREX instruction sets the exclusive monitor flag while reading the target address data, recording the current core's exclusive access to that address. Exclusive locking ensures that only one core in a concurrent multi-core environment can modify a specific memory area. Access requests from other cores are blocked at the hardware level until exclusive access is released. Acquiring exclusive access involves three atomic steps: address checking, state setting, and permission confirmation.

[0073] When encapsulating the state prediction value and prediction error covariance in a 64-byte aligned format, the cache line size characteristics of the ARM processor must be considered. The 64-byte alignment format ensures that the starting address of the data structure is an integer multiple of 64, preventing access efficiency degradation caused by data spanning multiple cache lines. Data encapsulation packages the state prediction value, prediction error covariance, timestamp, and dimension identifier into a unified data structure, adjusting the total length of the data structure to an integer multiple of 64 bytes. A dimension prediction data packet consists of a data header and a data payload. The header stores metadata information such as the data type, timestamp, and checksum, while the payload stores the actual predicted value. During the data encapsulation process, blank bytes are padded to the end of the data structure to ensure that the total length meets the alignment requirements.

[0074] The ARM exclusive store instruction, STREX, checks the exclusive monitor status flag when atomically writing a dimension prediction packet. Atomic write processing ensures that the packet write operation is either completely successful or completely unsuccessful, with no intermediate states of partial writes. The STREX instruction checks the exclusive status of the target address before executing the write operation. The actual memory write is performed only when the exclusive status is valid, and the exclusive monitor flag is automatically cleared after the write is complete. Persistently stored prediction result data remains stable in shared memory, and other cores can obtain the latest prediction results through read operations. The success of the atomic write is determined by the return value of the STREX instruction. A return value of 0 indicates a successful write, while a non-zero value indicates a write failure and requires a retry.

[0075] ARM memory barrier instructions ensure the order and visibility of memory operations when synchronizing and confirming write operations. Memory barrier instructions include two types: data synchronization barriers (DSBs) and data memory barriers (DMBs). DSBs ensure that all memory operations before the barrier are completed before operations after the barrier are executed. DMBs ensure the visibility order of memory operations across different processor cores. Synchronization confirmation processing includes two steps: a write completion check and cache consistency maintenance. The write completion check verifies that the data has been flushed from the processor cache to main memory, while cache consistency maintenance ensures that other cores can see the latest data content. The write completion flag is obtained by checking the execution status of the memory barrier instruction. Once the flag is set, the previously acquired exclusive access rights are released, allowing other cores to access the storage area. The output of the dimensional prediction data includes the predicted state value and the prediction error covariance. The data format is consistent with the input four-dimensional network state vector, facilitating subsequent fusion processing.

[0076] In a specific embodiment, the process of executing step S104 may specifically include the following steps:

[0077] The prediction data of each dimension is read and aggregated on the main core of the ARM main controller to obtain a prediction data set containing the four-dimensional state prediction values ​​and prediction error covariance;

[0078] According to the covariance cross fusion weight calculation rule, the prediction error covariance of each dimension is calculated by weight ratio to obtain the optimal fusion weight coefficient of each dimension in the fusion process;

[0079] The state prediction value of each dimension is weighted and summed with the corresponding optimal fusion weight coefficient to obtain the fused four-dimensional network state prediction result;

[0080] Based on the inverse of the prediction error covariance of each dimension and the inverse operation of the fusion covariance, the fused comprehensive prediction error covariance is obtained;

[0081] The confidence interval is processed by normal distribution calculation according to the fused comprehensive prediction error covariance to obtain the comprehensive confidence interval, and the fused four-dimensional network state prediction result and the comprehensive confidence interval are output.

[0082] Specifically, when the main core of the ARM main controller reads and aggregates the prediction data of each dimension, it obtains the prediction results by traversing the dedicated storage areas of the four independent processing cores. The reading and aggregation processing includes three steps: address positioning, data extraction, and format conversion. The main core calculates the address offset of each dedicated storage area according to the core number, and accesses the storage space of the delay dimension, packet loss rate dimension, bandwidth dimension, and jitter dimension in turn. During the data extraction process, the main core parses the data packet format of each storage area and extracts the state prediction value and prediction error covariance value from the 64-byte aligned data structure. The prediction data set is organized in the form of a structured array. The array contains four elements corresponding to the four network state dimensions, and each element contains fields such as the prediction value, covariance value, timestamp, and dimension identifier.

[0083] The covariance cross-fusion weight calculation rule is based on the optimal weight allocation theory in information theory. The prediction error covariance of each dimension reflects the uncertainty of the prediction result. The weight ratio calculation process uses the inverse of the covariance as the basis for weight calculation. The smaller the covariance value, the more reliable the prediction, and the larger the corresponding weight coefficient. The calculation process of the optimal fusion weight coefficient first calculates the inverse of the prediction error covariance of each dimension, and then divides each inverse value by the sum of all inverse values ​​to obtain the normalized weight coefficient. The weight coefficient ranges from 0 to 1, and the sum of the weight coefficients of all dimensions is equal to 1, ensuring the mathematical consistency of the fusion process. The weight distribution of each dimension in the fusion process reflects the difference in prediction quality. The dimension with high prediction accuracy obtains a greater weight, which affects the fusion result.

[0084] Vectorized operations are used to improve computational efficiency when performing a weighted summation of the state prediction values ​​of each dimension and the corresponding optimal fusion weight coefficients. The weighted summation process multiplies the prediction values ​​of the four dimensions by the corresponding weight coefficients, and then adds all the product results to obtain the fused prediction value. The fused four-dimensional network state prediction result maintains the same data structure as the original four-dimensional network state vector, including the fused delay time, packet loss rate, bandwidth utilization, and jitter value. The allocation of weight coefficients during the weighted summation process directly affects the characteristics of the fusion result. The prediction values ​​of high-weight dimensions dominate the fusion result, while the influence of low-weight dimensions is relatively small.

[0085] The calculation process for the inverse sum of the prediction error covariances for each dimension first takes the inverse of the covariance values ​​for each of the four dimensions, then adds all the inverse values ​​together to obtain the inverse sum. The inverse operation for the fused covariance is performed by taking the inverse of the inverse sum again to obtain the fused combined prediction error covariance value. The combined prediction error covariance reflects the overall uncertainty of the fused prediction result, with smaller values ​​indicating higher reliability. The mathematical principle behind this inverse operation is based on the theoretical foundation of the covariance cross-fusion algorithm, ensuring that the fused covariance meets optimality criteria. The calculated fused covariance provides uncertainty quantification parameters for the subsequent confidence interval calculation.

[0086] The covariance of the fused combined prediction error is calculated using a normal distribution to determine the bounds of the confidence interval. This normal distribution calculation is based on the statistical theory of confidence intervals, assuming that the fused prediction error follows a normal distribution. The confidence interval calculation involves two steps: determining the mean and the variance. The mean is the fused prediction value, and the variance is the covariance of the combined prediction error. The bounds of the combined confidence interval are determined by adding or subtracting a confidence coefficient from the fused prediction value multiplied by the square root of the covariance. The confidence coefficient is determined based on the desired confidence level. The confidence interval quantifies the credibility of the fused prediction result. The width of the interval reflects the uncertainty range of the prediction; a narrower interval indicates a more accurate prediction.

[0087] In a specific embodiment, the process of executing step S105 may specifically include the following steps:

[0088] Based on the comprehensive confidence interval, the probability of exceeding the threshold value of the future state of the main network interface is calculated to obtain the failure probability value of the main network interface experiencing performance degradation within 500 milliseconds;

[0089] The pre-switching trigger condition judgment result is obtained by comparing the fault probability value with the 80% probability threshold;

[0090] Based on the pre-switching trigger condition judgment result, a rapid quality assessment process is performed on the backup network interface to obtain a backup interface status report including physical connection status, IP address configuration status and routing table reachability;

[0091] Input the standby interface status report into the switching decision module for pre-switching preparation operation processing, and obtain a pre-switching preparation completion flag including TCP connection preheating, DNS cache preloading and session state synchronization;

[0092] When the actual measurement value of the main network interface reaches the switching threshold, the network traffic is redirected to the routing table, a network interface switching instruction is obtained, and the traffic redirection operation is completed.

[0093] Specifically, the cumulative probability density function of the normal distribution is used to calculate the probability of exceeding the threshold value of the future state of the main network interface based on the comprehensive confidence interval. The over-threshold probability calculation process uses the network performance threshold as the demarcation point to calculate the probability that the fusion prediction result exceeds the threshold. The calculation process of the fault probability value includes three steps: threshold setting, probability integration and result normalization. The threshold setting determines the critical values ​​of delay, packet loss rate, bandwidth utilization and jitter according to the network service quality requirements. The probability integral calculation uses the normal distribution function to integrate the confidence interval. The integration area is from the threshold to positive infinity. The integration result represents the probability that the predicted value exceeds the threshold. The 500-millisecond time window is based on the validity period of the network status prediction. The prediction accuracy outside this time range drops significantly. The fault probability value reflects the risk level of performance degradation of the main network interface within this time period.

[0094] The comparison and judgment process of the fault probability value and the 80% probability threshold uses a numerical comparison algorithm to determine whether to trigger the pre-switching process. The comparison and judgment process compares the calculated fault probability value with the preset 80% threshold. When the fault probability is greater than 80%, the judgment result is true, indicating that pre-switching preparation needs to be started. When the fault probability is less than or equal to 80%, the judgment result is false, indicating that monitoring continues without switching. The output format of the pre-switching trigger condition judgment result is a Boolean type value. The true value triggers the subsequent backup interface evaluation process, and the false value maintains the current monitoring status. The selection of the 80% probability threshold is based on the risk control strategy of network redundancy switching. This value balances the timeliness of pre-switching and the risk of false switching. Too low a threshold leads to frequent false switching, and too high a threshold affects the timeliness of switching.

[0095] The rapid quality assessment of the backup network interface based on the pre-switching trigger condition judgment results includes a multi-level status check process. The rapid quality assessment process checks the availability of the backup interface from three dimensions: the physical layer, the network layer, and the routing layer. The physical connection status check determines whether the interface has established a physical connection by reading the link status register of the network interface driver. The IP address configuration status check verifies whether the backup interface is assigned a valid IP address, subnet mask, and default gateway. The address information is obtained by parsing the network configuration file or calling the network configuration API. The routing table reachability check verifies the network connectivity of the backup interface by sending a test data packet to the target network. The target address of the test packet selects a key network node such as a DNS server or a default gateway. The data structure of the backup interface status report contains fields such as inspection items, inspection results, and timestamps. The report content provides a quantitative interface quality assessment for subsequent switching decisions.

[0096] After the backup interface status report is input into the switching decision module, the execution sequence of the pre-switching preparation operation is triggered. The switching decision module determines whether the backup interface meets the switching conditions based on the content of the status report. If the conditions are met, the pre-switching preparation process is initiated. If the conditions are not met, an error message is recorded and another backup interface is selected. The pre-switching preparation operation processing includes three parallel tasks: TCP connection warm-up, DNS cache preloading, and session state synchronization. TCP connection warm-up reduces the connection establishment time after the switch by establishing a TCP connection to the key server on the backup interface. DNS cache preloading copies the currently used domain name resolution results to the DNS cache of the backup interface to avoid domain name resolution delays after the switch. Session state synchronization backs up the currently active network session information to the session table of the backup interface, including TCP state information such as connection status, sequence number, and window size. The pre-switching preparation completion flag is generated by checking the execution status of the three tasks. The flag is set to true when all tasks are completed and set to false when any task fails.

[0097] The Linux kernel's netlink socket mechanism is used to redirect the routing table when the actual measured value of the primary network interface reaches the switching threshold. Routing table redirection involves three atomic operations: route entry deletion, route entry addition, and route table refresh. Route entry deletion uses a netlink message to remove the default route entry pointing to the primary network interface. Route entry addition modifies the default route's next hop address to the backup network interface's gateway address, setting the route priority to the highest to ensure the new route takes effect immediately. Network interface switching instructions are generated based on the successful status of the routing table modification. Successful modification generates a switch completion instruction; failure generates a switch failure instruction and triggers a rollback. Traffic redirection is performed through the kernel network protocol stack's route lookup mechanism. New network packets select the backup network interface as their egress port based on the updated routing table.

[0098] The above embodiment of the present application is used for the multi-network port dynamic redundant switching method of the ARM main controller. The following embodiment of the present application is used for the multi-network port dynamic redundant switching system of the ARM main controller. Figure 2 In one embodiment of the present application, a multi-network port dynamic redundant switching system for an ARM main controller includes:

[0099] The acquisition module is used to collect and process the real-time status parameters of each network interface through the hardware counter of the ARM main controller, and obtain a four-dimensional network state vector including network delay time, packet loss rate, bandwidth utilization and network jitter value;

[0100] A decoupling module is used to perform dimension decoupling and distribution processing on the four-dimensional network state vector according to the heterogeneous multi-core architecture characteristics of the ARM processor, thereby obtaining independent processing cores corresponding to the four network state dimensions;

[0101] The prediction module is used to perform prediction calculations on each independent processing core using the parallel Kalman filter algorithm of the ARM NEON instruction set to obtain the state prediction value and prediction error covariance of each dimension;

[0102] The fusion module is used to perform optimal weighted fusion processing on the state prediction value and prediction error covariance of each dimension according to the covariance cross fusion mechanism to obtain the fused four-dimensional network state prediction result and comprehensive confidence interval;

[0103] The switching module is used to perform predictive switching decision processing on the network interface through a dynamic event triggering mechanism based on the comprehensive confidence interval, obtain a network interface switching instruction and perform a traffic redirection operation.

[0104] above Figure 2 The multi-network port dynamic redundant switching system for the ARM main controller in the embodiment of the present invention is described in detail from the perspective of modular functional entities. The multi-network port dynamic redundant switching device for the ARM main controller in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0105] Reference Figure 3 In the embodiment of the present invention, a multi-network port dynamic redundant switching device for an ARM main controller is also provided. The multi-network port dynamic redundant switching device for an ARM main controller can be a server, and its internal structure can be as follows Figure 3 As shown. The multi-network port dynamic redundant switching device for the ARM main controller includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the computer-designed processor is used to provide computing and control capabilities. The memory of the multi-network port dynamic redundant switching device for the ARM main controller includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the multi-network port dynamic redundant switching device for the ARM main controller is used to store the corresponding data in this embodiment. The network interface of the multi-network port dynamic redundant switching device for the ARM main controller is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0106] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the multi-network port dynamic redundant switching device for the ARM main controller to which the solution of the present invention is applied.

[0107] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions. When the instructions are executed on a computer, the computer executes the steps of the multi-network port dynamic redundant switching method for an ARM main controller.

[0108] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0109] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a multi-network port dynamic redundant switching device for an ARM main controller (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0110] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A multi-network port dynamic redundant switching method for an ARM main controller, characterized in that: The method comprises: The hardware counters of the ARM main controller collect and process the real-time status parameters of each network interface to obtain a four-dimensional network state vector containing network delay time, packet loss rate, bandwidth utilization and network jitter value; According to the heterogeneous multi-core architecture characteristics of the ARM processor, the four-dimensional network state vector is dimensionally decoupled and distributed to obtain independent processing cores corresponding to the four network state dimensions; The parallel Kalman filter algorithm of the ARM NEON instruction set is used to perform prediction calculations on each independent processing core to obtain the state prediction value and prediction error covariance of each dimension; According to the covariance cross fusion mechanism, the state prediction value and prediction error covariance of each dimension are optimally weighted and fused to obtain the fused four-dimensional network state prediction result and comprehensive confidence interval; Based on the comprehensive confidence interval, a predictive switching decision process is performed on the network interface through a dynamic event triggering mechanism to obtain a network interface switching instruction and execute a traffic redirection operation.

2. The multi-network port dynamic redundant switching method for an ARM main controller according to claim 1, characterized in that: The hardware counter of the ARM main controller is used to collect and process the real-time status parameters of each network interface to obtain a four-dimensional network state vector including network delay time, data packet loss rate, bandwidth utilization and network jitter value, including: Create a network status monitoring module in the Linux kernel space of the ARM main controller, read and process the hardware counter data of each network interface, and obtain the original network statistics; Based on the ICMP echo request message, the round-trip time measurement is performed on the gateway device to obtain the network delay time; The packet loss rate is obtained by calculating the ratio of the number of packets sent and the number of received confirmation packets of the network interface to the packet loss statistics. The bandwidth utilization is calculated by dividing the value of the network interface traffic statistics counter by the nominal bandwidth of the interface. The standard deviation of ten consecutive delay measurement values ​​is calculated to obtain a network jitter value, and the network delay time, data packet loss rate, bandwidth utilization and network jitter value are assembled into a four-dimensional network state vector.

3. The multi-network port dynamic redundant switching method for an ARM main controller according to claim 1, characterized in that: The four-dimensional network state vector is dimensionally decoupled and distributed according to the heterogeneous multi-core architecture characteristics of the ARM processor to obtain independent processing cores corresponding to the four network state dimensions, including: Identify the core type configuration of the processor at the multi-core management layer of the ARM main controller, classify the high-performance Cortex-A78 core and the high-efficiency Cortex-A55 core, and obtain the heterogeneous core resource distribution; Allocating the network delay time and bandwidth utilization in the four-dimensional network state vector to the high-performance Cortex-A78 core for processing and binding, thereby obtaining an independent processing core for the delay dimension and an independent processing core for the bandwidth dimension; Assigning the packet loss rate and network jitter value in the four-dimensional network state vector to the high-efficiency Cortex-A55 core for processing and binding, thereby obtaining an independent processing core for the packet loss rate dimension and an independent processing core for the jitter dimension; In the shared memory area of ​​the ARM main controller, 1KB of dedicated cache space is allocated to each independent processing core for memory alignment, resulting in a core-specific storage area aligned with 64-byte cache lines; The inter-core communication interface configuration of each independent processing core is processed through ARM's cache coherent interconnection, and an inter-core data synchronization mechanism with a delay controlled within 1 microsecond is obtained.

4. The multi-network port dynamic redundant switching method for an ARM main controller according to claim 1, characterized in that: The parallel Kalman filter algorithm of the ARM NEON instruction set is used to perform prediction calculations on each independent processing core to obtain the state prediction value and prediction error covariance of each dimension, including: Initialization parameter configuration processing is performed on the one-dimensional Kalman filter on each independent processing core to obtain a filter parameter set including an initial state value, an initial covariance matrix, a process noise variance, and a measurement noise variance; The state prediction equation of the Kalman filter is vectorized and processed based on the four-element floating-point data type of the ARM NEON instruction set to obtain the one-step predicted state value of each dimension; The covariance prediction matrix operation is parallelized and multiplied by NEON parallel multiplication instructions to obtain the one-step prediction error covariance of each dimension; The prediction results of each independent processing core are written into the core dedicated storage area for atomic storage processing to obtain dimensional prediction data including the prediction state value and prediction error covariance; The ARM-based memory prefetch instruction performs memory prefetching on the historical data of the next computing cycle, obtains the network status historical data preloaded into the first-level cache, and outputs the state prediction value and prediction error covariance of each dimension.

5. The multi-network port dynamic redundant switching method for an ARM main controller according to claim 4, characterized in that: The prediction results of each independent processing core are written into the core dedicated storage area for atomic storage processing to obtain dimensional prediction data including the prediction state value and the prediction error covariance, including: Perform memory address calculation on the prediction result data on each independent processing core to obtain the target write address of the core dedicated storage area; Based on the ARM exclusive access instruction, the core dedicated storage area is exclusively locked to obtain exclusive access rights; The state prediction value and the prediction error covariance are encapsulated in a 64-byte aligned format to obtain a dimension prediction data packet; The dimension prediction data packet is atomically written using ARM exclusive storage instructions to obtain the prediction result data that has been persistently stored. Based on the ARM memory barrier instruction, the write operation is synchronously confirmed, the write completion flag is obtained and the exclusive access right is released, and the dimensional prediction data including the predicted state value and the prediction error covariance is output.

6. The multi-network port dynamic redundant switching method for an ARM main controller according to claim 1, characterized in that: The state prediction value and prediction error covariance of each dimension are optimally weighted and fused according to the covariance cross fusion mechanism to obtain the fused four-dimensional network state prediction result and comprehensive confidence interval, including: The prediction data of each dimension is read and aggregated on the main core of the ARM main controller to obtain a prediction data set containing the four-dimensional state prediction values ​​and prediction error covariance; According to the covariance cross fusion weight calculation rule, the prediction error covariance of each dimension is calculated by weight ratio to obtain the optimal fusion weight coefficient of each dimension in the fusion process; The state prediction value of each dimension is weighted and summed with the corresponding optimal fusion weight coefficient to obtain the fused four-dimensional network state prediction result; Based on the inverse of the prediction error covariance of each dimension and the inverse operation of the fusion covariance, the fused comprehensive prediction error covariance is obtained; The confidence interval is processed by normal distribution calculation according to the fused comprehensive prediction error covariance to obtain the comprehensive confidence interval, and the fused four-dimensional network state prediction result and the comprehensive confidence interval are output.

7. The multi-network port dynamic redundant switching method for an ARM main controller according to claim 1, characterized in that: The predictive switching decision processing of the network interface through a dynamic event triggering mechanism based on the comprehensive confidence interval, obtaining a network interface switching instruction and executing a traffic redirection operation includes: Based on the comprehensive confidence interval, the probability of exceeding the threshold value of the future state of the main network interface is calculated to obtain the failure probability value of the main network interface experiencing performance degradation within 500 milliseconds; The pre-switching trigger condition judgment result is obtained by comparing the fault probability value with the 80% probability threshold; Based on the pre-switching trigger condition judgment result, a rapid quality assessment process is performed on the backup network interface to obtain a backup interface status report including physical connection status, IP address configuration status and routing table reachability; Input the standby interface status report into the switching decision module for pre-switching preparation operation processing, and obtain a pre-switching preparation completion flag including TCP connection preheating, DNS cache preloading and session state synchronization; When the actual measurement value of the main network interface reaches the switching threshold, the network traffic is redirected to the routing table, a network interface switching instruction is obtained, and the traffic redirection operation is completed.

8. A multi-network port dynamic redundant switching system for an ARM main controller, characterized in that: A method for implementing a multi-network port dynamic redundant switching method for an ARM main controller according to any one of claims 1 to 7, wherein the multi-network port dynamic redundant switching system for an ARM main controller comprises: The acquisition module is used to collect and process the real-time status parameters of each network interface through the hardware counter of the ARM main controller, and obtain a four-dimensional network state vector including network delay time, packet loss rate, bandwidth utilization and network jitter value; A decoupling module is used to perform dimension decoupling and distribution processing on the four-dimensional network state vector according to the heterogeneous multi-core architecture characteristics of the ARM processor, thereby obtaining independent processing cores corresponding to the four network state dimensions; The prediction module is used to perform prediction calculations on each independent processing core using the parallel Kalman filter algorithm of the ARM NEON instruction set to obtain the state prediction value and prediction error covariance of each dimension; The fusion module is used to perform optimal weighted fusion processing on the state prediction value and prediction error covariance of each dimension according to the covariance cross fusion mechanism to obtain the fused four-dimensional network state prediction result and comprehensive confidence interval; The switching module is used to perform predictive switching decision processing on the network interface through a dynamic event triggering mechanism based on the comprehensive confidence interval, obtain a network interface switching instruction and perform a traffic redirection operation.

9. A multi-network port dynamic redundant switching device for an ARM main controller, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the computer program, the method for dynamic redundant switching of multiple network ports for an ARM main controller according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the processor executes the multi-network port dynamic redundant switching method for an ARM main controller according to any one of claims 1 to 7.

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