Logic synthesis method and device of FPGA (Field Programmable Gate Array) device

Abstract

The invention provides a logic synthesis method and device of an FPGA (Field Programmable Gate Array) device. The method comprises the following steps: identifying a plurality of memory structures corresponding to a target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least: capacity information; and according to the capacity information and the quantity of various types of storage resources supported by the target FPGA device, carrying out storage resource inference on the plurality of memory structures to obtain a target storage resource type of each memory structure. When storage resource inference is carried out on a plurality of memory structures, the plurality of memory structures are not directly inferred as one type of storage resources, and then how to process the memory structures exceeding the quantity of the type of storage resources supported by the target FPGA device is considered, but in the inference process, the number of the types of storage resources supported by the target FPGA device is not considered. Therefore, the capacity information and the quantity of various types of storage resources supported by the target FPGA device are considered, and the logic synthesis time is shortened.

Description

Technical Field

[0001] The present invention relates to the field of FPGA development technology, and in particular to a logic synthesis method and apparatus for an FPGA device. Background Art

[0002] During the logic synthesis process for field-programmable gate arrays (FPGAs), it is necessary to infer storage resources for the identified memory structures. However, when the number of storage resources required by the memory structure exceeds the upper limit supported by the hardware of the target FPGA, traditional solutions will directly report an error and terminate the process. Specifically, the logic synthesis tool will directly report an error and exit, forcing the user to modify the design or replace it with a higher-specification device. This results in poor design flexibility, extended development cycles, and an inability to adapt to resource-constrained scenarios. Alternatively, all identified memory structures will be inferred as a single type of storage resource, and then the handling of memory structures that exceed the upper limit supported by the hardware of the target FPGA will be considered. This will increase the time required for logic synthesis and affect the overall performance and resource utilization of the FPGA design. Summary of the Invention

[0003] The purpose of the present invention is to address the deficiencies in the above-mentioned prior art and provide a logic synthesis method and apparatus for FPGA devices so that, during the inference process, storage resources of multiple memory structures can be inferred based on capacity information and the number of various types of storage resources supported by the target FPGA device, and finally the target storage resource type of each memory structure can be obtained, thereby reducing the logic synthesis time.

[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0005] In a first aspect, an embodiment of the present application provides a logic synthesis method for an FPGA device, the method comprising:

[0006] Identifying a plurality of memory structures corresponding to the target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least: capacity information;

[0007] According to the capacity information and the number of each type of storage resources supported by the target FPGA device, storage resource inference is performed on the multiple memory structures to obtain the target storage resource type of each memory structure.

[0008] In an optional embodiment, performing storage resource inference on the multiple memory structures based on the capacity information and the number of each type of storage resources supported by the target FPGA device to obtain a logic resource inference result of the FPGA device includes:

[0009] sorting the plurality of memory structures from largest to smallest according to the capacity information;

[0010] According to the quantity of each type of storage resources supported by the target FPGA device, storage resource inference is performed on each sorted memory structure in turn to obtain the target storage resource type corresponding to each memory structure.

[0011] In an optional embodiment, the various types of storage resources include: block storage resources, distributed storage resources, and logical storage resources;

[0012] The method of performing storage resource inference on each sorted memory structure in turn according to the number of each type of storage resource supported by the target FPGA device to obtain a target storage resource type corresponding to each memory structure includes:

[0013] According to the number of target block storage resources supported by the target FPGA device, executing a first inference process for block storage resources on each of the sorted memory structures in sequence;

[0014] If the first inference process is completed, executing a second inference process for distributed storage resources on the first remaining memory structure after the first inference process is completed according to the number of target distributed storage resources supported by the target FPGA device;

[0015] If a second remaining memory structure still exists after the second inference process is executed, the second remaining memory structure is logically split according to the number of remaining logic storage resources supported by the target FPGA device.

[0016] In an optional embodiment, the first inference process for block storage resources is performed on each sorted memory structure in sequence according to the target number of block storage resources supported by the target FPGA device, including:

[0017] Determine the sum of the first block storage resource quantity required by the first to-be-inferred memory structure and the currently used second block storage resource quantity in each of the sorted memory structures as the required block storage resource quantity;

[0018] If the required number of block storage resources does not exceed the target number of block storage resources, inferring the target storage resource type corresponding to the first to-be-inferred memory structure as block storage resources;

[0019] If the required number of block storage resources exceeds the target number of block storage resources, it is determined that the first inference process is terminated.

[0020] In an optional embodiment, the step of performing a second inference process for distributed storage resources on the first remaining memory structure after the first inference process is completed based on the target number of distributed storage resources supported by the target FPGA device includes:

[0021] Determine the sum of the first distributed storage resource quantity required for the second to-be-inferred memory structure in the first remaining memory structure and the currently used second distributed storage resource quantity as the required distributed storage resource quantity;

[0022] If the required number of distributed storage resources does not exceed the target number of distributed storage resources, inferring the target storage resource type corresponding to the second memory structure to be inferred as a distributed storage resource;

[0023] If the required number of distributed storage resources exceeds the target number of distributed storage resources, it is determined that the second inference process is completed.

[0024] In an optional implementation, before performing logical resource splitting on the second remaining memory structure according to the number of remaining logical storage resources supported by the target FPGA device, the method further includes:

[0025] estimating the amount of logical resources required by the second remaining memory structure according to the capacity information of the second remaining memory structure;

[0026] The step of splitting the second remaining memory structure into logical resources according to the number of remaining logical storage resources supported by the target FPGA device includes:

[0027] If the number of logic resources required by the second remaining memory structure does not exceed the number of remaining logic storage resources, the second remaining memory structure is split into lookup table resources and register resources as logic resources.

[0028] In an optional embodiment, the method further comprises:

[0029] If the number of logical resources required by the second remaining memory structure exceeds the number of remaining logical storage resources, an error message regarding splitting the logical resources is output.

[0030] In an optional embodiment, the method further comprises:

[0031] If each of the memory structures also includes attribute constraint information, then storage resource inference is performed on each of the memory structures based on the attribute constraint information in each of the memory structures and the number of each type of storage resources supported by the target FPGA device to obtain the target storage resource type of each of the memory structures.

[0032] In an optional embodiment, performing storage resource inference on each memory structure based on the attribute constraint information in each memory structure and the number of each type of storage resources supported by the target FPGA device to obtain the target storage resource type of each memory structure includes:

[0033] Determine the required storage resource quantity of the storage resource type corresponding to the attribute constraint information of each memory structure and the target storage resource quantity of the corresponding storage resource type;

[0034] If the required storage resource quantity does not exceed the target storage resource quantity of the corresponding storage resource type, inferring the target storage resource type corresponding to each memory structure as the corresponding storage resource type;

[0035] If the required storage resource quantity exceeds the target storage resource quantity of the corresponding storage resource type, an inference error message for the corresponding storage resource type is output.

[0036] In a second aspect, an embodiment of the present application further provides a logic synthesis device for an FPGA device, the device comprising:

[0037] An identification module is used to identify multiple memory structures corresponding to the target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least: capacity information;

[0038] An inference module is used to perform storage resource inference on the multiple memory structures based on the capacity information and the number of each type of storage resources supported by the target FPGA device, so as to obtain a target storage resource type for each memory structure.

[0039] In a third aspect, an embodiment of the present application further provides an electronic device comprising: a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the program instructions to perform the steps of the logic synthesis method of the FPGA device as described in any one of the first aspects.

[0040] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the logic synthesis method for an FPGA device as described in any one of the first aspects are executed.

[0041] The beneficial effects of this application are:

[0042] An embodiment of the present application provides a logic synthesis method and apparatus for an FPGA device, the method comprising: identifying multiple memory structures corresponding to a target FPGA device from a logic design file of the target FPGA device; each memory structure comprising at least capacity information; and performing storage resource inference on the multiple memory structures based on the capacity information and the number of each type of storage resource supported by the target FPGA device, thereby obtaining a target storage resource type for each memory structure. When performing storage resource inference on the multiple memory structures, the multiple memory structures are not directly inferred as one type of storage resource, and then considering how to handle memory structures that exceed the number of storage resources of that type supported by the target FPGA device. Instead, the capacity information and the number of each type of storage resource supported by the target FPGA device are considered during the inference process, and finally the target storage resource type for each memory structure is obtained, thereby reducing logic synthesis time and avoiding affecting the overall performance and resource utilization of the target FPGA device design. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 One of the flow charts of a logic synthesis method for an FPGA device provided in an embodiment of the present application;

[0045] Figure 2 A second flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application;

[0046] Figure 3 A third flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application;

[0047] Figure 4 A fourth flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application;

[0048] Figure 5 A fifth flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application;

[0049] Figure 6 Flowchart 6 of a logic synthesis method for an FPGA device provided in an embodiment of the present application;

[0050] Figure 7Flowchart seven of a logic synthesis method for an FPGA device provided in an embodiment of the present application;

[0051] Figure 8 A schematic diagram of the functional modules of a logic synthesis device for an FPGA device provided in an embodiment of the present application;

[0052] Figure 9 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0054] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0055] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the application is usually placed when in use. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on this application.

[0056] In addition, the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0057] It should be noted that, in the absence of conflict, the features in the embodiments of this application can be combined with each other.

[0058] The logic synthesis method of the FPGA device provided in the embodiment of the present application is explained in detail below with reference to specific examples in conjunction with the accompanying drawings. Figure 1 This is one of the flow charts of a logic synthesis method for an FPGA device provided in an embodiment of the present application; Figure 1 As shown, the method includes:

[0059] S101. Identify multiple memory structures corresponding to the target FPGA device from a logic design file of the target FPGA device.

[0060] Each memory structure includes at least capacity information.

[0061] S102 : Perform storage resource inference on multiple memory structures based on the capacity information and the number of each type of storage resources supported by the target FPGA device to obtain a target storage resource type for each memory structure.

[0062] In this embodiment, in the design process of the target FPGA (field programmable gate array) device, a logic design file is first written using a hardware description language. The logic design file can be a register transfer level (RTL) design file, in which the logic design file records a detailed description of the logic function and structure of the target FPGA device.

[0063] Use a parsing tool or write a parsing program to read and analyze the logic design file line by line. The parsing tool can understand the syntax rules of the hardware description language (HDL) and then identify the various logical structures and components in the logic design file. The memory structure will be clearly defined in the logic design file. For example, in the hardware description language Verilog, use reg arrays or memory modules to define memory, use decoder to define decoders, and use shiftReg to define shift registers. For each identified memory structure, its capacity information is extracted. The capacity information includes read and write data bit width and address depth. It should be noted that each memory structure also includes other information required for inference, including: clock, read and write mode, read and write enable / control signal, reset mode, reset signal, port mode (single port, pseudo dual port, dual port, read-only), etc.

[0064] The target FPGA device usually provides multiple types of storage resources, such as block static random access memory (BSRAM), distributed static random access memory (SSRAM), etc., and each storage resource has its own specific capacity and performance characteristics. Then, based on the capacity information of each memory structure and the number of each type of storage resources supported by the target FPGA device, storage resource inference is performed on each memory structure, thereby completing the storage resource inference of each memory structure and obtaining the target storage resource type of each memory structure.

[0065] In summary, an embodiment of the present application provides a logic synthesis method for an FPGA device, comprising: identifying multiple memory structures corresponding to the target FPGA device from the logic design file of the target FPGA device; each memory structure includes at least: capacity information; based on the capacity information and the number of each type of storage resources supported by the target FPGA device, performing storage resource inference on the multiple memory structures to obtain the target storage resource type of each memory structure. When performing storage resource inference on the multiple memory structures, the multiple memory structures are not directly inferred as one type of storage resource, and then considering how to handle the memory structures that exceed the number of storage resources of this type supported by the target FPGA device. Instead, in the inference process, the capacity information and the number of each type of storage resources supported by the target FPGA device are considered, and finally the target storage resource type of each memory structure is obtained, thereby reducing the logic synthesis time and avoiding affecting the overall performance and resource utilization of the target FPGA device design.

[0066] The embodiment of the present application also provides another possible implementation of the logic synthesis method of the FPGA device. Figure 2 The second flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application; Figure 2 As shown, based on the capacity information and the number of various types of storage resources supported by the target FPGA device, storage resource inference is performed on multiple memory structures to obtain the logic resource inference results of the FPGA device, including:

[0067] S201 , sorting multiple memory structures from largest to smallest according to capacity information.

[0068] S202 , based on the number of each type of storage resource supported by the target FPGA device, perform storage resource inference on each sorted memory structure in turn to obtain a target storage resource type corresponding to each memory structure.

[0069] In this embodiment, sorting the multiple memory structures according to capacity information helps to more efficiently infer storage resources of the multiple memory structures later, and the capacity sorting result is obtained by sorting them from large to small according to capacity.

[0070] After sorting by capacity, large-capacity memory structures can be prioritized to avoid fragmented use of large-capacity storage resources, thereby improving resource utilization. For example, if small-capacity memory structures are processed first, when storage resources are insufficient, the large-capacity storage resources may be split into small pieces, consuming a large amount of logic resources.

[0071] Specifically, based on the capacity sorting results, storage resource inference is prioritized for the memory structures ranked higher, ensuring that the required storage resources of the type for the higher-ranked memory structures remain available. If all the storage resources of the target memory structure's required type are already occupied, another type of storage resource is inferred for the target memory structure. Finally, the target storage resource type corresponding to each memory structure is determined.

[0072] In the method provided in an embodiment of the present application, multiple memory structures are sorted from largest to smallest based on capacity information. Based on the number of storage resources of each type supported by the target FPGA device, storage resource inference is performed on each of the sorted memory structures to obtain the target storage resource type corresponding to each memory structure. By sorting the multiple memory structures, storage resource inference is prioritized for the memory structures ranked earlier, ensuring that the required storage resource type remains available for the memory structures ranked earlier.

[0073] An embodiment of the present application also provides another possible implementation method of a logic synthesis method for an FPGA device, wherein various types of storage resources include: block storage resources, distributed storage resources, and logical storage resources; wherein the block storage resources are BSRAM, the distributed storage resources are SSRAM, and the logical storage resources are lookup table resources and register resources. Figure 3 The third flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application; Figure 3 As shown, according to the number of each type of storage resources supported by the target FPGA device, the storage resources of each sorted memory structure are inferred in turn to obtain the target storage resource type corresponding to each memory structure, including:

[0074] S301 , executing a first inference process for block storage resources on sorted memory structures in sequence according to the target number of block storage resources supported by the target FPGA device.

[0075] In this embodiment, the block-type BSRAM storage resource has a large storage capacity and supports a wide data bit width and address depth. It also has two independent ports, enabling dual-port independent read and write functionality within a single block-type storage resource. Therefore, the memory structure is preferentially inferred as a block-type storage resource. Since the target FPGA device supports a limited number of target block-type storage resources, resource allocation requires rational use. Therefore, the first inference process is performed, prioritizing the memory structure ranked higher as a block-type storage resource.

[0076] S302: If the first inference process is completed, a second inference process for distributed storage resources is executed on the first remaining memory structure after the first inference process is completed according to the target distributed storage resource quantity supported by the target FPGA device.

[0077] Among them, the distributed storage resource SSRAM is a storage resource composed of the logic units of the target FPGA. Its capacity is relatively small, but it can be flexibly configured and is suitable for storing smaller capacity data.

[0078] Specifically, after the first inference process is completed, if there is still an uninferred memory structure, namely the first remaining memory structure, the second inference process is performed. Based on the first remaining memory structure and the number of target distributed storage resources supported by the FPGA device, the first remaining memory structure ranked first is preferentially inferred as a distributed storage resource.

[0079] S303: If a second remaining memory structure still exists after the second inference process is completed, the second remaining memory structure is split into logical resources according to the number of remaining logical storage resources supported by the target FPGA device.

[0080] Logic storage resources refer to storage functions implemented using the target FPGA's logic units (such as lookup tables and registers). Logic storage resources have a relatively small capacity and are less efficient than block and distributed storage resources. However, they can be used as a supplement when other storage resources are insufficient. Because the inferred memory structure in the first and second inference processes occupies some logic storage resources, the remaining logic storage resources supported by the target FPGA device are the remaining available logic storage resources after subtracting the occupied logic storage resources from the total supported logic storage resources.

[0081] Specifically, after the second inference process is completed, if there is still an uninferred memory structure, namely the second remaining memory structure, the second remaining memory structure is logically split according to the number of remaining logical storage resources supported by the target FPGA device to obtain the target storage resource type corresponding to the second remaining memory structure.

[0082] In the method provided in the embodiment of the present application, a first inference process for block storage resources is executed in sequence on each sorted memory structure according to the target number of block storage resources supported by the target FPGA device; if the first inference process is completed, a second inference process for distributed storage resources is executed on the first remaining memory structure after the first inference process is completed according to the target number of distributed storage resources supported by the target FPGA device; if there is still a second remaining memory structure after the second inference process is completed, the second remaining memory structure is logically split according to the remaining number of logical storage resources supported by the target FPGA device, avoiding direct logical resource splitting of the first remaining memory structure, and preferentially inferring the first remaining memory structure as a distributed storage resource SSRAM instead of directly splitting the first remaining memory structure into logical resources, thereby significantly reducing the occupation of logical resources, reducing power consumption, and optimizing the utilization of logical resources.

[0083] The embodiment of the present application also provides another possible implementation of the logic synthesis method of the FPGA device. Figure 4 The fourth flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application; Figure 4 As shown, according to the target number of block storage resources supported by the target FPGA device, the first inference process for block storage resources is executed on each sorted memory structure in sequence, including:

[0084] S401: Determine the sum of the quantity of first block storage resources required by the first to-be-inferred memory structure and the quantity of currently used second block storage resources in the sorted memory structures as the required quantity of block storage resources.

[0085] S402: If the required number of block storage resources does not exceed the target number of block storage resources, infer the target storage resource type corresponding to the first to-be-inferred memory structure as block storage resources.

[0086] S403: If the required number of block storage resources exceeds the target number of block storage resources, it is determined that the first inference process is terminated.

[0087] In this embodiment, among the multiple memory structures that have been sorted, one memory structure is selected in sequence according to the sorting order to perform storage resource inference, and the first memory structure to be inferred is the memory structure currently being processed.

[0088] Different memory structures have different capacities, while the block storage resources in the target FPGA device have fixed capacity specifications. To meet the storage requirements of the first memory structure to be inferred, the number of required block storage resources, i.e., the number of first block storage resources, must be calculated based on the capacity of the first memory structure to be inferred. For example, if a memory structure has a capacity of 32 KB and a single block storage resource has a capacity of 18 KB, then at least two block storage resources are required, i.e., the number of first block storage resources is 2.

[0089] Before inferring the first memory structure to be inferred, if the memory structure ranked earlier has already been allocated block storage resources, then the second block storage resource quantity is determined, where the second block storage resource quantity indicates the number of block storage resources that have been used. The first block storage resource quantity required by the first memory structure to be inferred and the currently used second block storage resource quantity are added together, and the resulting sum is the required block storage resource quantity.

[0090] The required number of block storage resources is compared with the target number of block storage resources. If the required number of block storage resources is less than or equal to the target number of block storage resources, indicating that sufficient block storage resources are currently available for allocation to the first memory structure to be inferred, the target storage resource type corresponding to the first memory structure to be inferred is inferred to be a block storage resource, and the first memory structure to be inferred may use the block storage resources to implement a storage function.

[0091] When the required number of block storage resources is greater than the target number of block storage resources, it means that the block storage resources supported by the current target FPGA device are no longer sufficient to simultaneously meet the requirements of the previously allocated memory structure and the first memory structure to be inferred. The first inference process is then terminated, and other types of storage resources need to be allocated to the first memory structure to be inferred and other memory structures that have not yet been inferred.

[0092] In the method provided in an embodiment of the present application, the sum of the number of first block storage resources required by the first memory structure to be inferred and the number of second block storage resources currently in use in each sorted memory structure is determined as the required number of block storage resources; if the required number of block storage resources does not exceed the target number of block storage resources, the target storage resource type corresponding to the first memory structure to be inferred is inferred as a block storage resource; if the required number of block storage resources exceeds the target number of block storage resources, it is determined that the first inference process is terminated, and block storage resources are reasonably allocated to the memory structure based on the target number of block storage resources supported by the target FPGA device. When resources are insufficient, the first inference process is terminated in a timely manner. By performing resource checking while inferring, redundant inference processes when resources are insufficient are avoided.

[0093] The embodiment of the present application also provides another possible implementation of the logic synthesis method of the FPGA device. Figure 5 The fifth flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application; Figure 5 As shown, according to the target number of distributed storage resources supported by the target FPGA device, a second inference process for distributed storage resources is executed on the first remaining memory structure after the first inference process is completed, including:

[0094] S501: Determine the sum of the number of first distributed storage resources required by the second to-be-inferred memory structure in the first remaining memory structure and the number of currently used second distributed storage resources as the required number of distributed storage resources.

[0095] S502: If the required number of distributed storage resources does not exceed the target number of distributed storage resources, the target storage resource type corresponding to the second memory structure to be inferred is inferred as a distributed storage resource.

[0096] S503: If the required number of distributed storage resources exceeds the target number of distributed storage resources, it is determined that the second inference process is finished.

[0097] In this embodiment, after completing the first inference process for block storage resources, the memory structures that have not been successfully allocated to block storage resources constitute the first remaining memory structure, and one memory structure is selected from the first remaining memory structure in sequence according to the sorting order for storage resource inference. The second memory structure to be inferred is the memory structure currently being processed.

[0098] Distributed storage resources are storage resources composed of logic units of an FPGA. Based on the capacity of the second memory structure to be inferred, the number of distributed storage resources required to meet its storage requirements, i.e., the number of first distributed storage resources, is calculated. Before inferring the second memory structure to be inferred, if the first remaining memory structure ranked first has already been allocated distributed storage resources, the number of second distributed storage resources is determined, and the second distributed storage resource number indicates the number of distributed storage resources that have been used. The number of first distributed storage resources required by the second memory structure to be inferred and the number of second distributed storage resources currently in use are added to obtain the required number of distributed storage resources.

[0099] The required number of distributed storage resources is compared with the target number of distributed storage resources. If the required number of distributed storage resources is less than or equal to the target number of distributed storage resources, sufficient distributed storage resources are available for allocation to the second memory structure to be inferred. The target storage resource type corresponding to the second memory structure to be inferred is inferred as a distributed storage resource, and the second memory structure to be inferred can use the distributed storage resources to implement storage functions.

[0100] When the required number of distributed storage resources is greater than the target number of distributed storage resources, it means that the distributed storage resources supported by the current target FPGA device are no longer sufficient to simultaneously meet the requirements of the previously allocated memory structure and the second memory structure to be inferred. The second inference process is then terminated, and other types of storage resources need to be used to allocate the second memory structure to be inferred and other memory structures that have not yet been inferred.

[0101] In the method provided in an embodiment of the present application, the sum of the number of first distributed storage resources required for the second memory structure to be inferred in the first remaining memory structure and the number of second distributed storage resources currently in use is determined as the required number of distributed storage resources; if the required number of distributed storage resources does not exceed the target number of distributed storage resources, the target storage resource type corresponding to the second memory structure to be inferred is inferred as a distributed storage resource; if the required number of distributed storage resources exceeds the target number of distributed storage resources, it is determined that the second inference process is terminated, and distributed storage resources are reasonably allocated to the memory structures in the first remaining memory structure according to the target number of distributed storage resources supported by the target FPGA device, and the second inference process is terminated in a timely manner when resources are insufficient.

[0102] The embodiment of the present application also provides another possible implementation of the logic synthesis method of the FPGA device. Figure 6 6 is a flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application; Figure 6 As shown, before performing logic resource splitting on the second remaining memory structure according to the number of remaining logic storage resources supported by the target FPGA device, the method further includes:

[0103] S601: Estimate the number of logic resources required by the second remaining memory structure according to capacity information of the second remaining memory structure.

[0104] In this embodiment, after completing the second inference process for distributed storage resources, the memory structures that have not been successfully allocated to storage resources constitute the second remaining memory structure. Since each memory structure has its own specific capacity, the number of logical resources required for the second remaining memory structure is estimated based on the capacity information of the second remaining memory structure.

[0105] Logic memory resources are composed of basic logic units such as lookup tables (LUTs) and registers within the FPGA device. Memory structures of varying capacities require varying amounts of logic resources to implement. The required number of logic resources can be estimated based on the capacity of the second remaining memory structure and the characteristics of the logic units within the FPGA. For example, a simple lookup table can implement a certain number of logic functions, and a register can store one bit of data. By analyzing the read / write logic and storage capacity of the memory structure, the number of lookup tables and registers required to implement the memory structure can be calculated, thereby determining the required number of logic resources.

[0106] Based on the remaining logic storage resources supported by the target FPGA device, the second remaining memory structure is split into logic resources, including:

[0107] S602: If the number of logic resources required by the second remaining memory structure does not exceed the number of remaining logic storage resources, split the second remaining memory structure into lookup table resources and register resources as logic resources.

[0108] Specifically, the number of logic resources required for the second remaining memory structure is compared with the number of remaining logic storage resources. If the required number of logic resources is less than or equal to the number of remaining logic storage resources, it means that the current FPGA device has sufficient logic resources to implement the second remaining memory structure.

[0109] If resource requirements are met, the second remaining memory structure is split into lookup table resources and register resources. The lookup table implements the memory's logical functions, such as address decoding and read / write control; the registers store the actual data. This split allows the complex second remaining memory structure to be implemented using basic logic units within the FPGA.

[0110] Optionally, if the number of logical resources required by the second remaining memory structure exceeds the number of remaining logical storage resources, an error message regarding splitting the logical resources is output.

[0111] Specifically, if the required number of logic resources is greater than the number of remaining logic storage resources, it means that the existing logic storage resources of the current FPGA device cannot meet the second remaining memory structure. When insufficient resources occur, a split error message for the logic resources is output. The split error message is used to inform the designer that the current design solution cannot be implemented on the FPGA device and the design needs to be adjusted. The split error message may include: indicating that the specific second remaining memory structure causes the problem of insufficient resources, outputting the required number of logic resources and the remaining number of logic storage resources, or providing suggestions, such as replacing a larger capacity FPGA device.

[0112] In the method provided in an embodiment of the present application, the number of logical resources required for the second remaining memory structure is estimated based on the capacity information of the second remaining memory structure. If the number of logical resources required for the second remaining memory structure does not exceed the number of remaining logical storage resources, the second remaining memory structure is split into lookup table resources and register resources as logical resources. Since the second inference process is also performed, the number of second remaining memory structures is small. At this time, the logical resources are split again, so that fewer register resources are occupied, thereby reducing the power consumption of the memory.

[0113] The embodiment of the present application further provides another possible implementation of a logic synthesis method for an FPGA device, the method further comprising:

[0114] If each memory structure also includes attribute constraint information, then storage resource inference is performed on each memory structure based on the attribute constraint information in each memory structure and the number of each type of storage resources supported by the target FPGA device to obtain the target storage resource type of each memory structure.

[0115] In this embodiment, during the logic synthesis process of the target FPGA device, in addition to considering the capacity information of each memory structure, the attribute constraints of each memory structure are also considered. Combined with the number of different types of memory resources supported by the target FPGA device, this allows for more accurate inference of the appropriate target memory resource type for each memory structure. The attribute constraints are the user-defined desired inferred memory resource types for each memory structure. These attribute constraints include inference as block storage resources, inference as distributed storage resources, or splitting into logical resources.

[0116] By analyzing the attribute constraint information and the number of various types of storage resources supported by the target FPGA device, the most appropriate target storage resource type is determined for each memory structure. For example, if the attribute constraint information of a memory structure is: inferred to be a block storage resource, then based on the capacity of the memory structure and the number of target block storage resources supported by the target FPGA device, the storage resource inference of the memory structure is performed to obtain the target storage resource type of the memory structure.

[0117] In the method provided in an embodiment of the present application, if each memory structure also includes attribute constraint information, storage resource inference is performed on each memory structure based on the attribute constraint information in each memory structure and the number of various types of storage resources supported by the target FPGA device to obtain the target storage resource type of each memory structure. By considering the attribute constraint information, the appropriate storage resource type can be selected for each memory structure more accurately, thereby improving the performance and resource utilization of the target FPGA device.

[0118] The embodiment of the present application also provides another possible implementation of the logic synthesis method of the FPGA device. Figure 7 FIG7 is a flow chart of a logic synthesis method for an FPGA device provided in an embodiment of the present application; Figure 7 As shown, based on the attribute constraint information in each memory structure and the number of each type of storage resources supported by the target FPGA device, storage resources are inferred for each memory structure to obtain the target storage resource type of each memory structure, including:

[0119] S701: Determine the required storage resource quantity and the target storage resource quantity of the storage resource type corresponding to the attribute constraint information of each memory structure.

[0120] S702: If the required storage resource quantity does not exceed the target storage resource quantity of the corresponding storage resource type, the target storage resource type corresponding to each memory structure is inferred as the corresponding storage resource type.

[0121] S703: If the required storage resource quantity exceeds the target storage resource quantity of the corresponding storage resource type, output inference error information for the corresponding storage resource type.

[0122] In this embodiment, the attribute constraint information for each memory structure determines the corresponding storage resource type. For example, if the attribute constraint information for a memory structure indicates that it is a block storage resource, the corresponding storage resource type for the memory structure is determined to be a block storage resource. Based on the capacity of the memory structure, the required number of block storage resources is calculated, and the target number of block storage resources supported by the target FPGA device is determined.

[0123] The required number of storage resources, ie, the required number of block storage resources, includes: the number of block storage resources required by the memory structure and the number of currently used block storage resources.

[0124] The required block storage resources are compared with the target block storage resources. If the required block storage resources are less than or equal to the target block storage resources, it indicates that the block storage resources in the current FPGA device are sufficient to meet the requirements of the memory structure. In this case, the target storage resource type corresponding to the memory structure is inferred to be block storage resources.

[0125] If the required block storage resources are greater than the target block storage resources, it means that the block storage resources in the current FPGA device cannot meet the requirements of the memory structure, and an inference error message for the block storage resources is output.

[0126] Similarly, if the attribute constraint information of a memory structure is: inferred as a distributed storage resource, then the storage resource type corresponding to the memory structure is determined to be a distributed storage resource, and based on the capacity of the memory structure, the number of required distributed storage resources is calculated, and the target number of distributed storage resources supported by the target FPGA device is determined. By comparing the required distributed storage resources with the target distributed storage resources, the memory structure is inferred. If the required number of distributed storage resources does not exceed the target number of distributed storage resources, the target storage resource type corresponding to the memory structure is inferred to be a distributed storage resource. If the required number of distributed storage resources exceeds the target number of distributed storage resources, an inference error message for the distributed storage resource is output.

[0127] In the method provided in the embodiment of the present application, the target storage resource type is reasonably inferred for each memory structure based on the attribute constraint information of each memory structure and the number of various types of storage resources supported by the FPGA device, and error information is output in a timely manner when resources are insufficient.

[0128] The following continues to explain the logic synthesis device and electronic device that implement the FPGA device provided by any of the above embodiments of the present application. The specific implementation process and the technical effects produced are the same as those of the corresponding method embodiments mentioned above. For the sake of brief description, for the parts not mentioned in this embodiment, please refer to the corresponding content in the method embodiment.

[0129] Figure 8 This is a functional module diagram of a logic synthesis device for an FPGA device provided in an embodiment of the present application. Figure 8 As shown, the logic synthesis device 100 of the FPGA device includes:

[0130] The identification module 110 is configured to identify a plurality of memory structures corresponding to the target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least capacity information;

[0131] The inference module 120 is configured to perform storage resource inference on multiple memory structures based on the capacity information and the number of each type of storage resources supported by the target FPGA device, and obtain a target storage resource type for each memory structure.

[0132] Optionally, the inference module 120 is also used to sort multiple memory structures from large to small according to capacity information; and perform storage resource inference on each sorted memory structure in turn according to the number of each type of storage resources supported by the target FPGA device to obtain the target storage resource type corresponding to each memory structure.

[0133] Optionally, each type of storage resource includes: block storage resources, distributed storage resources and logical storage resources; the inference module 120 is also used to execute the first inference process for block storage resources on each sorted memory structure in sequence according to the target number of block storage resources supported by the target FPGA device; if the first inference process is completed, then according to the target number of distributed storage resources supported by the target FPGA device, the second inference process for distributed storage resources is executed on the first remaining memory structure after the first inference process is completed; if there is still a second remaining memory structure after the second inference process is completed, then according to the remaining number of logical storage resources supported by the target FPGA device, the second remaining memory structure is logically split.

[0134] Optionally, the inference module 120 is further configured to determine the sum of the number of first block storage resources required for the first memory structure to be inferred and the number of second block storage resources currently used in the sorted memory structures as the required number of block storage resources; if the required number of block storage resources does not exceed the target number of block storage resources, infer the target storage resource type corresponding to the first memory structure to be inferred as block storage resources; if the required number of block storage resources exceeds the target number of block storage resources, determine that the first inference process is terminated.

[0135] Optionally, the inference module 120 is also used to determine the sum of the number of first distributed storage resources required for the second memory structure to be inferred in the first remaining memory structure and the number of second distributed storage resources currently used as the required number of distributed storage resources; if the required number of distributed storage resources does not exceed the target number of distributed storage resources, the target storage resource type corresponding to the second memory structure to be inferred is inferred as a distributed storage resource; if the required number of distributed storage resources exceeds the target number of distributed storage resources, it is determined that the second inference process is completed.

[0136] Optionally, the device further comprises:

[0137] an estimating module, configured to estimate the amount of logic resources required by the second remaining memory structure according to the capacity information of the second remaining memory structure;

[0138] The inference module 120 is further configured to split the second remaining memory structure into lookup table resources and register resources as logic resources if the number of logic resources required by the second remaining memory structure does not exceed the number of remaining logic storage resources.

[0139] Optionally, the device further comprises:

[0140] The output module is configured to output splitting error information for the logical resources if the number of logical resources required by the second remaining memory structure exceeds the number of remaining logical storage resources.

[0141] Optionally, the inference module 120 is also used to perform storage resource inference on each memory structure based on the attribute constraint information in each memory structure and the number of various types of storage resources supported by the target FPGA device if each memory structure also includes attribute constraint information, so as to obtain the target storage resource type of each memory structure.

[0142] Optionally, the inference module 120 is also used to determine the required storage resource quantity of the storage resource type corresponding to the attribute constraint information of each memory structure and the target storage resource quantity of the corresponding storage resource type; if the required storage resource quantity does not exceed the target storage resource quantity of the corresponding storage resource type, the target storage resource type corresponding to each memory structure is inferred as the corresponding storage resource type; if the required storage resource quantity exceeds the target storage resource quantity of the corresponding storage resource type, the inference error information for the corresponding storage resource type is output.

[0143] The above-mentioned device is used to execute the method provided in the above-mentioned embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0144] The above modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented by scheduling program code through a processing element, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0145] Figure 9 This is a schematic diagram of an electronic device provided in an embodiment of the present application, which can be used for logic synthesis of FPGA devices. Figure 9 As shown, the electronic device includes: a processor 210 , a storage medium 220 , and a bus 230 .

[0146] Storage medium 220 stores machine-readable instructions executable by processor 210. When the electronic device is running, processor 210 communicates with storage medium 220 via bus 230, and processor 210 executes the machine-readable instructions to perform the steps of the above method embodiment. The specific implementation methods and technical effects are similar and will not be repeated here.

[0147] Optionally, the present application further provides a storage medium 220 on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method embodiment are executed. The specific implementation and technical effects are similar and will not be repeated here.

[0148] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0150] In addition, the functional units in various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or hardware plus software functional units.

[0151] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (English: Read-Only Memory, abbreviated: ROM), a random access memory (English: Random Access Memory, abbreviated: RAM), a magnetic disk or an optical disk, and other media that can store program code.

[0152] The above are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A logic synthesis method for an FPGA device, characterized in that: The method comprises: Identifying a plurality of memory structures corresponding to the target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least: capacity information; Based on the capacity information and the number of each type of storage resources supported by the target FPGA device, storage resource inference is performed on the multiple memory structures to obtain a target storage resource type for each memory structure.

2. The method according to claim 1, characterized in that The performing storage resource inference on the multiple memory structures based on the capacity information and the number of each type of storage resources supported by the target FPGA device to obtain a logic resource inference result of the FPGA device includes: sorting the plurality of memory structures from largest to smallest according to the capacity information; According to the number of each type of storage resources supported by the target FPGA device, storage resource inference is performed on each sorted memory structure in turn to obtain the target storage resource type corresponding to each memory structure.

3. The method according to claim 2, characterized in that The various types of storage resources include: block storage resources, distributed storage resources and logical storage resources; The method of performing storage resource inference on each sorted memory structure in turn according to the number of each type of storage resource supported by the target FPGA device to obtain a target storage resource type corresponding to each memory structure includes: According to the number of target block storage resources supported by the target FPGA device, executing a first inference process for block storage resources on each of the sorted memory structures in sequence; If the first inference process is completed, executing a second inference process for distributed storage resources on the first remaining memory structure after the first inference process is completed according to the number of target distributed storage resources supported by the target FPGA device; If a second remaining memory structure still exists after the second inference process is executed, the second remaining memory structure is logically split according to the number of remaining logic storage resources supported by the target FPGA device.

4. The method according to claim 3, characterized in that The first inference process for block storage resources is sequentially executed on each sorted memory structure according to the target number of block storage resources supported by the target FPGA device, including: Determine the sum of the first block storage resource quantity required by the first to-be-inferred memory structure and the currently used second block storage resource quantity in each of the sorted memory structures as the required block storage resource quantity; If the required number of block storage resources does not exceed the target number of block storage resources, inferring the target storage resource type corresponding to the first to-be-inferred memory structure as block storage resources; If the required number of block storage resources exceeds the target number of block storage resources, it is determined that the first inference process is terminated.

5. The method according to claim 3, characterized in that The step of executing a second inference process for distributed storage resources on the first remaining memory structure after the first inference process is completed according to the target number of distributed storage resources supported by the target FPGA device includes: Determine the sum of the first distributed storage resource quantity required for the second to-be-inferred memory structure in the first remaining memory structure and the currently used second distributed storage resource quantity as the required distributed storage resource quantity; If the required number of distributed storage resources does not exceed the target number of distributed storage resources, inferring the target storage resource type corresponding to the second memory structure to be inferred as a distributed storage resource; If the required number of distributed storage resources exceeds the target number of distributed storage resources, it is determined that the second inference process is completed.

6. The method according to claim 3, characterized in that Before performing logical resource splitting on the second remaining memory structure according to the target number of logical storage resources supported by the target FPGA device, the method further includes: estimating the amount of logical resources required by the second remaining memory structure according to the capacity information of the second remaining memory structure; The step of splitting the second remaining memory structure into logical resources according to the number of remaining logical storage resources supported by the target FPGA device includes: If the number of logic resources required by the second remaining memory structure does not exceed the number of remaining logic storage resources, the second remaining memory structure is split into lookup table resources and register resources as logic resources.

7. The method according to claim 6, characterized in that The method further comprises: If the number of logical resources required by the second remaining memory structure exceeds the number of remaining logical storage resources, an error message regarding splitting the logical resources is output.

8. The method according to claim 1, characterized in that The method further comprises: If each of the memory structures also includes attribute constraint information, then storage resource inference is performed on each of the memory structures based on the attribute constraint information in each of the memory structures and the number of each type of storage resources supported by the target FPGA device to obtain the target storage resource type of each of the memory structures.

9. The method according to claim 8, characterized in that The performing storage resource inference on each memory structure based on the attribute constraint information in each memory structure and the number of each type of storage resources supported by the target FPGA device to obtain the target storage resource type of each memory structure includes: Determine the required storage resource quantity of the storage resource type corresponding to the attribute constraint information of each memory structure and the target storage resource quantity of the corresponding storage resource type; If the required storage resource quantity does not exceed the target storage resource quantity of the corresponding storage resource type, inferring the target storage resource type corresponding to each memory structure as the corresponding storage resource type; If the required storage resource quantity exceeds the target storage resource quantity of the corresponding storage resource type, an inference error message for the corresponding storage resource type is output.

10. A logic synthesis device for an FPGA device, characterized in that: The device comprises: An identification module is used to identify multiple memory structures corresponding to the target FPGA device from a logic design file of the target FPGA device; each memory structure includes at least: capacity information; An inference module is used to perform storage resource inference on the multiple memory structures based on the capacity information and the number of each type of storage resources supported by the target FPGA device, so as to obtain a target storage resource type for each memory structure.

Images