Display pixel signal processing method, display pixel driving circuit and display device

Abstract

The invention discloses a display pixel signal processing method, a display pixel driving circuit and a display device, and the method comprises the steps: adding a sub-pixel equalizer in a data driving circuit, and carrying out equalization processing on the digital gray scale signals or / and the digital voltage signals of the at least two sub-pixels sharing the same control unit in space and / or time according to a preset proportion. According to the display device, the data voltage of the sub-pixels can be balanced under the condition that the CUP area aperture ratio of the display device is increased, the color cast problem existing in the CUP area is solved, and the display effect of the display device is improved.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a display pixel signal processing method, a display pixel driving circuit and a display device. Background Art

[0002] In recent years, full-screen display devices have received widespread attention in the market and have broad application prospects. Figure 1 As shown, a photosensitive element 13, such as a camera, a light sensor, a fingerprint sensor, etc., is arranged below the display screen to realize a full-screen display device. The display screen includes an upper substrate, a lower substrate layer 10, and a control unit 11 (such as a TFT) arranged on the substrate layer 10 and sub-pixels 12 connected thereto. Figure 2 As shown, the photosensitive element 13 corresponds to the second display area 1 of the display screen, that is, the camera under panel (CUP) area, and the rest is the first display area 2, that is, the normal display area. The CUP area needs to be equipped with sub-pixels and their control circuits for normal display, and the photosensitive element 13 senses the light transmitted by the display screen. Therefore, compared with non-under-screen photosensitive devices, the transmittance of the CUP area is greatly reduced, which seriously affects the photosensitivity of the photosensitive device 13. In order to alleviate the problem of poor photosensitivity caused by the greatly reduced transmittance of the photosensitive CUP area, the following methods are often used in the prior art to solve this problem:

[0003] like Figure 3 in Figure 3 As shown in a, the source line in the CUP area is arranged as far away from the CUP area as possible. For example, the source line is arranged to expand outwards on both sides of the CUP area to increase the light transmittance of the CUP area. At the same time, transparent metal (ITO) is used as the anode layer of the OLED element to increase the aperture ratio. However, as Figure 3 As shown in b, this method leads to serious display unevenness.

[0004] In order to alleviate the aforementioned display unevenness, the prior art often adds a gamma voltage circuit to the sub-pixels in the CUP area to provide the matching voltage level required to achieve uniform display. However, the added gamma voltage circuit occupies a large area of ​​the data driving circuit, which is very unfavorable for the miniaturization of the display driver chip, and the addition of the gamma voltage circuit will greatly increase the difficulty of the manufacturing process and is not conducive to reducing costs. In order to balance the needs of miniaturization, cost reduction and uniform display of the display driver chip in the prior art, some have proposed setting the control units (such as thin film transistors TFT) of the sub-pixels in the CUP area to be shared. This can reduce the number of control units in the CUP area to increase the aperture ratio of the CUP area and thus improve the light transmission efficiency, and at the same time avoid the obstacles to miniaturization and cost reduction caused by the addition of a gamma voltage circuit. For example Figure 4The figure shows an example of a conventional method of sharing the control units (e.g., thin-film transistors (TFTs)) of the sub-pixels in the CUP region. In the CUP region, a single TFT is used to connect multiple sub-pixels to reduce the number of TFTs required, thereby increasing the aperture ratio. Sub-pixel G0 is passively shared with sub-pixel G1, and sub-pixel G2 is passively shared with sub-pixel G3. The control units TFTg1 and TFTg3 that originally controlled the actively shared sub-pixels G1 and G3 can be removed. However, this arrangement prevents the actively shared sub-pixels G1 and G3 from receiving their intended display pixel signals SG1 and SG3, resulting in severe display unevenness. For example, when the first pixel 121 and the second pixel 122 need to display different colors, for example, one needs to display black and the other needs to display white, the voltage level required by the green sub-pixel G0 is very different from the voltage level required by the green sub-pixel G1, but the same control unit TFT can only input the same voltage level to the green sub-pixel G0 and the green sub-pixel G1 at the same time, resulting in one of the first pixel 121 and the second pixel 122 inevitably unable to display the required color, thereby causing a color deviation problem, resulting in poor display effect of the display screen. Summary of the Invention

[0005] The object of the present invention is to provide a display pixel signal processing method, a display pixel driving circuit and a display device, which are used to solve the color shift problem in the CUP area while increasing the aperture ratio of the CUP area and improve the display effect of the display device.

[0006] In order to solve the above problems, the present invention is achieved through the following technical solutions:

[0007] A display pixel signal processing method adds a sub-pixel equalizer to a data driving circuit to equalize digital grayscale signals and / or digital voltage signals of at least two sub-pixels sharing the same control unit according to a preset ratio in space and / or time.

[0008] Optionally, the spatial equalization processing according to a preset ratio includes: within a same frame of image data, performing weighted averaging of the digital grayscale signals or / and digital voltage signals of sub-pixels sharing the same control unit according to a preset weight ratio for equalization processing. Alternatively, the temporal equalization processing according to a preset ratio includes: presetting a certain number of frames of image data as a cycle, and directly outputting the digital grayscale signals or / and digital voltage signals of sub-pixels sharing the same control unit in a time-sharing manner according to a preset frame ratio for equalization processing.

[0009] Optionally, the preset ratio includes an equal ratio or an unequal ratio.

[0010] Optionally, in the cycle, the frame ratio is selected with a certain number of frames between them or without any frame intervals.

[0011] Optionally, several sub-pixels form a first display area and a second display area on the display panel, the second display area corresponds to the under-screen camera area, and the first display area corresponds to the non-under-screen camera area.

[0012] Optionally, the sub-pixel equalizer is enabled and controlled to output an equalized signal when the second display area is displaying, and output a non-equalized signal otherwise.

[0013] Optionally, the sub-pixel equalizer processes signals of data lines matched with sub-pixels only throughout the second display area, or processes signals of data lines matched with sub-pixels only within a preset area of ​​the second display area and a first display area adjacent to the second display area.

[0014] Optionally, the sub-pixel equalizer includes at least one sub-equalizer, and one sub-equalizer is used to process a display pixel signal corresponding to at least one data line.

[0015] Optionally, at least two sub-pixels sharing the same control unit have the same color.

[0016] Optionally, the same color includes any one of red, green, blue, cyan, magenta, yellow, and white.

[0017] Optionally, blue sub-pixels sharing the same control unit are located in different columns, and / or red sub-pixels sharing the same control unit are located in different columns, and / or green sub-pixels sharing the same control unit are located in different columns and / or the same column.

[0018] Optionally, among the at least two sub-pixels, there is one active shared sub-pixel and at least one passive shared sub-pixel, wherein the at least one active shared sub-pixel is arranged in the second display area of ​​the display panel;

[0019] And / or, one or more control units are provided, and the control units are provided in the first display area and / or the second display area.

[0020] On the other hand, the present invention further provides a display pixel driving circuit according to the method described above, wherein the display pixel driving circuit includes a sub-pixel equalizer.

[0021] Optionally, the display pixel driving circuit further includes: a shift register module and a gamma voltage module; wherein the sub-pixel equalizer is integrated into the shift register module or the gamma voltage module, or the sub-pixel equalizer is independently arranged before or after the gamma voltage module.

[0022] Optionally, the sub-pixel equalizer includes an adder for adding the signals of the sub-pixels sharing the same control unit, and a divider for dividing the addition result of the adder into equal parts based on the number of sub-pixels sharing the same control unit.

[0023] Optionally, the sub-pixel equalizer includes a multiplier configured to assign a weight coefficient to each signal of the sub-pixels sharing the same control unit, and an adder configured to add the signals of the sub-pixels sharing the same control unit that are assigned the weight coefficients.

[0024] Optionally, the sum of the weight coefficients is equal to 1.

[0025] Optionally, the sub-pixel equalizer further includes a multiplexer for enabling control to directly output the signal of the passive shared sub-pixel or the equalized signal.

[0026] Optionally, the sub-pixel equalizer includes: a first multiplexer having at least two output channels, wherein different output channels are used to control the direct output of signals of passively shared sub-pixels or actively shared sub-pixels at a certain frame ratio for equalization processing; and a second multiplexer for enabling control of the direct output of signals of passively shared sub-pixels or signals selected for output by the first multiplexer.

[0027] Optionally, the first multiplexer includes two output channels, and the frame ratios of the two output channels are equal, and the frame ratios are selected at intervals of 1 frame.

[0028] On the other hand, the present invention also provides a display device, comprising: a display panel, the display panel comprising a first display area and a second display area; a display pixel driving circuit as described above, for driving the display panel to display an image; and a camera assembly, the camera assembly corresponding to the second display area being formed as an under-screen camera.

[0029] The present invention has at least one of the following technical effects:

[0030] The display pixel signal processing method provided by the present invention incorporates a sub-pixel equalizer in a data driver circuit. The sub-pixel equalizer is used to spatially and / or temporally equalize the digital grayscale signals and / or digital voltage signals of at least two sub-pixels sharing a common control unit according to a preset ratio. When the equalized display pixel signals are input to the corresponding sub-pixels for display, the color shift problem existing in existing display devices is resolved, improving display quality and further enabling smaller and more cost-effective display driver chips.

[0031] The present invention utilizes a sub-pixel equalizer to process signals from data lines matching sub-pixels in the second display region, or to process signals from data lines matching sub-pixels within a predetermined area of ​​the second display region and a first display region adjacent to the second display region. This equalized display pixel signal is then input to the corresponding sub-pixel for display, thereby resolving the color shift problem in the second display region of existing display devices, improving display quality, and further enabling smaller and more cost-effective display driver chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of an existing display device;

[0033] Figure 2 A schematic diagram of the partitions of an existing full-screen display;

[0034] Figure 3 A schematic diagram of the data line distribution structure and display effect of the CUP area in an existing display panel;

[0035] Figure 4 Schematic diagram of the distribution of some sub-pixels in the CUP area of ​​a display panel in the prior art;

[0036] Figure 5 A schematic flow chart of a display pixel signal processing method provided by one embodiment of the present invention;

[0037] Figure 6 A schematic diagram of a partial structure of a display pixel driving circuit provided by an embodiment of the present invention;

[0038] Figure 7 A schematic diagram of a partial structure of a display pixel driving circuit provided by another embodiment of the present invention;

[0039] Figure 8 A schematic diagram of the structure of a sub-equalizer provided by an embodiment of the present invention for spatially processing signals of two sub-pixels;

[0040] Figure 9 A schematic diagram of the structure of a sub-equalizer provided by an embodiment of the present invention for spatially processing signals of four sub-pixels;

[0041] Figure 10 A schematic diagram of the specific structure of a sub-equalizer for spatially equalizing signals of two sub-pixels at an equal ratio, provided by one embodiment of the present invention;

[0042] Figure 11 A schematic diagram of the specific structure of a sub-equalizer for equalizing signals of two sub-pixels at unequal ratios in space provided by an embodiment of the present invention;

[0043] Figure 12A schematic diagram of the structure of a sub-equalizer according to an embodiment of the present invention processing signals of two sub-pixels in time;

[0044] Figure 13 A schematic diagram of the structure of a sub-equalizer according to an embodiment of the present invention processing signals of four sub-pixels in time;

[0045] Figure 14 for Figure 12 The specific structural diagram of the sub-equalizer is shown. DETAILED DESCRIPTION

[0046] The following is a further detailed description of a display pixel signal processing method, a display pixel driving circuit surface and a display device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the implementation conditions of the present invention, so they have no technical substantive significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention.

[0047] like Figure 5 As shown, this embodiment provides a display pixel signal processing method, comprising: step S1, adding a sub-pixel equalizer to a data driving circuit; step S2, equalizing the digital grayscale signals and / or digital voltage signals of at least two sub-pixels sharing the same control unit in space and / or time according to a preset ratio.

[0048] Therefore, when the equalized display pixel signal is input to the corresponding sub-pixel for display, the display effect can be balanced, providing the possibility of miniaturization and cost reduction of the display driver chip while further solving the color cast problem existing in the existing display device / panel.

[0049] In this embodiment, the spatial equalization processing according to a preset ratio in step S2 includes: in the same frame of image data, the digital grayscale signals and / or digital voltage signals of the sub-pixels sharing the same control unit are weighted averaged according to a preset weight ratio for equalization processing.

[0050] Alternatively, the temporal equalization processing according to a preset ratio includes: presetting a certain number of frames of image data as a cycle, and directly outputting the digital grayscale signals and / or digital voltage signals of sub-pixels sharing the same control unit in a time-sharing manner according to a preset frame ratio for equalization processing.

[0051] Both of these equalization processes can achieve a balanced display effect of panel pixels, solving the color cast problem existing in existing display devices / panels.

[0052] In this embodiment or some other embodiments, the preset ratio includes an equal ratio or an unequal ratio.

[0053] The setting method of the preset ratio can freely set its value according to the display effect of the panel pixels, which can be specifically achieved by setting the chip register of the data driving circuit.

[0054] In this embodiment or some other embodiments, in the cycle, the frame ratio or the preset frame ratio is selected with a certain number of frames between intervals or without any intervals between frames.

[0055] In this embodiment, a plurality of sub-pixels form a first display area and a second display area on the display panel. The second display area corresponds to the under-screen camera area, and the first display area corresponds to the non-under-screen camera area. The first display area is the normal display area, and the pixel density of the second display area is lower than that of the first display area.

[0056] In this embodiment, the sub-pixel equalizer is enabled and controlled to output an equalized signal when the second display area is displaying, and output a non-equalized signal otherwise.

[0057] In this embodiment, the sub-pixel equalizer processes signals of data lines matched with sub-pixels only in the second display area, or processes signals of data lines matched with sub-pixels only in a preset area of ​​the second display area and a first display area adjacent to the second display area.

[0058] In this embodiment, the sub-pixel equalizer includes at least one sub-equalizer, and one sub-equalizer is used to process a display pixel signal corresponding to at least one data line.

[0059] In this embodiment, at least two sub-pixels sharing the same control unit have the same color.

[0060] In this embodiment, the same color includes any one of red, green, blue, cyan, magenta, yellow, and white.

[0061] In this embodiment, blue sub-pixels sharing the same control unit are located in different columns, and / or red sub-pixels sharing the same control unit are located in different columns, and / or green sub-pixels sharing the same control unit are located in different columns and / or the same column.

[0062] For example, Figure 6 As shown, sub-pixel G0 is passively shared with sub-pixel G1, and sub-pixel G2 is passively shared with sub-pixel G3. The control units TFTg1 and TFTg3 that originally control the actively shared sub-pixels G1 and G3 can be removed. The number of sub-pixels sharing the same control unit (e.g., Thin Film Transistor (TFT)) is two, and the color of the sub-pixels is green. The two green sub-pixels (refer to Figure 6 In the example, the sub-pixels (as shown by labels G0 and G1, or G2 and G3) are located in different columns, but in the specific embodiment, the number of shared sub-pixels, color type, and sub-pixel position are not limited thereto, and the colors of the shared sub-pixels are the same.

[0063] The additional sub-pixel equalizer (eg, sub-equalizer 300) is disposed on the display pixel signal transmission path of the passively shared sub-pixel. Figure 6 , it is shown that the sub-pixel equalizer (e.g., sub-equalizer 300) is integrated into the shift register (SREG) 220, and the data driving circuit includes a sub-pixel rendering (SPR) 200, a gamma voltage module (GMA) 210, a shift register (SREG) 220, and a digital-to-analog conversion module 230. In other embodiments, the sub-pixel equalizer (e.g., sub-equalizer 300) can also be integrated into the gamma voltage module (GMA) 210, or formed as a separate sub-pixel equalizer module. The sub-pixel equalizer can be composed of multiple sub-equalizers, and different sub-equalizers are used to process display pixel signals corresponding to different data lines. Figure 6 For example, the display pixel signals SG0 and SG1 of the green sub-pixel G0 and sub-pixel G1 are equalized to SG01 by the sub-pixel equalizer (e.g., the sub-equalizer 300) so as to be equally driven, and the display pixel signals SG2 and SG3 of the sub-pixel G2 and sub-pixel G3 are equalized to SG23 by the sub-pixel equalizer (e.g., the sub-equalizer 300) so as to be equally driven. To further illustrate this embodiment, as shown in FIG. Figure 7 As shown, examples of the number of sub-pixels sharing the same control unit are two or four, and the sub-pixels of the three primary colors of red, green, and blue are all provided with shared sub-pixels. Preferably, the number of sub-pixels sharing the same control unit is two, such as the two sub-pixels R0 and R3 are red, and the two red sub-pixels R0 and R3 are located in different columns. The two sub-pixels B1 and B2 are blue, and the two blue sub-pixels B1 and B2 are located in different columns. Preferably, the red sub-pixel R0 and the blue sub-pixel B2 are located in the same column, and the two control units are connected using the same data line.

[0064] The red sub-pixel R3 and the blue sub-pixel B1 are located in the same column, and the two control units are connected by another data line.

[0065] At the same time, there are four sub-pixels sharing the same control unit, and the color of the sub-pixels is green. Among them, the green sub-pixel G0 and the green sub-pixel G1 are located in different columns. The green sub-pixel G0 and the green sub-pixel G2 are located in the same column, and the green sub-pixel G1 and the green sub-pixel G3 are located in the same column.

[0066] The above-mentioned arrangements and combinations are only preferred examples. The arrangement of sub-pixels can be freely combined as required, and the present invention is not limited thereto.

[0067] like Figure 7 For example, through the added sub-pixel equalizer, the display pixel signals SG0, SG1, SG2, and SG3 of the green sub-pixels G0, G1, G2, and G3 are equalized to SG0123 through the sub-pixel equalizer (for example, the sub-equalizer 300) so that they are equally driven. The display pixel signals SR0 and SR3 of the red sub-pixel R0 and sub-pixel R3 are equalized to SR03 through the sub-pixel equalizer (for example, the sub-equalizer 300) so that they are equally driven. The display pixel signals SB1 and SB2 of the blue sub-pixel B1 and sub-pixel B2 are equalized to SB12 through the sub-pixel equalizer (for example, the sub-equalizer 300) so that they are equally driven.

[0068] The sub-pixels that share a control unit have the same color, which may include any one of red, green, blue, cyan, magenta, yellow, and white.

[0069] In this embodiment, among the at least two sub-pixels, there is one active shared sub-pixel and at least one passive shared sub-pixel, wherein at least one active shared sub-pixel is set in the second display area of ​​the display panel. And / or, one or more control units are set, and the control units are set in the first display area and / or the second display area. The so-called active shared sub-pixel is a sub-pixel whose control unit is removed and the control unit that needs to share other sub-pixels is removed, for example, Figure 7 The green sub-pixels G0, G1, and G3 shown in FIG are active shared sub-pixels; the so-called passive shared sub-pixels are sub-pixels whose own control unit needs to lend out for sharing with other sub-pixels, such as the attached Figure 7 The green sub-pixel G2 shown in FIG. 1 is a passive shared sub-pixel.

[0070] On the other hand, the present invention further provides a display pixel driving circuit according to the method described above, wherein the display pixel driving circuit includes a sub-pixel equalizer.

[0071] In this embodiment, the display pixel driving circuit further includes: a shift register module and a gamma voltage module; wherein the sub-pixel equalizer is integrated in the shift register module or the gamma voltage module, or the sub-pixel equalizer is independently arranged before or after the gamma voltage module, wherein the sub-pixel equalizer arranged before the gamma voltage module can perform equalization processing on the digital grayscale signal, and arranged after the gamma voltage module can perform equalization processing on the digital voltage signal.

[0072] For example, in this embodiment, please continue to refer to Figure 6 and Figure 7 As shown, the sub-pixel equalizer includes at least one sub-equalizer 300, wherein the sub-equalizer 300 is integrated into the shift register module 220. The output end of the shift register module 220 is connected to the sub-pixels of the first display area through multiple data lines.

[0073] The display pixel driving circuit further includes: a sub-pixel rendering module 200 connected to the gamma voltage module 210 , and the gamma voltage module 210 is connected to an input end of the shift register module 220 .

[0074] The image data includes multiple frames, and each frame of image data includes multiple rows of first digital grayscale signals; the sub-pixel rendering module 200 is used to process the first digital grayscale signal of each input row and output a second digital grayscale signal; the gamma voltage module 210 is used to process the second digital grayscale signal input and output the digital voltage signal to the input end of the shift register 220.

[0075] In this embodiment, the display pixel driving circuit also includes: a digital-to-analog conversion module 230, which is used to be connected to the corresponding control unit and the output end of the shift register module 220 through corresponding data lines, and is used to convert the digital voltage signal output by the shift register module 220 into an analog voltage signal and input it to the sub-pixel to drive the sub-pixel to display the corresponding color.

[0076] Please continue to refer to Figure 6 As shown, the sub-equalizer 300 is used to drive two green sub-pixels ( Figure 6 The first green digital voltage signal SG0 and the second green digital voltage signal SG1 (labeled G0 and G1) are equalized in space and / or time according to a preset ratio to obtain a green balanced digital voltage signal SG01, which is output to the corresponding digital-to-analog conversion module 230 through the shift register module 220. The digital-to-analog conversion module 230 converts the received green balanced digital voltage signal SG01 into a green balanced analog voltage signal and outputs it to the two green sub-pixels ( Figure 6(labeled G0 and G1).

[0077] The shift register module 220 further outputs the red digital voltage signal SR0 and the blue digital voltage signal SB1 to the corresponding digital-to-analog conversion module 230. The digital-to-analog conversion module 230 performs digital-to-analog conversion on the red sub-pixel R0 and the blue sub-pixel B1 respectively through the corresponding control unit. Similarly, the sub-equalizer 300 further equalizes the third green digital voltage signal SG2 and the fourth green digital voltage signal SG3 in space and / or time according to a preset ratio to obtain another green balanced digital voltage signal SG23, and outputs it to the two green sub-pixels ( Figure 6 As shown in the figure, the sub-equalizer 300 is set to equalize the intensity or size of the digital voltage signal, thereby solving the problem that the green sub-pixel ( Figure 6 Data lines and control units (numbered G1 and G3) Figure 6 As a result, the corresponding second green digital voltage signal SG1 and fourth green digital voltage signal SG3 cannot be input to the green sub-pixel labeled G1 and the green sub-pixel labeled G3, resulting in a color shift problem when the image is displayed in this area.

[0078] Please continue to refer to Figure 7 As shown, with two red sub-pixels ( Figure 7 The sub-equalizer 300 connected to the data lines (numbered R0 and R3) performs spatial and / or temporal equalization processing on the first red digital voltage signal SR0 and the second red digital voltage signal SR3 according to a preset ratio to obtain a red balanced digital voltage signal SR03, and outputs the red balanced digital voltage signal SR03 to the corresponding digital-to-analog conversion module 230 through the shift register module 220. The digital-to-analog conversion module 230 converts the received red balanced digital voltage signal SR031 into a red balanced analog voltage signal and outputs it to the two red sub-pixels ( Figure 7 with two blue sub-pixels ( Figure 7 The sub-equalizer 300 connected to the data lines (numbered B1 and B2) performs spatial and / or temporal equalization processing on the first blue digital voltage signal SB1 and the second blue digital voltage signal SB2 according to a preset ratio to obtain a blue balanced digital voltage signal SB12, and outputs the blue balanced digital voltage signal SB12 to the corresponding digital-to-analog conversion module 230 through the shift register module 220. The digital-to-analog conversion module 230 converts the received blue balanced digital voltage signal SB12 into a blue balanced analog voltage signal and outputs it to the two blue sub-pixels ( Figure 7(labeled B1 and B2).

[0079] With four green sub-pixels ( Figure 7 The sub-equalizer 300 connected to the data lines (numbered G0 to G3) performs spatial and / or temporal equalization processing on the first green digital voltage signal SG0 to the fourth green digital voltage signal SG3 according to a preset ratio to obtain a green balanced digital voltage signal SG0123, and outputs the green balanced digital voltage signal SG0123 to the corresponding digital-to-analog conversion module 230 through the shift register module 220. The digital-to-analog conversion module 230 converts the received green balanced digital voltage signal SG0123 into a green balanced analog voltage signal and outputs it to the four green sub-pixels ( Figure 7 The winning numbers are G0~G3).

[0080] It can be seen that the setting of the sub-equalizer 300 balances the intensity or size of the corresponding digital voltage signal, thereby alleviating the problem that the green sub-pixel ( Figure 7 Control unit (G1 and G3) Figure 7 The problem of color shift when displaying an image in this area may occur due to the failure of the green sub-pixel labeled TFTg1 and TFTg3 in the middle and other control units (for example, the control units connected to the red and blue sub-pixels) to input the corresponding second green digital voltage signal SG1 and fourth green digital voltage signal SG3 to the green sub-pixel labeled G1 and the green sub-pixel labeled G3; and / or the problem of color shift when displaying an image in this area may occur due to the failure of the red sub-pixel labeled R3 and the blue sub-pixel labeled B2 to input the corresponding second red digital voltage signal SR3 and second blue digital voltage signal SB2.

[0081] In this embodiment, if Figures 8 to 11 , illustrating the structure of the spatial sub-pixel equalizer, Figures 8 and 9 The following examples illustrate sub-pixel equalizers applicable to two and four sub-pixels shared, respectively. The enable signal is used to control whether to output the equalization signal. For example, the equalization signal is output when displaying in the second display area, and the display signal of the passive shared sub-pixel is normally output when displaying in the first display area. Figures 10-11 Examples of sub-pixel equalizer structures for two sub-pixels with equal or selectable (equal or unequal) ratios are provided. When the sub-pixel equalizer is used to spatially equalize display pixel signals according to a preset ratio, each sub-equalizer includes an adder for adding the signals of the sub-pixels sharing the same control unit. A divider is used to divide the result of the addition by the adder equally based on the number of sub-pixels sharing the same control unit.

[0082] For example, combined with Figure 6 and Figure 10 As shown, the number of sub-pixels sharing the same control unit is 2. Therefore, the sub-equalizer 300 is used to implement proportional equalization. The adder is used to add the first green digital voltage signal SG0 and the second green digital voltage signal SG1. Then, the result of the addition by the adder is divided by 2 by a divider to obtain the green balanced digital voltage signal SG01.

[0083] In this embodiment or some other embodiments, a sub-equalizer for implementing optional proportional equalization is further provided. Figure 11 As shown, the sub-pixel equalizer includes a multiplier for assigning a weight coefficient to the signal of each sub-pixel sharing the same control unit. An adder for adding the signals of the sub-pixels sharing the same control unit that are assigned the weight coefficients. In this embodiment or some other embodiments, the sum of the weight coefficients is equal to 1.

[0084] For example, combined with Figure 6 and Figure 11 As shown, a multiplier of the sub-equalizer 300 multiplies the first green digital voltage signal SG0 by a first weighting coefficient. Another multiplier of the sub-equalizer 300 multiplies the second green digital voltage signal SG1 by a second weighting coefficient. An adder of the sub-equalizer 300 adds the first green digital voltage signal SG0 and the second green digital voltage signal SG1, each assigned a weighting coefficient, to generate the green balanced digital voltage signal SG01. The first weighting coefficient is 1-α, the second weighting coefficient is α, and the sum of the first and second weighting coefficients is 1.

[0085] Combine Figure 10 and Figure 11 As shown, the sub-pixel equalizer further includes a multiplexer MUX for enabling control of directly outputting the signal of the passive shared sub-pixel or the equalized signal, thereby controlling the output of the equalized signal when displaying in the second display area and outputting the non-equalized signal when displaying in the first display area, thereby improving the display effect of the entire display area.

[0086] For example, combined with Figure 6 、 Figure 8 、 Figure 10 and Figure 11 As shown, the multiplexer MUX is controlled according to the enable signal enable to output the equalized green balanced digital voltage signal SG01 (or SG23) or directly output the green digital voltage signal SG0 (or SG2).

[0087] For further explanation, please refer to the attached Figure 9This example illustrates a spatial sub-pixel equalizer suitable for four sub-pixels sharing a single control unit. Display pixel signals SG0, SG1, SG2, and SG3 can be weighted averaged in equal or unequal proportions to obtain equalized signal SG0123 for improved display quality, or weighted averaged SG4, SG5, SG6, and SG7 to obtain equalized signal SG4567 for improved display quality.

[0088] In this embodiment, the present invention also provides a temporal sub-pixel equalizer. Figures 12-13 The temporal sub-pixel equalizer for sharing two or four sub-pixels is illustrated respectively. The enable signal is used to control the output of the equalization signal or directly output the display pixel signal of the passively shared sub-pixel. Frame_no%n ​​(n represents the number of sub-pixels sharing a control unit, and Frame_no%n ​​represents the control signal corresponding to the remainder 0 to n-1 when the number of frames in a cycle is divided by the number of sub-pixels sharing a control unit n) indicates that a certain number of frames is selected in time to directly output the display pixel signal of the passively shared sub-pixel, and another number of frames is selected to directly output the display pixel signal of the actively shared sub-pixel. Thus, the sub-pixel equalizer can equalize the display pixel signal according to a preset ratio in time. Figures 12-13 The cases of Frame_no% 2 and Frame_no% 4 are respectively exemplified.

[0089] For example, Figure 14 Each sub-equalizer of the sub-pixel equalizer includes a first multiplexer MUX11 having at least two output channels, with different output channels being used to control the direct output of signals of a certain frame ratio of passively shared sub-pixels or active shared sub-pixels for equalization processing. A second multiplexer MUX12 is used to enable control of the direct output of signals of passively shared sub-pixels or signals selected for output by the first multiplexer MUX11.

[0090] For example, please refer to Figure 14 As shown, the first multiplexer MUX11 is configured to select a corresponding digital voltage signal based on an input selection signal (select) and output it to the second multiplexer MUX12. The selection signal (select) switches the display signal output for active or passive shared sub-pixels based on the frame count of the image data. The second multiplexer MUX12 is configured to control whether to output the received digital voltage signal based on an enable signal (enable), thereby outputting an equalized signal when displaying in the second display area and a non-equalized signal when displaying in the first display area, thereby improving the display quality of the entire display area.

[0091] Please continue to refer to Figure 6 and Figure 14As shown, the select signal varies according to the frame count. Taking two sub-pixels G0 and G1 sharing (Frame_no %2) as an example, within a certain frame number cycle (for example, 10 (respectively labeled as frame_no 0 to 9 frame image signals) image signals as one cycle, where 10 frames is only an example and is not limited to this in specific embodiments), assuming that time proportional equalization is achieved, the logic program of the select signal can be:

[0092] if(frame_no==0|frame_no==2|frame_no==4|frame_no==6|frame_no==8)

[0093] select=0;

[0094] Else

[0095] select=1;

[0096] That is, the display pixel signal of the passive shared sub-pixel G0 is selected for output in the even-numbered frames, and the display pixel signal of the active shared sub-pixel G1 is selected for output in the odd-numbered frames.

[0097] Assuming that time non-uniform equalization is implemented (for example, when equalizing, the passive sub-pixels account for 40% and the active sub-pixels account for 60%), the logic program of the select signal can be:

[0098] if(frame_no==0|frame_no==2|frame_no==4|frame_no==6)

[0099] select=0;

[0100] Else

[0101] select=1;

[0102] That is, the display pixel signal output of the passive shared sub-pixel G0 is selected in the 0th, 2nd, 4th, and 6th frames, and the display pixel signal output of the active shared sub-pixel G1 is selected in the 1st, 3rd, 5th, and 7th to 9th frames. In a specific embodiment, this is not a limitation, and 40% of the frames in a cycle can be arbitrarily selected to select the display pixel signal output of the passive shared sub-pixel G0, and 60% of the frames can be used to select the display pixel signal output of the active shared sub-pixel G1. Optionally, in the number of frames within a cycle, the select signal is flipped once at intervals of a certain number of frames (for example, 0, 1, or more frames). Preferably, according to the number of passive shared sub-pixels and active shared sub-pixels that share a control unit, each sub-pixel outputs its own display pixel signal at intervals to achieve display uniformity to the greatest extent.

[0103] For further explanation, please see the attached Figure 13 , which illustrates a temporal sub-pixel equalizer suitable for four sub-pixels sharing a control unit. For example, four frames of image data (respectively labeled as frame_no0 to frame_no3) can be considered a cycle. In one cycle, the display pixel signals SG0, SG1, SG2, and SG3 corresponding to the 0th, 1st, 2nd, and 3rd frames of image data are output, which are equivalent to the equalization signal SG0123 for improved display effects. Alternatively, the display pixel signals SG4, SG5, SG6, and SG7 corresponding to the 0th, 1st, 2nd, and 3rd frames of image data are output, which are equivalent to the equalization signal SG4567 for improved display effects.

[0104] It can be seen that by providing a temporal sub-pixel equalizer, the temporal display effect of the CUP area and its surrounding areas will not always be biased towards the original display pixel signal of the active shared sub-pixel, nor will it always be biased towards the display pixel signal of the passive shared sub-pixel. This can further improve the color shift of the CUP area while ensuring the aperture ratio of the CUP area, thereby improving the display effect of the display device, low-cost manufacturing, and small-size scale.

[0105] like Figure 14 For example, the second multiplexer MUX12 is controlled by an enable signal (enable). When displaying in the second display area, enable = 1, and outputs the output signal of the first multiplexer MUX11, i.e., the sub-pixel equalization signal. When the frame count is even, the first multiplexer MUX11 selects the first green digital voltage signal SG0 for output, and when the frame count is odd, it selects the second green digital voltage signal SG1.

[0106] On the other hand, the present invention also provides a display device, comprising: a display panel, the display panel including the aforementioned first display area and second display area; the display pixel driving circuit as described above, for driving the display panel to display an image; and a camera assembly, the camera assembly corresponding to the second display area forming an under-screen camera.

[0107] In this embodiment, the sub-pixel equalizer in the display pixel driver circuit processes signals only for data lines matching sub-pixels in the second display region, or only for data lines matching sub-pixels within a predetermined area of ​​the second display region and a first display region adjacent to the second display region. This equalized display pixel signal is then input to corresponding sub-pixels for display, resulting in a balanced display effect. This facilitates smaller and lower-cost display driver chips, further addresses color shift issues in the second display region of existing display devices, and enhances the display quality of the display device.

[0108] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0109] It should be noted that the devices and methods disclosed in the embodiments of this document may also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the devices, methods, and computer program products according to the various embodiments of this document. In this regard, each box in the flowchart or block diagram may represent a module, program, or portion of code, wherein the module, program segment, or portion of code contains one or more executable instructions for implementing a specified logical function, and the module, program segment, or portion of code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the boxes may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

[0110] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0111] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A display pixel signal processing method, characterized in that: A sub-pixel equalizer is added to the data driving circuit to equalize the digital grayscale signals or / and digital voltage signals of at least two sub-pixels sharing the same control unit according to a preset ratio in space and / or time.

2. The display pixel signal processing method according to claim 1, wherein: The spatial equalization processing according to a preset ratio includes: in the same frame of image data, performing weighted averaging of the digital grayscale signals or / and digital voltage signals of the sub-pixels sharing the same control unit according to a preset weight ratio for equalization processing; Alternatively, the temporal equalization processing according to a preset ratio includes: presetting a certain number of frames of image data as a cycle, and directly outputting the digital grayscale signals and / or digital voltage signals of sub-pixels sharing the same control unit in a time-sharing manner according to a preset frame ratio for equalization processing.

3. The display pixel signal processing method according to claim 1 or 2, characterized in that: The preset ratio includes an equal ratio or an unequal ratio.

4. The pixel signal processing method according to claim 3, wherein: In the cycle, the frame ratio is selected with a certain number of frames between intervals or without intervals of frames.

5. The display pixel signal processing method according to claim 1, wherein: Several sub-pixels form a first display area and a second display area on the display panel, the second display area corresponds to the under-screen camera area, and the first display area corresponds to the non-under-screen camera area.

6. The display pixel signal processing method according to claim 5, wherein: The sub-pixel equalizer is enabled and controlled to output an equalized signal when the second display area is displaying, and output a non-equalized signal otherwise.

7. The display pixel signal processing method according to claim 6, wherein: The sub-pixel equalizer processes signals of data lines matched with sub-pixels only in the second display area, or processes signals of data lines matched with sub-pixels only in a preset area of ​​the second display area and a first display area adjacent to the second display area.

8. The display pixel signal processing method according to claim 1, wherein: The sub-pixel equalizer includes at least one sub-equalizer, and one sub-equalizer is used to process a display pixel signal corresponding to at least one data line.

9. The display pixel signal processing method according to claim 1, wherein: At least two sub-pixels sharing the same control unit have the same color.

10. The display pixel signal processing method according to claim 9, wherein: The same color includes any one of red, green, blue, cyan, magenta, yellow, and white.

11. The display pixel signal processing method according to claim 8, wherein: Blue sub-pixels sharing the same control unit are located in different columns, and / or red sub-pixels sharing the same control unit are located in different columns, and / or green sub-pixels sharing the same control unit are located in different columns and / or the same column.

12. The display pixel signal processing method according to claim 1, wherein: Among the at least two sub-pixels, there is one active shared sub-pixel and at least one passive shared sub-pixel, wherein the at least one active shared sub-pixel is arranged in the second display area of ​​the display panel; And / or, one or more control units are provided, and the control units are provided in the first display area and / or the second display area.

13. A display pixel driving circuit according to the method according to any one of claims 1 to 12, characterized in that: The display pixel driving circuit includes a sub-pixel equalizer.

14. The display pixel driving circuit according to claim 13, further comprising: Shift register module, gamma voltage module; The sub-pixel equalizer is integrated into the shift register module or the gamma voltage module, or the sub-pixel equalizer is independently arranged before or after the gamma voltage module.

15. The display pixel driving circuit according to claim 13, wherein: The sub-pixel equalizer includes: an adder, configured to add signals of the sub-pixels sharing a same control unit; A divider is used to divide the result of the addition by the adder into equal parts based on the number of sub-pixels sharing the same control unit.

16. The display pixel driving circuit according to claim 13, wherein: The sub-pixel equalizer includes: a multiplier, configured to assign a weight coefficient to the signal of each sub-pixel sharing the same control unit; An adder is used to add the signals of the sub-pixels that are assigned weight coefficients and share the same control unit.

17. The display pixel driving circuit according to claim 16, wherein: The sum of the weight coefficients is equal to 1.

18. The display pixel driving circuit according to any one of claims 15 to 16, wherein: The sub-pixel equalizer further includes a multiplexer for enabling control to directly output the signal of the passive shared sub-pixel or the equalized signal.

19. The display pixel driving circuit according to claim 13, wherein: The sub-pixel equalizer includes: The first multiplexer includes at least two output channels, wherein different output channels are used to control the direct output of signals of passively shared sub-pixels or actively shared sub-pixels at a certain frame ratio for equalization processing; The second multiplexer is used to enable and control the direct output of the signal of the passive shared sub-pixel, or the signal selected to be output by the first multiplexer.

20. The display pixel driving circuit according to claim 19, wherein: The first multiplexer includes two output channels, and the frame ratios of the two output channels are equal, and the frame ratios are selected at intervals of one frame.

21. A display device, characterized in that: include: A display panel, the display panel comprising a first display area and a second display area; The display pixel driving circuit according to any one of claims 13 to 20, configured to drive the display panel to display an image; A camera assembly is formed as an under-screen camera corresponding to the second display area.

Images