Memory read-write test acceleration system and method and storage medium

Abstract

The invention relates to the field of memory testing, and discloses a memory read-write test acceleration system and method and a storage medium. The system comprises a CPU and an SOC chip. The SOC chip comprises a read-write accelerator, a DDR (Double Data Rate) memory controller and a comparator; the CPU is used for continuously outputting a write instruction carrying a target address and target data when a read-write test in the SLT mode is executed; the read-write accelerator is used for sending target data to the comparator and sending a target address to the DDR memory controller when determining that the write instruction is a read instruction, so that the DDR memory controller initiates memory access to the to-be-tested memory to obtain read-back data; and the comparator is used for comparing the read-back data with the target data to obtain a comparison result. When the read-write test of the memory is executed in the SLT test mode, the CPU only issues the write instruction, and the read-write accelerator converts and issues the write instruction, so that the load of the CPU is reduced, and the test efficiency of the memory is improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to the Chinese patent application with application number 202411505580.X filed with the China Patent Office on October 28, 2024, and entitled “Memory Read and Write Test Acceleration Method and System”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of memory testing, and in particular to a memory read and write test acceleration system, method, and storage medium. Background Art

[0003] In traditional memory testing, the CPU or other test control unit first initiates a write operation, and then initiates a read operation. The CPU then determines the correctness of the data based on the read-back data. That is, the first step is for the CPU to control the write data, the second step is for the CPU to send a read address instruction, the third step is for the CPU to read the returned data, and the fourth step is for the CPU to compare whether the read data is correct to determine whether the memory is normal. Due to the processing delays of the bus, controller, and memory, it is necessary to wait for the data to be read, and the CPU has to compare it by itself. The entire process requires the participation of the CPU, resulting in a large number of additional tasks, affecting the CPU energy efficiency and delaying the test time. Therefore, there is an urgent need for a memory read and write test acceleration method and system that reduces the CPU load, improves detection efficiency, and shortens detection time. Summary of the Invention

[0004] In view of this, in order to solve the technical problems in the prior art that the processing delays of the technical bus, controller and memory require waiting time to read data, and the CPU compares it by itself, and the entire process requires the participation of the CPU, thus generating more additional tasks, affecting the CPU energy efficiency, and delaying the test time, the present application provides a memory read and write test acceleration system, method and storage medium.

[0005] In a first aspect, the present application provides a memory read / write test acceleration system, comprising a CPU and a SOC chip; the SOC chip internally integrates a read / write accelerator, a DDR memory controller, and a comparator; the CPU communicates with various components within the SOC chip via a bus interface; The CPU is configured to continuously output write instructions carrying an address sequence and target data when executing a read / write test in the SLT mode; the address sequence includes the target address; The read / write accelerator is configured to determine, during the transmission of the write instruction, whether the write instruction is a real write instruction or a read instruction; if the write instruction is determined to be a read instruction, extract the target address and the target data from the read instruction, send the target data as expected data to the comparator, and send the target address to the DDR memory controller; The DDR memory controller is used to initiate a memory access to the memory under test according to the target address to obtain the read-back data at the target address; The comparator is used to compare the read-back data with expected data to obtain a comparison result.

[0006] In an optional embodiment, the address sequence further includes an extension field, and the highest bit in the extension field serves as a flag bit; and determining whether the write instruction is a true write instruction or a read instruction includes: Decoding the flag bit in the extension field to obtain a value of the flag bit; If the value of the flag bit is the target value, determining that the write instruction is a real write instruction; If the value of the flag bit is not the target value, it is determined that the write instruction is a read instruction.

[0007] In an optional embodiment, the target value is 0.

[0008] In an optional embodiment, the read / write accelerator is further configured to extract the target address and the target data from the write instruction if it is determined that the write instruction is a true write instruction, and send the target address and the target data to the DDR memory controller; The DDR memory controller is further configured to initiate a memory access to the memory under test according to the target address, and write the target data to the target address.

[0009] In an optional embodiment, the read / write accelerator includes a flag bit decoding module, a write operation module, and a read operation module; The flag bit decoding module is used to decode the flag bit in the address sequence; The write operation module is configured to send the target address and the target data to the DDR memory controller when the write instruction is a real write instruction, so as to trigger the DDR memory controller to initiate a memory access for implementing a write operation; The read operation module is used to send the target data as expected data to the comparator when the write instruction is a read instruction, and send the target address to the DDR memory controller to trigger the DDR memory controller to initiate a memory access for implementing a read operation.

[0010] In an optional implementation manner, after determining that the write instruction is a read instruction and extracting the target address and the target data from the read instruction, the read / write accelerator is further configured to: The target data is cached in an internal storage queue, and the target data is sent to the comparator via the storage queue.

[0011] In an optional embodiment, the SOC chip further includes an interrupt processing unit; The comparator is further configured to determine that the memory to be tested is faulty if the comparison result shows that the read-back data is inconsistent with the expected data, and trigger the interrupt processing unit to send an error interrupt signal to the CPU; And / or, the CPU is configured to count the number of failures of the memory to be tested, and generate a memory status report based on the number of failures.

[0012] In an optional embodiment, the SOC chip further includes a PCIE interface; The CPU is configured to connect to the PCIE interface via a PCIE bus, and send the write instruction to the memory to be tested via the PCIE interface, the on-chip bus, the read / write accelerator, and the DDR memory controller; The CPU is used to receive the error interrupt signal through the PCIE interface.

[0013] In a second aspect, the present application provides a memory read and write test acceleration method, comprising: When executing the read and write test in the SLT mode, the CPU continuously outputs a write instruction carrying an address sequence and target data; the address sequence includes the target address; During the transmission of the write instruction, the read / write accelerator determines whether the write instruction is a real write instruction or a read instruction; if the write instruction is determined to be a read instruction, extracting target data from the read instruction, sending the target data as expected data to a comparator, and sending the read instruction to a DDR memory controller; Initiating a memory access to the memory under test according to the read instruction by the DDR memory controller to obtain the read-back data at the target address; The read-back data is compared with the expected data by the comparator to obtain a comparison result.

[0014] In a third aspect, the present application provides a computer storage medium storing a computer program, which, when executed on a processor, implements the aforementioned memory read and write test acceleration method.

[0015] The embodiments of the present application have the following beneficial effects: An embodiment of the present application provides a memory read and write acceleration system, which, in the SLT test mode, transfers one of the SLT test tasks (i.e., the read and write test task) from the CPU to other execution entities, wherein the read and write accelerator implements instruction conversion, and the comparator implements comparison and verification of data read operations, so that the CPU only needs to issue write instructions instead of read instructions, thereby eliminating the need to wait for lengthy read operation delays and continuously sending write instructions, significantly improving the memory test efficiency, thereby reducing the CPU load and shortening the memory read and write test time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solution of this application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of this application and should not be considered as limiting the scope of protection of this application. Those skilled in the art can also derive other relevant drawings based on these drawings without inventive effort.

[0017] Figure 1 A schematic diagram of the structure of a memory read and write acceleration system in an embodiment of the present application is shown; Figure 2 A logical diagram of the read / write accelerator processing a write instruction in an embodiment of the present application is shown; Figure 3 A logical diagram of the read instruction processing inside the read / write accelerator in an embodiment of the present application is shown; Figure 4 A schematic diagram showing the principle of waiting delay when a CPU sends an instruction in the prior art is shown; Figure 5 A schematic diagram showing the waiting delay principle when the CPU sends an instruction in an embodiment of the present application is shown; Figure 6 A flow chart of a memory read and write acceleration method in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0019] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0020] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0021] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0023] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0024] DDRMC: DDR memory controller (Memory Controller) is a key component in the computer storage system, mainly responsible for managing data transmission between memory and CPU.

[0025] DDRPHY: DDR physical layer interface (Physical Interface) is the physical layer interface used to control and manage DDR memory. DDRPHY is the bridge connecting DDR chips and DDRMC. It is responsible for converting data sent by DDRMC into signals that comply with the DDR protocol and sending them to the DDR chips. Conversely, it is responsible for converting data sent by DRAM into signals that comply with the standard protocol and sending them to DDRMC.

[0026] ATE (Automated Test Equipment) is completed in the test factory. It mainly applies the required stimulus signals to the chip input pipeline and monitors the chip output pins to ensure that the output signals meet expectations. It has a specific test platform.

[0027] SLT (System Level Test) is also performed in the test facility and, along with ATE, is referred to as final testing. SLT follows ATE and executes system software to test the functionality of each chip module to ensure proper operation. SLT simulates end-use scenarios and verifies the proper functioning of each chip module by running system software. This verification process does not rely on predefined test vectors but rather on actual system software execution.

[0028] It should be noted that the main body of SLT testing is the system software / processor, and the test platform or accelerator plays an auxiliary role, assisting the system software / processor to complete the test task; while in ATE testing, the system software / processor generates test stimuli and delivers them to the test platform for completion (the test platform requires a large number of storage units to cache the test stimuli). The system software / processor mainly plays the role of configuration management during the testing process, so the main body of testing is the test platform, not the system software / processor; and because the test scenarios of system software / processors are ever-changing, it is impossible to replace the highly random SLT test with regular test stimuli (i.e., ATE testing).

[0029] Obviously, there are essential differences between SLT testing and ATE testing in terms of their test environment, test execution entity, test purpose, test process and test results.

[0030] In the SLT test scenario, various test tasks, including read and write test tasks, require the full participation of the CPU, that is, the CPU serves as the executor of the SLT test tasks; however, due to delays in the bus, controller and memory, as well as the CPU's own task burden of data processing and test execution, the entire process takes a long time, affecting test efficiency.

[0031] Based on this, the present application provides a memory read and write test acceleration system based on the read and write test tasks in the SLT test tasks. The operation of the CPU is simplified through the combined action of a read and write accelerator, a comparator and other devices, and the data read test tasks required by the CPU are transferred to other execution entities. The read and write accelerator can realize the conversion and issuance of instructions, so that the CPU only needs to issue write instructions, without issuing read instructions, and thus there is no need to wait for lengthy read operation delays. Write instructions can be sent continuously, significantly improving the memory test efficiency. In short, the CPU can perform memory read and write tests at full speed without waiting for the completion of the read operation, thereby realizing the acceleration of memory testing.

[0032] For reference, the memory read / write test acceleration system provided in the embodiments of the present application includes a CPU and a SOC chip. The SOC chip integrates a read / write accelerator, a DDR memory controller (such as a DDR MC / DDR PHY), and a comparator. The CPU communicates with various components within the SOC chip via a bus interface (i.e., a PCIE bus and an intra-chip bus), and the DDR memory controller can connect to an external memory device (or memory chip) under test.

[0033] It is worth noting that there is no specific restriction on the setting method of the CPU, read-write accelerator, and DDR memory controller; for example, the CPU, read-write accelerator, and DDR memory controller are integrated in the same functional chip, and the CPU can be any CPU that can realize the above functions. In this embodiment, the CPU core of the CPU is RISC-V to improve the response effect; the CPU is communicated with the read-write accelerator through the bus in the functional chip, which is the on-chip bus of the functional chip, which can be an AXI bus. The read-write accelerator is communicated with the DDR memory controller, and a test interface is provided at the DDR memory controller end. The memory to be tested is plugged into the test interface. The memory to be tested can be any type of memory, such as DDR4, etc., and the test interface only needs to match it. The functional chip can also be a chip with a carrying function, which is a SOC chip in this embodiment to improve the integration effect.

[0034] Based on the above system structure, the CPU is used to continuously output write instructions carrying an address sequence and target data when executing read and write tests in SLT mode; the address sequence includes a target address; the read and write accelerator is used to determine whether the write instruction is a real write instruction or a read instruction during the transmission of the write instruction; wherein, if the write instruction is determined to be a read instruction, the target address and target data are extracted from the read instruction, the target data is sent to the comparator as the expected data, and the target address is sent to the DDR memory controller; the DDR memory controller is used to initiate a memory access to the memory under test according to the target address to obtain the readback data at the target address; the comparator is used to compare the readback data with the expected data to obtain a comparison result.

[0035] In one example, the read / write accelerator can be directly installed on the on-chip bus. In short, the read / write accelerator is only used for instruction conversion and transmission, similar to the function of a transmission channel, and does not involve specific testing and data processing functions.

[0036] It can be understood that this embodiment accelerates the CPU's access to the memory to be tested through a read-write accelerator. In the SLT test mode, when a memory read-write test needs to be performed, the CPU only needs to send write instructions and no longer needs to send read instructions. The read-write accelerator is responsible for converting these write instructions into corresponding read-write operations. In this way, the CPU does not need to wait for lengthy data readback delays and can send write instructions continuously and quickly, greatly improving operational efficiency.

[0037] In some examples, the SOC chip further includes an embedded processor and a PCIE interface; wherein, Figure 1 As shown, the CPU is connected to the PCIE interface through the PCIE interface bus; the embedded processor is connected to the read / write accelerator, DDR memory controller, PCIE interface and peripheral interface through an on-chip bus (such as AXI).

[0038] In some examples, the SOC chip further includes an interrupt processing unit; the interrupt processing unit is configured to generate an error interrupt signal to execute corresponding interrupt processing logic.

[0039] In one embodiment, the CPU sends a write instruction to the memory under test via the PCIE interface, the on-chip bus, the read / write accelerator, and the DDR memory controller; the CPU is also configured to receive an error interrupt signal via the PCIE interface.

[0040] In short, the CPU communicates with other devices in the system through the bus interface (PCIE bus and intra-chip bus), and then collaboratively completes the read and write tests and signal transmission in the SLT mode of the memory under test.

[0041] Furthermore, when executing the read and write test in the SLT mode, the CPU is used to send a write instruction through the bus interface, and the write instruction carries an address sequence and target data; the address sequence includes a real target address and an extension field, and the highest bit in the extension field serves as a mark bit, and the extension field is used to indicate that the write instruction is a real write instruction or a read instruction.

[0042] After receiving the write instruction, the read / write accelerator performs instruction conversion on the write instruction; wherein, the read / write accelerator decodes the flag bit in the extension field of the write instruction to obtain the value of the flag bit; and determines whether to convert the write instruction according to the value of the flag bit.

[0043] If the value of the mark bit is the target value, the write instruction is determined to be a real write instruction, and the write instruction does not need to be converted; otherwise, if the value of the mark bit is not the target value, the write instruction is determined to be a read instruction, and the write instruction needs to be converted.

[0044] In an optional embodiment, the target value is 0.

[0045] Exemplarily, the highest bit of the extended field of the write instruction reserves a flag bit (one bit), and the value of the flag bit is used to indicate whether the write instruction is a true write instruction or a read instruction. The value of the flag bit can be set accordingly based on actual needs, and the relationship between the value of the flag bit and the true write instruction or read instruction it indicates can also be set based on actual needs, which is not limited in this embodiment. For example, when the value of the flag bit is set to 0, it indicates that the write instruction is a true write instruction, and when the value of the flag bit is 1, it indicates that the write instruction is a read instruction.

[0046] That is, after receiving the write instruction, the read / write accelerator determines the authenticity of the write instruction, that is, determines whether the write instruction is a true write instruction or a read instruction. Figure 2 As shown, after receiving the write instruction, the read / write accelerator decodes the flag bit in the write instruction, identifies the value of the flag bit, and determines whether the write instruction is a real write instruction or a read instruction based on the value of the flag bit.

[0047] Furthermore, based on the value of the flag bit, the read / write accelerator extracts the target address and target data from the write instruction if it is a genuine write instruction. The target address and target data are then sent to the DDR memory controller. The DDR memory controller then initiates a memory access to the memory under test based on the target address and writes the target data to the target address, completing the data write operation.

[0048] If the write instruction is determined to be a read instruction, the target address and target data are extracted from the read instruction. The target address is sent to the DDR memory controller, and the target data is used as the expected data and sent to the comparator. The DDR memory controller initiates a memory access to the memory under test based on the target address and reads the readback data from the target address to complete the data read operation. The comparator then compares the readback data with the expected data to verify the accuracy of the data read operation.

[0049] For reference, the read-write accelerator can implement the above logic processing through the corresponding functional modules integrated internally. That is, the read-write accelerator includes a flag bit decoding module, a write operation module and a read operation module; Figure 2 and Figure 3 As shown, the flag bit decoding module is used to decode the flag bit in the address sequence; the write operation module is used to send the target address and target data to the DDR memory controller when the write instruction is a true write instruction, so as to trigger the DDR memory controller to initiate a memory access for implementing the write operation; the read operation module is used to send the target data as expected data to the comparator and send the target address to the DDR memory controller when the write instruction is a read instruction, so as to trigger the DDR memory controller to initiate a memory access for implementing the read operation.

[0050] Specifically, if Figure 2 As shown, after the read / write accelerator determines that the write instruction is a real write instruction based on the value of the flag bit, it extracts the target address and target data from the write instruction, and sends the target address and target data to the DDR memory controller through the internal write operation module, so that the DDR memory controller initiates a memory access to the memory to be tested to write the target data to the target address of the memory to be tested.

[0051] For example, an acceleration program integrated in the accelerator extracts the target address from the address sequence, and transmits the write instruction to the DDR memory controller, so that the DDR memory controller converts the write instruction into a data write instruction that is compatible with the memory to be tested, so as to write the data into the storage unit corresponding to the target address in the memory to be tested.

[0052] like Figure 3 As shown, after the read / write accelerator decodes the flag bit of the write instruction, it determines that the write instruction is a read instruction based on the value of the flag bit, and then extracts the target address and target data from the read instruction, wherein the target data is the expected data corresponding to the read instruction; then, the target address is sent to the DDR memory controller through the internal read operation module, so that the DDR memory controller initiates a memory access to the memory under test to read the corresponding readback data from the target address of the memory under test, and then the DDR memory controller sends the readback data to the comparator inside the SOC chip.

[0053] In one example, after determining that a write instruction is actually a read instruction, the read / write accelerator can cache the target data in the read instruction as expected data in a preset storage queue. The storage queue then sends the expected data to the comparator, which then compares the expected data with the readback data. In other words, the read / write accelerator can have a temporary storage function to assist with data storage.

[0054] For example, an acceleration program integrated in the accelerator extracts a target address from an address sequence, temporarily stores the desired data in a storage array in the accelerator, and transmits a read instruction to a preset controller, so that the controller converts the read instruction into a data read instruction that is compatible with the memory to be tested; based on the data read instruction, the storage data stored in the storage unit corresponding to the target address in the memory to be tested is read.

[0055] In another example, the read / write accelerator directly sends the expected data to the comparator, so that the comparator compares the readback data with the expected data.

[0056] It is understandable that the read-write memory may have a temporary storage function, and the expected data may be temporarily stored in the read-write accelerator or directly sent to the comparator via the read-write accelerator, which is not limited in this embodiment.

[0057] Furthermore, after receiving the readback data and the expected data, the comparator compares the readback data with the expected data to determine whether the readback data is consistent with the expected data, and obtains a comparison result.

[0058] Furthermore, if the read-back data is consistent with the expected data, it means that the data read test has passed; otherwise, if the read-back data is inconsistent with the expected data, it means that the data read test has failed.

[0059] In some examples, the comparator is further configured to determine that the memory under test is faulty if the comparison result shows that the readback data is inconsistent with the expected data, and trigger the interrupt processing unit to send an error interrupt signal to the CPU.

[0060] That is, the comparator can upload the comparison results to the interrupt processing unit inside the SOC chip, and the interrupt processing unit determines whether to trigger the corresponding process based on the comparison results. If the comparison result is that the data read test fails, the interrupt processing unit generates an error interrupt signal and sends the error interrupt signal to the CPU to notify the CPU that there is an abnormality in the current data read operation. In addition, the comparator can also send the comparison results directly to the CPU after each comparison is completed. This embodiment does not limit this process.

[0061] As an optional implementation, the CPU may also be configured to count the number of faults of the memory to be tested according to the comparison result sent by the comparator or the error interrupt signal received, and generate a memory status report based on the number of faults.

[0062] In this embodiment, when performing a read or write test on a memory in SLT test mode, the processor only issues write instructions. The read / write accelerator converts and issues these write instructions, allowing the DDR memory controller to receive the corresponding instructions and perform the corresponding memory access operation on the memory under test, thereby implementing a data read or data write operation. After the DDR memory controller performs the data read operation, it transmits the readback data to the comparator, which compares the readback data with the target data to obtain a comparison result.

[0063] It can be understood that in this embodiment, the execution body of verifying the data read operation result is transferred from the CPU to the comparator, which simplifies the CPU processing, and the CPU only needs to send write instructions, no read instructions, and the read-write accelerator completes the conversion and issuance of instructions. The CPU does not need to wait for the lengthy delay path of reading back data (transmission delay of the bus interface, processing delay of the memory chip), and can perform operations quickly, thereby accelerating the CPU's access efficiency.

[0064] It should be noted that the waiting delay before read and write acceleration (i.e., the waiting delay under the existing technology) is as follows Figure 4 As shown, the write instruction 2 must wait for the read instruction 1 to return data before the next instruction can be initiated. The total delay is t=t1+t2+t3+t4+tc ,in t1 It is the transmission delay from the CPU's read instruction to the DDR memory controller after being transmitted through the bus. t2 It is the transmission delay from the DDR memory controller to the memory chip. t3 It is the transmission delay of the return data to the DDR memory controller after being processed by the memory chip; t4 After being processed by the DDR memory controller, the return data reaches the CPU data bus and includes the transmission delay of the data bus; tc It is the processing delay between instructions, which is basically a fixed delay.

[0065] In this embodiment, the waiting delay after reading and writing acceleration is as follows: Figure 5 As shown, write instruction 3 does not need to wait for the readback data of write instruction 2 (real read operation), the total delay t=tc The actual read operation is completed by the read-write accelerator, and the CPU does not need to intervene and can continuously send write instructions. Figure 5 It can be seen that the instructions can basically be processed at a uniform speed.

[0066] During the read and write test in SLT mode, the CPU only needs to continuously send instructions and data. There is no need for the CPU to participate in the actual comparison and detection work, that is, there is no need to compare data, and there is no need to wait for sending data. This not only improves the memory test speed, but also reduces the CPU load, significantly improves the detection efficiency, saves CPU resources, and reduces the cost of the test system.

[0067] Please refer to Figure 6 , an embodiment of the present application also provides a memory read and write test acceleration method, the method comprising the following steps: S610, when executing the read / write test in the SLT mode, the CPU continuously outputs write instructions carrying an address sequence and target data; the address sequence includes the target address.

[0068] S620, during the transmission of the write instruction, determining, through the read / write accelerator, whether the write instruction is a real write instruction or a read instruction; wherein, if the write instruction is determined to be a read instruction, extracting target data from the read instruction, sending the target data as expected data to the comparator, and sending the read instruction to the DDR memory controller.

[0069] S630: Initiate a memory access to the memory under test according to the read instruction through the DDR memory controller to obtain read-back data at the target address.

[0070] S640 , comparing the read-back data with the expected data through a comparator to obtain a comparison result.

[0071] It can be understood that the method in this embodiment can be applied to the above-mentioned memory read and write test acceleration system. The various steps in this embodiment are the functions of each device in the above-mentioned system. Therefore, any optional items in the above-mentioned embodiment can be applied to this embodiment, so they will not be elaborated here.

[0072] The present application also provides a SOC chip. Exemplarily, the SOC chip includes a read-write accelerator, a DDR memory controller and a comparator, wherein a storage unit in the SOC chip stores a computer program and executes the above-mentioned memory test acceleration method after receiving a write instruction sent by the CPU by running the computer program.

[0073] The CPU can be an integrated circuit chip with signal processing capabilities. The CPU includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0074] The storage unit may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The storage unit is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0075] The present application also provides a computer storage medium for storing the computer program used in the above-mentioned computer device. The computer storage medium may be a readable storage medium, a non-volatile storage medium, or a volatile storage medium. For example, the computer storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0076] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0077] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0078] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0079] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A memory read and write test acceleration system, characterized in that: It includes a CPU and a SOC chip; the SOC chip integrates a read / write accelerator, a DDR memory controller and a comparator; the CPU communicates with various components inside the SOC chip via a bus interface; The CPU is used to continuously output write instructions carrying an address sequence and target data when executing a read and write test in the SLT mode; The address sequence includes a target address; The read / write accelerator is configured to determine, during the transmission of the write instruction, whether the write instruction is a real write instruction or a read instruction; if the write instruction is determined to be a read instruction, extract the target address and the target data from the read instruction, send the target data as expected data to the comparator, and send the target address to the DDR memory controller; The DDR memory controller is used to initiate a memory access to the memory under test according to the target address to obtain the read-back data at the target address; The comparator is used to compare the read-back data with expected data to obtain a comparison result.

2. The memory read / write test acceleration system according to claim 1, wherein: The address sequence further includes an extension field, wherein the highest bit in the extension field serves as a mark bit; The determining whether the write instruction is a real write instruction or a read instruction includes: Decoding the flag bit in the extension field to obtain a value of the flag bit; If the value of the flag bit is the target value, determining that the write instruction is a real write instruction; If the value of the flag bit is not the target value, it is determined that the write instruction is a read instruction.

3. The memory read / write test acceleration system according to claim 2, wherein: The target value is 0.

4. The memory read / write test acceleration system according to any one of claims 1 to 3, characterized in that: The read / write accelerator is further configured to extract the target address and the target data from the write instruction if it is determined that the write instruction is a true write instruction, and send the target address and the target data to the DDR memory controller; The DDR memory controller is further configured to initiate a memory access to the memory under test according to the target address, and write the target data to the target address.

5. The memory read / write test acceleration system according to any one of claims 1 to 3, characterized in that: The read-write accelerator includes a flag bit decoding module, a write operation module and a read operation module; The flag bit decoding module is used to decode the flag bit in the address sequence; The write operation module is configured to send the target address and the target data to the DDR memory controller when the write instruction is a real write instruction, so as to trigger the DDR memory controller to initiate a memory access for implementing a write operation; The read operation module is used to send the target data as expected data to the comparator when the write instruction is a read instruction, and send the target address to the DDR memory controller to trigger the DDR memory controller to initiate a memory access for implementing a read operation.

6. The memory read / write test acceleration system according to claim 1, characterized in that: After determining that the write instruction is a read instruction and extracting the target address and the target data from the read instruction, the read-write accelerator is further configured to: The target data is cached in an internal storage queue, and the target data is sent to the comparator via the storage queue.

7. The memory read / write test acceleration system according to claim 1, wherein: The SOC chip also includes an interrupt processing unit; The comparator is further configured to determine that the memory to be tested is faulty if the comparison result shows that the read-back data is inconsistent with the expected data, and trigger the interrupt processing unit to send an error interrupt signal to the CPU; And / or, the CPU is configured to count the number of failures of the memory to be tested, and generate a memory status report based on the number of failures.

8. The memory read / write test acceleration system according to claim 7, characterized in that: The SOC chip also includes a PCIE interface; The CPU is configured to connect to the PCIE interface via a PCIE bus, and send the write instruction to the memory to be tested via the PCIE interface, the on-chip bus, the read / write accelerator, and the DDR memory controller; The CPU is used to receive the error interrupt signal through the PCIE interface.

9. A memory read and write test acceleration method, characterized in that: include: When executing the read and write test in SLT mode, the CPU continuously outputs write instructions carrying the address sequence and target data; The address sequence includes a target address; During the transmission of the write instruction, the read / write accelerator determines whether the write instruction is a real write instruction or a read instruction; if the write instruction is determined to be a read instruction, extracting target data from the read instruction, sending the target data as expected data to a comparator, and sending the read instruction to a DDR memory controller; Initiating a memory access to the memory under test according to the read instruction by the DDR memory controller to obtain the read-back data at the target address; The read-back data is compared with the expected data by the comparator to obtain a comparison result.

10. A computer storage medium, characterized in that It stores a computer program, which, when executed on a processor, implements the memory read and write test acceleration method according to claim 9.

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