Read-only device supporting multi-channel M.2 interface

Abstract

The invention discloses a read-only device supporting multi-channel M.2 interfaces. The read-only device adopts a main control module and integrates PCIe and SATA protocol analysis engines, and the main control module identifies protocols followed by M.2 devices connected with all the interfaces and carries out protocol processing logic switching; the main control module is further provided with a plurality of arbitration logic units used for adjusting resource distribution among the interfaces. The interface module at least comprises multiple paths of M.2 interfaces, and each path of M.2 interface is independently provided with a PCIe channel and an SATA channel to be connected with the main control module; and the security interception module is used for synchronizing protocol information followed by the M.2 equipment connected with each interface and write protection state information of each interface from the main control module, and judging and executing whether write protection is carried out on the interface or not. According to the method and the device, the problem that the existing evidence obtaining equipment lacks M.2 native support and is coordinated with the requirement of high-concurrency secure data transmission of a plurality of transmission channels is solved.

Description

Technical Field

[0001] The present application relates to the field of reading and writing of electronic devices, and in particular to a read-only device supporting an M.2 interface. Background Art

[0002] With the increasing popularity of M.2 solid-state drives (SSDs), their application in scenarios such as electronic forensics, data security, and high-speed storage has surged. In these scenarios, read-only lock technology is required. This technology is a concurrency control mechanism that allows multiple threads to read shared resources simultaneously, but prohibits write operations. An exclusive lock cannot be acquired until all read locks are released. Specifically, a read-only lock typically has two states: read lock state and write lock state. In the read lock state, multiple threads can simultaneously acquire the read lock and share access to the resource. In the write lock state, only one thread is allowed to hold the write lock, and all read and write requests are blocked.

[0003] However, existing read-only lock technology has significant limitations and cannot meet the needs of multi-channel, high-concurrency data protection. The specific technical bottlenecks are as follows:

[0004] 1. Insufficient interface adaptability and reliance on transfer solutions

[0005] Current mainstream read-only locks are primarily designed for traditional interfaces like USB and SATA, lacking native support for the M.2 interface. Users who require read-only access to an M.2 drive must use a USB adapter card or PCIe adapter, which not only increases hardware complexity but can also lead to signal attenuation and reduced transfer rates.

[0006] 2. Insufficient hardware and protocol compatibility

[0007] The M.2 interface relies on PCIe or SATA protocols for data transmission. Existing adapters (such as USB to M.2) can cause compatibility issues due to protocol conversion, such as inability to recognize NVMe hard drives or limited transfer rates. Furthermore, resource conflicts are prone to occur when multiple channels are used concurrently, and there is a lack of effective bus arbitration mechanisms.

[0008] 3. Limited scalability of application scenarios

[0009] Existing devices mostly focus on a single interface or a small number of storage media types, and are unable to adapt to the diverse forms of M.2 hard drives (such as different sizes, protocol versions) and the needs of multi-device collaboration. Summary of the Invention

[0010] An embodiment of the present application provides a read-only device that supports a multi-channel M.2 interface, which is used to solve the problem that existing electronic forensics equipment lacks native support for the M.2 interface and is insufficiently adaptable to multi-channel, high-concurrency data protection requirements.

[0011] An embodiment of the present application provides a read-only device supporting a multi-channel M.2 interface, including:

[0012] A main control module, integrating PCIe and SATA protocol parsing engines, for invoking the PCIe and SATA protocol parsing engines to identify the protocols followed by the M.2 devices connected to each interface and switch the protocol processing logic; the main control module is also configured with a multi-channel arbitration logic unit for adjusting resource allocation between the various interfaces;

[0013] The interface module includes at least multiple M.2 interfaces, each of which is independently configured with a PCIe channel and a SATA channel to connect to the main control module. When the main control module identifies that the protocol followed by the M.2 device connected to the interface is the NVMe protocol, the interface module performs data transmission through the PCIe channel, and when the main control module identifies that the protocol followed is the SATA protocol, the interface module performs data transmission through the SATA channel;

[0014] The security interception module is connected to the main control module to synchronize the protocol information followed by the M.2 devices connected to each interface and the write protection status information of each interface from the main control module, and judge and execute whether to implement write protection for the interface based on the protocol information and write protection status information.

[0015] Furthermore, in the present invention, the main control module adopts the RK3568 chip, and each of the M.2 interfaces is independently connected to the RK3568 chip, wherein:

[0016] The M.2 interface that complies with the NVMe protocol is connected to the RK3568 chip as follows:

[0017] The clock signal pin of the M.2 interface is connected to the high-speed clock output pin corresponding to the RK3568 chip;

[0018] The M.2 interface's transmit data differential signal pair TX_P and TX_N are connected to the RK3568 chip's high-speed data receiving pins, and the M.2 interface's receive data differential signal pair RX_P and RX_N are correspondingly connected to the chip's high-speed data transmitting pins;

[0019] The M.2 interface that complies with the SATA protocol is connected to the RK3568 chip as follows:

[0020] The SATA data pins of the M.2 interface are respectively connected to the corresponding pins of the SATA controller inside the RK3568 chip.

[0021] Furthermore, the present invention further includes a USB 3.0 controller, and the interface module further includes a USB 3.0 interface, wherein the high-speed data transmission pin of the USB 3.0 interface is connected to the high-speed data pin of the USB 3.0 controller.

[0022] Furthermore, in the present invention, the step of determining and executing whether to implement write protection on the interface based on the protocol information and the write protection status information includes:

[0023] Configuring a PCIe TLP packet filter to intercept all TLP headers containing the MWr opcode to write-protect the M.2 interface;

[0024] Disconnect the write enable signal of the USB 3.0 device to write-protect the USB 3.0 interface.

[0025] Furthermore, in the present invention, the multi-way arbitration logic unit is used to adjust resource allocation between various interfaces, including:

[0026] Allocate initial bandwidth to the corresponding interface according to the protocol of each interface;

[0027] During data transmission, the CRC error rate of each channel is collected in real time. For M.2 channels with the same protocol:

[0028] When the CRC error rate of a certain M.2 channel exceeds the threshold, its link rate is gradually reduced until the error is eliminated;

[0029] Acquire in real time the sum of the reduced link rates of the M.2 channels whose link rates are reduced each time, and distribute the sum of the reduced link rates to the M.2 channels whose CRC error rates do not exceed the threshold in descending order based on the real-time CRC error rates of the M.2 channels whose current CRC error rates do not exceed the threshold;

[0030] When the CRC error rate of a certain M.2 channel changes from exceeding the threshold to being below the threshold for a continuous preset time, the link rate of the M.2 channel is restored to the average link rate of all M.2 channels currently transmitting whose CRC error rates do not exceed the threshold. Accordingly, the link rates of the M.2 channels that are higher than the average link rate are synchronously reduced, and the speed reduction proportion of each M.2 channel gradually decreases in descending order based on the link rate before the speed reduction.

[0031] Furthermore, in the present invention, when the CRC error rate of a certain M.2 channel exceeds a threshold, its link rate is gradually reduced until the error is eliminated;

[0032] Real-time monitoring of flash memory temperature sensor data of each M.2 interface;

[0033] When the temperature reaches a first threshold range, clock spread spectrum is performed on the corresponding M.2 interface;

[0034] When the temperature reaches a second threshold range, constraining the link rate of the corresponding M.2 interface to less than 50% of the nominal value until the temperature falls below the second threshold range, and then releasing the constraint on the link rate of the corresponding M.2 interface;

[0035] The temperature value in the first threshold range is smaller than that in the second threshold range.

[0036] Furthermore, in the present invention, the multi-way arbitration logic unit is used to adjust resource allocation between the interfaces and further includes:

[0037] When a forensic command signature is detected, all non-forensic channels are stopped from transmitting and the current link state is frozen;

[0038] Increase the TLP packet priority of the forensic channel to the highest level;

[0039] After the evidence collection is completed, the bandwidth of the evidence collection channel is allocated to the non-evidence collection channel, so that the bandwidth ratio of the non-evidence collection channel is restored to the level before it was frozen.

[0040] Furthermore, in the present invention, the method further includes: the multi-way arbitration logic unit is used to adjust resource allocation between the interfaces, and further includes:

[0041] When the USB device transmission times out, bandwidth is gradually and dynamically added to the USB 3.0 interface from the emergency bandwidth pool, where the emergency bandwidth pool is an exclusive bandwidth pre-configured specifically for the USB 3.0 interface.

[0042] Furthermore, in the present invention, the baseline bandwidth of the NVMe device is 1.8-2.5 times the baseline bandwidth of the SATA device.

[0043] Furthermore, in the present invention, there are at least four M.2 interfaces.

[0044] In an embodiment of the present application, a read-only device supporting a multi-channel M.2 interface is provided. The device adopts a main control module and integrates PCIe and SATA protocol parsing engines. The main control module is used to call the PCIe and SATA protocol parsing engines to identify the protocols followed by the M.2 devices connected to each interface and switch the protocol processing logic. The main control module is also configured with a multi-channel arbitration logic unit for adjusting resource allocation between the interfaces. The interface module includes at least multiple M.2 interfaces, each of which is independently configured with a PCIe channel and a SATA channel to connect to the main control module. When the main control module identifies that the protocol followed by the M.2 device connected to the interface is the NVMe protocol, the interface module transmits data through the PCIe channel, and when the main control module identifies that the protocol followed is the SATA protocol, the interface module transmits data through the SATA channel. The security interception module is connected to the main control module to synchronize the protocol information followed by the M.2 devices connected to each interface and the write protection status information of each interface from the main control module, and judges and executes whether to implement write protection on the interface based on the protocol information and the write protection status information. This application solves the problem that existing forensic equipment lacks native support for M.2 and the need for high-concurrency and secure data transmission across multiple transmission channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of this application. The exemplary embodiments and descriptions of this application are intended to explain this application and do not constitute an improper limitation on this application. In the accompanying drawings:

[0046] Figure 1 This is a schematic diagram of the composition of a read-only device supporting a multi-channel M.2 interface according to an embodiment of the present application.

[0047] Figure 2 is a schematic diagram of a method for adjusting resource allocation between interfaces by a multi-way arbitration logic unit according to an embodiment of the present application;

[0048] Figure 3 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0050] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0051] The embodiment of the present invention provides a read-only device that supports a multi-channel M.2 interface. The device can directly and natively support M.2 interface devices and coordinate multi-channel data transmission, such as Figure 1 As shown, the read-only device supporting a multi-channel M.2 interface includes:

[0052] The main control module integrates PCIe and SATA protocol parsing engines. The main control module is used to call the PCIe and SATA protocol parsing engines to identify the protocols followed by the M.2 devices connected to each interface and switch the protocol processing logic. The main control module is also configured with a multi-way arbitration logic unit for adjusting resource allocation between each interface.

[0053] The interface module includes at least multiple M.2 interfaces, each of which is independently configured with a PCIe channel and a SATA channel to connect to the main control module. When the main control module identifies that the protocol followed by the M.2 device connected to the interface is the NVMe protocol, the interface module transmits data through the PCIe channel, and when the main control module identifies that the protocol followed is the SATA protocol, the interface module transmits data through the SATA channel.

[0054] The security interception module is connected to the main control module to synchronize the protocol information followed by the M.2 devices connected to each interface and the write protection status information of each interface from the main control module, and judge and execute whether to implement write protection for the interface based on the protocol information and write protection status information.

[0055] This embodiment of a read-only device supporting a multi-channel M.2 interface natively supports M.2 devices by configuring PCIe and SATA channels to support different protocols for M.2 devices, eliminating the need for external converters. This reduces signal latency, with a measured 60% reduction. A multi-channel arbitration logic unit coordinates resource allocation across multiple channels, maintaining efficient multi-channel transmission coordination. A security interception module implements necessary write protection on the interface to prevent data tampering during forensics.

[0056] These devices support the intermixing of multiple NVMe / SATA M.2 devices. For example, using a four-way M.2 interface, they employ a two-way Samsung 980Pro NVMe + two-way Samsung 860EVO SATA M.2. The NVMe / SATA protocol type is identified by sending PCIe ConfigurationRead TLP packets, achieving a 100% recognition success rate. The native interface design reduces power consumption, with four concurrent connections consuming only 40W. This improves energy efficiency by 108% compared to traditional solutions requiring four adapters and an external lock. The four-way concurrent read speed reaches 55GB / min, a four-fold increase in efficiency compared to traditional solutions. In the field of electronic forensics, this reduces the time required for single, multi-device acquisition by 75% and reduces labor costs by 40%.

[0057] In some preferred embodiments, the main control module uses the RK3568 chip, and each of the M.2 interfaces is independently connected to the RK3568 chip, wherein:

[0058] The M.2 interface that complies with the NVMe protocol is connected to the RK3568 chip as follows:

[0059] The clock signal pin of the M.2 interface is connected to the high-speed clock output pin corresponding to the RK3568 chip;

[0060] The M.2 interface's transmit data differential signal pair TX_P and TX_N are connected to the RK3568 chip's high-speed data receiving pins, and the M.2 interface's receive data differential signal pair RX_P and RX_N are correspondingly connected to the chip's high-speed data transmitting pins;

[0061] The M.2 interface that complies with the SATA protocol is connected to the RK3568 chip as follows:

[0062] The SATA data pins of the M.2 interface are respectively connected to the corresponding pins of the SATA controller inside the RK3568 chip.

[0063] Because the SATA protocol has high requirements for signal integrity, when wiring, ensure that these data transmission lines are of equal length and as short as possible to reduce signal transmission delay and loss. Similarly, the power pin is connected to a stable power supply, and a suitable filtering circuit is set at the power input, such as a π-type filter circuit consisting of a ferrite bead and a capacitor in series, to further reduce the impact of power ripple on the device. In addition, by setting the specific GPIO pin level of the RK3568 chip, such as setting GPIO_X to a high level to indicate that the current M.2 interface is operating in SATA protocol mode, the chip's internal storage controller will switch to the corresponding protocol processing logic based on this level status. The four M.2 interfaces are connected to the corresponding pins of the RK3568 chip in the above manner. The clock, data, and control signals of each interface are independent of each other, ensuring that each M.2 device can operate in parallel.

[0064] In some preferred embodiments, a USB 3.0 controller is further included, and the interface module further includes a USB 3.0 interface, wherein a high-speed data transmission pin of the USB 3.0 interface is connected to a high-speed data pin of the USB 3.0 controller.

[0065] Due to the higher data transfer rates of USB 3.0, signal integrity requirements are extremely stringent. These high-speed data lines must be routed using differential pairs, with line widths and spacing designed strictly in accordance with USB 3.0 standards, typically with a line width of 5 mils and a line spacing of 4 mils. Furthermore, to reduce signal interference, high-speed data lines must maintain a certain distance from other low-frequency signal lines, for example, a minimum spacing of 10 mils. Common-mode inductors should be placed near the USB interface to suppress common-mode interference on the high-speed data lines and ensure accurate data transmission.

[0066] In this embodiment, in addition to the read-only M.2 interface, the device is also equipped with a USB3.0 read-only interface, which is compatible with traditional USB devices such as USB flash drives and mobile hard drives, providing more compatibility while ensuring data security.

[0067] In certain preferred embodiments, after the main control module obtains the protocol of the device connected to each interface and shares it with the secure connection module, the security interception module determines the type of each interface based on the protocol information and write protection status information, configures different write protection schemes for different protocol types, and write-protects interfaces that have not yet been write-protected, wherein:

[0068] For the M.2 interface, a PCIe TLP packet filter is configured to intercept all TLP headers containing the MWr opcode to write-protect the M.2 interface.

[0069] For the USB interface, the write enable signal of the USB 3.0 device is disconnected to write-protect the USB 3.0 interface.

[0070] In certain preferred embodiments, since multiple transmission channels are involved in the implementation of this application, and each transmission channel is independent of each other, in order to coordinate the channels to ensure transmission efficiency, this application uses the multi-channel arbitration logic unit to adjust the resource allocation between the various interfaces, and to control the initial configuration of transmission, dynamic adjustment of the transmission process, etc., to ensure efficient transmission coordination. Specifically, in this embodiment, a method for resource allocation between various interfaces is provided, including:

[0071] Step S101: Allocate initial bandwidth to the corresponding interface according to the protocol of each interface. In some preferred embodiments, the base bandwidth of the NVMe device is 1.8-2.5 times the base bandwidth of the SATA device.

[0072] Step S102: During data transmission, the CRC error rate of each channel is collected in real time. For M.2 channels of the same protocol, when the CRC error rate of a certain M.2 channel exceeds a threshold, its link rate is gradually reduced until the error is eliminated.

[0073] Step S103: Acquire in real time the sum of the reduced link rates of the M.2 channels whose link rates are reduced each time, and distribute the sum of the reduced link rates to the M.2 channels whose CRC error rates do not exceed the threshold in descending order according to the real-time CRC error rates of the M.2 channels whose current CRC error rates do not exceed the threshold.

[0074] Step S104: When the CRC error rate of a certain M.2 channel changes from exceeding a threshold to being below the threshold for a continuous preset time, the link rate of the M.2 channel is restored to the average link rate of all M.2 channels currently transmitting whose CRC error rates do not exceed the threshold. Accordingly, the link rates of the M.2 channels that are higher than the average link rate are synchronously reduced, and the reduction ratio of each M.2 channel is gradually reduced in descending order based on the link rate before the reduction.

[0075] CRC can detect single-bit errors, double-bit errors, odd-numbered errors, and errors with a burst length less than or equal to the generator polynomial. Therefore, CRC can detect errors that may occur during data transmission or storage, ensuring data integrity and correctness. Before receiving data, the receiver must perform error detection. The receiver will only accept the data if the error detection result is correct. Common CRC detection methods include parity check, Internet checksum, and cyclic redundancy check. These are not specifically limited in this embodiment.

[0076] In this embodiment, in step S102, when the CRC error rate exceeds the threshold, it means that the transmission error rate of the channel is high, therefore, the transmission efficiency is low, and the data integrity and correctness cannot be controlled to meet the standards. In addition, because the data packets need to be repeatedly transmitted, the transmission rate will be affected, so it is necessary to immediately investigate the cause. At this time, by gradually reducing the link rate until the error is eliminated, that is, first reducing a portion of the rate, and then paying attention to whether the CRC error rate can return to normal. If it can, the link rate will not be reduced again. If the CRC error rate cannot be restored, the rate will be further reduced a second time. This cycle repeats. As the link rate decreases, the transmission pressure of the channel is relieved. If necessary, a joint investigation and elimination of the cause of the fault can be carried out, so that the CRC error rate is maintained at a certain transmission rate without exceeding the threshold, and the link rate will not be reduced. The first and second times can be divided by time intervals or data transmission volume, for example, every 1 second, 2 seconds, or 3 seconds, or every 200MB, 300MB, 500MB, or 1GB successfully transmitted. The specific setting can be made by those skilled in the art as needed. The link rate reduced each time may be reduced at a uniform rate or in equal proportion. Each channel may adopt the same or different link reduction strategies each time, which may be configured by those skilled in the art as needed.

[0077] In certain optional embodiments, when the CRC error rate is detected to exceed a threshold for the first time, the link rate of the channel is reduced by 100 Mbps. Thereafter, the CRC error rate of the channel is detected every 2 seconds. If the CRC error rates detected twice exceed the threshold, and the CRC error rate detected twice exceeds the threshold, and the CRC error rate detected once is M% of the CRC error rate detected previously, if M is greater than or equal to 100, the link rate of the channel is reduced to 1 / M% of the previous CRC error rate. If M is less than 100, the link rate is reduced at a constant rate, that is, by 100 Mbps each time. This solution allows for rapid speed limiting of channels with no improvement in CRC error rates.

[0078] In step S103, taking the M.2 interface with 4 channels and all complying with the NVMe protocol as an example, when it is detected that the CRC error rate of the first and second channels exceeds the threshold, and the CRC error rate of the third and fourth channels does not exceed the threshold and the CRC error rate of the third channel is lower than the CRC error rate of the fourth channel, the link rate of the first channel and the second channel is reduced, and the total link rate D of the two channels that is reduced this time is 200Mbps, and more than half of the 200Mbps is allocated to the third channel, and the rest is allocated to the fourth channel. Specifically, when the ratio of the CRC error rate of the third channel to the error rate of the fourth channel is A:B, the link rate A / (A+B) in D is allocated to the third channel, and the remaining link rate is allocated to the fourth channel. In this way, channels with high transmission efficiency can be given priority support so that they can complete the transmission task efficiently.

[0079] In step S104, when the CRC error rate of a certain M.2 channel changes from exceeding the threshold to being lower than the threshold for a continuous preset time, it is considered that the channel has resumed normal transmission. During this period, if the continuous CRC error rate does not exceed the threshold each time, the link rate of the channel will no longer be reduced each time. After that, when the CRC error rate meets the requirement of being lower than the threshold for a continuous preset time, the channel will be accelerated. When accelerating, the link rate of other similar channels in real time will be referred to. Taking the aforementioned 4-channel NVMe protocol M.2 interface as an example, when the first channel meets the speed-up condition, at this time, the first, third, and fourth channels are all channels whose CRC error rates do not exceed the threshold. Therefore, the link rate of the first channel after speeding up is taken as the average of the current link rates of these three channels, and the channels in the third and fourth channels that are higher than the average of the current link rates are taken for corresponding speed reduction. The speed reduction ratio of each M.2 channel is gradually reduced in order from high to low according to the link rate before the speed reduction. For example, if the current average link rate is N, and the link rates of the third and fourth channels before speed reduction are E and F respectively, where E is greater than F and both are greater than N, then the speed reduction ratio of the third channel is greater than that of the fourth channel, so that the higher-speed channel resources are allocated more to the channel to be speeded up, and the speed changes of the channel to be speeded up before and after are controllable. On the one hand, it is convenient to further monitor whether its transmission process is normal, and on the other hand, it is necessary to balance the transmission of all channels.

[0080] In some preferred embodiments, since temperature may affect transmission performance, when the CRC error rate of a certain M.2 channel exceeds a threshold, the link rate is gradually reduced until the error is eliminated in step S102, further comprising:

[0081] S1021, real-time monitoring of flash memory temperature sensor data of each M.2 interface;

[0082] S1022: When the temperature reaches a first threshold range, perform clock spread spectrum on the corresponding M.2 interface;

[0083] S1023: When the temperature reaches a second threshold range, constrain the link rate of the corresponding M.2 interface to less than 50% of the nominal value until the temperature falls below the second threshold range, and then release the constraint on the link rate of the corresponding M.2 interface;

[0084] The temperature value in the first threshold range is smaller than that in the second threshold range.

[0085] When the temperature is too high, for example, within the first threshold range of 70°C to 85°C, clock spread spectrum can be used to reduce thermal concentration caused by the concentrated frequency. When the temperature further rises to the second threshold range, for example, greater than 85°C, speed limiting can be implemented to prevent adverse effects such as disk damage. In this embodiment, speed limiting due to excessive temperature takes precedence over speed limiting due to CRC errors.

[0086] The released bandwidth is preferentially allocated to the transmission of heat dissipation-related instructions (such as SMART data reading) of the USB interface. After the temperature returns to normal, in some specific embodiments, the original bandwidth is gradually restored at a gradient of 200 Mbps.

[0087] In some optional embodiments, in order to coordinate the allocation of transmission resources and ensure transmission stability, stability detection is performed during the link rate adjustment process:

[0088] After each link rate reallocation, monitor the following stability indicators:

[0089] Change in the skew value of the PCIe link (Δ<100ps);

[0090] USB eye opening (≥70% UI);

[0091] BER of the M.2 interface (<1E-12);

[0092] When indicators are abnormal, they automatically roll back to the previous stable configuration.

[0093] In some preferred embodiments, the multi-way arbitration logic unit is used to adjust resource allocation between various interfaces, and further includes:

[0094] S201, when a forensic instruction signature is detected, stop transmission of all non-forensic channels and freeze the current link state;

[0095] S202, raising the priority of the TLP packet of the evidence collection channel to the highest level;

[0096] S203: After evidence collection is completed, the bandwidth of the evidence collection channel is allocated to the non-evidence collection channel, so that the bandwidth ratio of the non-evidence collection channel is restored to the level before being frozen.

[0097] In this embodiment, the TLP packet characteristic of the forensic instruction is that the TC field in the Header is 3 (highest priority), and the data payload contains a SHA-256 hash signature (such as 0x9F2D...). Through the above method, channels with forensic requirements are given priority, thereby facilitating and quickly completing forensics.

[0098] In some optional examples, the multi-way arbitration logic unit is used to adjust resource allocation between various interfaces, and further includes: when the M.2 interface is fully loaded, dynamically reducing the clock frequency of the SATA protocol channel to 60%-80% of the baseline value.

[0099] In some optional examples, the multi-way arbitration logic unit is used to adjust the resource allocation between each interface, and also includes: when a high-speed storage device is inserted into the USB interface, triggering a bandwidth rebalancing mechanism to proportionally reduce the PCIe link width of the idle M.2 channel.

[0100] In some preferred embodiments, the multi-way arbitration logic unit is used to adjust resource allocation between various interfaces, and further includes:

[0101] S301: When a USB device transfer times out, dynamically and gradually allocate additional bandwidth to the USB 3.0 interface from an emergency bandwidth pool. The emergency bandwidth pool is pre-configured exclusive bandwidth specifically allocated for the USB 3.0 interface. For example, when a USB transfer times out, the USB 3.0 bandwidth is expanded by increasing the bandwidth by 10% every 2 seconds to expedite the transfer.

[0102] A read-only device also provided in an embodiment of the present application includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the electronic device implements the control method in the above embodiment.

[0103] In one embodiment, the read-only device may be a server. In this embodiment, the structure of the electronic device may be as follows: Figure 3 As shown, it includes a memory 2001 , a communication module 2003 and one or more processors 2002 .

[0104] Memory 2001 is used to store computer programs executed by processor 2002. Memory 2001 may primarily include a program storage area and a data storage area. The program storage area may store an operating system and programs required for running instant messaging functions, while the data storage area may store various instant messaging messages and operating instruction sets.

[0105] Memory 2001 may be a volatile memory, such as random-access memory (RAM); a non-volatile memory, such as read-only memory, flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); or any other medium capable of carrying or storing a desired computer program in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 2001 may be a combination of the aforementioned memories.

[0106] The processor 2002 may include one or more central processing units (CPUs) or digital processing units, etc. The processor 2002 is configured to implement the above-mentioned audio data processing method when calling the computer program stored in the memory 2001 .

[0107] The communication module 2003 is used to communicate with terminal devices and other servers.

[0108] The specific connection medium between the memory 2001, the communication module 2003 and the processor 2002 is not limited in the embodiment of the present application. Figure 3 In the embodiment, the memory 2001 and the processor 2002 are connected via a bus 2004. The bus 2004 is connected to the processor 2002 via a bus 2004. Figure 3 The arrows in the figure are used to illustrate the connection between the other components. The connection between the components is for illustrative purposes only and is not intended to be limiting. The bus 2004 can be divided into an address bus, a data bus, a control bus, etc. For ease of description, Figure 3 The diagram shows that only one arrow is used, but this does not mean that there is only one bus or one type of bus.

[0109] It should also be noted that although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, depending on the embodiment of the application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0110] Based on the same inventive concept as the above-mentioned method embodiment, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store a computer program, and when the computer program is run on a computer, the electronic device implements the control method in the above-mentioned embodiment. The computer-readable storage medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0111] Based on the same inventive concept as the above-mentioned method embodiment, an embodiment of the present invention further provides a computer program product, which includes a computer program. When the program product is run on an electronic device, the computer program is used to enable the electronic device to execute the steps of the control method according to the various exemplary embodiments of the present application described above in this specification. The program product can adopt any combination of one or more readable media. These computer program commands can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the commands executed by the processor of the computer or other programmable data processing device generate commands for implementing the steps in the process Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0112] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

Claims

1. A read-only device supporting a multi-channel M.2 interface, characterized in that: include: A main control module, integrating PCIe and SATA protocol parsing engines, which are used to call the PCIe and SATA protocol parsing engines to identify the protocols followed by the M.2 devices connected to each interface and switch the protocol processing logic; The main control module is also configured with a multi-channel arbitration logic unit for adjusting resource allocation between various interfaces; The interface module includes at least multiple M.2 interfaces, each of which is independently configured with a PCIe channel and a SATA channel to connect to the main control module. When the main control module identifies that the protocol followed by the M.2 device connected to the interface is the NVMe protocol, the interface module performs data transmission through the PCIe channel, and when the main control module identifies that the protocol followed is the SATA protocol, the interface module performs data transmission through the SATA channel; The security interception module is connected to the main control module to synchronize the protocol information followed by the M.2 devices connected to each interface and the write protection status information of each interface from the main control module, and judge and execute whether to implement write protection for the interface based on the protocol information and write protection status information.

2. The read-only device according to claim 1, wherein: The main control module uses the RK3568 chip, and each M.2 interface is independently connected to the RK3568 chip, wherein: The M.2 interface that complies with the NVMe protocol is connected to the RK3568 chip as follows: The clock signal pin of the M.2 interface is connected to the high-speed clock output pin corresponding to the RK3568 chip; The M.2 interface's transmit data differential signal pair TX_P and TX_N are connected to the RK3568 chip's high-speed data receiving pins, and the M.2 interface's receive data differential signal pair RX_P and RX_N are correspondingly connected to the chip's high-speed data transmitting pins; The M.2 interface that complies with the SATA protocol is connected to the RK3568 chip as follows: The SATA data pins of the M.2 interface are respectively connected to the corresponding pins of the SATA controller inside the RK3568 chip.

3. The read-only device according to claim 1, wherein: It also includes a USB 3.0 controller, and the interface module also includes a USB 3.0 interface, and a high-speed data transmission pin of the USB 3.0 interface is connected to a high-speed data pin of the USB 3.0 controller.

4. The read-only device according to claim 3, wherein: The determining and executing whether to implement write protection on the interface according to the protocol information and the write protection status information includes: Configuring a PCIe TLP packet filter to intercept all TLP headers containing the MWr opcode to write-protect the M.2 interface; Disconnect the write enable signal of the USB 3.0 device to write-protect the USB 3.0 interface.

5. The read-only device according to claim 4, wherein: The multi-channel arbitration logic unit is used to adjust resource allocation between various interfaces, including: Allocate initial bandwidth to the corresponding interface according to the protocol of each interface; During data transmission, the CRC error rate of each channel is collected in real time. For M.2 channels with the same protocol: When the CRC error rate of a certain M.2 channel exceeds the threshold, its link rate is gradually reduced until the error is eliminated; Acquire in real time the sum of the reduced link rates of the M.2 channels whose link rates are reduced each time, and distribute the sum of the reduced link rates to the M.2 channels whose CRC error rates do not exceed the threshold in descending order based on the real-time CRC error rates of the M.2 channels whose current CRC error rates do not exceed the threshold; When the CRC error rate of a certain M.2 channel changes from exceeding the threshold to being below the threshold for a continuous preset time, the link rate of the M.2 channel is restored to the average link rate of all M.2 channels currently transmitting whose CRC error rates do not exceed the threshold. Accordingly, the link rates of the M.2 channels that are higher than the average link rate are synchronously reduced, and the speed reduction proportion of each M.2 channel gradually decreases in descending order based on the link rate before the speed reduction.

6. The read-only device according to claim 5, wherein: When the CRC error rate of a certain M.2 channel exceeds a threshold, its link rate is gradually reduced until the error is eliminated. Real-time monitoring of flash memory temperature sensor data of each M.2 interface; When the temperature reaches a first threshold range, clock spread spectrum is performed on the corresponding M.2 interface; When the temperature reaches a second threshold range, constraining the link rate of the corresponding M.2 interface to less than 50% of the nominal value until the temperature falls below the second threshold range, and then releasing the constraint on the link rate of the corresponding M.2 interface; The temperature value in the first threshold range is smaller than that in the second threshold range.

7. The read-only device according to claim 5, wherein: The multi-channel arbitration logic unit is used to adjust resource allocation between various interfaces, and further includes: When a forensic command signature is detected, all non-forensic channels are stopped from transmitting and the current link state is frozen; Increase the TLP packet priority of the forensic channel to the highest level; After the evidence collection is completed, the bandwidth of the evidence collection channel is allocated to the non-evidence collection channel, so that the bandwidth ratio of the non-evidence collection channel is restored to the level before it was frozen.

8. The read-only device according to claim 5, wherein: The method further includes: the multi-way arbitration logic unit is used to adjust resource allocation between the various interfaces, and further includes: When the USB device transmission times out, bandwidth is gradually and dynamically added to the USB 3.0 interface from the emergency bandwidth pool, where the emergency bandwidth pool is an exclusive bandwidth pre-configured for the USB 3.0 interface.

9. The read-only device according to claim 5, wherein: The baseline bandwidth of the NVMe device is 1.8-2.5 times that of the SATA device.

10. The read-only device according to claim 1, wherein: There are at least 4 M.2 interfaces.

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