Method and apparatus for programmable integrated circuit coprocessor segment management

Abstract

The host processor may utilize the co-processor to accelerate the performance of the task. When an acceleration request is received from the host processor, the coprocessor may identify and select available logical segments within the coprocessor, which may be used to perform tasks associated with the acceleration request. In some cases, the selected logical section may not be configured to perform a task, in which case the selected logical section may be reconfigured. A configuration bit stream used to reconfigure selected logic segments to perform tasks may be retrieved from a stacked memory die mounted on the coprocessor, or the configuration bit stream may be retrieved from external memory by the host processor if the configuration bit stream is not stored in the stacked memory die. Load balancing may be performed to dynamically allocate additional logical segments to time-critical tasks.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201710975674.7, application date October 19, 2017, and invention name “Method and device for programmable integrated circuit coprocessor segment management”. Technical Field

[0002] The present disclosure relates to integrated circuits, and more particularly to programmable integrated circuits. Background Art

[0003] A programmable integrated circuit (IC) is a type of integrated circuit that can be programmed by the user to implement a desired custom logic function. Typically, a logic designer uses computer-aided design (CAD) tools to design custom logic circuits. Upon completion of the design process, the CAD tool generates configuration data. This configuration data is loaded into memory elements to configure the device to perform the functions of the custom logic circuit.

[0004] Configuration data can be supplied to a programmable device in the form of a configuration bitstream. After a first configuration bitstream is loaded onto the programmable device, the programmable device can be reconfigured by loading a different configuration bitstream in a process known as reconfiguration. Often, the entire set of configuration data is loaded during reconfiguration.

[0005] Programmable devices can be used for co-processing in big data or fast data applications. For example, programmable devices can be used in application acceleration tasks in data centers and can be reprogrammed to perform different tasks during data center operations. However, the speed of reconfiguration of programmable devices is traditionally several orders of magnitude slower than the desired rate of virtualization in data centers. Moreover, on-chip caching or buffering of pre-fetched configuration bitstreams to hide the delay of reconfiguration is undesirably expensive in terms of silicon substrate. In addition, repeatedly retrieving the configuration bitstream from off-chip storage via the entire configuration circuit chain is energy intensive.

[0006] Situations frequently arise where it would be desirable to design and implement a programmable device with increased reconfiguration speed, reduced energy consumption, and parallel reconfiguration capabilities.

[0007] The embodiments presented herein are within the scope of this context. Summary of the Invention

[0008] It will be appreciated that the present invention can be implemented in numerous ways (eg, as a process, an apparatus, a system, a device, or a method) on a computer readable medium. Several inventive embodiments of the present invention are described below.

[0009] A host processor can be tasked with executing a batch of work / tasks. To increase the speed of executing these tasks, a coprocessor integrated circuit can be used to execute a subset of the batch. The host processor can send an acceleration request to the coprocessor. This acceleration request can be received by a secure device manager in the coprocessor, which can identify one or more logical segments that can be used to execute the given task or tasks associated with the acceleration request.

[0010] During the execution phase, the security device manager can communicate with the local segment manager at each logical segment to determine whether any of the logical segments has been configured to perform a given task. If it is determined that such a pre-configured segment exists, that segment can be selected and used to perform the given task.

[0011] If it is determined that such a pre-configured segment does not exist, the host processor can provide the local segment manager of the available segment with a pointer to the location of the configuration bitstream required to perform a given task stored in the stacked memory die. However, in some cases, the required configuration bitstream may not be present in the stacked memory die. The local segment manager can determine whether the required configuration data is present in the stacked memory die.

[0012] If it is determined that the required configuration data is stored on the stacked memory die, the required configuration bitstream can be retrieved from the stacked memory die and used to reconfigure the available segments. The configuration data stored on the stacked memory die can be unencrypted. The stacked memory die can act as an instruction cache, and the configuration data is retrieved from the instruction cache by the local segment manager to reconfigure the logical segments.

[0013] If it is determined that the required configuration data is not stored on the stacked memory die, the local segment manager of the available segment can send a request to the host processor, asking the host processor to provide the required configuration bitstream to the stacked memory die. The local segment manager can then load the required configuration bitstream onto the available segment, thereby reconfiguring the available segment. In some cases, the local segment manager can receive the required configuration bitstream directly from the host processor through the secure device manager, in which case the required configuration bitstream can also be stored on the stacked memory die.

[0014] The coprocessor integrated circuit can perform steps for load balancing the work / tasks received from the host processor. The host processor can send non-deterministic work / tasks with a predetermined time budget to the coprocessor. Some tasks provided to the coprocessor can be deterministic in that they will take a predetermined amount of time to complete. In contrast, other tasks provided to the coprocessor can be non-deterministic in that it is impossible to predict the number of steps required to complete each task.

[0015] The coprocessor may analyze the received task and may allocate an initial number of logic segments in an attempt to complete the task within a required time budget. As the task is being executed by the initially allocated logic segments, the coprocessor may monitor the duration of the task. While monitoring the duration of the task, the coprocessor may determine that the initially allocated logic segments will not be able to complete the work within the required time budget.

[0016] In response to determining that the time budget cannot be adhered to using only the initially allocated logical segments, the coprocessor can introduce more parallelism by dynamically allocating additional segments to assist in processing the task. Specifically, idle segments can be requisitioned / borrowed and reconfigured or segments of less critical tasks can be manipulated to execute time-sensitive tasks. In some embodiments, the maximum number of segments that can run in parallel (e.g., simultaneously) can be optionally limited.

[0017] Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a diagram of an illustrative programmable integrated circuit in accordance with an embodiment.

[0019] Figure 2 is a diagram showing how configuration data is created by a logic design system and loaded into a programmable device to configure the device to operate in the system, according to an embodiment.

[0020] Figure 3 is a diagram showing how a programmable integrated circuit can be used as a co-processor to support a host processor, according to an embodiment.

[0021] Figure 4 is a diagram of an illustrative programmable integrated circuit having multiple logic segments managed by a local segment manager and a secure device manager in accordance with an embodiment.

[0022] Figure 5 is an illustrative integrated circuit package including a coprocessor programmable integrated circuit and one or more in-package stacked memory elements in accordance with an embodiment.

[0023] Figure 6is a method for loading a configuration bitstream into Figure 4 A flowchart of illustrative steps in a logic section of a programmable integrated circuit.

[0024] Figure 7 According to an embodiment, Figure 4 A flowchart of illustrative steps for programming a logic section of an integrated circuit to process an acceleration request received from a host processor.

[0025] Figure 8 According to an embodiment, Figure 4 A flowchart of illustrative steps for load balancing a programmable integrated circuit to process fixed-time budget work requests received from a host processor. DETAILED DESCRIPTION

[0026] Embodiments of the present invention relate to integrated circuits, and more particularly to programmable integrated circuits. Those skilled in the art will recognize that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations are not described in detail to avoid unnecessarily obscuring the present embodiments.

[0027] Programmable integrated circuits use programmable memory elements to store configuration data. The configuration data can be generated based on source code corresponding to specialized tasks executed in parallel on the programmable integrated circuit. During programming of the programmable integrated circuit, the configuration data is loaded into the memory elements. The memory elements can be organized in an array having many rows and columns. For example, a memory array circuit can be formed in hundreds or thousands of rows and columns on a programmable logic device integrated circuit.

[0028] During normal operation of a programmable integrated circuit, each memory element provides a static output signal. The static output signals provided by the memory elements serve as control signals. These control signals are applied to the programmable logic cells on the integrated circuit to customize the programmable logic cells to perform the desired logic functions.

[0029] It may sometimes be desirable to configure or reconfigure a programmable integrated circuit as an accelerator circuit to efficiently execute parallel processing tasks. Accelerator circuits can include multiple columns of soft processors of various types dedicated to different types of parallel tasks. Accelerator circuits can be dynamically reconfigured to optimally allocate and execute parallel tasks.

[0030] exist Figure 1 An illustrative programmable integrated circuit, such as a programmable logic device (PLD) 10, is shown in FIG. Figure 1As described in , the programmable integrated circuit 10 may have input-output circuits 12 for driving signals out of the device 10 and for receiving signals from other devices via input-output pins 14. Interconnect resources 16 (e.g., global and local vertical and horizontal conductive lines and buses) may be used to transmit signals on the device 10. Interconnect resources 16 include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between corresponding fixed interconnects). Programmable logic cells 18 may include combinational and sequential logic circuits. Programmable logic cells 18 may be configured to perform custom logic functions.

[0031] The programmable integrated circuit 10 includes a memory element 20 that can be loaded with configuration data (also referred to as programming data) using pins 14 and input-output circuits 12. Once loaded, the memory elements 20 can each provide a corresponding static control output signal that controls the state of the associated logic component in the programmable logic unit 18. Typically, the memory element output signal is used to control the gate of a metal oxide semiconductor (MOS) transistor. Some transistors may be p-channel metal oxide semiconductor (PMOS) transistors. Many of these transistors may be n-channel metal oxide semiconductor (NMOS) pass transistors in programmable components (e.g., multiplexers). When the memory element output is high, the NMOS pass transistor controlled by that memory element will be turned on to transmit the logic signal from its input to its output. When the memory element output is low, the pass transistor is turned off and does not transmit the logic signal.

[0032] The typical memory element 20 is formed of a plurality of transistors configured to form a cross-coupled inverter. Other arrangements (e.g., cells with more distributed inverter-like circuits) may also be used. Utilizing one suitable approach, complementary metal oxide semiconductor (CMOS) integrated circuit technology is used to form the memory element 20, so CMOS-based memory element implementations are described herein as examples. In the context of programmable integrated circuits, memory elements store configuration data and are therefore sometimes referred to as configuration random access memory (CRAM) cells.

[0033] exist Figure 2 An illustrative system environment for device 10 is shown in FIG. Device 10 may be mounted on board 36 in system 38. Typically, programmable logic device 10 may receive configuration data from a programming device or from other suitable devices or apparatuses. Figure 2 In the example of FIG, programmable logic device 10 is a type of programmable logic device that receives configuration data from an associated integrated circuit 40. With this type of arrangement, circuit 40 can be mounted on the same board 36 as programmable logic device 10, if desired.

[0034] Circuit 40 may be an erasable programmable read-only memory (EPROM) chip, a programmable logic device configuration data loading chip with built-in memory (sometimes referred to as a "configuration device"), or another suitable device. When system 38 is started (or at another suitable time), configuration data for configuring the programmable logic device may be supplied from device 40 to the programmable logic device, as schematically shown by path 42. The configuration data supplied to the programmable logic device may be stored in the programmable logic device in its configuration random access memory element 20.

[0035] System 38 may include processing circuitry 44, memory 46, and other system components 48 that communicate with device 10. The components of system 38 may be located on one or more boards (e.g., board 36) or other suitable mounting structures or housings, and may be interconnected by buses, traces, and other electrical pathways 50.

[0036] Configuration data for device 10 may be supplied to configuration device 40 via a path, such as path 52. Configuration device 40 may receive the configuration data, for example, from configuration data loading device 54 or other suitable device that stores this data in configuration device 40. Device 40 may be loaded with data before or after installation on board 36.

[0037] Designing and implementing the desired logic circuits in a programmable logic device can be a significant undertaking. Logic designers therefore typically use a logic device system based on computer-aided design (CAD) tools to assist them in designing the circuits. The logic design system can help logic designers design and test the complex circuits of their systems. Once the design is complete, the logic design system can be used to generate configuration data for electrically programming the appropriate programmable logic device.

[0038] like Figure 2 As shown in FIG, configuration data generated by logic design system 56 can be provided to device 54 via a path (e.g., path 58). Device 54 provides configuration data to device 40 so that device 40 can later provide this configuration data to programmable logic device 10 via path 42. Logic design system 56 can be based on one or more computers and one or more software programs. In general, software and data can be stored on any computer-readable medium (storage) in system 56 and can be stored on any computer-readable medium (storage) in system 56. Figure 2 Schematically shown as a reservoir 60.

[0039] In a typical scenario, logic design system 56 is used by logic designers to create custom circuit designs. System 56 generates corresponding configuration data that is provided to configuration device 40. When powered on, configuration device 40 and data loading circuitry on programmable logic device 10 are used to load the configuration data into CRAM cells 20 of device 10. Device 10 can then be used in normal operation of system 38.

[0040] After device 10 is initially loaded with a set of configuration data (e.g., using configuration device 40), device 10 can be reconfigured by loading a different set of configuration data. It may be desirable to reconfigure only a portion of the memory cells on device 10 via a process sometimes referred to as partial reconfiguration. Because memory cells are generally arranged in an array, partial reconfiguration can be performed by writing new data values ​​to only a selected portion(s) of the array, while maintaining portions of the array other than the selected portion(s) in their original state.

[0041] Partial reconfiguration can be a particularly useful feature when developing an acceleration framework. For example, consider a system (e.g., system 300) including a host processor 302 coupled to other network components via path 304 (see, e.g., Figure 3 ) situation. Figure 3 As shown in FIG, host processor 302 may be coupled to a coprocessor (e.g., an accelerator circuit), such as coprocessor 310 (sometimes referred to herein as accelerator circuit 310 or accelerator 310), via path 312. Accelerator circuit 310 may be a programmable integrated circuit, such as Figure 1 Alternatively, the plurality of accelerator circuits 310 may be in a programmable integrated circuit. The accelerator circuit 310 may include various processing nodes (e.g., processing cores, processor cores) such as cores P1-P4 to help accelerate the performance of the host processor 302. The cores P1-P4 may be configurable (e.g., programmable) soft processor cores or soft processors. In some instances, the processor cores (e.g., cores P1-P4) may be implemented as logic segments in the accelerator circuit 310.

[0042] Accelerator circuitry 310 configured in this manner may sometimes be referred to as a “hardware accelerator.” As an example, the processing cores on the coprocessor may be used to accelerate various functions including, but not limited to, encryption, fast Fourier transforms, video encoding / decoding, convolutional neural networks (CNNs), firewalls, command detection, database searches, domain name services (DNS), load balancing, caching network address translation (NAT), and other suitable network packet processing applications, to name a few.

[0043] For instances where cores P1-P4 are implemented as logical segments in the accelerator circuit 310, each logical segment may be managed using a local segment manager, which in turn may be managed using a secure device manager. Figure 4 As shown in FIG, the accelerator circuit 310 may include a plurality of logical segments 410 (sometimes referred to as segments 410). Each logical segment may be managed by a corresponding one of the local segment managers (LSMs) 412. The local segment managers 412 may be managed by the secure device manager 402. The hard processing controller 400 may be able to receive data from a host processor (e.g., Figure 3 The secure device manager 402 receives configuration data (e.g., a configuration bitstream) and / or accelerator requests from a host processor (e.g., a host processor). The secure device manager 402 can receive configuration data, accelerator requests, and commands from the hard processing controller 400. The hard processing controller 400 can be, for example, a microprocessor. The secure device manager 402 provides commands, configuration data, and acceleration requests to the local segment manager 412 via bus 414.

[0044] In some instances, the configuration data and accelerator requests may optionally be compressed and encrypted. Accordingly, the secure device manager 402 may include a decompression engine 404 and a decryption engine 406 for decompressing and decrypting data received from the host processor via the hard processing controller 400.

[0045] The logical segments 410 can be individually configurable / programmable. This allows each logical segment 410 to independently process different tasks in parallel. The parallel processing enabled by the logical segments 410 can be used to perform application acceleration for various tasks or workloads (e.g., in a data center) by simultaneously reconfiguring different subsets of the logical segments to perform the tasks.

[0046] In order to effectively manage application acceleration as new tasks are issued from the host processor to the accelerator circuit 310, it may be necessary to perform real-time reconfiguration on any logic section 410 that will be used to process a given newly received task. In other words, the reconfiguration of the logic section 410 can be performed while the accelerator circuit 310 is running and can be performed without interrupting the operation of the accelerator circuit 310.

[0047] The selection of which logical segments 410 to be used for a given task can be determined by identifying which segments are idle (e.g., not currently executing a task) and by identifying which segments are processing lower priority tasks (e.g., tasks without a fixed time budget) compared to the priority of the given task. Some or all logical segments 410 identified as idle or identified as performing less critical tasks can then be selected and, if necessary, reconfigured to perform the operations of the given task. The reallocation of logical segments 410 operating on lower priority tasks than the given task requiring segment allocation can be performed based on a load balancing mechanism. It should be noted that those logical segments 410 identified as already configured to perform a given task can be given a given selection priority over any segments that need to be reconfigured to perform the task.

[0048] The configuration data received by the accelerator circuit 310 may be stored in memory on the same circuit package as the accelerator circuit 310. Figure 5 As shown in , the coprocessor 310 and one or more in-package stacked memory elements 502 (sometimes referred to as memory elements 502 or memory dies 502 ) may be mounted on or integrated as part of an IC package 500 .

[0049] In some examples, the memory die 502 can be mounted directly on the accelerator circuit 310. The memory die 502 can be connected to the accelerator circuit 310 through through-silicon vias (TSVs), which pass through one or more silicon layers of the circuit die of the accelerator circuit 310. These TSVs can allow the memory die 502 to load configuration data onto the segments 410 of the accelerator circuit 310 up to three orders of magnitude faster than traditional reconfiguration techniques.

[0050] Configuration data from the host processor can be loaded onto the memory die 502 after being processed / routed (e.g., after being decompressed and decrypted) by the secure device manager 402 of the accelerator circuit 310. The configuration data can include one or more segment-level reconfiguration bitstreams. When one of the segments 410 is selected to perform a task, if that segment needs to be reconfigured to perform the task (e.g., because the segment is currently configured to perform a different task), the secure device manager 402 can provide the selected segment with a pointer to the location of the necessary configuration bitstream (e.g., persona) required to perform that task in the memory die 502.

[0051] In some cases, the memory die 502 may not already have the necessary configuration bitstream stored when the bitstream is needed by the selected segment. In this case, the secure device manager 402 can retrieve the necessary configuration bitstream from external memory and load the retrieved bitstream onto the selected segment and the memory die 502.

[0052] Combined with the above Figure 3-5 The accelerator circuit 310 and memory element 502 may perform steps for receiving and storing a configuration bitstream from a host processor during a prefetch phase of an instruction cycle (see, e.g., Figure 6 illustrative steps).

[0053] In step 600, a host processor (e.g. Figure 3 The host processor 302 of FIG. 1 initiates a prefetch phase for a set of expected configuration bitstreams (e.g., corresponding to processing tasks). These configuration bitstreams may be provided to the coprocessor (e.g., Figure 3-5 accelerator circuit 310).

[0054] At step 602, a secure device manager (e.g. Figure 4 The secure device manager 402 may receive a configuration bitstream from a host processor and may perform decompression and decryption operations on the received bitstream.

[0055] At step 606, the local segment manager (e.g. Figure 4 The local segment manager 412) can be used to load the selected bitstream into each logical segment to configure each logical segment with a corresponding function or "role" (e.g., to configure each segment to perform a specific task).

[0056] At step 608, all available decompressed and decrypted configuration bitstreams may be stored in one or more packaged stacked memory elements (e.g., Figure 5 502).

[0057] By storing decompressed and decrypted configuration bitstreams in the in-package stacked memory elements in this manner, these bitstreams can be easily accessed for reconfiguring logic segments with greater speed and power efficiency compared to traditional methods, in which the configuration bitstreams are only retrieved from off-chip memory.

[0058] Combined with the above Figure 3-5 The accelerator circuit 310 and the memory element 501 may perform steps for managing segments to execute a batch of work / tasks received from a host processor (see, e.g., Figure 7 illustrative steps).

[0059] In step 700, a host processor (e.g. Figure 3 To increase the speed at which these tasks are performed (e.g., to accelerate the tasks), coprocessors (e.g., Figure 3-5 The accelerator circuit 310) can be used to perform at least a subset of the batch of tasks.

[0060] In step 702, the host processor may send an acceleration request to the coprocessor. This acceleration request may be initiated by a secure device manager (e.g., Figure 4 The security device manager 402 receives the request, the security device manager may identify a device (eg, a server) that can be used to perform one or more given tasks (eg, current work) associated with the acceleration request. Figure 4 410 of logical segments) or more logical segments.

[0061] At step 704, during the execution phase of the instruction cycle, the secure device manager may communicate with the local segment manager (e.g., Figure 4 The local segment manager 412 of the system communicates to determine whether any logical segment has been configured to perform a given task. Depending on whether a segment pre-configured to perform a given task exists, the process may proceed to step 706 or step 708.

[0062] At step 706, if such a pre-configured segment exists, that segment may be selected and used to perform the given task.

[0063] At step 708, if such pre-configured segments do not exist, the host processor may provide the local segment manager with an available segment to execute the data stored on the stacked memory die (e.g., Figure 5 The configuration file stored on the stacked memory die may be unencrypted. However, the required configuration bitstream may not be present in the stacked memory die. Therefore, the local segment manager may check to determine whether the required configuration file exists in the stacked memory die. If the required configuration data exists in the stacked memory die, the process may proceed to step 710. Otherwise, the process may proceed to step 712.

[0064] At step 710, if the required configuration data is stored in the stacked memory die (e.g., if there is a cache hit), the required or desired configuration bitstream can be retrieved from the stacked memory die and can be used to reconfigure the available segments (e.g., by loading the required configuration bitstream onto the available segments). The configuration image stored in the stacked memory die may not be encrypted. The stacked memory die may act as an instruction cache from which configuration data (e.g., bitstream) is retrieved by the local segment manager for reconfiguring the logical segments.

[0065] In step 712, if the required configuration data is not stored on the stacked memory die (e.g., if there is a cache miss), the local segment manager of the available segment can send a request to the host processor asking the host processor to provide the required configuration bitstream to the stacked memory die. The local segment manager can then load the required configuration bitstream onto the available segment, thereby reconfiguring the available segment. In some cases, the local segment manager can receive the required configuration bitstream directly from the host processor through the secure device manager, in which case the required configuration bitstream can also be stored on the stacked memory die.

[0066] Combined with the above Figure 3-5 The accelerator circuit 310 may perform steps for load balancing the work / tasks received from the host processor (see, e.g., Figure 8 illustrative steps).

[0067] In step 800, a host processor (e.g. Figure 3 A host processor (e.g., a coprocessor) can send non-deterministic work / tasks with a predetermined (e.g., fixed) time budget to a coprocessor (e.g., Figure 3-5 accelerator circuit 310). Some tasks provided to the coprocessor may be deterministic in that they will take a predetermined amount of time to complete. In contrast, other tasks provided to the coprocessor may be non-deterministic in that it is impossible to predict the number of steps required to complete each task (e.g., due to iterative conditional loops). Therefore, given a fixed time budget, the amount of processing power and, therefore, the number of logic segments required to execute the non-deterministic tasks may need to be dynamically controlled to ensure that the tasks can be completed within the time budget.

[0068] In step 802, the coprocessor may analyze the received task and may allocate an initial number of logical segments (eg, Figure 4 logical section 410) to attempt to complete the task within the required time budget.

[0069] While the task is being executed by the originally assigned logic section, the coprocessor may monitor the duration of the task at step 804. While monitoring the duration of the task, the coprocessor may determine that the originally assigned logic section will not be able to complete the work within the required time budget.

[0070] In response to determining that the time budget cannot be adhered to with only the initially allocated logical segments, the coprocessor may introduce more parallelism by dynamically allocating additional segments to assist in processing the task at step 806. Specifically, idle segments may be requisitioned / borrowed and reconfigured or segments of less critical tasks may be manipulated to execute time-sensitive tasks.

[0071] By prioritizing time-critical tasks in this way, the overall efficiency of the coprocessor can be advantageously increased compared to conventional coprocessor approaches that lack load balancing functionality.

[0072] The maximum number of sections that can run in parallel (eg, simultaneously) can optionally be limited at step 808. This limit can help the coprocessor meet power conservation criteria or other operating constraints. Figure 7 and 8 The steps can be used together and are not mutually exclusive.

[0073] The embodiments have been described so far with respect to integrated circuits. The methods and apparatus described herein may be incorporated into any suitable circuit. For example, they may be incorporated into many types of devices, such as programmable logic devices, application specific standard products (ASSPs), and application specific integrated circuits (ASICs). Examples of programmable logic devices include programmable array logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), to name a few.

[0074] The programmable logic device described in one or more embodiments herein can be part of a data processing system that includes one or more of the following components: a processor; a memory; an IO circuit; and peripheral devices. Data processing can be used in various applications (e.g., computer networking, data networking, detection instruments, video processing, digital signal processing, or any other suitable application) where the advantages of using programmable or reprogrammable logic units are desirable. The programmable logic device can be used to perform various different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in conjunction with a system processor. The programmable logic device can also be used as an arbitrator for arbitrating access to shared resources in a data processing system. In another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device can be one of the device families owned by ALTERA / INTEL.

[0075] The foregoing merely illustrates the principles of the present invention and various modifications may be made by those skilled in the art.The foregoing embodiments may be implemented individually or in any combination.

Claims

1. A method for operating an integrated circuit, comprising: receiving a task to be performed on the integrated circuit; determining whether a given logic section among a plurality of logic sections on the integrated circuit is currently configured to perform the task; as well as In response to determining that the given logic section is not currently configured to perform the task, a determination is made as to whether a configuration bitstream corresponding to the task is stored in a memory die coupled to the integrated circuit.

2. The method according to claim 1, wherein The memory die is stacked directly on the integrated circuit.

3. The method according to claim 1, further comprising: In response to determining that the configuration bitstream corresponding to the task is stored in the memory die, the given logic section is configured with the stored configuration bitstream.

4. The method according to claim 3, further comprising: After configuring the given logic section with the stored configuration bitstream, the task is performed with the given logic section.

5. The method according to any one of claims 1 to 4, further comprising: In response to determining that the configuration bitstream corresponding to the task is not stored in the memory die, the configuration bitstream is requested from a host processor external to the integrated circuit.

6. The method according to claim 5, further comprising: receiving a requested configuration bitstream from the host processor; configuring the given logical section using the received configuration bitstream; as well as After configuring the given logic section with the received configuration bitstream, the task is performed with the given logic section.

7. The method according to claim 5, further comprising: The received configuration bitstream is stored in the memory die.

8. The method according to claim 1, further comprising: In response to determining that the given logic section is currently configured to perform the task, the task is performed with the given logic section.

9. A method for operating an integrated circuit, comprising: receiving work to be performed on the integrated circuit; allocating an initial number of logic segments on the integrated circuit to perform the work; as well as Different numbers of logic sections are dynamically allocated on the integrated circuit to perform the tasks.

10. The method according to claim 9, wherein: The task has a predetermined time budget, and the method further comprises: The work is monitored to determine whether the work is completed within the predetermined time budget.

11. The method according to claim 10, wherein: Dynamically allocating the different number of logical segments to perform the work includes dynamically allocating the different number of logical segments to perform the work in response to determining that the work cannot be completed within the predetermined time budget using the initial number of logical segments.

12. The method according to any one of claims 9 to 11, wherein: Dynamically allocating the different numbers of logic segments on the integrated circuit to perform the work includes requisitioning idle logic segments on the integrated circuit.

13. The method according to any one of claims 9 to 11, wherein: Dynamically allocating the different number of logic segments on the integrated circuit to perform the work includes borrowing logic segments on the integrated circuit that are currently being used to perform less critical work.

14. The method according to any one of claims 9 to 11, wherein: Dynamically allocating the different number of logic segments on the integrated circuit to perform the work includes adding an additional number of logic segments to the initial number to help perform the work faster.

15. The method according to any one of claims 9 to 11, further comprising: Limits the maximum number of logical segments currently used to perform the work.

16. A system comprising: a host processor that is tasked to perform work and generates a corresponding acceleration request to accelerate the work; a coprocessor that receives the acceleration request from the host processor; as well as a memory die stacked on the coprocessor, wherein the coprocessor comprises: multiple logical segments; and A logical segment manager retrieves a configuration bitstream from the memory die and configures a selected logical segment of the plurality of logical segments with the retrieved configuration bitstream.

17. The system according to claim 16, wherein: The coprocessor further comprises: A secure device manager provides additional configuration bitstreams to the local segment manager.

18. The system according to claim 17, wherein: The secure device manager includes circuitry selected from the group consisting of: decompression circuitry and decryption circuitry.

19. The system according to claim 18, wherein: The bitstream stored in the memory die is not encrypted.

20. The system according to any one of claims 16 to 19, wherein: The logical segment manager receives a pointer from the host processor, and wherein the logical segment manager determines whether there is a cache hit in the memory die based on the pointer.

21. An integrated circuit comprising: means for receiving a task to be performed on the integrated circuit; means for determining whether a given logic section among a plurality of logic sections on the integrated circuit is currently configured to perform the task; as well as Means for determining, in response to determining that the given logic section is not currently configured to perform the task, whether a configuration bitstream corresponding to the task is stored in a memory die coupled to the integrated circuit.

22. The integrated circuit of claim 21 , further comprising: means for, in response to determining that the configuration bitstream corresponding to the task is stored in the memory die, configuring the given logic section with the stored configuration bitstream; as well as Means for performing the task with the given logic section after configuring the given logic section with the stored configuration bitstream.

23. The integrated circuit of claim 21 , further comprising: means for requesting the configuration bitstream from a host processor external to the integrated circuit in response to determining that the configuration bitstream corresponding to the task is not stored in the memory die; means for receiving a requested configuration bitstream from the host processor; means for configuring the given logical section with the received configuration bitstream; as well as Means for performing the task with the given logical section after configuring the given logical section with the received configuration bitstream.

24. The integrated circuit of claim 23, further comprising: Means for storing the received configuration bitstream in the memory die.

25. The integrated circuit according to any one of claims 21 to 24, further comprising: Means for performing the task with the given logic section in response to determining that the given logic section is currently configured to perform the task.

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