Single particle latch-up resistant process fingerprint extraction method, device and equipment

Abstract

The invention discloses an anti-single event latch-up process fingerprint extraction method, device and equipment, relates to the technical field of integrated circuit chip anti-radiation capability prediction, and is used for solving the problem of poor precision of a constructed anti-radiation performance prediction model caused by incapability of accurately extracting an anti-single event latch-up process fingerprint in the prior art. Comprising the following steps: identifying a sensitive area through an electric latch test, positioning a key parasitic BJT structure, and establishing a TCAD model of the key parasitic BJT structure; based on the TCAD model, SEL simulation and electric latch simulation are carried out by adjusting and pulling different technological parameters, and a simulation result is obtained; preliminarily determining SEL process fingerprint characteristic quantity and parameter influence weight based on a simulation result; sensitivity analysis is carried out in combination with a Morris method and a Sobol method, the global influence weight of each SEL process fingerprint characteristic quantity is determined, and anti-SEL process parameters are optimized. According to the method, a more accurate anti-radiation performance prediction model can be constructed, and the behavior of the device in the track radiation environment can be further predicted more accurately.

Description

Technical Field

[0001] The present invention relates to the technical field of prediction of the radiation resistance of integrated circuit chips, and in particular to a method, device and equipment for extracting fingerprints of a single-particle latch-up resistance process. Background Art

[0002] In traditional aerospace engineering, the "performance-for-hardening" approach is a common paradigm for developing radiation-hardened components. However, with the rapid development of mega-constellations in low-Earth orbit (LEO), this model is no longer adaptable to the demands of rapid iteration and large-scale deployment. LEO constellations, with their high-frequency launches, rapid response, and flexible deployment, are reshaping the aerospace industry. Under this new development model, the traditional paradigm for developing radiation-hardened components faces significant challenges. Furthermore, traditional full-scenario irradiation testing methods have also exposed significant limitations. This approach is not only time-consuming and costly, but also fails to meet the rapid component screening and evaluation requirements of constellation projects.

[0003] Against this backdrop, the critical challenge of enabling the aerospace application of commercial-off-the-shelf (COTS) components has become a pressing issue. COTS components, with their high performance, low cost, and rapid iteration speed, are crucial for complex mission planning, image processing, and scientific data computation in aerospace applications. However, the successful application of these commercial components in aerospace engineering requires overcoming the limitations of traditional evaluation methods and radiation hardening technology systems. Currently, aerospace powers such as the United States and Europe have established comprehensive databases of chip manufacturing information and accumulated extensive experience in radiation hardening evaluation, resulting in a mature system of COTS component radiation hardening assessment methods. Through years of technological accumulation and practical exploration, these countries have established a comprehensive set of radiation hardening assessment standards and technical specifications, providing strong support for the application of COTS components in aerospace. However, my country is still lagging behind in chip manufacturing technology, making it difficult to directly adopt the existing COTS device application paradigms of the United States and Europe. This gap is reflected not only in manufacturing processes but also in evaluation methods, data accumulation, and experience summary.

[0004] Therefore, there is an urgent need to provide a more reliable single-particle latch-up resistant process fingerprint extraction solution to achieve the same-generation development of aerospace chips. Summary of the Invention

[0005] The purpose of the present invention is to provide a method, device and equipment for extracting anti-single-particle latch-up process fingerprints, which is used to solve the problem in the prior art that the anti-single-particle latch-up process fingerprint cannot be accurately extracted, resulting in poor accuracy of the constructed radiation resistance performance prediction model.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a method for extracting fingerprints from a single-event latch-up resistant process, comprising:

[0008] Electrical latch-up testing identifies sensitive areas and locates critical parasitic BJT structures;

[0009] Establishing a TCAD model of the key parasitic BJT structure;

[0010] Based on the TCAD model, SEL simulation and electrical latch simulation are performed by adjusting and biasing different process parameters to obtain simulation results;

[0011] Based on the simulation results, the SEL process fingerprint characteristics and parameter influence weights are preliminarily determined;

[0012] Sensitivity analysis was performed in combination with the Morris method and the Sobol method to determine the global influence weights of the SEL process fingerprint feature quantities and optimize the anti-SEL process parameters.

[0013] Optional electrical latch-up testing identifies sensitive areas and locates critical parasitic BJT structures, including:

[0014] The electrical latch-up test procedure applies electrical stress under specific conditions to obtain the fault response of different areas of the chip;

[0015] By monitoring the current and voltage fluctuations in different areas of the chip, the sensitive areas of the chip that are sensitive to SEL are located.

[0016] Optionally, establishing a TCAD model of the key parasitic BJT structure includes:

[0017] After identifying the sensitive area, a TCAD model of the critical parasitic BJT structure is established using a TCAD tool;

[0018] Based on the TCAD model, SEL simulation and electrical latch-up simulation were performed by adjusting and biasing different process parameters, and the simulation results included:

[0019] On the TCAD model of the key parasitic BJT structure, different process parameters are adjusted and biased, and SEL simulation and electrical latch simulation are performed to obtain simulation results.

[0020] Optionally, after establishing the TCAD model of the key parasitic BJT structure, the method further includes:

[0021] Based on the TCAD model, the effects of different process parameters on SEL sensitivity are simulated and analyzed, and the key parameter ranges are determined by fitting the SEL trigger conditions;

[0022] Before performing sensitivity analysis by combining the Morris method and the Sobol method to determine the global influence weight of each SEL process fingerprint feature and optimizing the anti-SEL process parameters, the following steps are also included:

[0023] Through the electrical latch-up test, the electrical latch-up threshold under different process parameter combinations is obtained to verify the simulation results.

[0024] Optionally, a sensitivity analysis is performed in combination with the Morris method and the Sobol method to determine the global influence weight of each of the SEL process fingerprint feature quantities and optimize the anti-SEL process parameters, including:

[0025] The Morris method is used to divide the initially obtained SEL process fingerprint characteristics into discrete networks, and multiple characteristic value sampling points are randomly generated.

[0026] A fixed-step perturbation is applied to each sampling point, and the latch-up threshold change rate caused by the perturbation is calculated through TCAD simulation. After multiple simulations, the mean and standard deviation of the single-step effect of each SEL process fingerprint characteristic are determined.

[0027] and distinguishing between parameters with significant effects, parameters with nonlinear or interactive effects, and parameters with minor effects based on the single-step effect means and standard deviations;

[0028] The Sobol method is used to calculate the first-order sensitivity index and total sensitivity index of each input parameter based on variance decomposition. The SEL process fingerprint feature quantities are sorted in order of size to determine the global influence weight of each SEL process fingerprint feature quantity. The SEL process fingerprint feature quantities include at least: material doping concentration, well depth and injection depth, contact resistance characteristics, structural layout characteristics of the well region and active region, and concentration distribution of material components.

[0029] Optionally, a fixed-step perturbation is applied to each sampling point, and the latch threshold change rate caused by the perturbation is calculated through TCAD simulation. After multiple simulations, the mean and standard deviation of the single-step effect of each SEL process fingerprint characteristic are determined, including:

[0030] Apply a certain step-length perturbation to the i-th characteristic value of the j-th sampling point and calculate the single-step effect EE i,j :

[0031]

[0032] Repeat the perturbation operation at each sampling point and then find the single-step effect. j means it is performed at the jth sampling point. Change j from 1 to r, where r represents the number of sampling points, to obtain a series of single-step effects.

[0033] For a series of EE i,j(j=1,2,…,r) take the mean and standard deviation:

[0034]

[0035] Get the mean and standard deviation of the single-step effect of the i-th feature quantity, change i and execute the loop until the preset conditions are met, and get the mean and standard deviation of the single-step effect of each feature quantity;

[0036] Among them, the process fingerprint feature x=(x1,x2,...,x i ), EE i,j represents the single-step effect after the perturbation of each feature value at each sampling point, f(x) represents the model output objective function, μ i represents the mean, σ i represents the standard deviation, Δe i Indicates the step size applied.

[0037] Optionally, the Sobol method is used to calculate the first-order sensitivity index and the total sensitivity index of each input parameter based on variance decomposition, and the SEL process fingerprint feature quantities are sorted in order of size to determine the global influence weight of each of the SEL process fingerprint feature quantities, including:

[0038] The process fingerprint feature is directly used as the input variable:

[0039] Y=f(x)=f(x1,x2,...,x d )

[0040] The total variance of the output Var(Y) is expressed as:

[0041]

[0042] First-order sensitivity index S i Expressed as:

[0043]

[0044] Total sensitivity index Expressed as:

[0045]

[0046] Among them, (x1,x2,...,x i ) represents the input SEL process fingerprint feature, Y is the model output objective function, Y=f(x)=f(x1,x2,...,x d ); Var(Y) represents the total variance, V i represents the variance caused by the i-th feature quantity, that is, the main effect variance of the i-th feature quantity, d represents the number of features, V ijV represents the variance caused by the i-th and j-th feature quantities, that is, the second-order interaction variance of the i-th and j-th feature quantities, 1,2,...,d It represents the variance of all parameters acting together; Var(E[Y|x~i]) represents the variance of the mean of Y after removing the influence of the i-th feature quantity, and E[Y|x~i] represents the mean of Y after removing the influence of the i-th feature quantity.

[0047] Compared with the prior art, the present invention provides a method for extracting a process fingerprint that resists single-particle latch-up. Sensitive areas are identified through electrical latch-up testing, and key parasitic BJT structures are located; a TCAD model of the key parasitic BJT structure is established; based on the TCAD model, SEL simulation and electrical latch-up simulation are performed by adjusting and biasing different process parameters to obtain simulation results; based on the simulation results, the SEL process fingerprint feature quantities and parameter influence weights are preliminarily determined; sensitivity analysis is performed in combination with the Morris method and the Sobol method to determine the global influence weights of each of the SEL process fingerprint feature quantities, and to optimize the anti-SEL process parameters. Key feature information reflecting the device's anti-latch-up capability is extracted from its production process parameters, material properties, and circuit structure to form a unique process fingerprint identifier. Based on the characteristic parameters of the anti-single-particle latch-up process fingerprint, a more accurate radiation resistance performance prediction model can be constructed. Based on the extracted SEL process fingerprint feature quantities, ground experiments, and simulations, a model can be established to more accurately predict the device's behavior in an orbital radiation environment.

[0048] In a second aspect, the present invention provides a fingerprint extraction device for a single-event latch-up resistant process, the device comprising:

[0049] Key parasitic BJT structure positioning module, used for electrical latch-up testing to identify sensitive areas and locate key parasitic BJT structures;

[0050] A TCAD model building module, used to build a TCAD model of the key parasitic BJT structure;

[0051] A simulation module, configured to perform SEL simulation and electrical latch simulation based on the TCAD model by adjusting and biasing different process parameters to obtain simulation results;

[0052] An initial process fingerprint feature determination module, configured to preliminarily determine the SEL process fingerprint feature and parameter influence weights based on the simulation results;

[0053] The global impact weight determination module and the process parameter optimization module are used to perform sensitivity analysis in combination with the Morris method and the Sobol method, determine the global impact weight of each SEL process fingerprint feature, and optimize the anti-SEL process parameters.

[0054] In a third aspect, the present invention provides a fingerprint extraction device for a single-event latch-up resistant process, the device comprising:

[0055] A memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be run by the processor; when the processor runs the computer program, the above-mentioned anti-single-particle latch process fingerprint extraction method is executed.

[0056] In a fourth aspect, the present invention provides a computer storage medium having instructions stored therein, which, when executed, implement the above-mentioned single-particle latch-up resistance process fingerprint extraction method.

[0057] The technical effects achieved by the device-type solution provided in the second aspect, the equipment-type solution provided in the third aspect, and the computer storage medium solution provided in the fourth aspect are the same as those of the method-type solution provided in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0059] Figure 1 A flow chart of a fingerprint extraction method for an anti-single event latch-up process provided by the present invention;

[0060] Figure 2 This is a structural diagram of a fingerprint extraction device for a single-event latch-up resistance process provided by the present invention;

[0061] Figure 3 This is a structural diagram of a fingerprint extraction device that is resistant to single-particle latching technology provided by the present invention. DETAILED DESCRIPTION

[0062] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0063] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0064] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0065] First, the abbreviations, English and key term definitions used in the embodiments of this specification are explained:

[0066] CMOS, Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor.

[0067] SCR, Silicon controlled rectifier, thyristor structure.

[0068] SEL, single event latch-up, single event latch-up.

[0069] BJT, bipolar junction transistor, bipolar junction transistor.

[0070] LET, Linear Energy Transfer, linear energy transfer of particles.

[0071] In response to the problems existing in the prior art, the present invention proposes a brand-new solution - the concept of 'anti-single-event latch-up (SEL) process fingerprint'. By deeply studying the homology theory between single-event latch-up and electrical latch-up, a complete anti-SEL process fingerprint extraction technology system is established. The core of the present invention is to extract key characteristic information reflecting the anti-latch-up capability of the device from its production process parameters, material properties and circuit structure to form a unique process fingerprint. Specifically, in CMOS integrated circuits, there is a silicon controlled rectifier (SCR) structure composed of two parasitic bipolar transistors between adjacent N and P wells. When high-energy charged particles bombard the active area of ​​the chip, a large number of electron-hole pairs will be ionized along their incident path. Under the action of the electric field, the holes are collected by the P-well contact and the NMOS source, while the electrons are collected by the N-well contact and the PMOS source. The directional movement of carriers generates a current, causing the parasitic transistor in the SCR structure to conduct. Due to the positive feedback characteristic, the internal current will continue to increase, causing a disturbance in the well potential and turning on the adjacent SCR structure, leading to single-event latch-up in the circuit, resulting in functional failure and even burnout of the chip. Because the physical quantities affecting single-event latch-up and electrical latch-up are the same, the characteristics extracted from electrical latch-up can be used as the process fingerprint for anti-single-event latch-up. The extracted process fingerprint characteristics are used as input parameters to build a high-precision model that incorporates multiple physical quantity coupling. This model can accurately predict the probability of single-event latch-up in devices exposed to space radiation environments and identify single-event latch-up vulnerabilities in chips, providing an important scientific basis for device design optimization and radiation hardening.

[0072] The introduction of a single-event latch-up (SEL)-resistant process fingerprint (PFI) provides a novel approach for studying, predicting, and improving spacecraft radiation hardening capabilities. Based on the characteristic parameters of the SEL-resistant PFI, a more accurate radiation hardening performance prediction model can be constructed. Currently, ground-based radiation experiments often struggle to fully replicate the complex radiation environment encountered in orbit due to limitations in experimental equipment capabilities and costs. Combining PFI with simulation modeling can address this shortcoming.

[0073] In order to systematically extract the anti-single event latch-up (SEL) process fingerprint, the technical solution provided by the present invention is divided into several key steps to ensure that the key parameters affecting SEL sensitivity are identified and optimized during chip design and manufacturing. Through the following steps, the impact of process parameters can be comprehensively analyzed and identified. Next, the solution steps provided in the embodiments of this specification are described in detail with reference to the accompanying drawings:

[0074] like Figure 1 As shown, the present invention provides a method for extracting fingerprints from a single-event latch-up resistance process, which may include the following steps:

[0075] Step 110: Electrical latch-up testing identifies sensitive areas and locates critical parasitic BJT structures.

[0076] Electrical latch-up testing is a method of evaluating and analyzing semiconductor devices such as integrated circuits. It is mainly used to determine whether the device will induce latch-up effects under different operating conditions, and to detect possible weak links and potential risk points.

[0077] In integrated circuits, certain areas are more susceptible to latch-up due to factors such as layout design and manufacturing processes. These areas are known as sensitive regions. Electrical latch-up testing identifies these sensitive areas by monitoring device parameters such as current changes and voltage response during testing, combined with analytical tools and methods.

[0078] In CMOS processes, the structure and layout of PMOS and NMOS transistors lead to the formation of parasitic PNP and NPN bipolar junction transistors (BJTs). For example, the source region, substrate, and N-well of a PMOS transistor can form a PNP parasitic transistor, while the source region, substrate, and N-well of an NMOS transistor can form an NPN parasitic transistor. These two parasitic transistors are coupled to form a silicon-controlled rectifier (SCR) structure, which is a key factor in causing latch-up.

[0079] After identifying the sensitive areas, further detailed circuit analysis, physical analysis, and other methods, combined with layout information and test results, are needed to accurately locate these critical parasitic BJT structures. For example, when latch-up is detected in a sensitive area, the layout design of that area can be carefully examined to identify the parts that meet the characteristics of the parasitic BJT structure, such as the location of each electrode of the PNP and NPN transistors, the base width, and the size of the collector and emitter regions.

[0080] Specifically, in step 110 , the SEL-sensitive regions in the chip can be identified and specific parasitic PNPN structures can be located by combining electrical latch-up testing with microscopic measurement (eg, FIB, TEM, SEM) and chemical analysis (eg, SIMS).

[0081] Step 120: Establish a TCAD model of the key parasitic BJT structure.

[0082] The geometric modeling tools in TCAD software can be used to construct the three-dimensional geometry of the parasitic BJT, including the shape, size, and distance between the emitter, base, and collector regions. Specifically, during implementation of step 120, a high-precision TCAD model of the parasitic PNPN / BJT structure can be established to characterize the device's electrical latch-up behavior under different process conditions. Based on the TCAD model, the effects of different process parameters on SEL sensitivity are simulated and analyzed, and the key parameter ranges are determined by fitting the SEL trigger conditions.

[0083] Step 130: Based on the TCAD model, by adjusting and biasing different process parameters, SEL simulation and electrical latch simulation are performed to obtain simulation results.

[0084] The SEL (single event latch-up) effect occurs when high-energy particles in the space environment strike a CMOS device, potentially causing a parasitic bipolar junction transistor (BJT) to conduct, creating a low-impedance path from power to ground, leading to device malfunction or even permanent damage. The primary purpose of SEL simulation is to investigate the mechanism, sensitive areas, and influencing factors of this effect. Electrical latch-up occurs when, during normal operation of a CMOS integrated circuit, external interference signals (such as power supply noise, ground noise, etc.) or internal factors (such as the positive feedback effect of a parasitic BJT) cause a parasitic silicon-controlled rectifier (SCR) structure to conduct, creating a high-current short circuit. The goal of electrical latch-up simulation is to predict the likelihood of electrical latch-up in a device under various operating conditions, analyze the key factors, and provide guidance for implementing effective protective measures.

[0085] Step 140: Based on the simulation results, preliminarily determine the SEL process fingerprint feature quantity and parameter influence weight.

[0086] The SEL process fingerprint features were initially extracted, and the impact of each feature on SEL performance was quantified by analyzing simulation data. Electrical latch-up thresholds were obtained for different process parameter combinations through electrical latch-up testing to verify the accuracy of the simulation results.

[0087] Step 150: Perform sensitivity analysis by combining the Morris method and the Sobol method to determine the global impact weight of each SEL process fingerprint feature quantity and optimize the anti-SEL process parameters.

[0088] The Morris method is a global sensitivity analysis method based on local variation. By changing one parameter while keeping the others constant, repeating this process multiple times, and calculating the parameter variation, the degree of influence of that parameter on the model output is determined. The Morris method designs a series of sample points, each corresponding to a set of parameter values, and then calculates the mean absolute variation and coefficient of variation for each parameter. The mean absolute variation reflects the overall impact of the parameter on the output, while the coefficient of variation indicates the degree of nonlinearity of the parameter's impact on the output. A large mean absolute variation indicates a significant impact on the model output; a large coefficient of variation indicates a nonlinear effect of the parameter on the model output.

[0089] The Sobol method is a global sensitivity analysis method based on variance decomposition. It decomposes the variance of the model output into the variance contributions of each input parameter, both individually and as a function of their interactions. This method then calculates each parameter's first-order sensitivity index (indicating the parameter's individual contribution to the output) and its total sensitivity index (indicating the total contribution of the parameter, both individually and through interactions with other parameters). A higher first-order sensitivity index indicates a more independent and significant impact of that parameter on the output; a higher total sensitivity index indicates a more important parameter in the model and the likelihood of strong interactions with other parameters.

[0090] The present invention combines the Morris method with the Sobol method and applies it to the weight analysis of anti-SEL process parameters.

[0091] Figure 1 The method in this paper identifies sensitive areas and locates key parasitic BJT structures through electrical latch-up testing; establishes a TCAD model of the key parasitic BJT structure; based on the TCAD model, performs SEL simulation and electrical latch-up simulation by adjusting and biasing different process parameters to obtain simulation results; based on the simulation results, preliminarily determines the SEL process fingerprint characteristics and parameter influence weights; combines the Morris method and the Sobol method to perform sensitivity analysis, determine the global influence weights of each SEL process fingerprint characteristic, and optimize the anti-SEL process parameters. Key characteristic information reflecting the device's anti-latch-up capability is extracted from the device's production process parameters, material properties, and circuit structure to form a unique process fingerprint identifier. Based on the characteristic parameters of the anti-single-particle latch-up process fingerprint, a more accurate radiation resistance performance prediction model can be constructed. Based on the extracted SEL process fingerprint characteristics, ground experiments, and simulations, a model can be established to more accurately predict the device's behavior in the orbital radiation environment.

[0092] based on Figure 1 The present specification also provides some specific implementation methods of the method, which are described below.

[0093] Figure 1In step 110, when the electrical latch test identifies sensitive areas, the electrical latch test procedure is first used to identify areas in the chip that are sensitive to SEL. This process usually involves applying electrical stress under specific conditions to observe the fault responses of different areas of the chip. By monitoring current and voltage fluctuations, sensitive areas that may cause SEL can be located. The specific positioning method is: Focused ion beam (FIB) slicing technology: FIB technology is used to cut the chip with micron-level precision to prepare a sample cross-section that can show the internal structure. In this process, FIB uses an ion beam to accurately remove material, exposing areas of interest, especially parts that may become SEL sensitive areas. This technology can be used not only for material removal, but also for material deposition, thereby building the required structure on the sample.

[0094] Microscope observation: Scanning electron microscope (SEM): Use SEM to observe the FIB-cut samples to obtain high-resolution surface morphology images. SEM can provide detailed information on the surface structure and help identify microscopic features and possible defects on the sample surface.

[0095] Transmission Electron Microscopy (TEM): TEM is used to analyze samples at higher resolution to observe internal structures and material properties. By penetrating the sample with an electron beam, TEM can clearly reveal the crystal structure and interface characteristics within the sample, providing a direct basis for identifying potentially sensitive areas.

[0096] Trap area measurement: The distribution and shape of the traps are analyzed by a mass spectrometer to determine the mass-to-charge ratio of these ions, thereby obtaining chemical information about the sample surface. This analysis helps quantify the content and distribution of various elements in the structure.

[0097] In step 120, when establishing the TCAD model of the critical parasitic BJT structure, after identifying the sensitive areas, a technical computer-aided design (TCAD) tool can be used to establish the corresponding parasitic bipolar junction transistor structure model. The TCAD model simulates the electrical latch-up behavior of the semiconductor device. This modeling process requires the realistic reproduction of the electrical model and parameters, geometric structure, and boundary conditions to ensure the reliability and validity of the simulation results.

[0098] In step 130, SEL and electrical latch-up simulations are performed by adjusting and shifting various process parameters based on the established model. This involves systematically varying process parameters such as doping concentration, well depth, and distance to the active area to observe how these parameters affect the SEL triggering conditions and electrical latch-up behavior. During this process, high-precision numerical simulations are used to identify process parameters that may significantly affect SEL sensitivity.

[0099] In step 140, the SEL process fingerprint characteristics and their influence weights are initially obtained. Based on the simulation results, the SEL process fingerprint characteristics can be preliminarily identified and quantified. This step not only reveals which parameters have a significant impact on SEL characteristics but also provides a preliminary assessment of the relative influence weights of these parameters. This information is crucial for subsequent optimization and control of process conditions.

[0100] In step 150, detailed analysis and evaluation of the anti-SEL process fingerprint can be performed using the Morris method, which further analyzes the initially obtained SEL process fingerprint features. The features are divided into discrete networks, and multiple eigenvalue sampling points are randomly generated. A fixed-step perturbation is applied to each sampling point. Through TCAD simulation, the rate of change of the latch-up threshold caused by the perturbation is calculated and recorded as the single-step effect. After multiple simulations, the mean and standard deviation of the single-step effect of each feature of the anti-SEL process fingerprint are calculated to distinguish significantly influencing parameters, parameters with nonlinear or interactive effects, and parameters with less significant impact.

[0101] A more refined global sensitivity analysis is performed using the Sobol method. Based on variance decomposition, the first-order sensitivity index and total sensitivity index of each input parameter are calculated, and the process fingerprint features are ranked by their magnitude. This process aims to clarify the influence weight of each feature, thereby optimizing process parameters to improve the chip's immunity to SEL. Through these steps, a systematic framework is established for extracting and optimizing the SEL resistance process fingerprint, ensuring the evaluation of chip SEL thresholds in practical applications.

[0102] Specifically, the Morris method randomly generates eigenvalue sampling points, applies a fixed-step perturbation to each sampling point, and statistically calculates the SEL threshold change rate caused by the perturbation to screen out parameters with significant influence.

[0103] Sobol method: Based on variance decomposition, the first-order sensitivity index and total sensitivity index of each process parameter are calculated to evaluate the nonlinear and interaction effects between parameters and further optimize the feature quantity ranking.

[0104] Furthermore, Morris's specific calculation method is as follows:

[0105] Apply a certain step-length perturbation to the i-th characteristic quantity of the j-th sampling point and calculate the single-step effect EE i,j , as shown in formula (1):

[0106]

[0107] Repeat the above perturbation operation at each sampling point and then calculate the single-step effect. The subscript j indicates that it is performed at the jth sampling point, which is equivalent to changing j from 1 to r, where r represents the number of sampling points. A series of single-step effects are obtained.

[0108] For a series of EE i,j (j=1,2,…,r) take the mean and standard deviation, as shown in formula group (2):

[0109]

[0110] Get the mean and standard deviation of the single-step effect of the i-th feature quantity, change i and execute the loop until the preset conditions are met, and get the mean and standard deviation of the single-step effect of each feature quantity;

[0111] Among them, the process fingerprint feature x=(x1,x2,...,x i ), EE i,j represents the single-step effect after the perturbation of each feature value at each sampling point, f(x) represents the model output objective function, μ i represents the mean, σ i represents the standard deviation, Δe i Indicates the step size applied.

[0112] Introduced into the Sobol method:

[0113] The process fingerprint feature is directly used as the input variable: Y = f(x) = f(x1, x2, ..., x d ). Substitute the output total variance Var(Y) into the variance contribution of the variables and their combinations, as shown in formula (3):

[0114]

[0115] The first-order sensitivity index is as shown in formula (4):

[0116]

[0117] The total sensitivity index (including interaction effects) is as follows:

[0118]

[0119] Among them, (x1,x2,...,x i ) represents the input SEL process fingerprint feature, Y is the model output objective function, Y=f(x)=f(x1,x2,...,x d ); Var(Y) represents the total variance, V i represents the variance caused by the i-th feature quantity, that is, the main effect variance of the i-th feature quantity, d represents the number of features, V ij V represents the variance caused by the i-th and j-th feature quantities, that is, the second-order interaction variance of the i-th and j-th feature quantities, 1,2,...,dIt represents the variance of all parameters acting together; Var(E[Y|x~i]) represents the variance of the mean of Y after removing the influence of the i-th feature quantity, and E[Y|x~i] represents the mean of Y after removing the influence of the i-th feature quantity.

[0120] The present invention provides a method for extracting a process fingerprint against single-event latch-up (SEL) and applies the Morris and Sobol methods for the first time to weighted analysis of SEL (anti-SEL) process parameters. The strategy for extracting SEL process feature quantities involves extracting these feature quantities through advanced characterization techniques such as FIB, TEM, and SIMS, including: material doping concentration (e.g., doping characteristics of P-type and N-type regions); well depth and injection depth; contact resistance characteristics; structural layout characteristics of the well and active regions; and concentration distribution of material components (e.g., chemical concentration distribution measured by SIMS). The present invention can also construct an SEL process fingerprint database based on multidimensional feature quantities, containing these multidimensional feature quantities and their influencing weights, to provide scientific guidance for optimizing chip radiation resistance under different manufacturing processes.

[0121] Furthermore, the present invention provides a method for extracting a process fingerprint that resists single-particle latch-up. The process fingerprint that resists single-particle latch-up can provide important technical support and scientific basis for ground prediction of spacecraft in radiation environments. In aerospace environments, devices and systems often face complex radiation threats, and chips are prone to single-particle latch-up. The process fingerprint that resists single-particle latch-up is the result of systematically extracting and quantifying key parameters in the device manufacturing process (such as doping concentration, diffusion depth, oxide layer thickness, etc.). These characteristic quantities can accurately reflect the intrinsic structural characteristics and process conditions of the device. Through sensitivity analysis methods (such as the Morris method and the Sobol method) combined with the weight evaluation of characteristic quantities, it can be determined which process parameters have a significant impact on the radiation resistance of the device, thereby providing key optimization directions for radiation-resistant design.

[0122] More importantly, based on the extracted process fingerprint characteristics, ground-based experiments and simulations can build models to more accurately predict device behavior in the orbital radiation environment. This approach effectively overcomes the inability of ground-based testing to fully replicate the space radiation environment, making the correlation between process parameters and space device performance clearer and more systematic. Therefore, process fingerprint extraction not only provides high-quality input parameters for ground-based testing and simulation modeling, but also provides strong support for improving spacecraft radiation resistance and ensuring the reliability of their on-orbit operations.

[0123] Based on the same idea, the present invention also provides a fingerprint extraction device that is resistant to single-particle latching process, such as Figure 2 As shown, the device may include:

[0124] a key parasitic BJT structure locating module 210 for identifying sensitive areas during electrical latch-up testing and locating key parasitic BJT structures;

[0125] A TCAD model building module 220 is used to build a TCAD model of the key parasitic BJT structure;

[0126] A simulation module 230 is configured to perform SEL simulation and electrical latch simulation based on the TCAD model by adjusting and biasing different process parameters to obtain simulation results;

[0127] An initial process fingerprint feature determination module 240 is used to preliminarily determine the SEL process fingerprint feature and parameter influence weights based on the simulation results;

[0128] The global impact weight determination module and the process parameter optimization module 250 are used to perform sensitivity analysis in combination with the Morris method and the Sobol method to determine the global impact weight of each of the SEL process fingerprint feature quantities and optimize the anti-SEL process parameters.

[0129] based on Figure 2 The device may further include some specific implementation units:

[0130] Optionally, the key parasitic BJT structure location module 210 may include:

[0131] a fault response acquisition unit, configured to obtain fault responses of different regions of the chip by applying electrical stress under specific conditions through an electrical latch test procedure;

[0132] The sensitive area determination unit is used to locate the sensitive areas of the chip that are sensitive to SEL by monitoring the current and voltage fluctuations in different areas of the chip.

[0133] Optionally, the TCAD model building module 220 may include:

[0134] A TCAD model building unit is used to build a TCAD model of the key parasitic BJT structure using a TCAD tool after identifying the sensitive area;

[0135] The simulation module 230 may include:

[0136] The simulation unit is used to adjust and bias different process parameters on the TCAD model of the key parasitic BJT structure, perform SEL simulation and electrical latch simulation, and obtain simulation results.

[0137] Optionally, the device may further include:

[0138] a key parameter range determination module, configured to simulate and analyze the effects of different process parameters on SEL sensitivity based on the TCAD model, and determine the key parameter range by fitting the SEL trigger conditions;

[0139] The simulation result verification module is used to obtain the electrical latch threshold under different process parameter combinations through electrical latch test and verify the simulation results.

[0140] Optionally, the global impact weight determination module and the process parameter optimization module 250 may include:

[0141] The characteristic value sampling point generating unit is used to divide the initially obtained SEL process fingerprint characteristic quantity into discrete networks by using the Morris method, and randomly generate multiple characteristic value sampling points;

[0142] The mean and standard deviation determination unit is used to apply a fixed-step perturbation to each sampling point and calculate the latch threshold change rate caused by the perturbation through TCAD simulation. After multiple simulations, the single-step effect mean and standard deviation of each SEL process fingerprint feature are determined;

[0143] a parameter determination unit, configured to distinguish significantly affecting parameters, parameters with nonlinear or interactive effects, and parameters with lesser effects based on the single-step effect means and standard deviations;

[0144] The SEL process fingerprint feature determination unit is used to calculate the first-order sensitivity index and total sensitivity index of each input parameter based on variance decomposition using the Sobol method, sort the SEL process fingerprint feature quantities in order of size, and determine the global influence weight of each SEL process fingerprint feature quantity; the SEL process fingerprint feature quantities include at least: material doping concentration, well depth and injection depth, contact resistance characteristics, structural layout characteristics of the well region and active region, and concentration distribution of material components.

[0145] Optionally, the mean and standard deviation determination unit can be used to:

[0146] Apply a certain step-length perturbation to the i-th characteristic value of the j-th sampling point and calculate the single-step effect EE i,j :

[0147]

[0148] Repeat the perturbation operation at each sampling point and then find the single-step effect. j means it is performed at the jth sampling point. Change j from 1 to r, where r represents the number of sampling points, to obtain a series of single-step effects.

[0149] For a series of EE i,j (j=1,2,…,r) take the mean and standard deviation:

[0150]

[0151] Get the mean and standard deviation of the single-step effect of the i-th feature quantity, change i and execute the loop until the preset conditions are met, and get the mean and standard deviation of the single-step effect of each feature quantity;

[0152] Among them, the process fingerprint feature x=(x1,x2,...,x i ), EE i,j represents the single-step effect after the perturbation of each feature value at each sampling point, f(x) represents the model output objective function, μ i represents the mean, σ i represents the standard deviation, Δe i Indicates the step size applied.

[0153] Optionally, the SEL process fingerprint feature determination unit may be used to:

[0154] The process fingerprint feature is directly used as the input variable:

[0155] Y=f(x)=f(x1,x2,...,x d )

[0156] The total variance of the output Var(Y) is expressed as:

[0157]

[0158] First-order sensitivity index x i Expressed as:

[0159]

[0160] Total sensitivity index Expressed as:

[0161]

[0162] Among them, (x1,x2,...,x i ) represents the input SEL process fingerprint feature, Y is the model output objective function, Y=f(x)=f(x1,x2,...,x d ); Var(Y) represents the total variance, V i represents the variance caused by the i-th feature quantity, that is, the main effect variance of the i-th feature quantity, d represents the number of features, V ij V represents the variance caused by the i-th and j-th feature quantities, that is, the second-order interaction variance of the i-th and j-th feature quantities, 1,2,...,dIt represents the variance of all parameters acting together; Var(E[Y|x~i]) represents the variance of the mean of Y after removing the influence of the i-th feature quantity, and E[Y|x~i] represents the mean of Y after removing the influence of the i-th feature quantity.

[0163] Based on the same idea, the embodiment of this specification also provides a fingerprint extraction device that is resistant to single-particle latching. Figure 3 As shown, the device includes:

[0164] A memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be run by the processor; when the processor runs the computer program, the aforementioned anti-single-particle latch process fingerprint extraction method is executed.

[0165] like Figure 3 As shown, the processor can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. There can be one or more communication interfaces. The communication interface can use any device such as a transceiver for communicating with other devices or a communication network.

[0166] like Figure 3 As shown, the terminal device may further include a communication line. The communication line may include a path for transmitting information between the components.

[0167] Optional, such as Figure 3 As shown, the terminal device may further include a memory. The memory stores a computer program executable by the processor; when the processor executes the computer program, the method provided by the embodiment of the present invention is implemented.

[0168] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application code, which is not specifically limited in the embodiment of the present invention. Figure 3 As shown, the processor may include one or more CPUs, such as Figure 3 CPU0 and CPU1 in.

[0169] In a specific implementation, as an embodiment, Figure 3 As shown, the terminal device may include multiple processors, such as Figure 3 Each of these processors can be a single-core processor or a multi-core processor.

[0170] Based on the same idea, the embodiments of this specification also provide a computer storage medium corresponding to the above embodiments. The computer storage medium stores instructions, and when the instructions are executed, the method in the above embodiments is implemented.

[0171] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the interaction between the various modules. It can be understood that, in order to realize the above functions, each module includes a hardware structure and / or software unit corresponding to the execution of each function. It should be easy for those skilled in the art to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0172] The embodiments of the present invention can be divided into functional modules according to the above-mentioned method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into a single processing module. The above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present invention is illustrative and is only a logical functional division. In actual implementation, other division methods may be used.

[0173] The processor in this specification may also function as a memory. The memory is used to store computer-executable instructions for implementing the solutions of the present invention, and the processor controls the execution of the instructions. The processor is used to execute the computer-executable instructions stored in the memory, thereby implementing the methods provided in the embodiments of the present invention.

[0174] The memory may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a communication line. The memory may also be integrated with the processor.

[0175] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0176] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor or by software instructions. The above processor may be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The methods, steps, and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in conjunction with the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor or by a combination of hardware and software modules in the decoding processor. The software modules can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in a memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0177] Although the present invention has been described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0178] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A fingerprint extraction method for resisting single event latch-up process, characterized in that: Methods include: Electrical latch-up testing identifies sensitive areas and locates critical parasitic BJT structures; Establishing a TCAD model of the key parasitic BJT structure; Based on the TCAD model, SEL simulation and electrical latch simulation are performed by adjusting and biasing different process parameters to obtain simulation results; Based on the simulation results, the SEL process fingerprint characteristics and parameter influence weights are preliminarily determined; Sensitivity analysis was performed in combination with the Morris method and the Sobol method to determine the global influence weights of the SEL process fingerprint feature quantities and optimize the anti-SEL process parameters.

2. The method for extracting fingerprints against single event latch-up according to claim 1, wherein: Electrical latch-up testing identifies sensitive areas and locates critical parasitic BJT structures, including: The electrical latch-up test procedure applies electrical stress under specific conditions to obtain the fault response of different areas of the chip; By monitoring the current and voltage fluctuations in different areas of the chip, the sensitive areas of the chip that are sensitive to SEL are located.

3. The method for extracting fingerprints against single event latch-up according to claim 1, wherein: Establish a TCAD model of the key parasitic BJT structure, including: After identifying the sensitive area, a TCAD model of the critical parasitic BJT structure is established using a TCAD tool; Based on the TCAD model, SEL simulation and electrical latch-up simulation were performed by adjusting and biasing different process parameters, and the simulation results included: On the TCAD model of the key parasitic BJT structure, different process parameters are adjusted and biased, and SEL simulation and electrical latch simulation are performed to obtain simulation results.

4. The method for extracting fingerprints against single event latch-up according to claim 1, wherein: After establishing the TCAD model of the key parasitic BJT structure, it also includes: Based on the TCAD model, the effects of different process parameters on SEL sensitivity are simulated and analyzed, and the key parameter ranges are determined by fitting the SEL trigger conditions; Before performing sensitivity analysis by combining the Morris method and the Sobol method to determine the global influence weight of each SEL process fingerprint feature and optimizing the anti-SEL process parameters, the following steps are also included: Through the electrical latch-up test, the electrical latch-up threshold under different process parameter combinations is obtained to verify the simulation results.

5. The method for extracting fingerprints against single event latch-up according to claim 1, wherein: Sensitivity analysis is performed by combining the Morris method and the Sobol method to determine the global influence weight of each SEL process fingerprint feature and optimize the anti-SEL process parameters, including: The Morris method is used to divide the initially obtained SEL process fingerprint characteristics into discrete networks, and multiple characteristic value sampling points are randomly generated. A fixed-step perturbation is applied to each sampling point, and the latch-up threshold change rate caused by the perturbation is calculated through TCAD simulation. After multiple simulations, the mean and standard deviation of the single-step effect of each SEL process fingerprint characteristic are determined. and distinguishing between parameters with significant effects, parameters with nonlinear or interactive effects, and parameters with minor effects based on the single-step effect means and standard deviations; The Sobol method is used to calculate the first-order sensitivity index and total sensitivity index of each input parameter based on variance decomposition. The SEL process fingerprint feature quantities are sorted in order of size to determine the global influence weight of each SEL process fingerprint feature quantity. The SEL process fingerprint feature quantities include at least: material doping concentration, well depth and injection depth, contact resistance characteristics, structural layout characteristics of the well region and active region, and concentration distribution of material components.

6. The method for extracting fingerprints against single event latch-up according to claim 5, wherein: A fixed-step perturbation is applied to each sampling point. The latch-up threshold change rate caused by the perturbation is calculated through TCAD simulation. After multiple simulations, the mean and standard deviation of the single-step effect of each SEL process fingerprint characteristic are determined, including: Apply a certain step-length perturbation to the i-th characteristic value of the j-th sampling point and calculate the single-step effect EE i,j : Repeat the perturbation operation at each sampling point and then find the single-step effect. j means it is performed at the jth sampling point. Change j from 1 to r, where r represents the number of sampling points, to obtain a series of single-step effects. For a series of EE i,j (j=1,2,…,r) take the mean and standard deviation: Get the mean and standard deviation of the single-step effect of the i-th feature quantity, change i and execute the loop until the preset conditions are met, and get the mean and standard deviation of the single-step effect of each feature quantity; Among them, the process fingerprint feature x=(x1,x2,...,x i ), EE i,j represents the single-step effect after the perturbation of each feature value at each sampling point, f(x) represents the model output objective function, μ i represents the mean, σ i represents the standard deviation, Δe i Indicates the step size applied.

7. The method for extracting fingerprints against single event latch-up according to claim 6, wherein: The Sobol method is used to calculate the first-order sensitivity index and total sensitivity index of each input parameter based on variance decomposition. The SEL process fingerprint features are sorted in order of size to determine the global influence weight of each SEL process fingerprint feature, including: The process fingerprint feature is directly used as the input variable: Y=f(x)=f(x1,x2,…,x d ) The total variance of the output Var(Y) is expressed as: First-order sensitivity index S i Expressed as: Total sensitivity index Expressed as: Among them, (x1,x2,...,x i ) represents the input SEL process fingerprint feature, Y is the model output objective function, Y=f(x)=f(x1,x2,...,x d ); Var(Y) represents the total variance, V i represents the variance caused by the i-th feature quantity, that is, the main effect variance of the i-th feature quantity, d represents the number of features, V ij V represents the variance caused by the i-th and j-th feature quantities, that is, the second-order interaction variance of the i-th and j-th feature quantities, 1,2,...,d It represents the variance of all parameters acting together; Var(E[Y|x~i]) represents the variance of the mean of Y after removing the influence of the i-th feature quantity, and E[Y|x~i] represents the mean of Y after removing the influence of the i-th feature quantity.

8. A fingerprint extraction device for resisting single event latch-up process, characterized in that: The device includes: Key parasitic BJT structure positioning module, used for electrical latch-up testing to identify sensitive areas and locate key parasitic BJT structures; A TCAD model building module, used to build a TCAD model of the key parasitic BJT structure; A simulation module, configured to perform SEL simulation and electrical latch simulation based on the TCAD model by adjusting and biasing different process parameters to obtain simulation results; An initial process fingerprint feature determination module, configured to preliminarily determine the SEL process fingerprint feature and parameter influence weights based on the simulation results; The global impact weight determination module and the process parameter optimization module are used to perform sensitivity analysis in combination with the Morris method and the Sobol method, determine the global impact weight of each SEL process fingerprint feature, and optimize the anti-SEL process parameters.

9. A fingerprint extraction device that resists single-particle latching process, characterized in that the device include: a memory, a processor, and a communication interface coupled to the processor; The memory stores a computer program executable by the processor; When the processor runs the computer program, it executes the anti-single event latch-up process fingerprint extraction method according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that The computer storage medium stores instructions, and when the instructions are executed by the processor, the anti-single event latch-up process fingerprint extraction method according to any one of claims 1 to 7 is implemented.

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