Numerical control crystal oscillator circuit with low noise and high stability

Abstract

The invention relates to the field of electronic circuit design, and discloses a numerical control crystal oscillator circuit with low noise and high stability. According to the circuit, a two-stage voltage regulator is adopted to suppress power supply noise, wide-range high-precision frequency regulation is realized through thick and thin capacitor array regulation, oscillation signal quality is ensured through automatic detection feedback and external programming double-loop control, and a special oscillation starting circuit is arranged to accelerate the starting process of a crystal oscillator. Meanwhile, targeted optimization is carried out on a core circuit and layout in the loop, and noise and distortion are further reduced. The digital controlled oscillator can effectively solve the problems that an existing digital controlled oscillator scheme is narrow in frequency modulation range, large in phase noise and the like, the characteristics of low noise, high stability, rapid starting and the like are achieved, an excellent frequency reference is provided for a wireless communication and high-precision timing system, and the digital controlled oscillator has remarkable practical value.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit design, and in particular to a circuit implementation technology for a high-performance digitally controlled crystal oscillator. Background Art

[0002] With the rapid development of wireless communications and high-precision electronic devices, the requirements for clock sources are increasing. On the one hand, systems require clock sources with excellent frequency stability and low phase noise to ensure communication link reliability and signal quality. On the other hand, clock sources must have a widely adjustable frequency output to accommodate different operating modes and frequency bands. Furthermore, fast startup and low power consumption are crucial for portable electronic devices.

[0003] Traditional crystal oscillator solutions struggle to simultaneously meet these multiple technical requirements. For example, while conventional crystal oscillators offer good frequency stability, their adjustment range is very limited, making them unable to keep up with the pace of modern communication systems. While voltage-controlled crystal oscillators (VCXOs) can somewhat expand the frequency adjustment range, they are highly sensitive to changes in control voltage and are easily affected by factors such as temperature. This makes adjustment accuracy and stability difficult to guarantee, and they also consume high power.

[0004] Digitally controlled crystal oscillators (DCXOs) have, to some extent, overcome the shortcomings of analog control schemes by introducing digital control mechanisms. However, existing DCXO technology still suffers from issues such as narrow frequency modulation range, high phase noise, and long startup time. This is primarily due to suboptimal circuit designs such as single-stage power supply regulation, a single LC frequency modulation network, and open-loop control. These factors collectively limit the potential for DCXO performance improvement.

[0005] Therefore, there is an urgent need for a new type of digitally controlled crystal oscillator circuit solution that can significantly reduce phase noise, accelerate startup speed, improve power supply stability, and adapt to a wide range of operating frequencies while ensuring precise frequency regulation, thereby fully meeting the needs of modern wireless communication equipment and high-performance electronic systems. Summary of the Invention

[0006] The purpose of this application is to provide a low-noise and high-stability digitally controlled crystal oscillator circuit to solve the problems raised in the above background technology.

[0007] The present application discloses a low-noise and high-stability digitally controlled crystal oscillator circuit, comprising:

[0008] A controllable reference current module includes a first-stage voltage regulator LDO1 and a current signal generating circuit Bias, wherein the input terminal of the first-stage voltage regulator is connected to a reference voltage Vref, the output terminal outputs a pre-stabilized voltage avdd, and the power terminal is connected to a power supply voltage Vin; the first input terminal of the current signal generating circuit is connected to the reference voltage, the second input terminal is connected to a digital feedback signal Df_Bias, the output terminal is connected to a crystal oscillator current control terminal XTAL_CF, and the power terminal is connected to the pre-stabilized voltage;

[0009] An oscillator module, whose input terminal is connected to the enable signal En, the output terminal is connected to the crystal oscillator input terminal XTAL_I, and the power terminal is connected to the pre-stabilized voltage;

[0010] An oscillator core module, whose input terminal is connected to the crystal oscillator input terminal, output terminal is connected to the crystal oscillator output terminal XTAL_O, and power terminal is connected to the crystal oscillator current control terminal;

[0011] An output signal driving module includes a second-stage voltage regulator LDO2, a first-stage output driving circuit Buffer1, and a second-stage output driving circuit Buffer2, wherein the input terminal of the second-stage voltage regulator is connected to the reference voltage, the output terminal outputs the driving voltage avdd_driver, and the power terminal is connected to the pre-stabilized voltage; the input terminal of the first-stage output driving circuit is connected to the crystal oscillator output terminal, the output terminal outputs the intermediate driving signal vo1, the first power terminal is connected to the crystal oscillator current control terminal, and the second power terminal is connected to the driving voltage; the input terminal of the second-stage output driving circuit is connected to the intermediate driving signal, the output terminal outputs the oscillator output signal OSC, and the power terminal is connected to the driving voltage;

[0012] A signal detection feedback module has an input terminal connected to the crystal oscillator input terminal and an output terminal connected to the digital feedback signal.

[0013] In a preferred embodiment, it also includes:

[0014] a first voltage-stabilizing capacitor CL1 , a positive terminal of which is connected to the pre-stabilized voltage, and a negative terminal of which is connected to the ground;

[0015] A second voltage-stabilizing capacitor CL2, with a positive terminal connected to the crystal oscillator control terminal and a negative terminal connected to the ground;

[0016] The third voltage-stabilizing capacitor CL3 has a positive terminal connected to the driving voltage and a negative terminal connected to the ground.

[0017] In a preferred embodiment, the current signal generating circuit includes: an operational amplifier amp, a first MOS transistor M0, a second MOS transistor M1, a third MOS transistor M2, and an adjustable resistor R0;

[0018] Wherein: the non-inverting input terminal of the operational amplifier is connected to the reference voltage, the inverting input terminal is connected to the feedback signal vfb_amp, the output terminal is connected to the first control node vg0, and the power supply terminal is connected to the pre-stabilized voltage; the gate of the first MOS transistor is connected to the first control node, the source is connected to the feedback signal, and the drain is connected to the second control node vbp; the source of the second MOS transistor is connected to the pre-stabilized voltage, the gate is connected to its drain and to the second control node; the source of the third MOS transistor is connected to the pre-stabilized voltage, the gate is connected to the second control node, and the drain is connected to the crystal oscillator current control terminal; the positive terminal of the adjustable resistor is connected to the feedback signal, and the negative terminal is grounded.

[0019] In a preferred embodiment, the oscillation module includes: a capacitor discharge circuit, a ring oscillator, and a tri-state gate;

[0020] Among them, the input end of the capacitor discharge circuit is connected to the enable signal, the first output end vct_clk is connected to the input end of the ring oscillator, and the second output end En_st is connected to the control end of the three-state gate; the output end vct_st of the ring oscillator is connected to the input end of the three-state gate; the output end of the three-state gate is connected to the crystal oscillator input end XTAL_I.

[0021] In a preferred embodiment, the oscillation core module includes: a resonator Xtal, a fourth MOS transistor M3, a fifth MOS transistor M4, and a feedback resistor Rf;

[0022] Wherein: the first end of the resonator is connected to the crystal oscillator input end, and the second end is connected to the crystal oscillator output end; the gate of the fourth MOS transistor is connected to the crystal oscillator input end, the source is connected to the crystal oscillator control end, and the drain is connected to the crystal oscillator output end; the gate of the fifth MOS transistor is connected to the crystal oscillator input end, the source is grounded, and the drain is connected to the crystal oscillator output end; one end of the feedback resistor is connected to the crystal oscillator input end, and the other end is connected to the crystal oscillator output end.

[0023] In a preferred embodiment, it also includes:

[0024] A first load capacitor C1, a positive terminal or a negative terminal of which is connected to the crystal oscillator input terminal, and a negative terminal or a positive terminal of which is grounded;

[0025] The second load capacitor C2 has a positive terminal or a negative terminal connected to the crystal oscillator output terminal, and a negative terminal or a positive terminal grounded.

[0026] In a preferred embodiment, the first load capacitor and the second load capacitor both include: a unit coarse adjustment capacitor array CFA, and a unit fine adjustment capacitor array FFA;

[0027] Wherein: the port P of the unit coarse tuning capacitor array is connected to the port P of the unit fine tuning capacitor array, and the port M of the unit coarse tuning capacitor array is connected to the port M of the unit fine tuning capacitor array; the unit coarse tuning capacitor array includes unit coarse tuning capacitor units controlled by n-bit binary coding, forming 2^n different capacitor combinations, each unit coarse tuning capacitor unit includes a unit coarse tuning capacitor Cc and a unit coarse tuning MOS switch M_C, and the unit coarse tuning MOS switch is controlled by a corresponding coarse tuning control signal ct_c; the unit fine tuning capacitor array includes unit fine tuning capacitor units controlled by m-bit binary coding, forming 2^m different capacitor combinations, each unit fine tuning capacitor unit includes a unit fine tuning capacitor Cf and a unit fine tuning MOS switch M_F, and the unit fine tuning MOS switch is controlled by a corresponding fine tuning control signal ct_f; wherein the capacitance value of the unit fine tuning capacitor unit is smaller than the capacitance value of the unit coarse tuning capacitor unit, and is used to achieve a combination of wide range coarse tuning and precise fine tuning.

[0028] In a preferred embodiment, the fifth MOS transistor includes: a fixed amplifier transistor M4_0, a first controllable amplifier transistor M4_1, a second controllable amplifier transistor M4_2, a first connecting switch M_S1, a second connecting switch M_S2, a first pull-down switch M_S3, and a second pull-down switch M_S4;

[0029] Wherein: the gate of the fixed amplifier tube is connected to the crystal oscillator input end, the source is grounded, and the drain is connected to the crystal oscillator output end; the source of the first controllable amplifier tube and the second controllable amplifier tube are both grounded, and the drain is both connected to the crystal oscillator output end; one end of the first connecting switch is connected to the crystal oscillator input end, and the other end is connected to the gate of the first controllable amplifier tube; one end of the second connecting switch is connected to the crystal oscillator input end, and the other end is connected to the gate of the second controllable amplifier tube; one end of the first pull-down switch is connected to the gate of the first controllable amplifier tube, and the other end is grounded; one end of the second pull-down switch is connected to the gate of the second controllable amplifier tube, and the other end is grounded.

[0030] In a preferred embodiment, the first-stage output driving circuit includes: a sixth MOS transistor M5, a seventh MOS transistor M6, a driver Buffer1_0, and a level converter lv1;

[0031] Wherein: the gates of the sixth MOS transistor and the seventh MOS transistor are connected and connected to the crystal oscillator input terminal, and their drains are connected to form a first intermediate node v1 and connected to the input terminal of the driver; the source of the sixth MOS transistor is connected to the crystal oscillator control terminal and to the positive terminal of the second voltage-stabilizing capacitor; the source of the seventh MOS transistor is grounded; the power supply terminal of the driver is connected to the crystal oscillator control terminal, and the output terminal is connected to the second intermediate node v2 and to the input terminal of the level converter; the first power supply terminal of the level converter is connected to the crystal oscillator control terminal, the second power supply terminal is connected to the drive voltage, and the output terminal outputs the intermediate drive signal.

[0032] This application utilizes a two-stage voltage regulator architecture. The first-stage voltage regulator, LDO1, generates a pre-stabilized voltage avdd, while the second-stage voltage regulator, LDO2, further generates a low-noise drive voltage avdd_driver. This effectively improves the power supply rejection performance of the output signal. For frequency regulation, this application utilizes a combination of a coarse-tuning capacitor array (CFA) and a fine-tuning capacitor array (FFA). The CFA uses an n-bit encoding signal to adjust the load capacitance in 2^n steps, enabling wide-range frequency regulation. The FFA uses an m-bit encoding signal to adjust the load capacitance in 2^m steps, achieving high-precision frequency fine-tuning. This combination balances both the width and accuracy of frequency regulation. For noise control, this application addresses both circuit and layout issues. Programmable op amp control is used to mitigate excess noise introduced by process variations, and the load capacitor layout is isolated to reduce coupling noise from the substrate and surrounding areas. Oscillation signal quality is ensured through both automatic detection feedback and external control. The signal detection and feedback module samples the signal at the crystal oscillator input terminal XTAL_I. After internal processing, it generates a sampled feedback signal D_fb, which is superimposed with the external control signal D_in containing other variables to generate a digital feedback signal Df_Bias to adjust the drive current. The start-up module ensures fast and stable startup of the oscillator. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal oscillator's resonant frequency to help the crystal oscillator start. The capacitor discharge circuit periodically shuts off the start-up signal, allowing the crystal oscillator to enter a steady state.

[0033] The start-up module ensures a fast and stable startup of the oscillator. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal's resonant frequency to help the crystal start. The capacitor discharge circuit periodically shuts off the start-up signal, allowing the crystal to enter a steady state.

[0034] In summary, this application achieves multiple technical goals such as low noise, high stability, wide adjustment range and fast startup through an innovative circuit architecture, providing an effective solution for high-performance clock sources.

[0035] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be considered as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a system block diagram of a low-noise, high-stability digitally controlled crystal oscillator circuit according to an embodiment of the present application, illustrating the connection relationship between various functional modules.

[0037] Figure 2 This is a circuit schematic diagram of the core module of a low-noise, high-stability digitally controlled crystal oscillator circuit according to an embodiment of the present application, which specifically shows the internal circuit structure of the controllable reference current module, the oscillation core module and the output signal drive module.

[0038] Figure 3 This is a circuit schematic diagram of an oscillation module in a low-noise, high-stability digitally controlled crystal oscillator circuit according to an embodiment of the present application, showing the connection method of a capacitor discharge circuit, a ring oscillator, and a tri-state gate.

[0039] Figure 4 This is a circuit schematic diagram of a programmable capacitor array used as a load capacitor in a low-noise, high-stability digitally controlled crystal oscillator circuit according to an embodiment of the present application, and the internal structures of a unit coarse-tuning capacitor array and a unit fine-tuning capacitor array are respectively given.

[0040] Figure 5 This is a schematic diagram of the layout design of the load capacitor in the low-noise and high-stability digitally controlled crystal oscillator circuit according to the embodiment of the present application, showing noise reduction measures such as multi-layer metal interlacing, upper and lower shielding layers, and surround connections.

[0041] Figure 6This is a schematic diagram of the controllable MOS tube structure of the inverting amplifier in the low-noise and high-stability digitally controlled crystal oscillator circuit according to an embodiment of the present application, and provides the connection method of the fixed tube, the controllable tube and the control switch.

[0042] In the specification of this application, in order to make the article more clear and concise, some technical features are represented by English letter codes. It should be clear that the technical features represented by letter codes in this application are exactly the same as the technical features represented by the corresponding Chinese names plus letter codes. For example, "avdd" and "pre-stabilized voltage avdd" refer to the same technical feature, "XTAL_CF" and "crystal oscillator control terminal XTAL_CF" refer to the same technical feature, and other similar technical features represented by English letter codes are equivalent to the technical features represented by their corresponding Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented by letter codes only as the same as the technical features represented by their corresponding Chinese names plus letter codes. The technical features with English letter codes involved include but are not limited to:

[0043] Voltage and Signal:

[0044] Pre-stabilized voltage avdd;

[0045] Reference voltage Vref;

[0046] Crystal oscillator control terminal XTAL_CF;

[0047] Power supply voltage Vin;

[0048] Digital feedback signal Df_Bias;

[0049] Intermediate driving signal vo1;

[0050] Oscillator output signal OSC;

[0051] Crystal oscillator input terminal XTAL_I;

[0052] Crystal oscillator output terminal XTAL_O;

[0053] Driving voltage avdd_driver;

[0054] First control node vg0;

[0055] The second control node vbp;

[0056] Feedback signal vfb_amp;

[0057] Clock control signal vct_clk;

[0058] Enable control signal En_st;

[0059] Oscillation signal vct_st;

[0060] Reference current I_ref;

[0061] Drive current I_core;

[0062] Enable signal En;

[0063] Coarse control signal ct_c;

[0064] Fine-tuning control signal ct_f;

[0065] Controllable transistor gate voltages vg4_1 and vg4_2; pull-up control signals sela_0 and sela_1; pull-down control signals selb_0 and selb_1; first intermediate node v1;

[0066] The second intermediate node v2;

[0067] Functional modules and devices:

[0068] The first stage voltage regulator LDO1;

[0069] The second stage voltage regulator LDO2;

[0070] Current signal generating circuit Bias;

[0071] Operational amplifier amp;

[0072] Oscillation circuit Start;

[0073] Oscillation core circuit Core;

[0074] First-stage output drive circuit Buffer1; second-stage output drive circuit Buffer2; first MOS transistor M0;

[0075] The second MOS tube M1;

[0076] The third MOS tube M2;

[0077] Fourth MOS tube M3;

[0078] The fifth MOS tube M4;

[0079] Sixth MOS tube M5;

[0080] The seventh MOS tube M6;

[0081] Adjustable resistor R0;

[0082] Feedback resistor Rf;

[0083] Resonator Xtal;

[0084] A first voltage stabilizing capacitor CL1;

[0085] A second voltage stabilizing capacitor CL2;

[0086] The third voltage stabilizing capacitor CL3;

[0087] Unit coarse capacitance array CFA;

[0088] Unit fine tuning capacitor array FFA;

[0089] Signal detection feedback module Det&FB;

[0090] Fixed amplifier tube M4_0;

[0091] Controllable amplifier tubes M4_1 and M4_2;

[0092] Connect switches M_S1 and M_S2;

[0093] Pull-down switches M_S3 and M_S4;

[0094] Unit coarse tuning capacitor Cc;

[0095] Unit coarse adjustment MOS switch M_C;

[0096] Unit fine-tuning capacitor Cf;

[0097] Unit fine-tuning MOS switch M_F;

[0098] driverBuffer1_0;

[0099] Level converter lvl;

[0100] Through hole CT;

[0101] First connecting hole V1;

[0102] Second connecting hole V2. DETAILED DESCRIPTION

[0103] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0104] Description of some concepts:

[0105] Digitally controlled crystal oscillator (DCXO): A crystal oscillator whose output signal is directly regulated via a digital interface. Compared to traditional voltage-controlled crystal oscillators (VCXOs), DCXOs offer stronger interference immunity and more convenient digital control.

[0106] Pre-regulated voltage (avdd): An intermediate voltage generated by the first-stage voltage regulator (LDO1). Its function is to provide a preliminary stable operating power supply for each module in the system, reduce power supply noise, and ensure safe and stable operation of other circuits.

[0107] Drive voltage (avdd_driver): The second-stage voltage regulator (LDO2) outputs a high-quality drive voltage. Its function is to provide the output drive circuit with strong driving capability and low-noise, highly stable power supply, minimizing the impact of power supply noise on the output signal.

[0108] Coarse-tuning Capacitor Array (CFA): A switched capacitor array controlled by an n-bit binary code that provides large step sizes for load capacitance changes. Its purpose is to achieve wide-range adjustment of the oscillator output frequency.

[0109] Fine-tuning Capacitor Array (FFA): A switched capacitor array controlled by an m-bit binary code, providing small step sizes for load capacitance changes. Its purpose is to fine-tune the oscillator's output frequency in addition to coarse tuning.

[0110] Crystal Oscillator Control Terminal (XTAL_CF): This terminal is a key node connected to the output of the controllable current source. Its voltage level directly determines the excitation strength and oscillation amplitude of the crystal oscillator, making it one of the core control points of the entire oscillator.

[0111] Digital feedback signal (Df_Bias): This is a digital control signal generated by the signal detection and feedback module, extracting the crystal oscillator signal. It automatically adjusts the crystal oscillator's excitation current and stabilizes the crystal's oscillation amplitude.

[0112] The following is a summary of some of the innovative features of this application:

[0113] In summary, this application addresses the technical challenges of wireless communications and high-precision electronic devices requiring high-stability and a wide frequency modulation range in clock sources. Through in-depth technical research, we propose a novel digitally controlled crystal oscillator circuit architecture. This architecture cleverly integrates a number of innovative designs, including a controllable current source, a starting circuit, a coarse-fine combined capacitor array, and dual-loop feedback control. Through close collaboration between various functional modules, it achieves simultaneous optimization and improvement of multiple key performance indicators.

[0114] Specifically, in terms of noise reduction, this application uniquely adopts a cascade structure of two-stage voltage regulators. The first-stage voltage regulator LDO1 generates a pre-stabilized voltage avdd, which is then further reduced by the second-stage voltage regulator LDO2 to obtain a stable, low-noise drive voltage avdd_driver. This two-stage architecture separates the internal power supply and drive voltage, providing sufficient drive capability while reducing noise introduction, significantly outperforming traditional single-stage LDO solutions. At the same time, a size-adjustable inverting amplifier is set in the crystal oscillator core circuit. By changing the transistor width, the noise introduced by process deviation is optimized, achieving a dynamic balance between noise figure, power consumption, and gain. In addition, the layout design of this application adopts a staggered layout of multi-layer metal shielding and isolation processing, which effectively reduces the impact of substrate noise on load capacitance and further improves the signal purity of the oscillator.

[0115] To improve oscillator startup speed, this application ingeniously designs a novel ring oscillator circuit using capacitor discharge timing triggering. Unlike traditional delay chain oscillator startup, this circuit utilizes a ring oscillator to generate an excitation signal close to the crystal oscillator's resonant frequency, and a timed capacitor discharge circuit controls the duration of the excitation, effectively resolving issues such as slow and unstable crystal oscillator startup. Furthermore, the clever combination of the startup circuit and a digitally controlled current source ensures a constant and sufficient drive current during startup, improving the success rate of oscillation.

[0116] To address the conflict between frequency control accuracy and adjustment range, this application creatively proposes a hierarchical frequency modulation method that combines a unit coarse adjustment capacitor array (CFA) with a unit fine adjustment capacitor array (FFA). The CFA uses binary code to switch capacitors with large step sizes, responsible for coarse frequency adjustment over a wide range; the FFA uses independent hot coding to switch capacitors with small step sizes, responsible for fine frequency calibration within a narrow range. Through a clever coding method, ultra-wide range and ultra-high precision frequency control are achieved with only a few control bits. This method far outperforms traditional single-capacitor array frequency modulation schemes and offers the advantages of digitalization and programmability.

[0117] In terms of adaptability, this application also designs a dual-loop feedback control method, consisting of a digital feedback loop and an external programming loop. The digital feedback loop automatically adjusts the output of the digitally controlled current source by sampling and comparing the crystal oscillator signal amplitude with a reference level, achieving constant amplitude control. The external programming loop allows the user or other control circuits to directly rewrite the control word of the digitally controlled current source, achieving higher-level system optimization. The synergy of the two feedback loops enhances the oscillator's adaptability to variations in process, temperature, and voltage, ensuring the stability of the oscillation signal in complex application environments.

[0118] In summary, the digitally controlled crystal oscillator circuit of this application has been meticulously designed and optimized at every level, from the system to the module to the layout. It incorporates numerous unique circuit innovations, achieving a perfect blend of key performance attributes, including low noise, high stability, wide frequency adjustment, fast startup, and adaptive compensation, with remarkable technical results. This deeply customized design is not a simple combination of known technologies, but rather, through highly targeted, specialized design, ingeniously utilizing the inherent connections between various functional modules. This demonstrates considerable creativity, significantly improving the overall performance of the digitally controlled oscillator, and providing an excellent frequency reference solution for modern high-end wireless communications and precision electronic equipment.

[0119] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0120] The first embodiment of the present application relates to a low-noise and high-stability digitally controlled crystal oscillator circuit, such as Figure 1 Shown, including:

[0121] A controllable reference current module includes a first-stage voltage regulator LDO1 and a current signal generating circuit Bias, wherein the input terminal of the first-stage voltage regulator is connected to a reference voltage Vref, the output terminal outputs a pre-stabilized voltage avdd, and the power terminal is connected to a power supply voltage Vin; the first input terminal of the current signal generating circuit is connected to the reference voltage, the second input terminal is connected to a digital feedback signal Df_Bias, the output terminal is connected to a crystal oscillator current control terminal XTAL_CF, and the power terminal is connected to the pre-stabilized voltage;

[0122] An oscillator module, whose input terminal is connected to the enable signal En, the output terminal is connected to the crystal oscillator input terminal XTAL_I, and the power terminal is connected to the pre-stabilized voltage;

[0123] An oscillator core module, whose input terminal is connected to the crystal oscillator input terminal, output terminal is connected to the crystal oscillator output terminal XTAL_O, and power terminal is connected to the crystal oscillator current control terminal;

[0124] An output signal driving module includes a second-stage voltage regulator LDO2, a first-stage output driving circuit Buffer1, and a second-stage output driving circuit Buffer2, wherein the input terminal of the second-stage voltage regulator is connected to the reference voltage, the output terminal outputs the driving voltage avdd_driver, and the power terminal is connected to the pre-stabilized voltage; the input terminal of the first-stage output driving circuit is connected to the crystal oscillator output terminal, the output terminal outputs the intermediate driving signal vo1, the first power terminal is connected to the crystal oscillator current control terminal, and the second power terminal is connected to the driving voltage; the input terminal of the second-stage output driving circuit is connected to the intermediate driving signal, the output terminal outputs the oscillator output signal OSC, and the power terminal is connected to the driving voltage;

[0125] A signal detection feedback module has an input terminal connected to the crystal oscillator input terminal and an output terminal connected to the digital feedback signal.

[0126] Optionally, also include:

[0127] a first voltage-stabilizing capacitor CL1 , a positive terminal of which is connected to the pre-stabilized voltage, and a negative terminal of which is connected to the ground;

[0128] A second voltage-stabilizing capacitor CL2, with a positive terminal connected to the crystal oscillator control terminal and a negative terminal connected to the ground;

[0129] The third voltage-stabilizing capacitor CL3 has a positive terminal connected to the driving voltage and a negative terminal connected to the ground.

[0130] Optionally, the current signal generating circuit includes: an operational amplifier amp, a first MOS transistor M0, a second MOS transistor M1, a third MOS transistor M2, and an adjustable resistor R0;

[0131] Wherein: the non-inverting input terminal of the operational amplifier is connected to the reference voltage, the inverting input terminal is connected to the feedback signal vfb_amp, the output terminal is connected to the first control node vg0, and the power supply terminal is connected to the pre-stabilized voltage; the gate of the first MOS transistor is connected to the first control node, the source is connected to the feedback signal, and the drain is connected to the second control node vbp; the source of the second MOS transistor is connected to the pre-stabilized voltage, the gate is connected to its drain and to the second control node; the source of the third MOS transistor is connected to the pre-stabilized voltage, the gate is connected to the second control node, and the drain is connected to the crystal oscillator current control terminal; the positive terminal of the adjustable resistor is connected to the feedback signal, and the negative terminal is grounded.

[0132] Optionally, the oscillation starting module includes: a capacitor discharge circuit, a ring oscillator, and a tri-state gate;

[0133] Among them, the input end of the capacitor discharge circuit is connected to the enable signal, the first output end vct_clk is connected to the input end of the ring oscillator, and the second output end En_st is connected to the control end of the three-state gate; the output end vct_st of the ring oscillator is connected to the input end of the three-state gate; the output end of the three-state gate is connected to the crystal oscillator input end XTAL_I.

[0134] Optionally, the oscillation core module includes: a resonator Xtal, a fourth MOS transistor M3, a fifth MOS transistor M4, and a feedback resistor Rf;

[0135] Wherein: the first end of the resonator is connected to the crystal oscillator input end, and the second end is connected to the crystal oscillator output end; the gate of the fourth MOS transistor is connected to the crystal oscillator input end, the source is connected to the crystal oscillator control end, and the drain is connected to the crystal oscillator output end; the gate of the fifth MOS transistor is connected to the crystal oscillator input end, the source is grounded, and the drain is connected to the crystal oscillator output end; one end of the feedback resistor is connected to the crystal oscillator input end, and the other end is connected to the crystal oscillator output end.

[0136] Optionally, also include:

[0137] A first load capacitor C1, a positive terminal or a negative terminal of which is connected to the crystal oscillator input terminal, and a negative terminal or a positive terminal of which is grounded;

[0138] The second load capacitor C2 has a positive terminal or a negative terminal connected to the crystal oscillator output terminal, and a negative terminal or a positive terminal grounded.

[0139] Optionally, the first load capacitor and the second load capacitor both include: a unit coarse tuning capacitor array CFA, and a unit fine tuning capacitor array FFA;

[0140] Wherein: the port P of the unit coarse tuning capacitor array is connected to the port P of the unit fine tuning capacitor array, and the port M of the unit coarse tuning capacitor array is connected to the port M of the unit fine tuning capacitor array; the unit coarse tuning capacitor array includes unit coarse tuning capacitor units controlled by n-bit binary coding, forming 2^n different capacitor combinations, each unit coarse tuning capacitor unit includes a unit coarse tuning capacitor Cc and a unit coarse tuning MOS switch M_C, and the unit coarse tuning MOS switch is controlled by a corresponding coarse tuning control signal ct_c; the unit fine tuning capacitor array includes unit fine tuning capacitor units controlled by m-bit binary coding, forming 2^m different capacitor combinations, each unit fine tuning capacitor unit includes a unit fine tuning capacitor Cf and a unit fine tuning MOS switch M_F, and the unit fine tuning MOS switch is controlled by a corresponding fine tuning control signal ct_f; wherein the capacitance value of the unit fine tuning capacitor unit is smaller than the capacitance value of the unit coarse tuning capacitor unit, and is used to achieve a combination of wide range coarse tuning and precise fine tuning.

[0141] Optionally, the fifth MOS transistor includes: a fixed amplifying transistor M4_0, a first controllable amplifying transistor M4_1, a second controllable amplifying transistor M4_2, a first connecting switch M_S1, a second connecting switch M_S2, a first pull-down switch M_S3, and a second pull-down switch M_S4;

[0142] Wherein: the gate of the fixed amplifier tube is connected to the crystal oscillator input end, the source is grounded, and the drain is connected to the crystal oscillator output end; the source of the first controllable amplifier tube and the second controllable amplifier tube are both grounded, and the drain is both connected to the crystal oscillator output end; one end of the first connecting switch is connected to the crystal oscillator input end, and the other end is connected to the gate of the first controllable amplifier tube; one end of the second connecting switch is connected to the crystal oscillator input end, and the other end is connected to the gate of the second controllable amplifier tube; one end of the first pull-down switch is connected to the gate of the first controllable amplifier tube, and the other end is grounded; one end of the second pull-down switch is connected to the gate of the second controllable amplifier tube, and the other end is grounded.

[0143] Optionally, the first-stage output driving circuit includes: a sixth MOS transistor M5, a seventh MOS transistor M6, a driver Buffer1_0, and a level converter lv1;

[0144] Wherein: the gates of the sixth MOS transistor and the seventh MOS transistor are connected and connected to the crystal oscillator input terminal, and their drains are connected to form a first intermediate node v1 and connected to the input terminal of the driver; the source of the sixth MOS transistor is connected to the crystal oscillator control terminal and to the positive terminal of the second voltage-stabilizing capacitor; the source of the seventh MOS transistor is grounded; the power supply terminal of the driver is connected to the crystal oscillator control terminal, and the output terminal is connected to the second intermediate node v2 and to the input terminal of the level converter; the first power supply terminal of the level converter is connected to the crystal oscillator control terminal, the second power supply terminal is connected to the drive voltage, and the output terminal outputs the intermediate drive signal.

[0145] More specifically, if Figure 1 As shown, this embodiment mainly consists of five functional modules and three voltage-stabilizing capacitors, realizing a high-quality digitally controlled crystal oscillation function.

[0146] The controllable reference current module is located in Figure 1 The upper left section includes the first-stage voltage regulator LDO1 and the current signal generation circuit Bias. The first-stage voltage regulator LDO1 uses the reference voltage Vref as its reference input and converts the power supply voltage Vin into a pre-stabilized voltage avdd. The current signal generation circuit Bias receives the reference voltage Vref and the digital feedback signal Df_Bias. Using the pre-stabilized voltage avdd as its power source, it outputs a control current to the crystal oscillator control terminal XTAL_CF.

[0147] The oscillator circuit module is located in Figure 1 The lower left section is labeled "Start." This module receives the enable signal En as an input trigger, uses the pre-stabilized voltage avdd as its power source, and outputs it to the crystal oscillator input terminal XTAL_I. The start-up module's primary function is to provide a temporary oscillation signal during the system's initial startup phase, helping the crystal oscillator quickly stabilize.

[0148] The oscillation core module is located in Figure 1 The center section, labeled "Core," consists of the resonator XTAL and its associated circuitry. Its input is connected to the crystal oscillator's input, XTAL_I; its output is connected to the crystal oscillator's output, XTAL_O; and its power supply is connected to the crystal oscillator's control terminal, XTAL_CF. This module is the core of the entire oscillator, responsible for generating a stable oscillation signal.

[0149] The output signal driver module is located at Figure 1 The upper right portion consists of the second-stage voltage regulator LDO2, the first-stage output driver circuit Buffer1, and the second-stage output driver circuit Buffer2. The second-stage voltage regulator LDO2 further adjusts the pre-regulated voltage avdd to a more stable drive voltage avdd_driver. The first-stage output driver circuit Buffer1, powered by the crystal oscillator control terminal XTAL_CF and the drive voltage avdd_driver, converts the signal at the crystal oscillator output terminal XTAL_O into the intermediate drive signal vo1. The second-stage output driver circuit Buffer2, powered by the drive voltage avdd_driver, further amplifies the intermediate drive signal vo1 into the final oscillator output signal OSC.

[0150] The signal detection feedback module is located in Figure 1 The lower middle section is labeled "Det&FB." This module monitors the signal at the crystal oscillator input terminal XTAL_I, generates a digital feedback signal Df_Bias, and outputs it to the second input terminal of the current signal generation circuit Bias, forming a closed-loop control.

[0151] The system also includes three voltage-stabilizing capacitors and two load capacitors: the first voltage-stabilizing capacitor CL1 is connected between the pre-stabilized voltage avdd and ground; the second voltage-stabilizing capacitor CL2 is connected between the crystal oscillator control terminal XTAL_CF and ground; the third voltage-stabilizing capacitor CL3 is connected between the drive voltage avdd_driver and ground; the first load capacitor C1 is connected between the crystal oscillator input terminal XTAL_I and ground; the second load capacitor C2 is connected between the crystal oscillator output terminal XTAL_O and ground.

[0152] This embodiment uses a controllable reference current source to provide the current required by the crystal oscillator and introduces auxiliary circuits such as oscillation start-up and detection feedback. Through modular design, it effectively solves technical problems such as narrow frequency modulation range and high phase noise in existing DCXO solutions, achieving the performance characteristics of fast startup, low noise and high stability. It is particularly suitable for application in wireless communications and high-precision electronic equipment.

[0153] like Figure 2 As shown, this embodiment provides the main circuit details of the digitally controlled crystal oscillator circuit system, including the detailed structures of the reference current generating circuit, the oscillation core circuit and the output driving circuit.

[0154] The reference current generation circuit is located in Figure 2 The upper left portion includes the first-stage voltage regulator LDO1 and the current signal generation circuit Bias, which consists of multiple components. The first-stage voltage regulator LDO1 converts the reference voltage Vref into a pre-stabilized voltage avdd. In the current signal generation circuit, the operational amplifier amp has its non-inverting input connected to the reference voltage Vref, its inverting input connected to the feedback signal vfb_amp, and its output connected to the first control node vg0. The gate of the first MOS transistor M0 is connected to the first control node vg0, its source connected to the feedback signal vfb_amp, and its drain connected to the second control node vbp. The second and third MOS transistors M1 and M2 form a current mirror, amplifying the reference current and outputting it to the crystal oscillator control terminal XTAL_CF. The source of the second MOS transistor M1 is connected to the pre-stabilized voltage avdd, and its gate and drain are short-circuited and connected to the second control node vbp. The source of the third MOS transistor M2 is connected to the pre-stabilized voltage avdd, its gate connected to the second control node vbp, and its drain connected to the crystal oscillator control terminal XTAL_CF. One end of the adjustable resistor R0 is connected to the feedback signal vfb_amp, and the other end is grounded. Through the action of the operational amplifier amp, the feedback signal vfb_amp is locked at the reference voltage Vref, generating a reference current on the adjustable resistor R0.

[0155] The oscillation core circuit is located in Figure 2The lower middle portion includes the resonator Xtal, the fourth MOS transistor M3, the fifth MOS transistor M4, and the feedback resistor Rf. The resonator Xtal is connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O. The fourth MOS transistor M3 has its gate connected to the crystal oscillator input terminal XTAL_I, its source connected to the crystal oscillator control terminal XTAL_CF, and its drain connected to the crystal oscillator output terminal XTAL_O. The fifth MOS transistor M4 has its gate connected to the crystal oscillator input terminal XTAL_I, its source connected to ground, and its drain connected to the crystal oscillator output terminal XTAL_O. The fourth and fifth MOS transistors M3 and M4 form an inverting amplifier, with the feedback resistor Rf connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O. The figure also shows the first load capacitor C1 and the second load capacitor C2, connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O and ground, respectively, to adjust the frequency of the crystal oscillator.

[0156] The output driver circuit is located in Figure 2 The right side includes the second-stage voltage regulator LDO2, the first-stage output driver circuit, and the second-stage output driver circuit. The second-stage voltage regulator LDO2 further adjusts the pre-regulated voltage avdd to a low-noise, stable drive voltage avdd_driver. The first-stage output driver circuit includes a sixth MOS transistor M5, a seventh MOS transistor M6, a first-stage driver Buffer1_0, and a level shifter lv1. The gate of the sixth MOS transistor M5 is connected to the crystal oscillator input terminal XTAL_I, the source is connected to the crystal oscillator control terminal XTAL_CF and the second stabilizing capacitor CL2, and the drain is connected to the first intermediate node v1. The gate of the seventh MOS transistor M6 is connected to the crystal oscillator input terminal XTAL_I, the source is grounded, and the drain is connected to the first intermediate node v1. The first intermediate node v1 is connected to the input of the first-stage driver Buffer1_0, and its output is connected to the second intermediate node v2. The input of the level shifter lv1 is connected to the second intermediate node v2, the first power supply terminal is connected to the crystal oscillator control terminal XTAL_CF, the second power supply terminal is connected to the drive voltage avdd_driver, and the output terminal outputs the intermediate drive signal vo1. The input terminal of the second-stage output driving circuit Buffer2 is connected to the intermediate driving signal vo1 , the power supply terminal is connected to the driving voltage avdd_driver , and the output terminal outputs the final oscillator output signal OSC.

[0157] exist Figure 2In the figure, you can also see the third voltage-stabilizing capacitor CL3, one end of which is connected to the driving voltage avdd_driver and the other end is grounded. It is mainly used for filtering and voltage stabilization, and further filters out the high-frequency noise in the driving voltage. One end of the second voltage-stabilizing capacitor CL2 is connected to the crystal oscillator control terminal avdd_xtal and the other end is grounded, which mainly plays a role in voltage stabilization. Further, optionally, the actual circuit also includes a first voltage-stabilizing capacitor CL1, which is connected to the pre-stabilized voltage avdd end, similar to CL3, and mainly plays the role of filtering and voltage stabilization. The load capacitors on both sides of the resonator are used to adjust the oscillation frequency of the crystal oscillator. The present embodiment adopts a two-stage voltage adjustment and two-stage output drive architecture, and sets voltage stabilization and filtering capacitors at key nodes, which effectively realizes power supply noise suppression and frequency precision control, and is the key to achieving low-noise and high-precision oscillation.

[0158] like Figure 3 As shown, this embodiment provides the detailed structure of the oscillator startup circuit module. This module is primarily used to provide an initial oscillation signal during system startup to accelerate the crystal oscillator startup process. The oscillator startup circuit consists of three main components: a capacitor discharge circuit, a ring oscillator, and a tri-state gate.

[0159] The capacitor discharge circuit receives an enable signal, En, as its input. When the enable signal, En, transitions from a low level to a high level, the capacitor discharge circuit begins discharging, generating two output signals: a discharge signal, vct_clk, and a control signal, En_st. The discharge signal, vct_clk, exhibits a waveform that gradually decreases from a high level, while the control signal, En_st, is initially high.

[0160] The ring oscillator consists of multiple inverters connected in series. Its input is connected to the discharge signal vct_clk, and its output generates an oscillation signal vct_st. When the discharge signal vct_clk is within the appropriate level range, the ring oscillator is activated and generates an oscillation signal with a frequency close to the parallel resonant frequency of the crystal.

[0161] The tri-state gate's input is connected to the oscillation signal vct_st, its control terminal is connected to the control signal En_st, and its output is connected to the crystal oscillator input terminal XTAL_I. When the control signal En_st is high, the tri-state gate is in the on state, allowing the oscillation signal vct_st to be transmitted to the crystal oscillator input terminal, providing initial oscillation excitation for the crystal oscillator.

[0162] The entire oscillator startup circuit operates as follows: When the system is powered on and the enable signal En goes high, the capacitor discharge circuit begins operating. The control signal En_st is set high, turning on the tri-state gate. Simultaneously, the discharge signal vct_clk begins to gradually decrease from a high level. During this process, the oscillation signal vct_st generated by the ring oscillator is transmitted to the crystal oscillator input through the tri-state gate, helping the crystal oscillator to quickly establish oscillation. When the capacitor discharges to a certain level and the discharge signal vct_clk drops below a certain threshold, the ring oscillator stops operating and the control signal En_st is set low, closing the tri-state gate. At this point, the crystal oscillator has established self-sustaining oscillation and no longer requires external excitation. The discharge time of the capacitor discharge circuit is designed to exceed the crystal oscillator startup time to ensure stable startup.

[0163] This oscillation circuit design effectively shortens the start-up time of the crystal oscillator and is the key to achieving the fast start-up feature of this embodiment.

[0164] like Figure 4 As shown, this embodiment provides a detailed structural design of an adjustable load capacitor, which is a key part for achieving precise frequency adjustment of a digitally controlled crystal oscillator. Figure 4 The specific implementation of the unit coarse adjustment capacitor array CFA and the unit fine adjustment capacitor array FFA inside the load capacitor C1 / C2 is demonstrated.

[0165] Load capacitors C1 / C2 have two main ports, P and M. The coarse-tuning capacitor array CFA and the fine-tuning capacitor array FFA are connected at port P and port M. Together, they form a variable capacitor network that achieves frequency adjustment through binary code control.

[0166] The unit coarse tuning capacitor array (CFA) is controlled by an n-bit binary code and can provide 2^n different capacitor combinations. The CFA contains n coarse tuning unit capacitors, labeled Cc1, Cc2, through Ccn. One end of each coarse tuning unit capacitor is connected to port P, and the other end is connected to port M through corresponding unit coarse tuning MOS switches M_C1, M_C2, ..., M_Cn. These MOS switches are controlled by coarse tuning control signals ct_c0, ct_c1, ..., ct_cn-1, respectively. When the control signal is high, the corresponding MOS switch is turned on, and the corresponding capacitor is connected to the total capacitance. When the control signal is low, the MOS switch is turned off, and the corresponding capacitor is disconnected.

[0167] The structure of the unit fine tuning capacitor array (FFA) is similar to the unit coarse tuning capacitor array, but it is controlled by an m-bit binary code, achieving 2^m levels of load capacitance adjustment. The FFA contains m fine tuning unit capacitors, labeled Cf1, Cf2, through Cfm. One end of each fine tuning unit capacitor is connected to port P, and the other end is connected to port M through corresponding unit fine tuning MOS switches M_F1, M_F2, ..., M_Fm. These MOS switches are controlled by fine tuning control signals ct_f0, ct_f1, ..., ct_fm-1, respectively, and operate in the same way as the coarse tuning unit.

[0168] It's important to note that the capacitance of the fine-tuning capacitors is smaller than that of the coarse-tuning capacitors. The coarse-tuning capacitor array handles wide-range frequency adjustment, while the fine-tuning capacitor array handles narrow-range fine frequency adjustment. This combination of coarse and fine tuning allows the oscillator frequency to be adjusted over a wide range while achieving high frequency accuracy.

[0169] By controlling the two groups of capacitor arrays through external digital coding, this embodiment achieves high-precision and wide-range digital control of the crystal oscillator frequency.

[0170] like Figure 5 As shown, this embodiment provides a layout structure design of load capacitors, which is mainly used to reduce the impact of substrate and surrounding environmental noise on the quality of crystal oscillator signals.

[0171] The layout structure consists of multiple layers from bottom to top. The bottom layer is the substrate isolation layer, which is used to isolate the capacitor structure from the chip substrate and reduce substrate noise coupling. Above the substrate isolation layer are the first metal layer M1, the second metal layer M2, and the third metal layer M3. These three metal layers are arranged in an interlaced manner to form a metal-oxide-metal MOM capacitor structure. In some embodiments, a top metal layer may be added on top as a shielding layer.

[0172] Each metal layer is connected via vias: a through-hole (CT) connects the substrate isolation layer to the first metal layer (M1); a first via (V1) connects the first metal layer (M1) to the second metal layer (M2); and a second via (V2) connects the second metal layer (M2) to the third metal layer (M3). These vias not only provide electrical connections but also form a wraparound structure around the edge of the layout, enhancing isolation from external noise.

[0173] The bottom of the layout can be shielded in two ways: by providing a polysilicon layer or by using a P-type substrate isolation layer. A metal layer can be added to the top as a shield. The upper and lower shielding layers, together with the surrounding CT, M1, V1, M2, V2, and M3, form a complete electromagnetic shielding structure, effectively preventing external noise interference.

[0174] The key to this layout design is the use of multi-layer metal and vias CT, M1, V1, M2, V2, and M3 staggered stacking, combined with upper and lower shielding layers and an edge-wrap connection structure to form a three-dimensional shield, significantly reducing the impact of substrate noise and external interference on the capacitance value, thereby improving the quality of the crystal oscillator signal and frequency stability.

[0175] This noise-resistant layout structure is an important basis for achieving high-performance, low-noise digitally controlled crystal oscillators in this embodiment.

[0176] like Figure 6 As shown, this embodiment provides a controllable structure design for the fifth MOS transistor M4 in the oscillation core circuit to optimize the circuit noise performance. This structure allows the effective size of the amplifier to be dynamically adjusted via digital signals to accommodate the additional noise introduced by process variations.

[0177] The entire structure consists of a fixed amplifier transistor M4_0, two controllable amplifier transistors M4_1 and M4_2, and four control switches S1, S2, S3, and S4. The gate of the fixed amplifier transistor M4_0 is connected to the crystal oscillator input terminal XTAL_I, the source is grounded, and the drain is connected to the crystal oscillator output terminal XTAL_O. The controllable amplifier transistors M4_1 and M4_2 have their sources grounded, their drains connected to the crystal oscillator output terminal XTAL_O, and their gates connected to their respective control nodes vg4_1 and vg4_2.

[0178] Of the four control switches, S1 and S2 are connect switches, while S3 and S4 are pull-down switches. S1 is connected between the crystal oscillator input XTAL_I and vg4_1 and is controlled by sela_0. S2 is connected between the crystal oscillator input XTAL_I and vg4_2 and is controlled by sela_1. S3 is connected between vg4_1 and ground and is controlled by selb_0. S4 is connected between vg4_2 and ground and is controlled by selb_1.

[0179] The structure works as follows:

[0180] By controlling the on / off states of switches S1 through S4, controllable amplifiers M4_1 and M4_2 can be selectively enabled or disabled, allowing them to operate in parallel with fixed amplifier M4_0 or independently, thus flexibly adjusting the effective size of the amplifier. Control signals sela_0 and selb_0 are complementary, and sela_1 and selb_1 are complementary, ensuring that each pair of switches is in opposite states, preventing the occurrence of inactive states.

[0181] This size-controllable MOS transistor array design is an important technical means for optimizing noise performance in this embodiment. It can dynamically adjust the noise introduced by process deviations to achieve a balance between noise figure, power consumption, and gain.

[0182] Working principle:

[0183] The working principle of the low-noise and high-stability digitally controlled crystal oscillator circuit of the present application is as follows.

[0184] After the system is powered on, the power supply voltage Vin passes through the first-stage voltage regulator LDO1 Figure 1 Converted into pre-stabilized voltage avdd, providing working power for the oscillator module, current signal generating circuit Bias, etc. When the enable signal En changes from low level to high level, the oscillator module starts working. Figure 3 As shown, the capacitor discharge circuit in the start-up module begins discharging, and the discharge signal vct_clk gradually decreases from a high level. Simultaneously, the control signal En_st is set to a high level, turning on the tri-state gate. Under the control of the discharge signal vct_clk, the ring oscillator generates an oscillation signal vct_st close to the crystal resonant frequency. This signal is fed to the crystal oscillator input terminal XTAL_I through the tri-state gate, helping the crystal oscillator to start quickly.

[0185] As the capacitor discharges, when the discharge signal vct_clk drops below the threshold voltage, the ring oscillator stops operating, the control signal En_st goes low, and the tri-state gate turns off. At this point, the crystal oscillator has established stable self-sustaining oscillation with the help of the start-up module, and the oscillation signal is presented through the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O.

[0186] like Figure 2 As shown, in the current signal generating circuit Bias, the operational amplifier amp locks the feedback signal vfb_amp to a level equal to the reference voltage Vref, generating a constant current across the adjustable resistor R0. The gate of the first MOS transistor M0 is connected to the op amp output vg0, the source is connected to the feedback signal vfb_amp, and the drain is connected to the second control node vbp. The generated current is amplified by the current mirror formed by the second MOS transistor M1 and the third MOS transistor M2. It then flows from the drain of the third MOS transistor M2 into the crystal oscillator control terminal XTAL_CF, acting as the drive current to provide energy for the crystal oscillation. The digital feedback signal Df_Bias adjusts the resistance of the adjustable resistor R0, and thus the drive current.

[0187] The crystal oscillator continues to oscillate under the driving current. Figure 2 As shown, in the oscillator core circuit, the fourth MOS transistor M3 and the fifth MOS transistor M4 form an inverting amplifier. Their gates are connected to the crystal oscillator input terminal XTAL_I, providing negative resistance to the crystal oscillator to offset internal losses and maintain oscillation. Feedback resistor Rf is connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O, providing the necessary bias for the inverting amplifier to ensure oscillation conditions are met. A first load capacitor C1 and a second load capacitor C2 are connected in parallel across the crystal oscillator, and the oscillation frequency can be adjusted by changing the capacitance. Figure 4The structure of the unit coarse tuning capacitor array (CFA) and the unit fine tuning capacitor array (FFA) used for the load capacitor is demonstrated. Through n-bit coarse tuning binary coding and m-bit fine tuning binary coding, the load capacitance value can be precisely adjusted over a wide range, achieving high-precision control of the oscillation frequency. The capacitance value of the unit fine tuning capacitor cell is much smaller than that of the unit coarse tuning capacitor cell, which enables the system to achieve both a wide range of frequency adjustment and extremely high frequency resolution.

[0188] The oscillation signal is transmitted from the crystal oscillator output terminal XTAL_O to the driver module. Figure 2 As shown, the second-stage voltage regulator LDO2 further adjusts the pre-regulated voltage avdd to a low-noise, stable drive voltage avdd_driver. In the first-stage output driver circuit Buffer1, the sixth and seventh MOS transistors M5 and M6 are the same size as M3 and M4 in the oscillator core. As a buffer stage, they can replicate the crystal oscillator's oscillation waveform without affecting its normal oscillation. Subsequently, the first-stage driver Buffer1_0 and level converter lv1 convert the buffered signal to the appropriate amplitude and DC level, forming the intermediate drive signal vo1. The second-stage output driver circuit Buffer2 further enhances the drive capability of the intermediate drive signal, ultimately delivering a high-quality clock signal from the output port OSC.

[0189] The signal detection feedback module monitors the peak-to-peak value of the signal at the crystal oscillator input terminal XTAL_I in real time, and generates a digital feedback signal Df_Bias to control the current signal generation circuit Bias, thereby achieving automatic adjustment and stabilization of the oscillation amplitude.

[0190] In each module of this application, a variety of noise reduction and stabilization measures are adopted, such as two-stage voltage adjustment, two-stage drive, load capacitor multi-layer shielding layout Figure 5 , adjustable size amplifier tube array Figure 6 The first, second, and third stabilizing capacitors CL1, CL2, and CL3 are connected between the pre-stabilized voltage avdd, the crystal oscillator control terminal XTAL_CF, and the drive voltage avdd_driver, respectively, and ground, forming a multi-stage filtering network that works together to suppress high-frequency noise and ripple in each power supply stage, further improving the system's anti-interference capability and signal purity.

[0191] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0192] This example proposes a low noise and high stability digital controlled crystal oscillator circuit. Figure 1 As shown, it includes a controllable reference current module, an oscillation starting module, an oscillation core module, an output signal driving module, a signal detection feedback module and three voltage stabilizing capacitors.

[0193] The controllable reference current module includes a first-stage voltage regulator LDO1 and a current signal generating circuit Bias. The first-stage voltage regulator LDO1 has an input terminal connected to a reference voltage Vref, an output terminal outputting a pre-stabilized voltage avdd, and a power terminal connected to a power supply voltage Vin. The current signal generating circuit Bias has a first input terminal connected to the reference voltage Vref, a second input terminal connected to a digital feedback signal Df_Bias, an output terminal connected to a crystal oscillator control terminal XTAL_CF, and a power terminal connected to the pre-stabilized voltage avdd.

[0194] The current signal generating circuit Bias includes an operational amplifier (AMP) with its positive terminal connected to a reference voltage (Vref), its negative terminal connected to a feedback node (vfb_amp), its output terminal connected to a control node (vg0), and its power terminal connected to a pre-regulated voltage (avdd). The circuit also includes three MOS transistors (MOS transistors): the first MOS transistor (M0) with its source connected to the feedback node (vfb_amp), its gate connected to the control node (vg0), and its drain connected to a bias node (vbp). The second MOS transistor (M1) has its source connected to the pre-regulated voltage (avdd), its gate connected to its drain and to the bias node (vbp). The third MOS transistor (M2) has its source connected to the pre-regulated voltage (avdd), its gate connected to the bias node (vbp), and its drain connected to the crystal oscillator control terminal (XTAL_CF). An adjustable resistor (R0) has its positive terminal connected to the feedback node (vfb_amp) and its negative terminal connected to ground. The circuit uses the operational amplifier (AMP) to lock the voltage at the feedback node (vfb_amp) to the reference voltage (Vref), generating an adjustable reference current across the adjustable resistor. The reference current flows through the first MOS transistor M0 and the second MOS transistor M1 at the same time, and after being amplified in a 1:n ratio by the current mirror formed by the second MOS transistor M1 and the third MOS transistor M2, it flows from the drain of the third MOS transistor M2 into the crystal oscillator control terminal XTAL_CF to provide energy for the oscillation core module.

[0195] The input terminal of the oscillator module is connected to the enable signal En, the output terminal is connected to the crystal oscillator input terminal XTAL_I, and the power terminal is connected to the pre-stabilized voltage avdd. Its structure is as follows Figure 3 As shown, it includes a capacitor discharge circuit and a series ring oscillator circuit. During the startup phase, the output signal of the oscillator module is connected to the crystal oscillator input terminal XTAL_I, providing an initial oscillation signal for the slow-starting crystal oscillator, helping the crystal oscillator to oscillate quickly and maintain stability.

[0196] The oscillator core module's input terminal is connected to the crystal oscillator input terminal XTAL_I, its output terminal is connected to the crystal oscillator output terminal XTAL_O, and its power terminal is connected to the crystal oscillator control terminal XTAL_CF. This module includes an external resonator Xtal, whose two ends are connected to the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O, respectively. An RLC network is formed within Xtal. The gates of the fourth MOS transistor M3 and the fifth MOS transistor M4 are connected and connected to the crystal oscillator input terminal XTAL_I, while their drains are connected and connected to the crystal oscillator output terminal XTAL_O. The source of the fourth MOS transistor M3 is connected to the crystal oscillator control terminal XTAL_CF, and the source of the fifth MOS transistor M4 is connected to ground, forming an inverting amplifier that provides sufficient phase for the loop. A feedback resistor Rf is connected between the crystal oscillator input terminal XTAL_I and the crystal oscillator output terminal XTAL_O to provide the required bias for the inverting amplifier.

[0197] The output signal driver module includes a second-stage voltage regulator LDO2, a first-stage output driver circuit Buffer1, and a second-stage output driver circuit Buffer2. The second-stage voltage regulator LDO2 has its input connected to the reference voltage Vref, its output connected to the drive voltage avdd_driver, and its power supply connected to the pre-stabilized voltage avdd. The first-stage output driver circuit Buffer1 has its input connected to the crystal oscillator output terminal XTAL_O, its output connected to the intermediate drive signal vo1, its first power supply connected to the crystal oscillator control terminal XTAL_CF, and its second power supply connected to the drive voltage avdd_driver. The second-stage output driver circuit Buffer2 has its input connected to the intermediate drive signal vo1, its output connected to the oscillator output signal OSC, and its power supply connected to the drive voltage avdd_driver. This module adjusts the pre-processed voltage avdd from the first-stage voltage regulator to a more stable voltage avdd_driver with less power supply noise. The first-stage driver circuit, using the crystal oscillator control terminal XTAL_CF as its power supply voltage, adjusts the crystal oscillator output signal XTAL_O to the voltage range of the drive voltage avdd_driver. The second-stage driver circuit then amplifies the intermediate drive signal vo1 to the oscillator output signal OSC, which has stronger drive capability.

[0198] The signal detection feedback module's input terminal is connected to the crystal oscillator input terminal XTAL_I, and its output terminal is connected to the digital feedback signal Df_Bias. This module collects the peak-to-peak value of the crystal oscillator input terminal XTAL_I and calculates and generates a series of digital signals to control the reference current of the current signal generation circuit Bias.

[0199] In addition, the circuit also includes three voltage-stabilizing capacitors: a first voltage-stabilizing capacitor CL1, whose positive terminal is connected to the pre-stabilized voltage avdd, and whose negative terminal is connected to the ground; a second voltage-stabilizing capacitor CL2, whose positive terminal is connected to the crystal oscillator control terminal XTAL_CF, and whose negative terminal is connected to the ground; and a third voltage-stabilizing capacitor CL3, whose positive terminal is connected to the drive voltage avdd_driver, and whose negative terminal is connected to the ground.

[0200] It should be noted that this example uses two sets of programmable capacitor arrays to increase the adjustable frequency range while adjusting the frequency accuracy; improves the output signal quality by focusing on the power supply and its own structure; uses automatic detection plus external phase control to control the oscillation amplitude of the crystal oscillator to ensure signal quality; and introduces a simple structure to accelerate the crystal's start-up and achieve the goal of fast and stable oscillation.

[0201] More specifically, if Figure 1 As shown, the circuit system of this example includes: a reference current generating circuit, which is used to generate a pre-stabilized voltage avdd and a driving current I_core; an oscillation starting circuit, which is used to generate an oscillation signal equivalent to the series resonant frequency of the crystal oscillator during the startup phase; an oscillation core circuit, which is used to generate a stable and high-quality oscillation signal; an output signal driving circuit, which is used to adjust the periodic signal generated by the crystal oscillator to the required peak-to-peak value and driving capability; a sampling feedback circuit, which samples the oscillation signal of the crystal oscillator and generates a series of digital signals with crystal oscillation signal information after processing. The driving current generating circuit proposed in this example has a structure including: a first-stage pre-stabilized voltage regulator LDO1, whose input terminal is connected to Vref, the power supply voltage Vin, and the output voltage avdd, and a driving current generating circuit Bias, whose input terminal is connected to Vref and the input control terminal is connected to Df_bias; an oscillator circuit, whose input terminal enables the signal En and the output terminal is connected to XTAL_I; an oscillation core circuit, one end of which is connected to XTAL_I and the other end is connected to XTAL_O; an output signal driving circuit, whose structure includes: a second-stage low-noise voltage regulator LDO2, whose input terminal is connected to Vref, the power supply voltage avdd, and the output voltage avdd_driver; a first-stage driving circuit, whose input signal is XTAL_O with XTAL_CF as the highest peak-to-peak value, and whose output signal is vo1 with avdd_driver as the highest peak-to-peak value; a second-stage driving circuit, whose input signal is vo1 and whose output is OSC, whose peak-to-peak value is avdd_driver; a sampling feedback circuit, whose input signal is XTAL_I and whose output signal is Df_Bias. The output voltage stabilizing capacitors CL1, CL2, and CL3 are connected to avdd, XTAL_CF, and avdd_driver respectively.

[0202] The driving current generating circuit mentioned in this example is Figure 2As shown, its working method is as follows: the first-stage pre-stabilized voltage regulator stabilizes the power supply voltage to avdd with reference to the reference voltage Vref, and the reference current generating circuit uses the pre-stabilized voltage avdd as the power supply; the operational amplifier amp, the MOS transistor M0, and the adjustable resistor R0 form a negative feedback loop, and the virtual short characteristic of the operational amplifier is used to force the voltage vfb_amp at the positive terminal of the resistor R1 to be equal to the reference voltage Vref. According to Ohm's law, the current flowing through the resistor R1 is the reference current I_ref, which also flows through the MOS transistors M0 and M1; the current mirror structure formed by the MOS transistors M1 and M2 has a size ratio of 1:n, so that the reference current I_ref can be amplified by n times to obtain the driving current I_core.

[0203] The oscillator circuit mentioned in this example is Figure 3 As shown, its structure includes a capacitor discharge circuit, a ring oscillator circuit, and a tri-state gate. The connections are as follows: the capacitor discharge circuit's input is connected to the enable signal En, its output 1 is connected to vct_clk, and its output 2 is connected to En_st. The ring oscillator's input is connected to vct_clk, and its output is connected to vct_st. The tri-state gate's input is connected to vct_st, its output is connected to Start_core, and its control terminal is connected to En_st. It operates as follows: When the enable signal En goes high, the capacitor discharge circuit begins discharging, vct_clk gradually decreases from a high level, and En_st reaches a high level. At this point, the tri-state gate opens, and the ring oscillator begins oscillating at a parallel resonant frequency close to the crystal oscillator's. The output vct_st is then output through the tri-state gate, accelerating the crystal oscillator's startup. When the capacitor discharge circuit's output vct_clk falls below a certain threshold, the ring oscillator stops oscillating, and the output signal En_st is reset to zero, closing the tri-state gate. The crystal oscillator now operates in a stable oscillation state through its own feedback. The discharge time of the capacitor discharge circuit should be greater than the crystal oscillator's startup time.

[0204] The oscillation core circuit mentioned in this example is Figure 2As shown in Figure 1, its operation is as follows: The resonator Xtal utilizes the piezoelectric effect to convert voltage and stress into each other, forming an internal RLC network. By providing an initial periodic voltage to Xtal, Xtal automatically generates a periodic voltage signal. To ensure stable and automatic periodic signal generation, an inverting amplifier, consisting of M3 and M4, is introduced to form a feedback loop and provide a phase greater than 180 degrees. Feedback resistor Rf is introduced to provide the bias required for stable operation of the inverting amplifier. This completes the feedback loop and enables the crystal oscillator to continuously output an oscillating signal. Due to temperature, process, and aging effects, the frequency of the output signal is not accurate. Therefore, a pair of crystal load capacitors C1 and C2 are connected across the crystal oscillator. The positive terminal of C1 is connected to XTAL_I and the negative terminal is connected to ground. The positive terminal of C2 is connected to XTAL_O and the negative terminal is connected to ground.

[0205] The crystal oscillator load adjustable capacitor networks C1 and C2 mentioned in this example are two identical circuits. The C1 / C2 circuit structure is as follows: Figure 4 As shown in Figure 1, its structure includes a unit coarse tuning capacitor network CFA and a unit fine tuning capacitor network FFA. The connections are: the positive terminal of the CFA is connected to the positive terminal of the FFA, and the positive and negative terminals of the CFA are connected to the negative terminal of the FFA. Its operation is as follows: This circuit is a variation of the typical Pierce oscillator, primarily but not limited to generating clock sources for digital circuits. Its parallel resonant frequency is: f p ≈f s (1+C1 / 2(C0+C L )), where f s is the series resonant frequency: We can precisely control the oscillation frequency by adjusting the load capacitance CL. To ensure a wide and precise frequency adjustment range, this example combines a coarse-frequency array (CFA) with a fine-frequency array (FFA). The specific adjustment of the digital coding sequence is controlled by off-chip sampling and coding feedback of the output signal OSC. The unit coarse adjustment capacitor array mentioned in this example is connected as follows: the positive terminal of the coarse adjustment unit capacitor Cc1 is connected to port P, the negative terminal is connected to the drain of the MOS switch M_C1, the source of M_C1 is connected to ground, and the gate is connected to the control potential ct_c0; the positive terminal of the coarse adjustment unit capacitor Cc2 is connected to port P, the negative terminal is connected to the drain of the MOS switch M_C2, the source of M_C2 is connected to ground, and the gate is connected to the control potential ct_c1; the positive terminal of the coarse adjustment unit capacitor Cc3 is connected to port P, the negative terminal is connected to the drain of the MOS switch M_C3, the source of M_C3 is connected to ground, and the gate is connected to the control potential ct_c2; the positive terminal of the coarse adjustment unit capacitor Ccn is connected to port P, the negative terminal is connected to the drain of the MOS switch M_Cn, the source of M_Cn is connected to ground, and the gate is connected to the control potential ct_c(n-1). Its operating principle is as follows: Cc represents the unit capacitor of the coarse tuning capacitor, and M_C represents the MOS switch of the coarse tuning capacitor. When the control signal ct_c is low, the M_C switch is off, disconnecting the capacitor. When the control signal ct_c is high, the M_C switch is on, shorting the negative terminal of the capacitor to port M. Cc1 and M_C1 form a group consisting of one unit capacitor and one MOS switch in series. Cc2 and M_C2 form two groups in parallel, Cc3 and M_C3 form three groups in parallel, and Cc2^n and M_Cn form n groups in parallel. This allows for 2^n different combinations of control for each binary code. The unit fine tuning capacitor array described in this example has similar connections and operating principles to the unit coarse tuning capacitor array, except that this capacitor array is controlled by an m-bit binary code, allowing for 2^m different capacitor combinations. Furthermore, the unit capacitors for fine tuning are much smaller than the unit coarse tuning capacitors, and the smallest unit fine tuning capacitor determines the accuracy of the final adjustable oscillation frequency.

[0206] The crystal oscillator load adjustable capacitor network C1 and C2 mentioned in this example takes into account that there may be a lot of noise in the chip application environment, especially the substrate noise has a great impact on the signal quality of the crystal oscillator. Therefore, the patent mentions a method for processing the substrate noise in the layout, such as Figure 5As shown, its structure includes: the bottom substrate isolation layer, the first metal layer, the second metal layer, the third metal layer, the top metal layer (optional) and the through hole CT, the connection hole V1 between the first metal layer and the second metal layer, the connection hole V2 between the second metal layer and the third metal layer, etc. Its principle is as follows: the staggered stacked metals M1, M2, and M3 constitute a mom capacitor, a shielding layer is added around them to isolate the noise source from the surrounding environment, and a layer of polysilicon or active doping is added at the bottom.

[0207] In the oscillation core circuit mentioned in this example, the noise comes not only from the coupling of the adjustable capacitor to the noise in the environment, but also from the feedback resistor and the inverting amplifier circuit. We know that the sources of resistor noise are divided into thermal noise Flicker noise The simplest way to optimize resistor noise is to select resistors with low noise and stability. At the same time, increasing the size of the resistor can suppress the high-frequency thermal noise of the resistor. For the noise of the inverting amplifier, the source of MOS noise is thermal noise. Flicker noise High-frequency gate-induced noise This shows that a suitable MOS tube size is crucial for noise optimization, so the MOS array can be increased to optimize the noise caused by process and bias.

[0208] The above MOS array takes NMOS as an example. Figure 6As shown, its structure includes: a fixed MOS transistor M4_0 of appropriate size, two gate-controllable MOS transistors M4_1 and M4_2, two connecting switches S1 and S2, and two pull-down switches S3 and S4. Their connections are as follows: M4_0's source is grounded, its gate is connected to XTAL_I, and its drain is connected to XTAL_O; M4_1's source is grounded, its gate is connected to vg4_1, and its drain is connected to XTAL_O; M4_2's source is grounded, its gate is connected to vg4_2, and its drain is connected to XTAL_O; switch S1's positive terminal is connected to XTAL_I, its negative terminal is connected to vg4_1, and its control terminal is connected to sela_0; switch S2's positive terminal is connected to XTAL_I, its negative terminal is connected to vg4_2, and its control terminal is connected to sela_1; switch S3's positive terminal is connected to vg4_1, its negative terminal is grounded, and its control terminal is connected to selb_0; switch S4's positive terminal is connected to vg4_2, its negative terminal is grounded, and its control terminal is connected to selb_1. The working mode is as follows: MOS tubes M4_0, M4_1, and M4_2 serve as amplifier tubes of the inverting amplifier, and their sizes remain consistent. The number of each tube is set according to the required adjustable range. Under normal circumstances, one of M4_1 or M4_2 is opened. When the size needs to be increased, the switch is controlled so that S1 and S2 are both opened, and S3 and S4 are both closed. When the size needs to be reduced, S1 and S2 are both closed, and S3 and S4 are both opened; S1 and S2 are connecting switches. When closed, the gate vg4_1 of M4_1 is short-circuited with XTAL_I, and the gate vg4_2 of M4_2 is short-circuited with XTAL_I. When disconnected, the branch is disconnected; S3 and S4 are pull-down switches. When closed, the gate vg4_1 of M4_1 is short-circuited with ground, and the gate vg4_2 of M4_2 is short-circuited with ground. When disconnected, the branch is disconnected. The control signals sela_0 and selb_0 are a pair of inverted signals, and sela_0 and selb_0 are a pair of inverted signals. sela_0, selb_0, sela_1, and selb_1 can be controlled by off-chip coding.

[0209] The output signal driving circuit proposed in this example is Figure 2As shown, the structure includes a second-stage voltage regulator LDO2, a first-stage voltage driver circuit Buffer1, and a second-stage voltage driver circuit Buffer2. The second-stage voltage regulator LDO2 proposed in this example is connected as follows: the input reference voltage is connected to Vref, the power supply is connected to avdd, and the output is connected to avdd_driver and a large load capacitor C3. LDO2 must have low output noise and a high PSR. The first-stage voltage driver circuit Buffer1 proposed in this example consists of M5 and M6 as a buffer stage, buffer1_0 as a driver, and voltage converter lv1. The connections are as follows: the gates of M5 and M6 are connected to XTAL_I, and their drains are connected as the output, outputting v1. The sources of M5 and M3 are connected to the positive terminal of CL2, and the source of M6 is connected to ground. The input of ffer1_0 is connected to v1, and the output is v2, the power supply voltage is connected to XTAL_CF. The input of lv1 is connected to v2, the output is connected to vo1, and the power supply is connected to XTAL_CF and avdd_driver. The principle is as follows: M5 and M3 are identical in size, and M6 and M4 are identical in size. Buffer1_0 drives level 1, which converts the amplitude from the XTAL_CF voltage domain to the avdd_driver voltage threshold. The second-level voltage driver, Buffer2, proposed in this example, is connected as follows: its input is connected to vo1, its output is connected to OSC, and its power supply is connected to avdd_driver. This driver provides sufficient drive capability for the output while minimizing noise input.

[0210] The sampling feedback circuit proposed in this example is Figure 1 As shown, the connection method is: the input is connected to XTAL_I, the output is connected to D_fb, and the output signal D_fb is superimposed on the external programmable signal D_in to output Df_Bias. Its working method is as follows: the circuit samples the oscillation amplitude of the crystal oscillator, compares it with the reference value, and then processes it by digital logic to obtain a series of binary codes (D_fb) for dynamically controlling the drive current I_core. The user can provide an external control programming code D_in as needed to better control the drive current I_core. The adjustment principle is as follows: When the signal collected by the sampling circuit (which can be approximated as the voltage value of XTAL_CF) is compared with a suitable reference voltage, the comparison result will be multi-bit binary encoded D_f through the logic circuit. The encoded signal is superimposed with the external encoded signal D_in to obtain a set of new encoded signals Df_Bias (where D_in can be defined by the user, such as detecting the output signal, detecting the temperature, etc.). If the detection signal is lower than the expected reference voltage, this new string of codes will be adjusted Figure 2The R0 resistor in the circuit is reduced to increase the reference current I_ref, thereby increasing the drive current I_core to stabilize the voltage at XTAL_CF and make the crystal oscillator oscillate stably.

[0211] The above embodiments have the following technical effects:

[0212] The above embodiment adopts a two-stage voltage regulator architecture. The first-stage voltage regulator LDO1 generates a pre-stabilized voltage avdd, and the second-stage voltage regulator LDO2 further generates a low-noise drive voltage avdd_driver, effectively improving the power supply rejection performance of the output signal. For frequency regulation, the above embodiment uses a combination of a unit coarse tuning capacitor array (CFA) and a unit fine tuning capacitor array (FFA). The CFA uses an n-bit encoding signal to adjust the load capacitance in 2^n steps, achieving wide-range frequency regulation. The FFA uses an m-bit encoding signal to adjust the load capacitance in 2^m steps, enabling high-precision frequency fine-tuning. The combination of these two ensures both frequency regulation width and accuracy. For noise control, the above embodiment addresses both circuit and layout issues. Programmable op amp control is used to mitigate excess noise introduced by process variations, and isolation of the load capacitor layout reduces coupling noise from the substrate and surrounding areas. Oscillation signal quality is ensured through both automatic detection feedback and external control. The signal detection and feedback module samples the signal at the crystal oscillator input terminal XTAL_I. After internal processing, it generates a sampled feedback signal D_fb, which is superimposed with the external control signal D_in containing other variables to generate a digital feedback signal Df_Bias to adjust the drive current. The start-up module ensures fast and stable startup of the oscillator. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal oscillator's resonant frequency to help the crystal oscillator start. The capacitor discharge circuit periodically shuts off the start-up signal, allowing the crystal oscillator to enter a steady state.

[0213] The start-up module ensures a fast and stable startup of the oscillator. When the enable signal En is triggered, the ring oscillator generates a signal close to the crystal's resonant frequency to help the crystal start. The capacitor discharge circuit periodically shuts off the start-up signal, allowing the crystal to enter a steady state.

[0214] In summary, the above embodiments achieve multiple technical goals such as low noise, high stability, wide adjustment range and fast startup through an innovative circuit architecture, providing an effective solution for high-performance clock sources.

[0215] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0216] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A low-noise, high-stability digitally controlled crystal oscillator circuit, characterized in that: include: A controllable reference current module includes a first-stage voltage regulator (LDO1) and a current signal generating circuit (Bias), wherein the first-stage voltage regulator has an input terminal connected to a reference voltage (Vref), an output terminal outputting a pre-stabilized voltage (avdd), and a power supply terminal connected to a power supply voltage (Vin); the current signal generating circuit has a first input terminal connected to the reference voltage, a second input terminal connected to a digital feedback signal (Df_Bias), an output terminal connected to a crystal oscillator current control terminal (XTAL_CF), and a power supply terminal connected to the pre-stabilized voltage; An oscillator module, whose input terminal is connected to the enable signal (En), the output terminal is connected to the crystal oscillator input terminal (XTAL_I), and the power terminal is connected to the pre-stabilized voltage; An oscillator core module, whose input terminal is connected to the crystal oscillator input terminal, the output terminal is connected to the crystal oscillator output terminal (XTAL_O), and the power terminal is connected to the crystal oscillator current control terminal; An output signal driving module includes a second-stage voltage regulator (LDO2), a first-stage output driving circuit (Buffer1), and a second-stage output driving circuit (Buffer2), wherein the input terminal of the second-stage voltage regulator is connected to the reference voltage, the output terminal outputs a driving voltage (avdd_driver), and the power terminal is connected to the pre-stabilized voltage; the input terminal of the first-stage output driving circuit is connected to the crystal oscillator output terminal, the output terminal outputs an intermediate driving signal (vo1), the first power terminal is connected to the crystal oscillator current control terminal, and the second power terminal is connected to the driving voltage; The input terminal of the second-stage output driving circuit is connected to the intermediate driving signal, the output terminal outputs the oscillator output signal (OSC), and the power terminal is connected to the driving voltage; A signal detection feedback module has an input terminal connected to the crystal oscillator input terminal and an output terminal connected to the digital feedback signal.

2. The digital controlled crystal oscillator circuit according to claim 1, wherein: Also includes: a first voltage-stabilizing capacitor (CL1), a positive terminal of which is connected to the pre-stabilized voltage and a negative terminal of which is connected to ground; a second voltage-stabilizing capacitor (CL2), a positive terminal of which is connected to the crystal oscillator control terminal, and a negative terminal of which is connected to ground; A third voltage-stabilizing capacitor (CL3) has a positive terminal connected to the driving voltage and a negative terminal connected to the ground.

3. The digital controlled crystal oscillator circuit according to claim 1 or 2, characterized in that: The current signal generating circuit includes: an operational amplifier (amp), a first MOS transistor (M0), a second MOS transistor (M1), a third MOS transistor (M2), and an adjustable resistor (R0); The operational amplifier comprises a non-inverting input terminal connected to the reference voltage, an inverting input terminal connected to a feedback signal (vfb_amp), an output terminal connected to a first control node (vg0), and a power supply terminal connected to the pre-stabilized voltage; a gate terminal of the first MOS transistor connected to the first control node, a source terminal connected to the feedback signal, and a drain terminal connected to a second control node (vbp); a source terminal of the second MOS transistor connected to the pre-stabilized voltage, a gate terminal connected to its drain terminal and to the second control node; a source terminal of the third MOS transistor connected to the pre-stabilized voltage, a gate terminal connected to the second control node, and a drain terminal connected to the crystal oscillator current control terminal; and a positive terminal of the adjustable resistor connected to the feedback signal, and a negative terminal connected to ground.

4. The digital controlled crystal oscillator circuit according to claim 1 or 2, characterized in that: The oscillation module includes: a capacitor discharge circuit, a ring oscillator, and a tri-state gate; Among them, the input end of the capacitor discharge circuit is connected to the enable signal, the first output end (vct_clk) is connected to the input end of the ring oscillator, and the second output end (En_st) is connected to the control end of the three-state gate; the output end (vct_st) of the ring oscillator is connected to the input end of the three-state gate; the output end of the three-state gate is connected to the crystal oscillator input end (XTAL_I).

5. The digital controlled crystal oscillator circuit according to claim 1 or 2, characterized in that: The oscillation core module includes: a resonator (Xtal), a fourth MOS transistor (M3), a fifth MOS transistor (M4), and a feedback resistor (Rf); Wherein: the first end of the resonator is connected to the crystal oscillator input end, and the second end is connected to the crystal oscillator output end; the gate of the fourth MOS transistor is connected to the crystal oscillator input end, the source is connected to the crystal oscillator control end, and the drain is connected to the crystal oscillator output end; the gate of the fifth MOS transistor is connected to the crystal oscillator input end, the source is grounded, and the drain is connected to the crystal oscillator output end; one end of the feedback resistor is connected to the crystal oscillator input end, and the other end is connected to the crystal oscillator output end.

6. The digital controlled crystal oscillator circuit according to claim 5, characterized in that: Also includes: a first load capacitor (C1), wherein the positive terminal or the negative terminal is connected to the crystal oscillator input terminal, and the negative terminal or the positive terminal is grounded; A second load capacitor (C2) has a positive terminal or a negative terminal connected to the crystal oscillator output terminal, and a negative terminal or a positive terminal grounded.

7. The digital controlled crystal oscillator circuit according to claim 6, wherein: The first load capacitor and the second load capacitor each include: a unit coarse capacitance array (CFA) and a unit fine capacitance array (FFA); Wherein: the port P of the unit coarse tuning capacitor array is connected to the port P of the unit fine tuning capacitor array, and the port M of the unit coarse tuning capacitor array is connected to the port M of the unit fine tuning capacitor array; the unit coarse tuning capacitor array includes unit coarse tuning capacitor units controlled by n-bit binary coding, forming 2^n different capacitor combinations, each unit coarse tuning capacitor unit includes a unit coarse tuning capacitor (Cc) and a unit coarse tuning MOS switch (M_C), and the unit coarse tuning MOS switch is controlled by a corresponding coarse tuning control signal (ct_c); the unit fine tuning capacitor array includes unit fine tuning capacitor units controlled by m-bit binary coding, forming 2^m different capacitor combinations, each unit fine tuning capacitor unit includes a unit fine tuning capacitor (Cf) and a unit fine tuning MOS switch (M_F), and the unit fine tuning MOS switch is controlled by a corresponding fine tuning control signal (ct_f); wherein the capacitance value of the unit fine tuning capacitor unit is smaller than the capacitance value of the unit coarse tuning capacitor unit, so as to achieve a combination of wide range coarse tuning and precise fine tuning.

8. The digital controlled crystal oscillator circuit according to claim 5, characterized in that: The fifth MOS transistor includes: a fixed amplifier transistor (M4_0), a first controllable amplifier transistor (M4_1), a second controllable amplifier transistor (M4_2), a first connecting switch (M_S1), a second connecting switch (M_S2), a first pull-down switch (M_S3), and a second pull-down switch (M_S4); Wherein: the gate of the fixed amplifier tube is connected to the crystal oscillator input end, the source is grounded, and the drain is connected to the crystal oscillator output end; the source of the first controllable amplifier tube and the second controllable amplifier tube are both grounded, and the drain is both connected to the crystal oscillator output end; one end of the first connecting switch is connected to the crystal oscillator input end, and the other end is connected to the gate of the first controllable amplifier tube; one end of the second connecting switch is connected to the crystal oscillator input end, and the other end is connected to the gate of the second controllable amplifier tube; one end of the first pull-down switch is connected to the gate of the first controllable amplifier tube, and the other end is grounded; one end of the second pull-down switch is connected to the gate of the second controllable amplifier tube, and the other end is grounded.

9. The digital controlled crystal oscillator circuit according to claim 1 or 2, characterized in that: The first-stage output drive circuit includes: a sixth MOS transistor (M5), a seventh MOS transistor (M6), a driver (Buffer1_0), and a level converter (lv1); The gates of the sixth MOS transistor and the seventh MOS transistor are connected to each other and to the crystal oscillator input terminal, and their drains are connected to form a first intermediate node (v1) and to the input terminal of the driver; the source of the sixth MOS transistor is connected to the crystal oscillator control terminal and to the positive terminal of the second voltage-stabilizing capacitor; the source of the seventh MOS transistor is grounded; the power supply terminal of the driver is connected to the crystal oscillator control terminal, and the output terminal is connected to a second intermediate node (v2) and to the input terminal of the level converter; the first power supply terminal of the level converter is connected to the crystal oscillator control terminal, the second power supply terminal is connected to the driving voltage, and the output terminal outputs the intermediate driving signal.

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