Method for forming ONO dielectric layer in flash memory

Abstract

The invention discloses a method for forming an oxide-nitride-oxide (ONO) dielectric layer in a flash memory, and aims at solving the problem of Flash reading interference. The method comprises the following steps: providing a substrate, and forming a first oxide layer on the substrate (preferably on a preformed floating gate); forming a silicon oxynitride (SiON) layer on the first oxide layer, wherein the forming process comprises introducing mixed gas containing dichlorosilane gas, ammonia gas and nitrous oxide gas into the reaction chamber for chemical vapor deposition; and forming a second oxide layer on the silicon oxynitride layer, and subsequently forming a control gate. By introducing nitrous oxide gas to form the SiON layer to replace a traditional silicon nitride layer, the number of traps in the dielectric layer is effectively reduced, and the electrical insulation performance is enhanced, so that the loss of floating gate electrons during reading operation is remarkably inhibited, the reading interference characteristic is improved, and the reliability of the flash memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming an ONO dielectric layer in a flash memory. Background Art

[0002] Flash memory, as a non-volatile storage technology, has been widely used in mobile devices, solid-state drives, and embedded systems due to its high density, low power consumption, and rewritable nature. The basic unit of flash memory typically consists of a floating gate (FG) transistor, which stores charge in the floating gate to represent the logic state "0" or "1."

[0003] However, with the continuous increase in memory integration and the continued reduction in cell size, flash memory reliability issues are becoming increasingly prominent. Read disturb (RD) is a key factor affecting its reliability. Read disturb occurs when a specific memory cell (target cell) in a memory array is subjected to prolonged or frequent read operations. The read voltage applied to the target cell's control gate (CG) can adversely affect other unselected memory cells (disturb cells) on the same wordline or bitline. Specifically, the read voltage applied to the control gate can cause a small amount of electrons to tunnel from the floating gate of the disturbing cell to the control gate, or to be injected from the channel into the floating gate. For cells storing a logic "0" (usually indicating a high number of electrons stored in the floating gate), this electron loss from the floating gate to the control gate can lower their threshold voltage, ultimately causing the cell originally storing "0" to be incorrectly read as "1," resulting in a "0" to "1" flip error. This error can prevent the product from successfully reading the stored information, seriously impacting data integrity and device reliability.

[0004] Existing flash memory cells typically use a three-layer oxide-nitride-oxide (ONO) structure as the gate dielectric layer, located between the floating gate and the control gate. The insulating properties of this ONO structure are crucial for suppressing read disturb. If the ONO film, especially the silicon nitride (SiN) layer, has poor electrical insulation properties or contains many defects and traps, the control gate voltage will attract electrons in the floating gate to tunnel through the ONO layer more easily during long-term read operations, resulting in electron loss and thus triggering read disturb failure. For example, in Flash products with 55nm or 90nm process nodes, read disturb failures caused by prolonged read operations on specific addresses (CG terminals) have been observed. The main reason for this is attributed to the poor quality of the ONO film layer, which easily leads to electron loss from FG to CG.

[0005] Therefore, how to improve the quality of the ONO dielectric layer, reduce the number of charge traps therein, and enhance its electrical insulation performance to effectively inhibit floating gate electrons from tunneling through the ONO layer during read operations, thereby improving the read disturb characteristics of Flash memory, is a technical problem that needs to be urgently solved in the current field of semiconductor storage technology. Summary of the Invention

[0006] The present invention aims to address the problem in existing flash memory technology where the gate dielectric layer (particularly the silicon nitride layer in the traditional ONO structure) has poor electrical insulation properties or numerous defects, leading to the easy loss of floating gate charge during read operations, which in turn causes read disturb (RD) failures. In particular, cells storing "0" are prone to "0" to "1" flips. The present invention is dedicated to providing an improved method for forming the oxide-nitride-oxide (ONO) dielectric layer in flash memory. This method improves the quality of the ONO dielectric layer, reduces charge traps, and enhances its electrical insulation properties, thereby effectively suppressing read disturb and improving the reliability of the flash memory.

[0007] To solve the above technical problems, the present invention provides a method for forming an oxide-nitride-oxide (ONO) dielectric layer in a flash memory, comprising the following steps:

[0008] Step 1: providing a substrate and forming a first oxide layer on the substrate;

[0009] Step 2: forming a silicon oxynitride (SiON) layer on the first oxide layer, wherein forming the silicon oxynitride layer comprises introducing a mixed gas comprising dichlorosilane (DCS) gas, ammonia (NH3) gas, and nitrous oxide (N2O) gas into a reaction chamber for chemical vapor deposition; and

[0010] Step three: forming a second oxide layer on the silicon oxynitride layer.

[0011] In a preferred embodiment, in step 1, the first oxide layer is formed on a floating gate pre-formed on the substrate.

[0012] In a preferred embodiment, the method further comprises: after step three, forming a control gate on the second oxide layer.

[0013] In a preferred embodiment, in step 2, the forming of the silicon oxynitride layer further comprises: before introducing the dichlorosilane gas, introducing the ammonia gas and the nitrous oxide gas into the reaction chamber in advance.

[0014] In a more preferred embodiment, in step 2, before the dichlorosilane gas is introduced, the time for pre-introducing ammonia gas and nitrous oxide gas is 1 minute.

[0015] In a preferred embodiment, in step 2, the reaction temperature of the chemical vapor deposition is 750°C to 810°C.

[0016] In a preferred embodiment, in step 2, the reaction pressure of the chemical vapor deposition is 0.25 torr to 0.45 torr. In a more preferred embodiment, the reaction pressure of the chemical vapor deposition is 0.3 torr.

[0017] In a preferred embodiment, in step 2, the flow rate of the ammonia gas is 0.04 to 0.08 liters. In a more preferred embodiment, the flow rate of the ammonia gas is 0.06 liters.

[0018] In a preferred embodiment, in step 2, the flow rate of the nitrous oxide gas is 0.17 liter to 0.37 liter. In a more preferred embodiment, the flow rate of the nitrous oxide gas is 0.27 liter.

[0019] In a preferred embodiment, in step 2, the flow rate of the dichlorosilane gas is 0.12 liters to 0.18 liters. In a more preferred embodiment, the flow rate of the dichlorosilane gas is 0.15 liters.

[0020] In a preferred embodiment, in step 2, the reaction time of the chemical vapor deposition is 20 minutes to 40 minutes.

[0021] As described above, the method of forming an ONO dielectric layer in a flash memory of the present invention has the following beneficial effects:

[0022] The present invention deposits SiON films in the presence of nitrous oxide (N2O). Due to the incorporation of an appropriate amount of oxygen, the film effectively reduces defects such as dangling bonds and charge traps that are prone to forming in existing silicon nitride films. The introduction of oxygen helps passivate these defects, forming a dielectric film with more stable chemical bonds and a denser structure. Compared to traditional SiN layers, the SiON layer produced by the present invention exhibits superior electrical insulation properties and stronger charge blocking capabilities. This can significantly reduce the probability of electrons tunneling from the floating gate to the control gate under the action of an electric field such as during a read operation. Due to the improved quality and enhanced insulation properties of the SiON layer, it can effectively inhibit floating gate electrons from penetrating the ONO dielectric layer during long-term or high-frequency read operations, especially inhibiting the loss of electrons from the floating gate to the control gate, thereby significantly improving the read disturb characteristics of the Flash memory and reducing the risk of a "0" to "1" error occurring in a cell storing "0". By reducing read disturb failures, the method of the present invention can improve the data retention capability and overall reliability of flash memory products and extend the service life of the device. The method proposed in the present invention is an improvement on the existing ONO process, mainly adjusting the deposition gas composition and process parameters of the intermediate dielectric layer. It has good compatibility with existing semiconductor manufacturing processes and is easy to implement.

[0023] In summary, the present invention optimizes the preparation process of the nitride layer in the ONO dielectric layer and introduces a silicon oxynitride layer, which effectively improves the read disturbance resistance of the flash memory and has important practical application value for improving the performance and reliability of modern high-density flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0025] Figure 2 Shown is a schematic diagram of forming a first oxide layer according to the present invention;

[0026] Figure 3 Schematic diagram showing the formation of a silicon oxynitride (SiON) layer on the first oxide layer of the present invention;

[0027] Figure 4 Schematic diagram showing the formation of a second oxide layer on the silicon oxynitride layer according to the present invention;

[0028] Figure 5 Shown is a schematic diagram of forming a control gate on the second oxide layer of the present invention;

[0029] Figure 6 Shown is a schematic diagram of a device accelerated aging test in the prior art;

[0030] Figure 7 Shown is a schematic diagram of the accelerated aging test of a device according to the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] To address the problem in existing flash memories of poor quality ONO dielectric layers, particularly insufficient electrical insulation or a high number of traps in silicon nitride layers, which results in read disturb failure and makes cells storing "0" susceptible to "0" to "1" flipping, the present invention provides a method for improving read disturb in flash memories. Specifically, it provides an improved method for forming an oxide-nitride-oxide (ONO) dielectric layer in flash memories.

[0033] See also Figure 1 The method for forming an oxide-nitride-oxide (ONO) dielectric layer in a flash memory comprises the following steps:

[0034] Step 1: Provide a substrate (not shown in the figure) and form a first oxide layer 102 on the substrate to form an inlet. Figure 2 The first oxide layer 102 is usually used as the bottom oxide in the ONO structure, directly contacting the underlying functional structure (such as the floating gate 101), and plays the role of initial insulation and interface buffer.

[0035] In some embodiments, in step 1, the first oxide layer 102 is formed on the floating gate 101 (FG) pre-formed on the substrate. This ensures that the ONO dielectric layer is precisely positioned between the floating gate 101 and the subsequently formed control gate 105. The first oxide layer 102 directly covers the floating gate 101, providing a first layer of electrical insulation for it.

[0036] Step 2: forming a silicon oxynitride (SiON) layer 103 on the first oxide layer 102 to form a Figure 3The structure shown in FIG. 1 , wherein the formation of the silicon oxynitride layer 103 includes introducing a mixed gas comprising dichlorosilane (DCS) gas, ammonia (NH3) gas and nitrous oxide (N2O) gas into a reaction chamber for chemical vapor deposition. This is the core improvement of the present invention. By introducing nitrous oxide (N2O) gas into a conventional silicon nitride (SiN) deposition process (typically using DCS and NH3), the dielectric layer formed is no longer a simple silicon nitride, but a silicon oxynitride (SiON). Nitrous oxide decomposes at high temperatures, providing an oxygen source, which reacts with the silicon source and nitrogen source from DCS and NH3. The SiON film formed can effectively reduce the number of defects and charge traps that are easily generated in the original silicon nitride film, such as dangling bonds, due to the incorporation of an appropriate amount of oxygen. The introduction of oxygen helps to passivate these defects, forming a dielectric film with more stable chemical bonds and a denser structure. Therefore, compared to the conventional SiN layer, the SiON layer has better electrical insulation properties and stronger charge blocking ability. This significantly reduces the probability of electrons tunneling from the floating gate 101 to the control gate 105 under the influence of an electric field during a read operation, effectively suppressing the read disturb effect. Specifically, it prevents cells storing a "0" from erroneously flipping to a "1" due to electron loss. This step directly improves the overall quality of the ONO dielectric layer, thereby enhancing the reliability and data retention characteristics of the flash memory.

[0037] In some embodiments, in step 2, forming the silicon oxynitride layer 103 further includes pre-introducing ammonia gas and nitrous oxide gas into the reaction chamber before introducing the dichlorosilane gas. This pre-introduction helps stabilize the atmosphere within the reaction chamber, removes any residual impurities that may be present, and creates favorable initial conditions for the subsequent introduction of dichlorosilane and the uniform, high-quality growth of the silicon oxynitride film, thereby ensuring uniformity of the film composition and interface quality.

[0038] In some embodiments, in step 2, ammonia and nitrous oxide gases are pre-gassed for one minute before dichlorosilane gas is introduced. This specific pre-gassed time, optimized through process optimization, effectively prepares the reaction environment without significantly increasing the overall process time, ensuring stability and repeatability of subsequent SiON film deposition.

[0039] In some embodiments, in step 2, the chemical vapor deposition reaction temperature is 750° C. to 810° C. Within this temperature range, the reactant gases can fully decompose and chemically react to form a dense silicon oxynitride film, while avoiding other negative effects that may be caused by excessively high temperatures, such as undesirable diffusion or stress.

[0040] In some embodiments, in step 2, the reaction pressure of chemical vapor deposition is 0.25 Torr to 0.45 Torr. An appropriate reaction pressure helps control the mean free path of gas molecules and the reaction rate, ensuring uniformity and quality of thin film growth.

[0041] In some embodiments, in step 2, the reaction pressure of the chemical vapor deposition is 0.3 Torr. This specific pressure value is a preferred process parameter, and a silicon oxynitride film with good morphology and electrical properties can be obtained under this pressure.

[0042] In some embodiments, in step 2, the flow rate of ammonia gas is 0.04 L to 0.08 L. As one of the nitrogen sources, the flow rate of ammonia gas directly affects the nitrogen content in the silicon oxynitride film and the stoichiometric ratio of the film.

[0043] In some embodiments, in step 2, the flow rate of ammonia gas is 0.06 L, which is a specific preferred flow rate value that helps to obtain a silicon oxynitride film with a desired composition.

[0044] In some embodiments, in step 2, the flow rate of nitrous oxide gas is 0.17 L to 0.37 L. As an oxygen source, the flow rate of nitrous oxide controls the oxygen content in the film, which is crucial for adjusting the dielectric constant and defect density of the film.

[0045] In some embodiments, in step 2, the flow rate of nitrous oxide gas is 0.27 L. This specific flow rate value is a better choice for optimizing the performance of SiON film.

[0046] In some embodiments, in step 2, the flow rate of dichlorosilane gas is 0.12 L to 0.18 L. Dichlorosilane is the main silicon source, and its flow rate determines the growth rate and silicon content of the film.

[0047] In some embodiments, in step 2, the flow rate of the dichlorosilane gas is 0.15 L. This flow rate is a proven optimal value that helps achieve a stable thin film deposition process.

[0048] In some embodiments, in step 2, the reaction time of chemical vapor deposition is 20 minutes to 40 minutes. The reaction time determines the thickness of the silicon oxynitride film formed and needs to be precisely controlled according to the target thickness.

[0049] Step 3: forming a second oxide layer 104 on the silicon oxynitride layer 103, forming a Figure 4 The second oxide layer 104 is usually used as the top oxide in the ONO structure, covering the SiON layer and contacting the subsequently formed control gate 105. It further enhances the insulation performance of the entire ONO dielectric stack and protects the underlying SiON layer.

[0050] In some embodiments, the method further includes: after step three, forming a control gate 105 (CG) on the second oxide layer 104, forming Figure 5 The structure shown. This complete structure, namely floating gate 101 / first oxide layer 102 / silicon oxynitride layer 103 / second oxide layer 104 / control gate 105, forms a high-performance flash memory cell. The improved ONO dielectric layer (particularly the middle SiON layer) effectively isolates floating gate 101 from control gate 105, maintaining the charge stored in floating gate 101, thereby ensuring the normal operation of the flash memory and significantly improving its read disturb resistance.

[0051] The ONO dielectric layer prepared using the above method significantly improves the quality of the dielectric layer because the intermediate layer uses silicon oxynitride (SiON) instead of traditional silicon nitride (SiN). Compared with SiN films, SiON films have lower internal trap density and better insulation performance. This is attributed to the introduction of oxygen, which effectively reduces defects in the Si-N network. Therefore, during the read operation (i.e., the control gate 105 applies a read voltage), it is more difficult for electrons in the floating gate 101 to tunnel through the entire ONO stack to reach the control gate 105. This directly leads to a significant improvement in the read interference phenomenon.

[0052] Specifically, when a flash memory performs a read operation on a specific address (CG terminal) for a long time, the FG electrons in the traditional ONO structure are easily lost to the CG due to the voltage applied to the control gate 105. This causes the threshold voltage of the cell storing "0" (with a large number of electrons in the FG) to drop, ultimately causing it to be mistakenly recognized as "1". The present invention effectively suppresses this electron loss from the FG to the CG by forming a high-quality SiON layer.

[0053] See also Figure 6 and Figure 7 Experimental data shows that when flash memory cells fabricated using the present invention are subjected to accelerated aging tests at elevated temperatures, such as 85°C, and subjected to oxide stress on the control gate 105, for example, by applying a voltage of 9.0 volts to the control gate 105, the magnitude of the abnormal increase in current (i.e., threshold voltage drift) in cells storing logic "0" is significantly reduced. This means that even under harsh read conditions, the memory cell can better maintain its original storage state, significantly reducing the probability of read disturb failures, thereby improving the reliability and durability of the entire flash memory product. This improvement is particularly important for enhancing the performance of high-density flash memory at advanced process nodes.

[0054] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for forming an ONO dielectric layer in a flash memory, characterized in that: At least: Step 1: providing a substrate and forming a first oxide layer on the substrate; Step 2: forming a silicon oxynitride layer on the first oxide layer, wherein forming the silicon oxynitride layer comprises introducing a mixed gas comprising dichlorosilane gas, ammonia gas, and nitrous oxide gas into a reaction chamber for chemical vapor deposition; and Step three: forming a second oxide layer on the silicon oxynitride layer.

2. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step one, the first oxide layer is formed on a floating gate pre-formed on the substrate.

3. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: The method further includes: after step three, forming a control gate on the second oxide layer.

4. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step 2, the forming of the silicon oxynitride layer further includes: before introducing the dichlorosilane gas, pre-introducing the ammonia gas and the nitrous oxide gas into the reaction chamber.

5. The method for forming an ONO dielectric layer in a flash memory according to claim 4, wherein: In step 2, before the dichlorosilane gas is introduced, the time for pre-introducing ammonia gas and nitrous oxide gas is 1 minute.

6. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step 2, the reaction temperature of the chemical vapor deposition is 750° C. to 810° C.

7. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step 2, the chemical vapor deposition reaction pressure is 0.25 Torr to 0.45 Torr.

8. The method for forming an ONO dielectric layer in a flash memory according to claim 7, wherein: In step 2, the reaction pressure of the chemical vapor deposition is 0.3 Torr.

9. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step 2, the flow rate of the ammonia gas is 0.04 liter to 0.08 liter.

10. The method for forming an ONO dielectric layer in a flash memory according to claim 9, wherein: In step 2, the flow rate of the ammonia gas is 0.06 liter.

11. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step 2, the flow rate of the nitrous oxide gas is 0.17 liters to 0.37 liters.

12. The method for forming an ONO dielectric layer in a flash memory according to claim 11, wherein: In step 2, the flow rate of the nitrous oxide gas is 0.27 liters.

13. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step 2, the flow rate of the dichlorosilane gas is 0.12 liters to 0.18 liters.

14. The method for forming an ONO dielectric layer in a flash memory according to claim 13, wherein: In step 2, the flow rate of the dichlorosilane gas is 0.15 liters.

15. The method for forming an ONO dielectric layer in a flash memory according to claim 1, wherein: In step 2, the reaction time of the chemical vapor deposition is 20 minutes to 40 minutes.

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