Semiconductor device, preparation method, integrated circuit and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method, an integrated circuit and electronic equipment, and the semiconductor device comprises a channel layer, a dielectric layer above the channel layer, a source region and a drain region which are located at the two opposite sides of the channel layer and the dielectric layer, and a metal gate structure. The dielectric layer comprises an annular first dielectric region and second dielectric regions located on the two opposite sides of the first dielectric region, and the metal gate structure is wrapped in the first dielectric region. In the preparation process, a plurality of sub-sacrificial layers with different Ge material concentrations are stacked to form a sacrificial laminated layer, and the positions of the sub-sacrificial layers with different Ge material concentrations are controlled to control the etching rates of different positions on the periphery of the sacrificial laminated layer, so that the shape of the metal gate structure is controlled, and the metal gate structure is formed. The risk of short circuit between the metal gate structure and the source electrode region / drain electrode region at the top surface and the bottom surface is reduced, the dielectric capacitance of the second dielectric region at the position is effectively reduced, and the delay of an RC signal from the metal gate structure to the source electrode region / drain electrode region can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method, an integrated circuit, and an electronic device. Background Art

[0002] With the continuous development of semiconductor technology, the manufacturing process of semiconductor devices is becoming increasingly advanced. Currently, semiconductor devices have achieved micron and nanometer-level manufacturing, and in the future, they will further develop to the sub-nanometer level. This means that the size of transistors will be even smaller than it is today, and more transistors will be integrated on the same chip (also known as an integrated circuit). The integration density of chips will continue to increase, and the integrated functions will become increasingly powerful.

[0003] However, as transistor size shrinks, the short channel effect (SCE) of transistors becomes more and more obvious. In order to suppress SCE, it is necessary to improve the control capability of the gate. Figure 1a , the traditional transistor adopts a planar structure, also known as a planar field-effect transistor (PFET). The channel of the PFET is flat on the bottom surface of the gate, and the contact area between the two is small, which makes the electrostatic control effect from the gate to the channel not ideal. Based on this, refer to Figure 1b Compared to PFET, the gate of FinFET spans three sides of the channel, which greatly increases the contact area between the gate and the channel, and the electrostatic control from the gate to the channel is relatively improved. However, as the size of the transistor shrinks to below 7nm, the SCE of FinFET is aggravated, and the electrostatic control of FinFET is not enough to suppress the aggravated SCE, which prompts the transistor to change from a tri-gate architecture to a full-ring gate architecture. Figure 1c , so the gate-all-around FET (GAAFET) appeared. The gate of GAAFET surrounds the four sides of the channel, which further increases the contact area between the gate and the channel, thereby providing better electrostatic control characteristics than FinFET.

[0004] However, the current mainstream GAAFET has the risk of short circuit between the gate and the source / drain, and has the problem of large effective capacitance. The larger the dielectric capacitance between the gate and the source / drain, the longer the signal transmission delay between the gate and the source / drain, which is less conducive to improving the switching performance of the GAAFET.

[0005] In summary, how to reduce the risk of short circuit between the gate and the source / drain and reduce the dielectric capacitance of semiconductor devices is a technical problem that urgently needs to be solved in the GAAFET field. Summary of the Invention

[0006] Embodiments of the present application provide a semiconductor device, a manufacturing method, an integrated circuit, and an electronic device for reducing the risk of short circuit between the gate and the source / drain, and reducing the dielectric capacitance of the semiconductor device.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect, the present application provides a semiconductor device, which may specifically include: a channel layer, a dielectric layer located above the channel layer, a source region and a drain region located on opposite sides of the channel layer and the dielectric layer, and a metal gate structure. The dielectric layer includes a first annular dielectric region and a second dielectric region located on opposite sides of the first dielectric region, and the metal gate structure is wrapped in the first dielectric region. The surface of the metal gate structure facing the channel layer has a first spacing from the source region or the drain region, and the side of the metal gate structure has a minimum spacing from the source region or the drain region, and the first spacing is greater than or equal to the minimum spacing.

[0009] By using the above semiconductor device, it is possible to ensure that the second dielectric region has a larger length at the edge position, so that the second dielectric region has good electrical insulation performance at the edge position, reducing the risk of short circuit between the metal gate structure and the source / drain region at this position. At the same time, increasing the distance between the metal gate structure and the source / drain region at this position can reduce the dielectric capacitance, thereby reducing the signal transmission delay and improving the switching performance of the semiconductor device.

[0010] In one possible design, the dielectric constant of the first dielectric region is higher than that of the second dielectric region. For example, the first dielectric region is made of a high-dielectric material, and the second dielectric region is made of a low-dielectric material. With this design, by surrounding the first metal gate structure with a high-dielectric material, it can be used to replace the gate oxide layer, increasing the thickness of the gate oxide layer and suppressing tunneling leakage current generated by the first metal gate structure. Furthermore, by placing a low-dielectric material between the high-dielectric material and the source or drain region, the relatively small dielectric constant of the low-dielectric material can be used to reduce dielectric capacitance, minimize RC signal delay, and increase the operating frequency of the semiconductor device.

[0011] In one possible design, a maximum spacing exists between the side of the metal gate structure and the source / drain region, which can be equal to the first spacing. This design maximizes the length of the second dielectric region at the edge, ensuring good electrical insulation at the edge, reducing the risk of short circuits between the metal gate structure and the source / drain region at this location. Furthermore, increasing the spacing between the metal gate structure and the source / drain region at this location can reduce dielectric capacitance, thereby reducing signal transmission delay and improving the switching performance of the semiconductor device.

[0012] In one possible design, the side of the metal gate structure can protrude toward the source / drain region. This design can reduce the number of breakdown points in the second dielectric region and reduce the probability of breakdown from the metal gate structure to the source or drain region.

[0013] In one possible design, the spacing between the side surfaces of the metal gate structure and the source / drain regions is uniform at all locations. This design ensures that the second dielectric region has a relatively uniform length at all locations, resulting in good electrical insulation performance for the entire second dielectric region. This reduces the risk of short circuits between the metal gate structure and the source / drain regions, while also ensuring a relatively uniform spacing between the metal gate structure and the source / drain regions, thereby improving the overall gate control capability of the channel layer 200.

[0014] In one possible design, a semiconductor device includes a substrate, N+1 aforementioned channel layers, N aforementioned dielectric layers, and N aforementioned first metal gate structures. The N+1 channel layers and the N dielectric layers are alternately stacked above the substrate, and the N first metal gate structures are enclosed in the first dielectric regions of the N dielectric layers, where N is a positive integer. With this design, by having one more channel layer than the sacrificial layer, the channel layer can be exposed at the topmost layer, facilitating the subsequent expansion of more components on the channel layer.

[0015] In one possible design, the N metal gate structures include a first metal gate structure and a second metal gate structure. A first average spacing is defined between a side surface of the first metal gate structure and the source or drain region, and a second average spacing is defined between a side surface of the second metal gate structure and the source or drain region. The first average spacing and the second average spacing have different values. Using this design, the average length of the second dielectric layer between the first metal gate structure and the source / drain region, and the average length of the second dielectric layer between the second metal gate structure and the source / drain region, can be set to be opposite to the resistance mismatch trend, thereby balancing the RC signal delay from the first metal gate structure and the second metal gate structure to the source / drain region.

[0016] In one possible design, the average spacing between the side surfaces of each of the N metal gate structures and the source or drain regions is different. This design balances the RC signal delays from different metal gate structures to the source / drain regions.

[0017] In one possible design, the average spacing between the side surfaces of each metal gate structure and the source or drain region increases along the stacking direction. With this design, when the signal terminal is located at the top of each channel layer, the resistance of each channel layer can be kept relatively consistent, thereby balancing the RC signal delay from different metal gate structures to the source / drain region.

[0018] In a further possible design, the semiconductor device further includes an insulating layer, a third metal gate structure, and a protective layer. The insulating layer and the third metal gate structure are sequentially stacked above the topmost channel layer, and the protective layer surrounds the third metal gate structure on three sides except the insulating layer. With this design, the semiconductor device can be encapsulated from above to protect its internal structure.

[0019] In a second aspect, the present application provides a method for preparing a semiconductor device, comprising: first, alternately forming a stacked channel layer and a sacrificial stack; then, etching the outer portion of the sacrificial stack to form a first cavity; then, depositing a second dielectric material in the first cavity to form a second dielectric region; then, forming a source region and a drain region on either side of the channel layer and the second dielectric region, respectively; then, etching the remaining sacrificial layer to form a second cavity; and finally, sequentially depositing a first dielectric material and a metal gate material in the second cavity to form a first dielectric region and a metal gate structure wrapped by the first dielectric region. The sacrificial stack comprises at least two stacked sub-sacrificial layers, wherein the concentration of Ge material in adjacent sub-sacrificial layers is different, such that a first spacing exists between the surface of the formed metal gate structure facing the channel layer and the source region or the drain region, and a minimum spacing exists between the side of the metal gate structure and the source region or the drain region, wherein the first spacing is greater than or equal to the minimum spacing.

[0020] By adopting the above-mentioned method for preparing semiconductor devices, a sacrificial stack is formed by stacking multiple sub-sacrificial layers with different Ge material concentrations. By controlling the positions of the sub-sacrificial layers with different Ge material concentrations, the etching rates at different positions around the sacrificial stack are controlled, thereby controlling the shape of the metal gate structure, reducing the risk of short circuit between the metal gate structure and the source / drain region at the top and bottom surfaces, and effectively reducing the dielectric capacitance of the second dielectric region at this position, thereby reducing the delay of the RC signal from the metal gate structure to the source / drain region and improving the switching performance of the semiconductor device.

[0021] In one possible design, the at least two sub-sacrificial layers include a first sub-sacrificial layer and a second sub-sacrificial layer. The concentration of Ge material in the first sub-sacrificial layer is higher than that in the second sub-sacrificial layer, the thickness of the first sub-sacrificial layer is greater than that of the second sub-sacrificial layer, and the first sub-sacrificial layer is located between the second sub-sacrificial layer and the channel layer. With this design, by controlling the concentration of Ge material in the two sub-sacrificial layers, the etching rates of the two sub-sacrificial layers can be controlled, increasing the etching amount at the upper and lower edges of the etched surface of the sacrificial stack 700, and controlling the final morphology of the etched surface of the sacrificial stack 700 and the first cavity.

[0022] In one possible design, alternately stacking channel layers and sacrificial layers includes alternately forming a stack of channel layers and sacrificial layers, including alternately forming N+1 channel layers and N sacrificial layers on a substrate, where N is a positive integer. With this design, by having one more channel layer than sacrificial layer, the channel layer can be exposed at the topmost layer, facilitating the subsequent expansion of more components on the channel layer.

[0023] In a further possible design, the N-layer sacrificial stack includes a first sacrificial stack and a second sacrificial stack, and the average concentration of Ge material in the first sacrificial stack is different from the average concentration of Ge material in the second sacrificial stack. Using the above design, the first sacrificial stack can be used to form a first metal gate structure, and the second sacrificial stack can be used to form a second metal gate structure. The average length of the second dielectric layer between the first metal gate structure and the source / drain region, and the average length of the second dielectric layer between the second metal gate structure and the source / drain region, can be set to be opposite to the resistance mismatch trend to balance the RC signal delay from the first metal gate structure and the second metal gate structure to the source / drain region.

[0024] In a further possible design, the average concentration of Ge material in each sacrificial stack increases along the stacking direction. With this design, when the signal terminal is placed at the top of each channel layer, the resistance of each channel layer can be kept relatively consistent, thereby balancing the RC signal delay from different metal gate structures to the source / drain regions.

[0025] A further possible design, after alternately forming the stacked channel layers and sacrificial layers, further includes: sequentially forming an insulating layer and a third metal gate structure above the topmost channel layer; and forming a protective layer on three sides of the third metal gate structure, excluding the insulating layer. With this design, the semiconductor device can be packaged above to protect its internal structure.

[0026] In a third aspect, the present application provides an integrated circuit, comprising a circuit board and one or more semiconductor devices as designed in the first aspect or any one of the first aspects, wherein the one or more semiconductor devices are arranged on the circuit board.

[0027] In one possible design, the integrated circuit may further include a signal input / output interface (IO) circuit disposed on a circuit board, the IO circuit being located on the periphery of the semiconductor device. The devices included in the IO circuit are typically formed simultaneously with the semiconductor device, and the two have the same film layer stacking relationship. Therefore, the IO circuit may include a sacrificial stack that is not selectively etched away, the sacrificial stack being located in the same film layer as the metal gate structure in the semiconductor device. The sacrificial stack may specifically include at least two stacked sub-sacrificial layers, with the concentration of Ge material in adjacent sub-sacrificial layers being different.

[0028] There are various ways to arrange the sub-sacrificial layers within the sacrificial stack, and the details can be referred to the description of the first aspect and are not described in detail here. For example, in one possible design, the sacrificial stack may specifically include a first sub-sacrificial layer and a second sub-sacrificial layer, the concentration of Ge material in the first sub-sacrificial layer is higher than the concentration of Ge material in the second sub-sacrificial layer, the thickness of the first sub-sacrificial layer is greater than the thickness of the second sub-sacrificial layer, and the first sub-sacrificial layer is located between the second sub-sacrificial layer and the channel layer.

[0029] In a fourth aspect, the present application provides an electronic device comprising a housing and an integrated circuit as in the third aspect or any one of the designs of the third aspect above, wherein the integrated circuit is disposed in the housing, for example, can be encapsulated in the housing, to achieve protection of the integrated circuit.

[0030] The technical effects that can be achieved in the above-mentioned second to fourth aspects can refer to the description of the beneficial effects in the above-mentioned first aspect, and will not be repeated here one by one. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a Schematic diagram of the structure of a PFET;

[0032] Figure 1b A schematic diagram of the structure of a FinFET;

[0033] Figure 1c A schematic diagram of the structure of a GAAFET;

[0034] Figure 2 A schematic diagram of a possible application scenario provided by an embodiment of the present application;

[0035] Figure 3a A schematic diagram of the partial structure of a gate-all-around semiconductor device provided to the industry;

[0036] Figure 3b A schematic flow chart of a method for preparing a gate-all-around semiconductor device provided to the industry;

[0037] Figure 4 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0038] Figure 5 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0039] Figure 6a A schematic diagram of another sacrificial stack formed during the fabrication of a semiconductor device according to an embodiment of the present application;

[0040] Figure 6b A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0041] Figure 7a A schematic diagram of another sacrificial stack formed during the fabrication process of the semiconductor device provided in an embodiment of the present application;

[0042] Figure 7b A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of the partial structure of another all-around gate semiconductor device provided to the industry;

[0044] Figure 9a A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0045] Figure 9b A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0046] Figure 9c A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0047] Figure 10 A schematic flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0048] Figure 11 A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0049] Figure 12 A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0050] Figure 13 A schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 100-substrate, 200-channel layer, 300-dielectric layer, 310-first dielectric region, 320-second dielectric region, 400-metal gate structure, 401-top surface, 402-bottom surface, 403-side surface, 410-first metal gate structure, 420-second metal gate structure, 430-third metal gate structure, 500-source region, 600-drain region, 701-sacrificial layer, 700-sacrificial stack, 710-first sub-sacrificial layer, 720-second sub-sacrificial layer, 730-third sub-sacrificial layer, 740-fourth sub-sacrificial layer, 800-insulating layer, 900-protective layer, 110-isolation layer. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0054] In the following description of this application, "plurality" means two or more. " / " means or, for example, "A / B" means A or B. The word "optionally" or "exemplarily" is used to indicate an example, illustration or description. Any embodiment or design described in this application as "example" or "optional" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Alternatively, it can be understood that the use of the word "example" or "optional" is intended to present concepts in a specific way and does not constitute a limitation on this application.

[0055] In addition, the various numbers involved in this application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. For example, the terms "first", "second", "third" and the like are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. In addition, the terms "comprise" and "have" and any of their variations are intended to cover non-exclusive inclusions, for example, comprising a series of steps or units. Methods, products or equipment are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0056] Furthermore, the following content is only one possible embodiment provided by this application. The structure or method of this embodiment can also be extended to any device or component that requires dielectric capacitors. Moreover, as the system architecture evolves and new scenarios emerge, the structure or method provided by this application is also applicable to similar technical problems, and this application does not specifically limit this.

[0057] Below, some of the terms used in this application are first explained. It should be noted that these explanations are for the purpose of facilitating understanding by those skilled in the art and do not limit the scope of protection claimed in this application.

[0058] 1. Dielectric Constant and Dielectric Capacitance

[0059] The dielectric constant is the main parameter that reflects the dielectric properties or polarization properties of piezoelectric material dielectrics under the action of an electrostatic field, usually represented by ε. When two conductors are separated by a piezoelectric material dielectric (referred to as a dielectric plate), the dielectric capacitance between the two conductors can be expressed as the following formula (1.1):

[0060]

[0061] Where C is the dielectric capacitance, A is the area of ​​the dielectric plate, and d is the thickness of the dielectric plate.

[0062] The above formula (1.1) can also be called the capacitance law. According to formula (1.1), when the area and thickness of the dielectric plate are fixed, the dielectric capacitance and the dielectric constant are positively correlated. The smaller the dielectric constant, the smaller the dielectric capacitance, which in turn reduces the switching delay between the two conductors. Therefore, reducing the dielectric constant is an effective means of improving the switching performance of semiconductor devices.

[0063] 2. Sacrificial Layer

[0064] Sacrificial layer technology is one of the manufacturing processes that distinguishes micro-electro-mechanical systems (MEMS) from traditional integrated circuits (ICs). This technology uses a thin film of corrodible or etchable material as an intermediate layer between a structural layer and a substrate, or between two structural layers. After the structural layer is patterned, the intermediate layer is removed using wet or dry etching to create a cavity or movable microstructure. Because the removed intermediate layer only serves as a separation layer, it is called a sacrificial layer.

[0065] 3. Resistance Law

[0066] The resistance law of metal film can be expressed as the following formula (12):

[0067]

[0068] Where r is the resistance of the metal film, ρ is the resistivity of the metal film, l is the length of the metal film, and s is the cross-sectional area of ​​the metal film.

[0069] According to formula (1.2), when the resistivity and thickness of the metal film are fixed, the longer the metal film is, the greater the resistance of the metal film is. In other words, the resistance of the metal film is positively correlated with its length.

[0070] The previous text introduced some of the terms involved in this application. The following text introduces the possible application scenarios of this application.

[0071] The semiconductor device provided in this application can be integrated into an integrated circuit, which can be applied to electronic devices. Figure 2, a schematic diagram of a possible application scenario of the present application is shown as an example, which takes the integration of a semiconductor device inside an electronic device as an example. The electronic device may include a housing, a circuit board arranged in the housing, and a semiconductor device fixed on the circuit board. Optionally, there may be multiple semiconductor devices, and multiple semiconductor devices integrated on the same circuit board may constitute an integrated circuit. In addition, a signal input and output interface (IO) circuit is generally provided on the periphery of the multiple semiconductor devices on the circuit board. The devices contained in the IO circuit are usually formed at the same time as the semiconductor devices, and the two have the same film layer stacking relationship.

[0072] Exemplarily, the above-mentioned electronic devices can be any type of device with processing capabilities, such as smart terminals (mobile phones, computers, tablets, PDAs, desktops, headphones, speakers, wearable devices, vehicle-mounted devices, virtual reality devices, augmented reality devices, etc.), smart home devices (such as TVs, TV set-top boxes, sweeping robots, smart desk lamps, smart broadband, audio systems, smart lighting systems, electrical control systems, home background music, home theater systems, intercom systems, or video surveillance, etc.), smart manufacturing equipment (such as industrial equipment), smart transportation equipment (such as unmanned vehicles, smart cars, electric cars, digital cars, automated guided vehicles (AGVs), unmanned transport vehicles, trucks, ships, airplanes, drones, trains, subways, or high-speed railways, etc.), robots (navigation robots, autonomous food delivery robots, medical robots or industrial robots, etc.) or surveying and mapping equipment, etc.

[0073] It should be understood that the above application scenarios are only examples, and the semiconductor devices provided in this application can also be applied to other possible scenarios, not limited to the scenarios exemplified above. For example, semiconductor devices can also be used in telecommunications equipment, such as wireless networks, fixed networks, servers, and cloud servers, etc., to increase the speed of providing network services to terminal devices. For another example, semiconductor devices can also be used in electronic devices, such as processors, memories, controllers, input / output modules, and chip modules, etc., to provide switching functions, inverting functions, computing functions, and control functions. For another example, semiconductor devices can also be used in smart life scenarios, such as automatic following trolley cases, smart dining chairs, or smart travel tools, etc. They are not listed here one by one.

[0074] It should be noted that the application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application.

[0075] As described in the background technology, the current mainstream semiconductor devices are gradually evolving from a tri-gate architecture to a full-gate architecture. Figure 3aA gate-all-around semiconductor device provided by the industry includes a channel layer 200 disposed on a substrate 100, a dielectric layer 300 disposed on the channel layer 200, a source region 500 and a drain region 600 disposed on opposite sides of the channel layer 200 and the dielectric layer 300, and a metal gate structure 400. The dielectric layer 300 includes a first dielectric region 310 and a second dielectric region 320 disposed on opposite sides of the first dielectric region 310. The first dielectric region 310 is annular in shape, and the metal gate structure 400 is wrapped in the first dielectric region 310. The first dielectric region 310 is made of a high-dielectric (high-K) material and is primarily used to replace the gate oxide layer, increase the gate oxide thickness, and suppress gate tunneling leakage current. The second dielectric region 320 is made of a low-dielectric material (low K). The low-dielectric material has a relatively small dielectric constant, which can reduce the dielectric capacitance and the delay of the resistance-capacitance (RC) signal from the metal gate structure 400 to the source region 500 / drain region 600, thereby improving the operating frequency of the GAAFET.

[0076] Reference Figure 3b The specific process of a method for preparing a ring-gated semiconductor device provided by the industry includes: first, forming an alternating stack of channel layers 200 and sacrificial layers 701; then, performing selective etching to etch the outer portion of the sacrificial layer 701 to a fixed size (for example, 3nm-6nm), thereby forming a first cavity; then, filling the first cavity with a low-dielectric material, and removing excess low-dielectric material on the sidewalls, leaving only the second dielectric region 320 in the first cavity, thereby exposing the channel layer 200; then, forming a source region 500 and a drain region 600 on both sides of the channel layer 200 and the second dielectric region 320 respectively; then, etching the remaining sacrificial layer 701 to form a second cavity; finally, depositing a high-dielectric material and a metal gate material in the second cavity in sequence to form a first dielectric region 310 and a metal gate structure 400 wrapped by the first dielectric region 310.

[0077] In the above preparation process, the channel layer 200 is generally made of Si material, and the sacrificial layer 701 is generally made of SiGe material. In the process of selectively etching the SiGe material to form the first cavity, due to the mass transport effect, the etching amount in the middle position of the SiGe material is larger, and the etching amount in the upper and lower edge positions is smaller. Finally, the etched surface of the SiGe material presents a circular arc shape (rounding) with the middle position concave inward, which affects the shape of the first cavity to be a circular arc shape convex toward the sacrificial layer 701, resulting in the second dielectric area 320 formed by subsequent filling being similar to a half-moon shape. At the edge position of the half-moon-shaped second dielectric area 320, that is, Figure 3aAt the dotted circle, good electrical insulation cannot be guaranteed, resulting in a greater risk of short circuits between the metal gate structure 400 and the source / drain regions 500 / 600. Furthermore, according to formula (1.1), the proximity of the metal gate structure 400 to the source / drain regions 500 / 600 at the edge of the crescent-shaped second dielectric region 320 increases dielectric capacitance, thereby increasing signal transmission delay. Furthermore, the shape of the first cavity affects the shape of the metal gate structure 400, weakening gate control at the corners of the channel layer 200.

[0078] In view of this, the present application provides a semiconductor device, which adopts a sacrificial stack formed by stacking multiple sub-sacrificial layers with different Ge material concentrations. By controlling the positions of the sub-sacrificial layers with different Ge material concentrations, the etching rates at different positions around the sacrificial stack are controlled, and then the shape of the metal gate structure is controlled, thereby reducing the risk of short circuit between the metal gate structure and the source / drain region at the top and bottom surfaces, and effectively reducing the dielectric capacitance of the second dielectric region at this position, which can reduce the delay of the RC signal from the metal gate structure to the source / drain region.

[0079] The semiconductor device proposed in this application is described in detail below with reference to specific drawings.

[0080] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0081] Furthermore, in this application, the terms "greater than," "less than," and "equal to" do not imply absolute correlations; a certain degree of engineering error is permitted. "Thickness" does not imply absolute values; a certain degree of engineering error is permitted. Furthermore, the positional relationship between two components described in the drawings and textual descriptions does not imply an absolute relationship; a certain degree of engineering error is permitted.

[0082] Reference Figure 4 A semiconductor device provided in the present application may be, for example, a GAAFET, which includes a channel layer 200, a dielectric layer 300 located above the channel layer 200, a source region 500 and a drain region 600 located on opposite sides of the channel layer 200 and the dielectric layer 300, and a metal gate structure 400.

[0083] In the present application, the dielectric layer 300 includes a first dielectric region 310 and a second dielectric region 320 disposed on opposite sides of the first dielectric region 310. The first dielectric region 310 and the second dielectric region 320 are regions composed of dielectric materials, which can also be called insulating materials. Dielectric materials can be used to isolate charged conductors or conductors with different potentials, allowing current to flow in a certain direction. The greater the resistivity of the dielectric material, the greater the dielectric constant and the better the insulation performance. Optionally, the dielectric constant of the first dielectric region 310 can be higher than the dielectric constant of the second dielectric region 320. For example, the first dielectric region 310 is composed of a high dielectric material, and the second dielectric region 320 is composed of a low dielectric material. The high dielectric material refers to a material with a high dielectric constant, for example, it can include but is not limited to aluminum oxide (AlO), titanium dioxide (TiO2), aluminum oxide-silicon nitride composite materials, ferroelectric materials, polyethylene or polystyrene, etc. The dielectric constant of these materials is very high, usually above 10. Similarly, low-dielectric materials refer to materials with low dielectric constants, such as but not limited to silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxycarbide (SiOC), or silicon oxynitride (SiCN). The dielectric constants of these materials are relatively low, usually around 3 to 5. The first dielectric region 310 is annular, which can be understood as the first dielectric region 310 being a ring-shaped structure connected end to end. The outer contour of the ring structure is consistent with the shape of the metal gate structure 400. The shape of the contact surface between the ring structure and the second dielectric region 320 is determined by the selective etching of the sacrificial stack during the preparation process, which will be described in detail later. The metal gate structure 400 is wrapped in the first dielectric region 310. By surrounding the metal gate structure 400 with a high-dielectric material, it can be used to replace the gate oxide layer, increase the thickness of the gate oxide layer, and suppress the generation of tunneling leakage current in the metal gate structure 400. By placing the low dielectric material between the high dielectric material and the source region 500 / the drain region 600 , the relatively small dielectric constant of the low dielectric material can be used to reduce dielectric capacitance, reduce RC signal delay, and increase the operating frequency of the semiconductor device.

[0084] In the present application, the metal gate structure 400 is used to form the gate of a semiconductor device and is typically made of a metal material, such as, but not limited to, aluminum, tungsten, molybdenum, silver, aluminum-copper, and titanium-aluminum alloys. The metal gate structure 400 can be prepared in a variety of ways. For example, the gate metal material can be first filled into the corresponding cavity through a preparation process such as physical vapor deposition, electron beam evaporation, or magnetron sputtering, and then the surface can be flattened through chemical-mechanical polishing (CMP) to obtain a smooth metal gate structure.

[0085] Specifically, refer to Figure 5In the present application, the preparation process of the metal gate structure 400 and the dielectric layer 200 specifically includes: first, forming an alternating stack of channel layers 200 and sacrificial stacks 700; then, performing selective etching to etch the outer portion of the sacrificial stack 700 to a fixed size (e.g., 3nm-6nm), thereby forming a first cavity; then, filling the first cavity with a low-dielectric material, and removing excess low-dielectric material on the sidewalls, leaving only the second dielectric region 320 in the first cavity, thereby exposing the channel layer 200; then, forming a source region 500 and a drain region 600 on both sides of the channel layer 200 and the second dielectric region 320, respectively; then, etching the remaining sacrificial stack 700 to form a second cavity; finally, depositing a high-dielectric material and a metal gate material in the second cavity in sequence to form a first dielectric region 310 and a metal gate structure 400 surrounded by the first dielectric region 310.

[0086] In the present application, the principle that the etching rate of SiGe material changes with the change of Ge concentration is utilized, and multiple layers of SiGe materials with different Ge material concentrations and different thicknesses are grown as sub-sacrificial layers to form a sacrificial stack, so that the sacrificial stack 700 includes at least two stacked sub-sacrificial layers, and the concentrations of Ge materials in two adjacent sub-sacrificial layers are set to be different. According to the mass transport effect, the etching amount in the middle of the sacrificial stack 700 is greater, and the etching amount at the upper and lower edge positions is less. By controlling the concentration of Ge materials in different sub-sacrificial layers, the etching rates of different sub-sacrificial layers can be controlled, the etching amount of the etched surface of the sacrificial stack 700 at the upper and lower edge positions can be increased, and the final morphology of the etched surface of the sacrificial stack 700 and the first cavity can be controlled. Reference Figure 4 , so that there is a first spacing d1 between the surface of the finally deposited metal gate structure 400 facing the channel layer 200 and the source region 500 / drain region 600, and there is a minimum spacing dmin between the side surface 403 of the metal gate structure 400 and the source region 500 / drain region 600, and the first spacing d1 is greater than or equal to the minimum spacing dmin. When the sacrificial stack 700 is sandwiched between the two channel layers 200, the surface of the metal gate structure 400 facing the channel layer 200 refers to the top surface 401 and the bottom surface 402 of the metal gate structure 400. By controlling the etched surface of the sacrificial stack 700 and the final morphology of the first cavity, it can be ensured that the second dielectric region 320 has a larger length at the edge position, that is, Figure 4 At the dotted circle in the middle, the second dielectric region 320 has good electrical insulation performance at the edge position, reducing the risk of short circuit between the metal gate structure 400 and the source region 500 / drain region 600 at this location. At the same time, increasing the distance between the metal gate structure 400 and the source region 500 / drain region 600 at this location can reduce the dielectric capacitance, thereby reducing the signal transmission delay and improving the switching performance of the semiconductor device.

[0087] In the present application, a sacrificial stack is formed by using multiple layers of sub-sacrificial layers with different Ge material concentrations. The sacrificial stack can also be increased as a whole. After a certain sub-sacrificial layer reaches the critical thickness (critical thickness) of SiGe single crystal growth, SiGe with another Ge material concentration is grown to increase the controllable total growth height of the sacrificial stack.

[0088] Reference Figure 5 In some embodiments of the present application, the at least two sub-sacrificial layers may specifically include a first sub-sacrificial layer 710 and a second sub-sacrificial layer 720. The first sub-sacrificial layer 710 is located between the second sub-sacrificial layer 720 and the channel layer 200. That is, the first sub-sacrificial layer 710 is closer to the channel layer 200 than the second sub-sacrificial layer 720. When the sacrificial stack 700 is sandwiched between two channel layers 200, the sacrificial stack 720 includes at least two first sub-sacrificial layers 710. The concentration of Ge material in the first sub-sacrificial layer 710 is higher than that in the second sub-sacrificial layer 720, and the thickness of the first sub-sacrificial layer 710 is greater than that of the second sub-sacrificial layer 720. Therefore, the etching rate of the first sub-sacrificial layer 710 is greater than that of the second sub-sacrificial layer 720. After selective etching of the sacrificial stack 700, the first cavity exhibits a shape in which the edge of the first sub-sacrificial layer 710 is more inwardly contracted relative to the edge of the second sub-sacrificial layer 720.

[0089] Reference Figure 5In some embodiments of the present application, when the sacrificial stack 700 is formed by stacking two first sub-sacrificial layers 710 and one second sub-sacrificial layer 720, the second sub-sacrificial layer 720 can be considered to form the minimum distance dmin between the side surface 403 of the metal gate structure 400 and the source region 500 / drain region 600. The first sub-sacrificial layer 710 can be considered to form the first distance d1 between the surface of the metal gate structure 400 facing the channel layer 200 and the source region 500 / drain region 600. The first distance d1 is greater than the minimum distance dmin. Furthermore, the first sub-sacrificial layer 710 can also be considered to form the maximum distance dmax between the side surface 403 of the metal gate structure 400 and the source region 500 / drain region 600. That is, the maximum distance dmax can be equal to the first distance d1. This ensures that the second dielectric region 320 has a maximum length at the edge, providing good electrical insulation at the edge. This reduces the risk of a short circuit between the metal gate structure 400 and the source region 500 / drain region 600 at this location. Furthermore, increasing the distance between the metal gate structure 400 and the source region 500 / drain region 600 at this location can reduce dielectric capacitance, thereby reducing signal transmission delay and improving the switching performance of the semiconductor device. Furthermore, the side surface 403 of the metal gate structure 400 can be considered to be convex toward the source region 500 / drain region 600. This reduces the number of potential breakdown points in the second dielectric region 320 and reduces the probability of breakdown from the metal gate structure 400 to the source region 500 / drain region 600.

[0090] Reference Figure 6a In some other embodiments of the present application, multiple first sub-sacrificial layers 710 and multiple second sub-sacrificial layers 720 may be alternately stacked in the sacrificial stack 700 , for example Figure 6a The three first sub-sacrificial layers 710 and the two second sub-sacrificial layers 720 are shown. After selectively etching the sacrificial stack 700, the first cavity presents a shape where the edge of the first sub-sacrificial layer 710 is more inwardly retracted than the edge of the second sub-sacrificial layer 720, making the first cavity present a shape similar to a "bow". Figure 6b At this time, the maximum distance dmax between the side surface 403 of the metal gate structure 400 and the source region 500 / drain region 600 is formed at the position of the middle first sub-sacrificial layer 710, the first distance d1 between the surface of the metal gate structure 400 facing the channel layer 200 and the source region 500 / drain region 600 is formed at the positions of the upper and lower first sub-sacrificial layers 710, and the minimum distance dmin between the side surface 403 of the metal gate structure 400 and the source region 500 / drain region 600 is formed at the positions of the two second sub-sacrificial layers 720. The first distance d1 is greater than the minimum distance dmin and less than the maximum distance dmax.

[0091] Reference Figure 7aIn some other embodiments of the present application, sub-sacrificial layers with multiple Ge material concentrations can be set in the sacrificial stack 700. For example, in addition to the first sub-sacrificial layer 710 and the second sub-sacrificial layer 720, the sacrificial stack 700 can also include a third sub-sacrificial layer 730 and a fourth sub-sacrificial layer, etc. The concentration of the Ge material in the fourth sub-sacrificial layer 740, the third sub-sacrificial layer 730, the first sub-sacrificial layer 710 and the second sub-sacrificial layer 720 decreases in sequence, and the fourth sub-sacrificial layer 740, the third sub-sacrificial layer 730, the first sub-sacrificial layer 710, the second sub-sacrificial layer 720, the first sub-sacrificial layer 710, the third sub-sacrificial layer 730 and the fourth sub-sacrificial layer 740 are stacked in this order, that is, according to the stacking direction, i.e., from bottom to top, the concentration of the Ge material in the sub-sacrificial layer decreases from the maximum value to the minimum value and then increases to the maximum value. After providing a sufficient number of sub-sacrificial layers, by adjusting the difference in Ge material concentration and thickness of each sub-sacrificial layer, after selectively etching the sacrificial stack 700, the first cavity can present a shape in which the edges of each sub-sacrificial layer are roughly aligned, so that the first cavity appears to be similar to a rectangle. Figure 7b At this point, the spacing between the side surface 403 of the metal gate structure 400 and the source region 500 / drain region 600 is approximately the same at all locations. By controlling the etched surface of the sacrificial stack 700 and the final morphology of the first cavity, the second dielectric region 320 can be ensured to have a relatively uniform length at all locations, giving the second dielectric region 320 good electrical insulation performance as a whole, reducing the risk of short circuits between the metal gate structure 400 and the source region 500 / drain region 600. At the same time, the spacing between the metal gate structure 400 and the source region 500 / drain region 600 can be ensured to be relatively uniform, thereby improving the overall gate control capability of the channel layer 200.

[0092] In the present application, the channel layer 200 can be made of a conductive material. In a full-ring gate semiconductor device, the conductive material may include, for example, but is not limited to, nanosheets or nanowires of single-crystal silicon. Nanowires can provide the best electrostatic control, while wider nanosheets can provide a higher "on" current, but also have better electrostatic control than FinFETs. When a voltage is applied to the metal gate structure 400, the electrons in the channel layer 200 will move, causing the ions in the source region 500 / drain region 600 in contact with the channel layer 200 to move, thereby forming a current between the source region 500 and the drain region 600, thereby realizing signal transmission between the source region 500 and the drain region 600. However, this signal transmission is affected by RC signal delay, which is positively correlated with the capacitance (C) of the second dielectric layer 320 and the resistance (R) of the portion of the channel layer 200 that contacts the second dielectric layer 320. The smaller the capacitance C and resistance R, the smaller the RC signal delay, the faster the signal transmission between the source region 500 and the drain region 600, and the easier it is to improve the switching performance of the semiconductor device. Therefore, to improve the switching performance of the semiconductor device, it is necessary to reduce the capacitance C of the second dielectric layer 320 and the resistance R of the portion of the channel layer 200 that contacts the second dielectric layer 320.

[0093] In this application, the positions of the source region 500 and the drain region 600 can be interchanged. The source region 500 is used to form the source of the semiconductor device, and the drain region 600 is used to form the drain of the semiconductor device. The source region 500 and the drain region 600 are generally made of highly doped silicon material, or metal material, to ensure that the source region 500 can provide sufficient electrons and the drain region 600 can absorb electrons.

[0094] In some embodiments of the present application, reference Figure 4 、 Figure 6a and Figure 7b Specifically, the semiconductor device may include N+1 channel layers 200, N dielectric layers 300, and N metal gate structures 400. It may also include a substrate 100, wherein the N+1 channel layers 200 and the N dielectric layers 300 are alternately stacked on the substrate 100, and the N metal gate structures 400 are wrapped in the first dielectric regions 310 of the N dielectric layers 300 in a one-to-one correspondence. The source region 500 and the drain region 600 are arranged on opposite sides of the N+1 channel layers 200 and the N dielectric layers 300. For example, the source region 500 is arranged on the left side of the N+1 channel layers 200 and the N dielectric layers 300 in the figure, and the drain region 600 is arranged on the right side of the N+1 channel layers 200 and the N dielectric layers 300 in the figure. Wherein, N can be any positive integer, such as Figure 4N=4 is taken as an example, but in other examples, N can also be other values. For example, in one example, N can also be 1. In this case, only two channel layers 200 and one dielectric layer 300 are stacked on the substrate 100, and the dielectric layer 300 is sandwiched between the two channel layers 200. For another example, N can also be 2. In this case, three channel layers 200 and two dielectric layers 300 are stacked on the substrate 100. These five layers are stacked in the order of channel layer 200, dielectric layer 300, channel layer 200, dielectric layer 300, and channel layer 200. For another example, in yet another example, N can also be an integer greater than 4. They are not listed here one by one.

[0095] Reference Figure 8 When multiple channel layers 200 are present in the gate-all-around semiconductor device provided by the industry, the current in the source region 500 / drain region 600 is generally transmitted in the direction of the arrow in the figure. Therefore, there is a relatively large resistance difference from the topmost channel layer 200 to the bottommost channel layer 200. For example, the resistance of the topmost channel layer 200 includes R1+R, and the resistance of the bottommost channel layer 200 includes R1+R2+R3+R4+R5+R, resulting in resistance mismatch between the various channel layers 200, causing different RC signal delays from each metal gate structure 400 to the source region 500 / drain region 600.

[0096] Based on this, when the semiconductor device has a multi-layer metal gate structure 400, in order to balance the RC signal delay from each metal gate structure 400 to the source region 500 / drain region 600. In other embodiments of the present application, refer to Figures 9a to 9cThe multi-layer metal gate structure 400 may include a first metal gate structure 410 and a second metal gate structure 420. A first average distance D1 is defined between the side surface 403 of the first metal gate structure 410 and the source / drain regions 500 / 600. A second average distance D2 is defined between the side surface 403 of the second metal gate structure 420 and the source / drain regions 500 / 600. The first average distance D1 and the second average distance D2 have different values. The average distance refers to the average distance between the side surface 403 of the metal gate structure 400 and the source / drain regions 500 / 600 at different locations. In other words, the first average distance D1 can be considered to be the average length of the second dielectric layer 320 between the first metal gate structure 410 and the source / drain regions 500 / 600, and the second average distance D2 is the average length of the second dielectric layer 320 between the second metal gate structure 420 and the source / drain regions 500 / 600. By controlling the average length of the second dielectric layer 320, the resistances R33, R44, and R55 of the portions of the adjacent channel layer 200 that are in contact with the second dielectric layer 320 can be adjusted. Specifically, the longer the average length of the second dielectric layer 320, the greater the resistance of the portions of the channel layer 200 that are in contact with the second dielectric layer 320. The average length of the second dielectric layer 320 between the first metal gate structure 410 and the source / drain regions 500 / 600, and the average length of the second dielectric layer 320 between the second metal gate structure 420 and the source / drain regions 500 / 600, are set to be opposite to the resistance mismatch trend to balance the RC signal delay from the first metal gate structure 410 and the second metal gate structure 420 to the source / drain regions 500 / 600. Figure 9a Any two metal gate structures 400 can be used as the first metal gate structure 410 and the second metal gate structure 420. In the figure, the two metal gate structures at the bottom are used as the first metal gate structure 410 and the second metal gate structure 420. Figures 9a to 9c In the figure, the distance between the side surface of the metal gate structure 400 and the source region 500 / the drain region 600 is the same at all positions. In actual application, it can be applied to structures where the side surface 403 of the metal gate structure 400 has various shapes.

[0097] In some embodiments of the present application, reference Figures 9a to 9c When the semiconductor device has a multi-layer metal gate structure 400, the average spacing between the side surface 403 of each metal gate structure 400 and the source region 500 / drain region 600 can be set to be different, so that the resistances R11, R22, R33, R44, and R55 of the portions of adjacent channel layers 200 that contact the second dielectric layer 320 are different, so as to balance the RC signal delays from different metal gate structures to the source region 500 / drain region 600.

[0098] In some embodiments of the present application, reference Figure 9a When the signal terminal is disposed at the top of each channel layer 200, the average spacing between the side surface 403 of each metal gate structure 400 and the source region 500 / drain region 600 can be increased successively along the stacking direction, i.e., from bottom to top. This allows the resistances R11, R22, R33, R44, and R55 of the portion of each channel layer 200 in contact with the second dielectric layer 320 to decrease successively along the top to bottom. This balances the resistance differences between each metal gate structure 400 and the source region 500 / drain region 600, ensuring that the resistances of each channel layer 200 are relatively consistent and balancing the RC signal delays from each metal gate structure 400 to the source region 500 / drain region 600.

[0099] In other embodiments of this application, refer to Figure 9b When the signal terminal is disposed at the bottom of each channel layer 200, the average spacing between the side surface 403 of each metal gate structure 400 and the source region 500 / drain region 600 can decrease successively along the stacking direction, i.e., from bottom to top. This allows the resistance of the portion of each channel layer 200 in contact with the second dielectric layer 320 to increase successively along the top to bottom direction. This balances the resistance difference between each metal gate structure 400 and the source region 500 / drain region 600, ensures that the resistance of each channel layer 200 is relatively consistent, and balances the RC signal delay from each metal gate structure 400 to the source region 500 / drain region 600.

[0100] In other embodiments of this application, refer to Figure 9c Alternatively, based on the RC signal delay degree from each metal gate structure 400 to the source region 500 / drain region 600 obtained from actual tests, the average spacing between the side surface 403 of the metal gate structure 400 where the RC signal delay degree is most severe and the source region 500 / drain region 600 may be set to the minimum, and the average spacing of other metal gate structures 400 may be set similarly. Figure 9c The example in which the RC signal delay from the second metal gate structure 400 to the source region 500 / drain region 600 is the most serious along the stacking direction, i.e., from bottom to top, is used for illustration. In actual application, adjustments can be made based on test results.

[0101] Based on the semiconductor device described above, the present application also provides a method for preparing the semiconductor device. Figure 10 , to prepare Figure 9a Taking the semiconductor device shown in FIG. 1 as an example, the preparation method may include the following steps 1 to 6.

[0102] Step 1: alternately forming stacked channel layers 200 and sacrificial stacks 700 on a substrate 100 .

[0103] Optionally, assuming that a layer of channel layer 200 and a layer of sacrificial stack 700 are called a group, the number of alternately formed stacking groups can be set according to demand. For example, when the demand for integration is relatively high, the number of alternately formed stacking groups can be set to be larger, such as greater than or equal to 4, and when the demand for low cost is relatively high, the number of alternately formed stacking groups can be set to be smaller, such as less than 4.

[0104] Furthermore, optionally, the number of channel layers 200 may be one more than the number of sacrificial stack layers 700. For example, when the sacrificial stack layers 700 are N layers, the number of channel layers 200 may be N+1 layers, where N is a positive integer. Figure 10 Taking N as an example, there are five channel layers 200 and four sacrificial stacks 700. The five channel layers 200 and the four sacrificial stacks 700 are alternately stacked on the substrate 100, so that both the bottom and top layers are channel layers 200. Thus, by exposing the channel layer 200 at the top layer, it is easier to subsequently expand more components on the channel layer 200.

[0105] However, it should be understood that in another example, the number of channel layers 200 can be the same as the number of sacrificial stacks 700, for example, the channel layer 200 is the bottom layer and the sacrificial stack 700 is the top layer, or the channel layer 200 is the top layer and the sacrificial stack 700 is the bottom layer. Alternatively, in another example, the number of sacrificial stacks 700 can be greater than the number of channel layers 200. In this case, both the bottom layer and the top layer are sacrificial stacks 700. This application does not specifically limit the relationship between the number of channel layers 200 and the number of sacrificial stacks 700.

[0106] In the present application, each sacrificial stack 700 includes at least two stacked sub-sacrificial layers, and the concentration of Ge material in the adjacent two sub-sacrificial layers is different. There are many ways to set the sub-sacrificial layers in the sacrificial stack 700, and the specific method is as follows: Figure 5 、 Figure 6a and Figure 7a , which will not be described in detail here. Figure 7a For example, in each sacrificial stack 700, the concentration of the Ge material in the sub-sacrificial layer decreases from the maximum value to the minimum value and then increases to the maximum value in the stacking direction, i.e., from bottom to top. The average concentration of the Ge material in each sacrificial stack 700 can be calculated. When it is necessary to balance the resistance mismatch of each channel layer 200, the average concentration of the Ge material in each sacrificial stack 700 can be adjusted. The multiple sacrificial stacks may include a first sacrificial stack and a second sacrificial stack. The average concentration of the Ge material in the first sacrificial stack is different from the average concentration of the Ge material in the second sacrificial stack. The first sacrificial stack can be used to form a first metal gate structure, and the second sacrificial layer can be used to form a second metal gate structure. To prepare Figure 9aTaking the semiconductor device shown in FIG. as an example, along the stacking direction, i.e., from bottom to top, the average concentration of Ge material in each sacrificial stack can be increased successively. Figure 9b In the semiconductor device shown in FIG. 1 , the average concentration of the Ge material in each sacrificial stack may decrease successively along the stacking direction, that is, from bottom to top.

[0107] Step 2: Etching the outer portion of the sacrificial stack 700 to form a first cavity.

[0108] Optionally, a selective etching technique can be used to etch inward from the outermost end of the sacrificial stack 700 to a depth of approximately 3 to 6 nm, thereby forming a first cavity between the sacrificial stack 700 and the two adjacent channel layers 200. Because the Ge material concentrations in the sub-sacrificial layers within each sacrificial stack 700 vary, the etching rates of the sub-sacrificial layers differ. By adjusting the Ge material concentrations in the sub-sacrificial layers, the lengths of the upper and lower edges of each first cavity can be increased. Furthermore, because the average Ge material concentrations in each sacrificial stack 700 vary, the average lengths of the ultimately formed first cavities vary; a higher average concentration results in a longer first cavity.

[0109] Step 3: depositing a second dielectric material in the first cavity to form a second dielectric region 320 .

[0110] Optionally, the second dielectric material can be a low-dielectric (LowK) material, such as SiOC or SiCN. Since the second dielectric region 320 is made of a low-dielectric material, it can also be referred to as a low-dielectric material region, and its dielectric constant is typically 3.2 to 5. The shape of the second dielectric region 320 is consistent with that of the first cavity.

[0111] Step 4: forming a source region 500 and a drain region 600 on both sides of the channel layer 200 and the second dielectric region 320 respectively.

[0112] For example, a single crystal silicon material may be first deposited on the left side of the channel layer 200 and the second dielectric region 320 in the figure, and then a high concentration of ions may be doped into the single crystal silicon material to form the source region 500. Similarly, a single crystal silicon material may be first deposited on the right side of the channel layer 200 and the second dielectric region 320 in the figure, and then a high concentration of other ions may be doped into the single crystal silicon material to form the drain region 600.

[0113] Step 5: Etch the remaining sacrificial stack 700 to form a second cavity.

[0114] Here, the second cavity is obtained by etching the sacrificial stack 700 , and therefore, the shape of the second cavity is the same as that of the sacrificial stack 700 .

[0115] Step six: depositing a first dielectric material in the second cavity to form a ring-shaped first dielectric region 310 , and then depositing a metal gate material in the first dielectric region 310 to form a metal gate structure 400 .

[0116] Optionally, the first dielectric material may be a high dielectric material (HighK), such as AlO or TiO2, etc. Since the first dielectric region 310 is made of a high dielectric material, the first dielectric region 310 may also be referred to as a high dielectric material region, and its dielectric constant is generally greater than 10.

[0117] The metal gate structure 400 is wrapped by the first dielectric region 310 . Therefore, the first dielectric region 310 can be used to isolate the metal gate structure 400 from the channel layer 200 , while allowing electrons in the channel layer 200 to flow, thereby achieving conduction or disconnection between the source region 500 and the drain region 600 .

[0118] The above content introduces the specific structure of the semiconductor device provided by this application and the corresponding preparation method, but it should be understood that the structure and preparation method are only examples. The actual semiconductor device may also include more or fewer layers or structures, and the actual preparation method may also include more or fewer steps. This application does not make specific limitations on this.

[0119] In other embodiments of this application, refer to Figure 11 In addition to the aforementioned channel layer 200, dielectric layer 300, source region 500, drain region 600 and metal gate structure 400, the semiconductor device may also include an insulating layer 800, a third metal gate structure 430 and a protective layer 900. The insulating layer 800 is located above the top channel layer 200, the third metal gate structure 430 is located above the insulating layer 800, and the protective layer 900 surrounds three sides of the third metal gate structure 430 except the insulating layer 800, such as the left, top and right sides shown in the figure.

[0120] Optionally, the third metal gate structure 430 may also be used to form a gate of a semiconductor device, and may generally be made of metal materials, such as but not limited to aluminum, tungsten, molybdenum, silver, aluminum-copper, and titanium-aluminum alloy.

[0121] Optionally, the protective layer 900 may also be referred to as a barrier layer or mask, and may be used to protect the third metal gate structure 430 located therein from being affected by the external environment. The protective layer 900 may be made of a variety of materials, including but not limited to metal materials such as titanium, tantalum, chromium, aluminum, and copper, or non-metallic materials such as barium fluoride and calcium fluoride, or a combination of metal and non-metal materials.

[0122] Optionally, the insulating layer 800 can be used to isolate the third metal gate structure 430 from the underlying channel layer 200. The function of the insulating layer 800 is similar to that of the first dielectric region 310. For example, when a voltage is applied to the third metal gate structure 430, the voltage drives electrons in the underlying channel layer 200 to move. Consequently, under the isolation effect of the insulating layer 800, electrons in the source region 500 / drain region 600 are caused to accumulate on the upper surface of the channel layer through the channel layer 200, or electrons in the channel layer 200 are caused to disperse to the source region 500 / drain region 600, thereby achieving conduction between the third metal gate structure 430 and the source region 500 / drain region 600.

[0123] Furthermore, optionally, the insulating layer 800 may be prepared using metal oxides, such as but not limited to aluminum oxide (Al2O3), iron oxide (Fe2O3), sodium oxide (Na2O), magnesium oxide (MgO) and potassium oxide (K2O).

[0124] It is understandable that if you want to prepare Figure 11 The semiconductor device shown in Figure 10 In step 1 shown, after the channel layer 200 and the sacrificial stack 700 are alternately stacked on the substrate 100, an insulating layer 800 can be deposited on the top channel layer 200, and a third metal gate structure 430 can be deposited on the insulating layer 800. Then, a mask is deposited on the periphery of the third metal gate structure 430 to obtain a protective layer 900. After that, the subsequent steps 2 to 6 are performed based on this structure to obtain Figure 11 The semiconductor device shown.

[0125] in addition, Figure 11 The figure shows that only one row and one column of semiconductor devices are prepared on a substrate. In order to improve the integration of semiconductor devices, multiple rows and columns of semiconductor devices can usually be prepared on a substrate at the same time. Figure 12 At least three columns of semiconductor devices can be fabricated on a substrate 100, with each column having at least two rows. Adjacent rows of semiconductor devices can be separated by an isolation layer 110 to reduce mutual interference between adjacent rows of semiconductor devices. Adjacent columns of semiconductor devices can share the same source region 500 or drain region 600. For example, from left to right, the first column of semiconductor devices and the second column of semiconductor devices share the same drain region 600, while the second column of semiconductor devices and the third column of semiconductor devices share the same source region 500. The shared source region or drain region can reduce the difficulty of fabrication and further improve the integration.

[0126] It should be noted that in Figure 11 or Figure 12In the semiconductor device shown, the concepts, explanations, detailed descriptions and other steps involved can be found in the descriptions of the aforementioned structures and method embodiments, which will not be repeated here.

[0127] Based on the semiconductor device described above, the present application further provides an integrated circuit, which may include a circuit board and one or more semiconductor devices disposed on the circuit board, wherein the semiconductor device may be the semiconductor device in any of the aforementioned embodiments, such as Figure 4 、 Figure 5 、 Figure 6b 、 Figure 7b 、 Figure 9a 、 Figure 9b 、 Figure 9c or Figure 11 The semiconductor device shown.

[0128] Reference Figure 13 The integrated circuit may also include a signal input / output interface IO circuit provided on the circuit board. The IO circuit is located on the periphery of the semiconductor device. The devices included in the IO circuit are usually formed at the same time as the semiconductor device, and the two have the same film layer stacking relationship. Therefore, the IO circuit may include a sacrificial stack that is not removed by selective etching. The sacrificial stack is located in the same film layer as the metal gate structure in the semiconductor device. Figure 5 、 Figure 6a 、 Figure 7a or Figure 10 The sacrificial stack includes at least two stacked sub-sacrificial layers, and the concentration of Ge material in two adjacent sub-sacrificial layers is different.

[0129] There are many ways to set the sub-sacrificial layer in the sacrificial stack 700. Figure 5 、 Figure 6a and Figure 7a , which will not be described in detail here. For example, in some embodiments of the present application, the sacrificial stack may specifically include a first sub-sacrificial layer and a second sub-sacrificial layer, the concentration of Ge material in the first sub-sacrificial layer is higher than the concentration of Ge material in the second sub-sacrificial layer, the thickness of the first sub-sacrificial layer is greater than the thickness of the second sub-sacrificial layer, and the first sub-sacrificial layer is located between the second sub-sacrificial layer and the channel layer.

[0130] Based on the integrated circuit described above, the present application also provides an electronic device, referring to Figure 2 The electronic device may include a housing and the aforementioned integrated circuit, with the integrated circuit disposed within the housing. For example, a circuit board within the integrated circuit may be secured to the inner wall of one side of the housing, with the semiconductor devices on the circuit board facing the inner wall of the other side of the housing, thereby encapsulating the integrated circuit as a whole within the housing and protecting the integrated circuit.

[0131] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: A channel layer, a dielectric layer located above the channel layer, a source region and a drain region located on opposite sides of the channel layer and the dielectric layer, and a metal gate structure; The dielectric layer includes a first annular dielectric region and second dielectric regions located on opposite sides of the first dielectric region, and the metal gate structure is wrapped in the first dielectric region; There is a first distance between the surface of the metal gate structure facing the channel layer and the source region or the drain region, and a minimum distance between the side of the metal gate structure and the source region or the drain region, and the first distance is greater than or equal to the minimum distance.

2. The semiconductor device according to claim 1, wherein A maximum distance exists between the side surface of the metal gate structure and the source region or the drain region, and the maximum distance is equal to the first distance.

3. The semiconductor device according to claim 2, wherein The side surface of the metal gate structure protrudes toward the source region or the drain region.

4. The semiconductor device according to claim 1, wherein The distance between the side surface of the metal gate structure and the source region or the drain region is the same at all locations.

5. The semiconductor device according to any one of claims 1 to 4, wherein The semiconductor device includes a substrate, N+1 channel layers, N dielectric layers and N metal gate structures. The N+1 channel layers and the N dielectric layers are alternately stacked above the substrate. The N metal gate structures are wrapped in the first dielectric region of the N dielectric layers in a one-to-one correspondence, where N is a positive integer.

6. The semiconductor device according to claim 5, wherein The N metal gate structures include a first metal gate structure and a second metal gate structure, wherein a first average spacing is provided between the side surface of the first metal gate structure and the source region or the drain region, and a second average spacing is provided between the side surface of the second metal gate structure and the source region or the drain region, and the values ​​of the first average spacing and the second average spacing are different.

7. The semiconductor device according to claim 6, wherein Among the N metal gate structures, the average distance between the side surface of each metal gate structure and the source region or the drain region is different.

8. The semiconductor device according to claim 7, wherein Along the stacking direction, the average distance between the side surface of each metal gate structure and the source region or the drain region increases successively.

9. The semiconductor device according to any one of claims 5 to 8, wherein: Also includes an insulating layer, a third metal gate structure and a protective layer; The insulating layer and the third metal gate structure are sequentially stacked above the uppermost channel layer, and the protection layer surrounds three sides of the third metal gate structure except the insulating layer.

10. A method for preparing a semiconductor device, characterized in that: include: Alternately forming stacked channel layers and sacrificial stacks; etching a peripheral portion of the sacrificial stack to form a first cavity; depositing a second dielectric material in the first cavity to form a second dielectric region; forming a source region and a drain region on both sides of the channel layer and the second dielectric region respectively; Etching the remaining sacrificial layer to form a second cavity; sequentially depositing a first dielectric material and a metal gate material in the second cavity to form a first dielectric region and a metal gate structure wrapped by the first dielectric region; In which, the sacrificial stack includes at least two stacked sub-sacrificial layers, and the concentration of Ge material in two adjacent sub-sacrificial layers is different, so that there is a first distance between the surface of the formed metal gate structure facing the channel layer and the source region or the drain region, and there is a minimum distance between the side of the metal gate structure and the source region or the drain region, and the first distance is greater than or equal to the minimum distance.

11. The method according to claim 10, wherein The at least two sub-sacrificial layers include a first sub-sacrificial layer and a second sub-sacrificial layer, the concentration of Ge material in the first sub-sacrificial layer is higher than the concentration of Ge material in the second sub-sacrificial layer, the thickness of the first sub-sacrificial layer is greater than the thickness of the second sub-sacrificial layer, and the first sub-sacrificial layer is located between the second sub-sacrificial layer and the channel layer.

12. The method according to claim 10 or 11, wherein: The alternately stacked channel layers and sacrificial stacks include: N+1 layers of the channel layers and N layers of the sacrificial stacks are alternately stacked on the substrate, where N is a positive integer.

13. The method according to claim 12, wherein: The N-layer sacrificial stack includes a first sacrificial stack and a second sacrificial stack, and an average concentration of Ge material in the first sacrificial stack is different from an average concentration of Ge material in the second sacrificial stack.

14. The method according to claim 13, wherein Along the stacking direction, the average concentration of the Ge material in each of the sacrificial stacks increases successively.

15. The method according to any one of claims 11 to 14, wherein: After alternately forming the stacked channel layers and the sacrificial stacked layers, the method further includes: forming an insulating layer and a third metal gate structure in sequence above the uppermost channel layer; A protection layer is formed on three sides of the third metal gate structure except the insulating layer.

16. An integrated circuit, characterized in that: The method comprises a circuit board and one or more semiconductor devices according to any one of claims 1 to 9, wherein the one or more semiconductor devices are arranged on the circuit board.

17. The integrated circuit according to claim 16, wherein: Also included is a signal input and output interface IO circuit provided on the circuit board, wherein the IO circuit is located outside the one or more semiconductor devices; The IO circuit includes a sacrificial stack, which is located in the same film layer as the metal gate structure in the semiconductor device. The sacrificial stack includes at least two stacked sub-sacrificial layers, and the concentration of Ge material in two adjacent sub-sacrificial layers is different.

18. The integrated circuit according to claim 17, wherein: The at least two sub-sacrificial layers include a first sub-sacrificial layer and a second sub-sacrificial layer, the concentration of Ge material in the first sub-sacrificial layer is higher than the concentration of Ge material in the second sub-sacrificial layer, the thickness of the first sub-sacrificial layer is greater than the thickness of the second sub-sacrificial layer, and the first sub-sacrificial layer is located between the second sub-sacrificial layer and the channel layer.

19. An electronic device, characterized in that: The invention comprises a housing and the integrated circuit according to any one of claims 16 to 18, wherein the integrated circuit is arranged in the housing.

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