A solar cell, a photovoltaic module and a method for manufacturing a solar cell

Abstract

The application discloses a solar cell, a photovoltaic module and a manufacturing method of the solar cell, and relates to the technical field of solar cells, and aims to solve the problem of how to make the photoelectric efficiency of the solar cell reach a high level. The solar cell comprises a semiconductor substrate, a first doped layer and a second doped layer. The semiconductor substrate comprises opposite first and second surfaces, and the first surface comprises a first electrode area and a first non-electrode area. The surface of the first electrode area has a first texture structure, the first non-electrode area has a second texture structure and a third texture structure, the second texture structure is located in the middle region of the semiconductor substrate, the third texture structure is located in the edge region of the semiconductor substrate, the width of the edge region is less than or equal to 3 mm, and the fluctuation degree of the third texture structure is less than the fluctuation degree of the second texture structure. The first doped layer is arranged in the first electrode area, the second doped layer is arranged in the first non-electrode area, and the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a solar cell, a photovoltaic module and a manufacturing method of the solar cell. BACKGROUND

[0002] A solar cell is a device that converts solar energy into electricity through the photoelectric effect or photochemical effect.

[0003] At present, the solar cell mainly includes an IBC cell (Interdigitated Back Contact), a TOPCON cell (Tunnel Oxide Passivated Contact), a PERC cell (Passivated emitter and real cell), a heterojunction cell and a bifacial solar cell.

[0004] At present, there are many improvements in the structure of the cell. However, how to make the photoelectric efficiency of the solar cell reach a high level is still a technical problem to be solved in the current industry. SUMMARY

[0005] The present application aims to provide a solar cell, a photovoltaic module and a manufacturing method of the solar cell to improve the efficiency of the solar cell.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, the present application provides a solar cell. The solar cell comprises a semiconductor substrate, a first doped layer and a second doped layer. The semiconductor substrate comprises opposite first and second surfaces, the first surface comprising a first electrode region and a first non-electrode region. The surface of the first electrode region has a first texture structure, the first non-electrode region has a second texture structure and a third texture structure, the second texture structure being located in the middle region of the semiconductor substrate, the third texture structure being located in the edge region of the semiconductor substrate, the width of the edge region being less than or equal to 3mm, the fluctuation degree of the third texture structure being less than the fluctuation degree of the second texture structure. The first doped layer is arranged in the first electrode region, and the second doped layer is arranged in the first non-electrode region. The doping concentration of the first doped layer is greater than the doping concentration of the second doped layer.

[0007] The solar cell provided by the application has the following advantages: the first doping layer arranged in the first electrode area has a doping concentration greater than that of the second doping layer arranged in the first non-electrode area; by reducing the doping concentration of the first non-electrode area, the area with high concentration on the front surface of the solar cell is reduced, the problem of recombination of the semiconductor substrate surface caused by high doping concentration is reduced, the open-circuit voltage of the solar cell is increased; meanwhile, the first doping layer arranged in the first electrode area is retained, the contact resistance between the electrode and the first doping layer is small, the series resistance of the solar cell is reduced, the fill factor is improved, and thus the efficiency of the solar cell is improved. The first non-electrode area is not shielded by the grid lines, and the first non-electrode area focuses on the light trapping effect and passivation performance of the front surface of the solar cell, and the first electrode area focuses on the contact performance and passivation performance. Based on the above functional differences between the first electrode area and the first non-electrode area, the first non-electrode area needs to consider the light trapping effect and the passivation performance of the passivation layer film. In the application, the first non-electrode area has a second texture structure located in the middle region of the semiconductor substrate and a third texture structure located in the edge region of the semiconductor substrate, and the fluctuation degree of the third texture structure is less than that of the second texture structure. That is, in the application, the first non-electrode area extending to the edge region of the semiconductor substrate has a third texture structure with a relatively flat fluctuation degree, the third texture structure can provide a good surface for the subsequent passivation layer, and the fluctuation degree is small, which means that the specific surface area of the semiconductor substrate located in the edge region is small. In the same plating process, a thicker passivation layer can be formed to meet the passivation performance of the edge of the solar cell, and the efficiency of the solar cell is ensured.

[0008] In an implementation manner, the third texture structure comprises one or more of a tower base structure, a prismatic structure, an inverted pyramid structure, a prismatic-pyramid structure or a pyramid structure.

[0009] In an implementation manner, the first texture structure and / or the second texture structure is a pyramid structure.

[0010] In an implementation manner, the first texture structure and / or the second texture structure is a pyramid structure.

[0011] In an implementation manner, the first texture structure and / or the second texture structure is a pyramid structure.

[0012] In an implementation manner, the first texture structure and / or the second texture structure is a pyramid structure.

[0013] In an implementation, the partial edge region is provided with a tunneling layer and / or a doped conductive layer; the tunneling layer and the doped conductive layer are arranged on the first doped layer and / or the second doped layer; the first doped layer and the second doped layer have the same doping type, and the doping type of the doped conductive layer is opposite to that of the first doped layer and the second doped layer.

[0014] With the technical solution, the chemical passivation of the tunneling layer and the field passivation of the doped conductive layer can significantly reduce the recombination degree of the surface of the semiconductor substrate. The tunneling layer and the doped conductive layer can further passivate the edge of the cell piece and reduce the recombination of the edge of the cell piece. In addition, the partial edge region provided with the tunneling layer and / or the doped conductive layer can reduce the damage to the surface of the middle part of the first surface in the process step of removing the side tunneling layer and / or the doped conductive layer, reduce the probability of damaging the first texture structure and the second texture structure, and improve the light trapping effect of the front surface.

[0015] In an implementation, the semiconductor substrate further includes a plurality of side surfaces between the first surface and the second surface; at least part of the side surfaces is provided with a groove, the groove bottom is lower than the surface of the side surface, and the height difference between the groove bottom and the surface of the side surface is greater than or equal to 0.5 μm and less than or equal to 7 μm.

[0016] With the technical solution, when the doped conductive layer is formed on the second surface, the side surfaces and the first electrode area of the first surface of the semiconductor substrate will also be plated with the doped conductive layer. The doped conductive layer on the first surface and the second surface is separated by the groove arranged on at least part of the side surfaces, so as to avoid the short circuit and edge leakage of the solar cell. The groove can also increase the distance between the first surface and the second surface, and increase the difficulty of the doped conductive layer on the first surface and the second surface to lap on the side surface. In the preparation process, the semiconductor substrate on the side surface of the cell is etched to remove the inner extension layer formed in the semiconductor substrate during the formation of the doped conductive layer, thereby reducing the possibility of short circuit caused by the contact of the doped conductive layers with opposite polarities.

[0017] If the height difference between the groove bottom and the surface of the side surface is less than 0.5 μm, the depth of the groove is relatively shallow, at this time, the groove arranged on the side surface cannot effectively isolate the doped conductive layer on the first surface and the second surface, and cannot guarantee the complete removal of the inner expansion layer of the side surface of the battery, resulting in an increase in the probability of short circuit and edge leakage of the solar cell. If the height difference between the surface of the groove and the surface of the side surface is greater than 7 μm, the depth of the groove is relatively deep, at this time, the side surface of the semiconductor substrate is removed more, which will reduce the mechanical strength of the battery as a whole. And the solar cell generates electricity by separating electrons and holes from the semiconductor substrate under light, if the semiconductor substrate is removed too much, the light absorption rate of the semiconductor substrate will be reduced, resulting in a decrease in the number of photo-generated carriers, i.e. holes and electrons, generated on the semiconductor substrate under light, which in turn will reduce the photoelectric conversion rate of the solar cell. In summary of the above two aspects, the height difference between the surface of the groove and the surface of the side surface is set within a reasonable range, which avoids the short circuit and edge leakage of the solar cell, guarantees a high light absorption rate of the semiconductor substrate, and prevents the photoelectric conversion rate of the solar cell from being reduced, and also guarantees that the battery piece has sufficient mechanical strength.

[0018] In an implementation manner, the surface of the side surface includes a surface close to the first surface and a surface close to the second surface, and the distance between the groove bottom and the surface close to the first surface of the surface of the side surface is greater than the distance between the groove bottom and the surface close to the second surface of the surface of the side surface.

[0019] In an implementation manner, along the thickness direction of the semiconductor substrate, the first electrode region is higher than the first non-electrode region, and the distance between the first electrode region and the first non-electrode region ranges from 2 μm to 7 μm.

[0020] In the case of adopting the technical solution, the first non-electrode region is recessed relative to the first electrode region, so that light can be reflected and absorbed in the groove, thereby reducing the reflectivity of the second texture structure and the third texture structure.

[0021] In an implementation manner, the second surface includes a second electrode region and a second non-electrode region, the second electrode region and the second non-electrode region are arranged alternately on the second surface, the tunneling layer is arranged on the surface of the second electrode region, the doped conductive layer is arranged on the second electrode region and located on the side of the tunneling layer away from the semiconductor substrate, along the thickness direction of the semiconductor substrate, the second electrode region is higher than the second non-electrode region, and the distance between the second electrode region and the second non-electrode region ranges from 2 μm to 6 μm.

[0022] In the case of the technical solution, if the distance between the second electrode region and the second non-electrode region along the thickness direction of the semiconductor substrate is greater than 6 μm, and the depth of the second non-electrode region is relatively deep, the second surface of the semiconductor substrate is removed more, which reduces the mechanical strength of the whole solar cell sheet. Moreover, the solar cell generates electricity by separating electrons and holes on the semiconductor substrate under light. If the semiconductor substrate is removed too much, the transmission path of the light on the semiconductor substrate is reduced, the light absorption rate of the semiconductor substrate is reduced, the number of photogenerated carriers, i.e. holes and electrons, generated on the semiconductor substrate under light is reduced, and the photoelectric conversion rate of the solar cell is reduced. In the present application, the distance between the second electrode region and the second non-electrode region along the thickness direction of the semiconductor substrate is set within the above value range, which ensures that the light absorption rate of the semiconductor substrate is high, the photoelectric conversion rate of the solar cell is not reduced, and the solar cell sheet also has sufficient mechanical strength.

[0023] In an implementation manner, a projection of the first non-electrode region on the first surface and a projection of the second non-electrode region on the first surface at least partially overlap along the thickness direction of the semiconductor substrate.

[0024] In the case of the technical solution, when the second non-electrode region and the first non-electrode region are both recessed into the semiconductor substrate, if the second non-electrode region and the first non-electrode region completely correspond along the thickness direction of the semiconductor substrate, the thickness of the semiconductor substrate located in the second non-electrode region and the first non-electrode region is smaller than the thickness of the semiconductor substrate located in the second electrode region and the first electrode region. That is, the thickness of the semiconductor substrate in the non-electrode region is smaller than the thickness of the semiconductor substrate in the electrode region, which greatly reduces the mechanical strength of the semiconductor substrate in the non-electrode region. In the present application, the second non-electrode region and the first non-electrode region are staggered along the thickness direction of the semiconductor substrate, which can meet the requirement of the mechanical strength of the semiconductor substrate and reduce or eliminate the probability of fracture of the semiconductor substrate.

[0025] In an implementation manner, the second non-electrode region has a fourth texture structure, and the size consistency of the fourth texture structure is lower than the size consistency of the first texture structure.

[0026] In the case of the technical solution, the fourth texture structure includes a pyramid structure and a tower base structure. Compared with the second non-electrode region without the texture structure, the reflectivity of the second non-electrode region is significantly reduced, and the battery efficiency is not affected by cooperating with the optimization of the passivation process, thereby further improving the double-sided rate of the battery.

[0027] In a second aspect, the present application also provides a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes a plurality of interconnections and a plurality of solar cells as described in the above technical solution. The interconnections are used to connect the plurality of solar cells together to form the cell string. The encapsulation layer is used to cover the surface of the cell string.

[0028] The photovoltaic module provided by the application has the same beneficial effects as the solar cell described in the above technical solution, which will not be repeated here.

[0029] In a third aspect, the application further provides a method for manufacturing a solar cell. The method comprises:

[0030] First, a semiconductor substrate is provided, which has opposite first and second surfaces. The first and second surfaces are subjected to a texturing process to form a first texture structure. The first surface comprises a first electrode region and a first non-electrode region.

[0031] Next, the first surface of the semiconductor substrate is subjected to a diffusion process to form a first doped layer and a first doped oxide layer formed on the first doped layer.

[0032] Next, the first doped oxide layer on the first non-electrode region is removed.

[0033] Next, the first doped layer in the first non-electrode region is etched to form a second doped layer, so that the doping concentration of the second doped layer is less than that of the first doped layer.

[0034] Next, a tunneling layer and a doped conductive layer are deposited on the edge region of the first surface and the second surface, and part of the tunneling layer and the doped conductive layer on the edge region of the first surface is removed.

[0035] Next, after removing part of the tunneling layer and the doped conductive layer on the edge region of the first surface, a secondary texturing process is performed to form a texture structure on the first non-electrode region.

[0036] The method for manufacturing a solar cell provided by the application has the same beneficial effects as the solar cell described in the above technical solution, which will not be repeated here. Further, the chemical passivation of the tunneling layer and the field passivation of the doped conductive layer can significantly reduce the recombination degree of the semiconductor substrate surface. At the same time, the tunneling layer can also ensure the effective tunneling of the majority carriers, and the doped conductive layer can significantly improve the conduction performance of the photo-generated carriers, thereby improving the open-circuit voltage and the fill factor of the solar cell. When the tunneling layer and the doped conductive layer are simultaneously stacked on the edge region of the first surface and the second surface, the tunneling layer and the doped conductive layer form a passivation contact structure. The tunneling layer allows the majority carrier electrons to tunnel into the doped conductive layer while blocking the hole recombination of the minority carriers, thereby allowing the electrons in the doped conductive layer to be collected by the metal in a horizontal direction, greatly reducing the metal contact recombination current and improving the open-circuit voltage and short-circuit current of the cell, thereby improving the cell efficiency.

[0037] In an implementation, the second surface includes a second electrode region and a second non-electrode region; after the deposition of the tunneling layer and the doped conductive layer on the edge region of the first surface and the second surface, before the removal of the tunneling layer and the doped conductive layer on the edge region of the first surface, the method further includes: using a second laser to irradiate the tunneling layer and the doped conductive layer on the second non-electrode region, and etching the tunneling layer and the doped conductive layer on the second non-electrode region.

[0038] In the secondary texturing process, a fourth texture structure is formed on the second non-electrode region.

[0039] Compared with the second non-electrode region being a polished surface, the reflectivity of the second non-electrode region is significantly reduced, and the cell efficiency is not affected by optimizing the passivation process, thereby improving the double-sided rate of the cell.

[0040] In an implementation, the semiconductor substrate includes a plurality of side surfaces between the first surface and the second surface; before the deposition of the tunneling layer and the doped conductive layer on the edge region of the first surface and the second surface, the method further includes:

[0041] The first doped oxide layer and the first doped layer on the second surface and the part of the side surface close to the second surface are removed, and a recessed region is formed on at least part of the side surface, the bottom surface of the recessed region being lower than the surface of the side surface;

[0042] The method further includes:

[0043] The bottom surface of part of the recessed region is etched to form a groove;

[0044] The surface of the side surface includes a surface close to the first surface and a surface close to the second surface, and the distance between the groove bottom of the groove and the surface close to the first surface of the surface of the side surface is greater than the distance between the groove bottom of the groove and the surface close to the second surface of the surface of the side surface.

[0045] The above-mentioned groove separates the doped conductive layer on the first surface and the second surface, avoiding short circuit and edge leakage of the solar cell. The groove can also increase the distance between the first surface and the second surface, and increase the difficulty of the doped conductive layer on the first surface and the second surface to lap on the side surface. In the preparation process, the semiconductor substrate on the side surface of the cell is etched, and the inner extension layer formed in the semiconductor substrate during the formation of the doped conductive layer is removed, reducing the possibility of short circuit caused by contact between the doped conductive layers with opposite polarities.

[0046] In an implementation, after the secondary texturing process, the method further includes:

[0047] A passivation layer is formed on the doped conductive layer and the first surface and the second surface of the semiconductor substrate;

[0048] An electrode is formed on the passivation layer, and the electrode is located in the first electrode region and the second electrode region, respectively.

[0049] The passivation layer can perform passivation treatment on the surface of the semiconductor substrate, reduce surface recombination, and improve open circuit voltage and fill factor. BRIEF DESCRIPTION OF DRAWINGS

[0050] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0051] Figure 1 is a sectional view of a first solar cell in an embodiment of the application;

[0052] Figure 2 is a sectional view of a second solar cell in an embodiment of the application;

[0053] Figure 3 is an enlarged schematic view of part of the structure in the first surface of a solar cell in an embodiment of the application Figure 1 ;

[0054] Figure 4 is an enlarged schematic view of part of the structure in the first surface of a solar cell in an embodiment of the application Figure 2 ;

[0055] Figure 5 is an enlarged schematic view of part of the structure in the second surface of a solar cell in an embodiment of the application.

[0056] REFERENCE NUMERALS

[0057] 1 - semiconductor substrate, 10 - first surface, 100 - first electrode region, 101 - first non-electrode region, 102 - first texture structure, 103 - second texture structure; 11 - second surface, 110 - second electrode region, 111 - second non-electrode region, 112 - fourth texture structure; 12 - side surface, 120 - groove; 3 - tunneling layer, 4 - doped conductive layer, 5 - passivation layer, 50 - aluminum oxide passivation layer, 51 - silicon nitride passivation layer; 6 - first electrode, 7 - second electrode. DETAILED DESCRIPTION

[0058] In order to make the technical problems to be solved by the application, the technical solutions and the beneficial effects clearer, the application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application.

[0059] It should be noted that when an element is referred to as being "fixed" or "set" on another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, the terms "first", "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0060] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0061] In a first aspect, an embodiment of the present application provides a solar cell. Referring to Figure 1 The solar cell includes a semiconductor substrate 1, a first doped layer and a second doped layer. The semiconductor substrate 1 includes opposite first and second faces 10 and 11, the first face 10 including a first electrode region 100 and a first non-electrode region 101. The surface of the first electrode region 100 has a first textured structure 102, and the first non-electrode region 101 has a second textured structure 103 and a third textured structure (not shown) Figure 1The second texture structure 103 is located in the middle region of the semiconductor substrate 1, and the third texture structure is located in the edge region of the semiconductor substrate 1, the width of the edge region is less than or equal to 3mm, and the third texture structure has a smaller fluctuation than the second texture structure 103. The first doped layer is arranged in the first electrode region 100, and the second doped layer is arranged in the first non-electrode region 101. The doping concentration of the first doped layer is greater than that of the second doped layer. The edge region refers to the region close to the four edges of the semiconductor substrate 1, and the edge region surrounds the middle region. The width of the edge region refers to the distance from the side of the edge region away from the edge of the semiconductor substrate 1 to the edge of the semiconductor substrate 1.

[0062] In terms of shape, the first surface and the second surface of the semiconductor substrate 1 can be the same or different. In the embodiment of the present application, the first surface and the second surface are the same. For example, the shape of the first surface 10 or the second surface 11 can be square, rectangular, rounded square, circular, etc.

[0063] In terms of material, the semiconductor substrate 1 can be a substrate of any semiconductor material such as silicon substrate, germanium-silicon substrate, germanium substrate or gallium arsenide substrate.

[0064] In terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an N-type conductive substrate or a P-type conductive substrate. Preferably, the semiconductor substrate 1 is a P-type conductive substrate or an N-type conductive substrate. Compared with the intrinsic conductive substrate, the P-type conductive substrate or the N-type conductive substrate has better conductivity, so that the final solar cell has lower bulk resistivity, thereby improving the efficiency of the solar cell. For example, the semiconductor substrate 1 is an N-type silicon substrate. Compared with the P-type conductive substrate, the N-type silicon substrate has the advantages of high minority carrier lifetime, no light decay and good weak light performance.

[0065] In terms of light receiving, when the first surface 10 is the light receiving surface, the second surface 11 is the back light surface.

[0066] Referring to Figure 1 In the solar cell provided by the embodiment of the present application, the doping concentration of the first doped layer arranged in the first electrode region 100 is greater than that of the second doped layer arranged in the first non-electrode region 101. By reducing the doping concentration of the first non-electrode region 101, the area of high concentration on the front surface of the solar cell is reduced, the problem of recombination caused by high doping concentration on the surface of the semiconductor substrate 1 is reduced, and the open circuit voltage of the cell is increased. At the same time, the first doped layer of the first electrode region 100 is retained, so that the contact resistance between the electrode and the first doped layer is small, the series resistance of the cell is reduced, the fill factor is improved, and the efficiency of the solar cell is improved.

[0067] Referring to Figure 1, the first non-electrode region 101 is focused on the light trapping effect and passivation performance of the front side of the cell, and the first electrode region 100 is focused on the contact performance and passivation performance. Based on the above functional distinction between the first electrode region 100 and the first non-electrode region 101, the first non-electrode region 101 needs to take into account the light trapping effect and the passivation performance of the passivation layer film. In the present application, the first non-electrode region 101 has a second texture structure 103 located in the middle region of the semiconductor substrate 1 and a third texture structure located in the edge region of the semiconductor substrate 1, and the fluctuation degree of the third texture structure is smaller than that of the second texture structure 103. That is, in the present application, the first non-electrode region 101 extending to the edge region of the semiconductor substrate 1 has a third texture structure with a relatively flat fluctuation degree, which can provide a good surface for the subsequent passivation layer coverage, and at the same time, the fluctuation degree is small, indicating that the specific surface area of the semiconductor substrate 1 located in the edge region is small, and in the same plating process, a thicker passivation layer can be formed to meet the passivation performance of the edge of the solar cell and ensure the efficiency of the solar cell.

[0068] As a possible implementation, regarding "the doping concentration of the first doped layer is greater than the doping concentration of the second doped layer", the doping concentration of the second doped layer is greater than or equal to zero.

[0069] Referring to Figure 1 When the doping concentration of the second doped layer is zero, the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 form a PN junction, and the first non-electrode region 101 of the semiconductor substrate 1 does not have a PN junction; that is, the first side 10 of the solar cell includes a heavily doped region and an undoped region. At this time, the recombination level of the first non-electrode region 101 in the first side 10 is effectively reduced, the open circuit voltage of the cell is improved, and at the same time, high doping can be performed in the first electrode region 100, the contact resistance between the electrode and the first doped layer is improved, the series resistance of the cell is reduced, and the fill factor is improved, thereby improving the efficiency of the solar cell.

[0070] Further, the "doping concentration of the first doped layer" can refer to the doping concentration of the surface of the first doped layer, or the average concentration of the concentration at different positions along the thickness direction of the first doped layer.

[0071] Similarly, the "doping concentration of the second doped layer" can refer to the doping concentration of the surface of the second doped layer, or the average concentration of the concentration at different positions along the thickness direction of the second doped layer.

[0072] The "doping concentration of the first doped layer is greater than the doping concentration of the second doped layer" can be that the doping concentration of the surface of the first doped layer is greater than the doping concentration of the surface of the second doped layer. Alternatively, the average concentration of the first doped layer along the different positions of the thickness direction is greater than the average concentration of the second doped layer along the different positions of the thickness direction.

[0073] In some embodiments, referring to Figure 1 The first doped layer described above can be a film layer additionally formed on the semiconductor substrate 1, or the first doped layer is formed by diffusion treatment on the first surface 10 of the semiconductor substrate 1, and the top surface of the first doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0074] In some embodiments, referring to Figure 1 The second doped layer described above can be a film layer additionally formed on the semiconductor substrate 1, or the second doped layer is formed by diffusion treatment on the first surface 10 of the semiconductor substrate 1, and the top surface of the second doped layer is coplanar with the first surface 10 of the semiconductor substrate.

[0075] As a possible implementation, referring to Figures 1 to 4 The semiconductor substrate 1 is an N-type silicon substrate, the first doped layer is a P-type doped layer, the second doped layer is a P-type doped layer, and the first doped layer and the second doped layer are diffusion layers on the surface of the semiconductor substrate 1. At this time, the surface of the first doped layer and the second doped layer is a single crystal silicon surface, and the doping concentration of the second doped layer is set to be less than the doping concentration of the first doped layer, which improves the passivation of the subsequent passivation layer on the surface of the semiconductor substrate 1, and is more important than the battery structure with an additional doped layer.

[0076] As a possible implementation, the third texture structure includes one or more of a tower base structure, a prismatic structure, an inverted pyramid structure, a prismatic structure, or a pyramid structure. At this time, the shape selectivity of the third texture structure is increased, and the application scenarios of the solar cell are increased.

[0077] As a possible implementation, referring to Figure 1 The first texture structure 102 and / or the second texture structure 103 is a pyramid structure. At this time, it is beneficial to increase the surface area of the semiconductor substrate 1 and improve the light trapping effect of the semiconductor substrate 1, and it is beneficial to make more light be refracted into the semiconductor substrate 1 through the area where the first texture structure 102 and / or the second texture structure 103 is located and be utilized by the semiconductor substrate 1, so that the solar cell has a higher photoelectric conversion efficiency.

[0078] In an optional manner, referring to Figure 1, the first texture structure 102 is a pyramid structure, the height of the pyramid of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 4 μm, and the size of the base of the first texture structure 102 is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the first texture structure 102 can be square, rhombic, rectangular, parallelogram, approximately rhombic or approximately rectangular. The size of the base of the first texture structure 102 can be the length, the short side, the diagonal or the farthest distance between two endpoints of the base shape. The height of the pyramid and the size of the base of the first texture structure 102 can be the height of the pyramid or the size of the base of a single texture structure, or the average of the height of the pyramid or the size of the base of the first texture structure 102 in a certain area. For example, in the range of 1 μm x 1 μm, the height of the pyramid of the first texture structure 102 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm, etc. The size of the base of the first texture structure 102 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm, etc.

[0079] In an optional manner, referring to Figure 1 , the second texture structure 103 is a pyramid structure, the height of the pyramid of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 4 μm, and the size of the base of the second texture structure 103 is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the second texture structure 103 can be square, rhombic, rectangular, parallelogram, approximately rhombic or approximately rectangular. The size of the base of the second texture structure 103 can be the length, the short side, the diagonal or the farthest distance between two endpoints of the base shape. The height of the pyramid and the size of the base of the second texture structure 103 can be the height of the pyramid or the size of the base of a single texture structure, or the average of the height of the pyramid or the size of the base of the second texture structure 103 in a certain area. For example, in the range of 1 μm x 1 μm, the height of the pyramid of the second texture structure 103 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm, etc. The size of the base of the second texture structure 103 can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm, etc.

[0080] Referring to Figure 1 , the height of the pyramid or the size of the base of the first texture structure 102 and the second texture structure 103 can be equal or not equal.

[0081] As a possible implementation, referring to Figures 1 to 5 , the partial edge region has a tunneling layer 3 and / or a doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 are arranged on the first doped layer and / or the second doped layer, the first doped layer and the second doped layer have the same doping type, and the doping type of the doped conductive layer 4 is opposite to that of the first doped layer and the second doped layer.

[0082] Referring to Figures 1 to 5 , the chemical passivation of the tunneling layer 3 and the field passivation of the doped conductive layer 4 can significantly reduce the recombination degree of the surface of the semiconductor substrate 1. The tunneling layer 3 and the doped conductive layer 4 can further passivate the edges of the cell sheet and reduce the recombination of the edges of the cell sheet. In addition, due to the partial edge region provided with the tunneling layer 3 and / or the doped conductive layer 4, the damage to the surface of the middle part of the first surface 10 can be reduced in the process step of removing the tunneling layer 3 and / or the doped conductive layer 4 of the side surface 12, the probability of damaging the first texture structure 102 and the second texture structure 103 is reduced, and the light trapping effect of the front surface is improved.

[0083] Referring to Figures 1 to 5 , the material and thickness of the tunneling layer 3 can be set according to actual conditions, which are not specifically limited here. For example, the material of the tunneling layer 3 can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbon nitride, aluminum nitride, titanium nitride, and titanium carbon nitride. The thickness of the tunneling layer 3 is greater than or equal to 1 nm and less than or equal to 2 nm, for example, the thickness of the tunneling layer 3 can be 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 1.8 nm, or 2 nm, etc. Further, the doped conductive layer 4 can be a doped polysilicon layer, which can be a phosphorus-doped polysilicon layer, and can also be doped with other substances, which are not specifically limited here.

[0084] As a possible implementation, referring to Figure 2 , the semiconductor substrate 1 further includes a plurality of side surfaces 12 between the first surface 10 and the second surface 11; at least part of the side surfaces 12 are provided with grooves 120, and the groove bottoms of the grooves 120 are lower than the surfaces of the side surfaces 12.

[0085] Referring to Figure 2 , when the doped conductive layer 4 is formed on the second surface, the doped conductive layer 4 will also be formed on the side surfaces 12 and the first electrode area 100 of the first surface 10 by plating. The doped conductive layer 4 on the first surface 10 and the second surface is separated by the grooves 120 provided on at least part of the side surfaces 12, so as to avoid short circuit and edge leakage of the solar cell. The grooves 120 can also increase the distance between the first surface 10 and the second surface, and increase the difficulty of the doped conductive layer 4 on the first surface 10 and the second surface overlapping on the side surface 12. In the preparation process, the semiconductor substrate 1 on the side surface of the cell is etched to remove the inner extension layer formed in the semiconductor substrate 1 during the formation of the doped conductive layer 4, thereby reducing the possibility of short circuit caused by contact between the doped conductive layers 4 with opposite polarities.

[0086] In some embodiments, referring to Figure 2When the solar cell is a whole solar cell, the four sides 12 of the semiconductor substrate 1 can all be provided with grooves 120, or at least one side 12 can be provided with grooves 120.

[0087] See Figure 2 When the solar cell is a segmented solar cell, grooves 120 can be provided on three of the four sides 12 of the semiconductor substrate 1, excluding the segmented side, or grooves 120 can be provided on at least one side 12 other than the segmented side.

[0088] In some embodiments, participate Figure 2 The height difference between the bottom of the groove 120 and the surface of the side 12 is ( Figure 2 The height difference (H1 and H2 in the figure) is greater than or equal to 0.5 μm and less than or equal to 7 μm. For example, the height difference can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm or 7 μm, etc.

[0089] In some embodiments, see 1 to Figure 5 Along the thickness direction of the semiconductor substrate 1, the width of the groove 120 accounts for 50% to 95% of the width of the side surface 12, and the width of the groove 120 is greater than or equal to 60 μm and less than or equal to 130 μm. For example, the percentage can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 86%, 90%, or 95%. Along the thickness direction of the semiconductor substrate 1, the width of the side surface 12 is 140 μm, and the width of the groove 120 can be 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 120 μm, or 130 μm. By setting the groove 120 within the above width range, the probability of overlap between the doped layer (i.e., the first doped layer and / or the second doped layer) or the doped conductive layer 4 can be reduced by increasing the area of ​​the side surface 12, thereby reducing the leakage risk of the solar cell due to the overlap of the doped layer or the doped conductive layer 4 on the side surface 12.

[0090] In some embodiments, see 1 to Figure 5 The boundary line between the sidewall of the groove 120 and the side surface 12 is wavy. Therefore, the proportion of the width of the groove 120 to the width of the side surface 12 is not equal in every part of the solar cell, showing a random distribution.

[0091] Based on the preceding description, see [link / reference]. Figure 1 The first doped layer may be an additional film layer formed on the semiconductor substrate 1; or, the first doped layer may be formed by diffusion treatment of the first surface 10 of the semiconductor substrate 1, in which case the top surface of the first doped layer is coplanar with the first surface 10 of the semiconductor substrate 1.

[0092] The following describes the way of obtaining or calculating the height difference between the groove bottom of the groove and the surface of the side surface in three possible cases. It should be noted that the following description is for understanding only and is not used for specific definition.

[0093] The first kind: see Figure 1 and Figure 2 When the first doped layer is a film layer additionally formed on the semiconductor substrate 1, the first distance between the groove bottom of the groove 120 and the outer side surface of the first doped layer and the thickness of the first doped layer formed on the side surface 12 where the groove 120 is located are obtained; then, the difference between the first distance and the thickness of the first doped layer is calculated, which is the height difference between the groove bottom of the groove 120 and the surface of the side surface 12.

[0094] The second kind: see Figure 1 and Figure 2 When the first doped layer is a film layer additionally formed on the semiconductor substrate 1, the height difference between the groove bottom of the groove 120 and the surface of the side surface 12 is directly measured, which is the interface between the semiconductor substrate 1 and the first doped layer.

[0095] The third kind: when the first doped layer is formed by diffusion treatment on the first surface 10 of the semiconductor substrate 1, the height difference between the groove bottom of the groove 120 and the surface of the side surface 12 is directly measured.

[0096] See Figure 2 If the height difference between the groove bottom of the groove 120 and the surface of the side surface 12 is less than 0.5 μm, the depth of the groove 120 is relatively shallow, at this time, the groove 120 provided on the side surface 12 cannot effectively isolate the doped conductive layer 4 on the first surface 10 and the second surface, and cannot guarantee that the inner diffusion layer of the side surface 12 of the battery is completely removed, which increases the probability of short circuit and edge leakage of the solar cell. If the height difference between the groove bottom of the groove 120 and the surface of the side surface 12 is greater than 7 μm, the depth of the groove 120 is relatively deep, at this time, the side surface 12 of the semiconductor substrate 1 is removed more, which reduces the overall mechanical strength of the battery piece; and the solar cell generates electricity by separating electrons and holes on the semiconductor substrate 1 under light, if the semiconductor substrate 1 is removed too much, the light absorption rate of the semiconductor substrate 1 is reduced, which reduces the number of photo-generated carriers, i.e. holes and electrons, generated on the semiconductor substrate 1, thereby reducing the photoelectric conversion rate of the solar cell. In view of the above two aspects, the application sets the height difference between the surface of the groove 120 and the surface of the side surface 12 within a reasonable range, avoids the short circuit and edge leakage of the solar cell, guarantees a high light absorption rate of the semiconductor substrate 1, and prevents the photoelectric conversion rate of the solar cell from being reduced, and also guarantees that the battery piece has sufficient mechanical strength.

[0097] In some embodiments, referring to Figure 2 , the surface of the side surface 12 includes a surface close to the first surface 10 and a surface close to the second surface, the distance H1 between the groove bottom of the groove 120 and the surface close to the first surface 10 among the surface of the side surface 12 is greater than the distance H2 between the groove bottom of the groove 120 and the surface close to the second surface among the surface of the side surface 12. Since H1 and H2 are not formed in the same process step, H2 is set to be less than H1, the etching depth of the solar cell side surface 12 is reduced, and the mechanical strength of the solar cell is ensured.

[0098] As a possible implementation, referring to Figures 1 to 5 , along the thickness direction A of the semiconductor substrate 1, the first electrode area 100 is higher than the first non-electrode area 101. Along the thickness direction of the semiconductor substrate 1, the distance L1 between the first electrode area 100 and the first non-electrode area 101 is greater than or equal to 2 μm and less than or equal to 7 μm. At this time, the first non-electrode area 101 is recessed relative to the first electrode area 100, so that light can be reflected and absorbed in the groove 120 to reduce the reflectivity of the second texture structure 103 and the third texture structure.

[0099] Referring to Figures 2 to 4 , the distance L1 between the first electrode area 100 and the first non-electrode area 101 can be the distance between the top surface of the first electrode area 100 and the top surface of the first non-electrode area 101, or the distance between the bottom surface of the first electrode area 100 and the bottom surface of the first non-electrode area 101, or the distance between the bottom surface of the first electrode area 100 and the top surface of the first non-electrode area 101, or the distance between the top surface of the first electrode area 100 and the bottom surface of the first non-electrode area 101. Exemplarily, the distance L1 between the top surface of the first electrode area 100 and the top surface of the first non-electrode area 101 can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm or 7 μm, etc.

[0100] It is worth noting that, referring to Figures 2 to 4 , the top surface of the first electrode area 100 is composed of the top points of a plurality of first texture structures 102, which varies based on the size of different first texture structures 102. Here, the top surface is the plane composed of the top points of most first texture structures 102 in the first electrode area 100, and the proportion of most first texture structures 102 in the first electrode area 100 can be flexibly selected according to actual conditions. Similarly, the top surface of the first non-electrode area 101 is composed of the top points of a plurality of second texture structures 103.

[0101] As a possible implementation, referring to Figures 1 to 5The reflectivity of the first electrode area 100 where the first texture structure 102 is located is greater than the reflectivity of the first non-electrode area 101 where the second texture structure 103 is located. The surface of the first non-electrode area 101 where the second texture structure 103 is located is not blocked by the grid lines, and the low reflectivity of the second texture structure 103 can better utilize the incident light and improve the light absorption rate, thereby improving the photoelectric conversion rate of the solar cell.

[0102] As a possible implementation, see Figure 1 and Figure 2 The second surface 11 includes a second electrode area 110 and a second non-electrode area 111. The second electrode area 110 and the second non-electrode area 111 are arranged alternately on the second surface. The tunneling layer 3 is arranged on the surface of the second electrode area 110, and the doped conductive layer 4 is arranged on the second electrode area 110 and located on the side of the tunneling layer 3 away from the semiconductor substrate 1. The surface of the second electrode area 110 includes a tower base structure, the fluctuation degree of the tower base structure is less than that of the pyramid structure, and the reflectivity of the surface of the area where the tower base structure is located is greater than that of the surface of the area where the pyramid structure is located.

[0103] See Figure 1 and Figure 2 The second electrode area 110 and the second non-electrode area 111 are arranged on the second surface 11, and the second non-electrode area 111 is not provided with the tunneling layer 3 and the doped conductive layer 4, which can reduce the area of the doped conductive layer 4 on the second surface 11, reduce the parasitic absorption on the second surface 11, and improve the utilization rate of the incident light on the second surface 11 of the solar cell. In the preparation process of the tunneling layer 3 and the doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 are usually deposited on the second surface 11 in a whole layer, and then removed from the second non-electrode area 111 by laser, wet etching and other methods. Therefore, arranging the second electrode area 110 higher than the second non-electrode area 111 can ensure that the inner extension layer on the surface of the semiconductor substrate 1 in the second non-electrode area 111 is removed at the same time as the tunneling layer 3 and the doped conductive layer 4 in the second non-electrode area 111 are removed, reducing the Auger recombination caused by the doping elements in the second non-electrode area 111, reducing the probability of carrier recombination in the second non-electrode area 111, and improving the battery efficiency.

[0104] In some embodiments, see Figure 2 and Figure 5, along the thickness direction A of the semiconductor substrate, the second electrode region 110 is higher than the second non-electrode region 111. The distance L2 between the second electrode region 110 and the second non-electrode region 111 is greater than or equal to 2 pm and less than or equal to 6 pm. The distance L2 between the second electrode region 110 and the second non-electrode region 111 can be the distance between the top surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the bottom surface of the second non-electrode region 111, or the distance between the bottom surface of the second electrode region 110 and the top surface of the second non-electrode region 111, or the distance between the top surface of the second electrode region 110 and the bottom surface of the second non-electrode region 111. Exemplarily, the distance L2 between the second electrode region 110 and the second non-electrode region 111 can be 2 pm, 2.5 pm, 3 pm, 3.5 pm, 4 pm, 4.5 pm, 5 pm, 5.5 pm, or 6 pm, etc.

[0105] Referring to Figures 1 to 5 , if the distance between the second electrode region 110 and the second non-electrode region 111 along the thickness direction A of the semiconductor substrate is greater than 6 pm, the depth of the second non-electrode region 111 is deeper, at this time, the second surface 11 of the semiconductor substrate 1 is removed more, which will reduce the mechanical strength of the whole battery piece; and the solar cell generates electricity by separating electrons and holes on the semiconductor substrate 1 under light, if the semiconductor substrate 1 is removed too much, the transmission path of light in the semiconductor substrate 1 will be reduced, the light absorption rate of the semiconductor substrate 1 will be reduced, which will reduce the number of photo-generated carriers, i.e. holes and electrons, generated on the semiconductor substrate 1, and further reduce the photoelectric conversion rate of the solar cell. In the present application, the distance between the surface of the second electrode region 110 and the surface of the second non-electrode region 111 along the thickness direction of the semiconductor substrate 1 is set within the above value range, which ensures that the light absorption rate of the semiconductor substrate 1 is high, the photoelectric conversion rate of the solar cell will not be reduced, and also ensures that the battery piece has sufficient mechanical strength.

[0106] In some embodiments, referring to Figures 1 to 5 , in the process of forming the fourth texture structure 112 by texturing the second non-electrode region 111 of the second surface 11, a part of the semiconductor substrate 1 located in the second non-electrode region 111 is removed by corrosion, so that along the thickness direction A of the semiconductor substrate, the surface of the second non-electrode region 111 is higher than the surface of the second electrode region 110.

[0107] Referring to Figures 1 to 5At this time, the surface of the second non-electrode region 111 is composed of the vertices of the plurality of fourth texture structures 112, and the surface of the second non-electrode region 111 is a plane composed of the vertices of the most fourth texture structures 112 on the second non-electrode region 111. The proportion of the most fourth texture structures 112 in the second non-electrode region 111 can be flexibly selected according to actual conditions.

[0108] In some embodiments, referring to Figures 1 to 5 , the projection of the first non-electrode region 101 on the first surface 10 and the projection of the second non-electrode region 111 on the first surface 10 at least partially overlap along the thickness direction A of the semiconductor substrate 1.

[0109] Referring to Figures 1 to 5 , in actual production of solar cells, the second non-electrode region 111 is a laser-acting region. When the laser acts on the second surface 11 of the semiconductor substrate 1, it will affect the first surface 10 of the semiconductor substrate 1, causing the surface of the first surface 10 corresponding to the laser-acting region to change. Based on this, when the second non-electrode region 111 and the first non-electrode region 101 are arranged to overlap along the thickness direction of the semiconductor substrate 1, the laser-affected region on the other surface (i.e., the first non-electrode region 101) affected by the laser-acting region (i.e., the second non-electrode region 111) can be etched and removed in the process, reducing the area of the first surface 10 and the second surface 11 of the semiconductor substrate 1 affected by the laser, and providing a good surface foundation for subsequent film plating and electrode printing. When the second non-electrode region 111 and the first non-electrode region 101 are both recessed into the semiconductor substrate 1, if the second non-electrode region 111 and the first non-electrode region 101 completely correspond along the thickness direction of the semiconductor substrate 1, the thickness of the semiconductor substrate 1 located in the second non-electrode region 111 and the first non-electrode region 101 is smaller than the thickness of the semiconductor substrate 1 located in the second electrode region 110 and the first electrode region 100. That is, the thickness of the semiconductor substrate 1 in the non-electrode region is smaller than the thickness of the semiconductor substrate 1 in the electrode region, thereby significantly reducing the mechanical strength of the semiconductor substrate 1 in the non-electrode region. In this application, the second non-electrode region 111 and the first non-electrode region 101 are arranged to stagger along the thickness direction of the semiconductor substrate 1, which can meet the requirements of the mechanical strength of the semiconductor substrate 1 and reduce or eliminate the probability of fracture of the semiconductor substrate 1.

[0110] In an optional way, referring to Figure 1 and Figure 2 , the second non-electrode region 111 has fourth texture structures 112. The fourth texture structures 112 include pyramid-type structures and tower base structures. Compared with the second non-electrode region 111 without texture structures, the reflectivity of the second non-electrode region 111 is significantly reduced, and the battery efficiency is not affected by cooperating with the optimization of the passivation process, further improving the double-side rate of the battery.

[0111] In an alternative, referring to Figure 1 and Figure 2 , the second non-electrode region 111 has a fourth texture structure 112, and the fourth texture structure 112 has a size consistency lower than that of the first texture structure 102. For example, the fourth texture structure 112 and the first texture structure 102 are pyramid structures.

[0112] Referring to Figure 1 and Figure 2 , the size consistency refers to the consistency of the base one-dimensional size and / or the height of the pyramid structure. The size consistency is the difference between the size of the pyramid structure in a certain region and the average size of the pyramid structure in the region. For example, the base one-dimensional size of the pyramid structure in a unit area of the first non-electrode region 101 and the base one-dimensional size of the pyramid structure in the second non-electrode region 111 can be counted respectively, and the variance or range of the size of the pyramid structure in the first non-electrode region 101 and the second non-electrode region 111 can be calculated respectively. The variance or range of the pyramid structure in the first non-electrode region 101 and the second non-electrode region 111 can be used as a reference for consistency, and different pyramid structures can be compared in terms of the size of the variance or range to compare the consistency. The smaller the variance or range, the better the size consistency.

[0113] As a possible implementation, referring to Figure 1 and Figure 2 , the second non-electrode region 111 has a fourth texture structure 112, and the middle region of the first non-electrode region 101 has a second texture structure 103, and the second texture structure 103 has a size consistency greater than that of the fourth texture structure 112.

[0114] Referring to Figure 1 and Figure 2The first non-electrode region 101 is located on the light-receiving surface of the bifacial solar cell. Compared with the second non-electrode region 111, most of the incident light is incident from the light-receiving surface, and therefore better light-trapping effect and passivation performance are required to ensure that the incident light enters the semiconductor substrate 1 from the light-receiving surface instead of being reflected or incident to the surface of the light-receiving surface and being recombined by the recombination center on the light-receiving surface, to improve the possibility of the incident light transmitting to the laser light-generated carrier in the semiconductor substrate 1, thereby increasing the utilization rate of the solar cell for the incident light. The second texture structure 103 located on the light-receiving surface has higher size consistency than the fourth texture structure 112 located on the back light surface, which can ensure that the middle region of the first non-electrode region 101 has better light-trapping effect at different positions, reduces the probability of the incident light being reflected to the outside of the solar cell, and at the same time, the size consistency of the second texture structure 103 is good, which can provide a relatively regular surface, which is more favorable to the thickness uniformity of the subsequent passivation layer 5, thereby improving the passivation performance of the surface of the first non-electrode region 101, reducing the possibility of the incident light being recombined on the surface of the first non-electrode region 101, and ensuring that the incident light has a greater probability of being incident to the semiconductor substrate 1 and not being recombined by the surface defect when being incident to different positions of the first non-electrode region 101. The size consistency of the second texture structure 103 is designed to be greater than that of the fourth texture structure 112, and the prepared second texture structure 103 and fourth texture structure 112 can meet the requirements of light-trapping and passivation of the light-receiving surface of the solar cell, and the requirement of improving the light-trapping performance of the back light surface. In combination with the preparation process, the size differentiation setting of the second texture structure 103 and the fourth texture structure 112 can reduce the etching degree of the second non-electrode region 111 of the solar cell, reduce the loss in the thickness direction of the semiconductor substrate 1, ensure the thickness of the cell sheet, increase the utilization of the absorbed incident light, and ensure the mechanical strength of the cell sheet.

[0115] Referring to Figure 1 and Figure 2The size consistency of the fourth texture structure 112 of the second non-electrode area 111 is good, the light trapping effect on the surface of the second non-electrode area 111 can be improved, the light trapping effect of the back surface of the solar cell on the incident light can be improved, and the probability that the light transmitted to the back surface of the solar cell is reflected out of the solar cell can be reduced; meanwhile, the size consistency of the first texture structure 102 in the first electrode area 100 and the second texture structure 103 of the first non-electrode area 101 is better, the reflection of the front surface of the solar cell is enhanced, the light trapping effect of the front surface of the solar cell is improved, the uniformity of the thickness of the passivation layer 5 at different positions during the plating of the passivation layer 5 on the front surface of the solar cell is enhanced, the passivation performance of the front surface of the solar cell is improved, and the probability that the incident light is recombined on the light receiving surface is reduced. Through the matching of the structure of the electrode area and the non-electrode area on the light receiving surface and the back surface and the texture structure on different areas, the light utilization rate is improved from two aspects of improving the light trapping effect and reducing the recombination probability of the incident light, and then the efficiency of the solar cell is improved.

[0116] As a possible implementation manner, refer to Figure 1 and Figure 2 , the first electrode area 100 and / or the second electrode area 110 include a current collecting electrode area and a busbar electrode area, the extension direction of the current collecting electrode area and the extension direction or arrangement direction of the busbar electrode area intersect; the width of the busbar electrode area is greater than the width of the current collecting electrode area. The busbar electrode area includes a continuous busbar electrode, or an intermittent busbar electrode and a terminal line structure arranged at the edge of the cell piece, for welding of the interconnection such as a solder strip in the assembly.

[0117] Refer to Figure 1 and Figure 2 , the contact performance of the busbar electrode with the solar cell is lower than that of the current collecting electrode, or the busbar electrode needs to be welded with the interconnection such as a solder strip, and the contact area with the surface of the solar cell or the interconnection is increased by increasing the width of the busbar electrode to improve the contact performance and welding performance of the busbar electrode. Therefore, the width of the busbar electrode area in the first electrode area 100 and the second electrode area 110 is greater than the width of the current collecting electrode area, the area of the first electrode area 100 and the second electrode area 110 is reduced, and the contact performance and welding performance of the busbar electrode with the solar cell are ensured.

[0118] In a second aspect, the embodiments of the present application also provide a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string includes a plurality of interconnections and a plurality of solar cells as described in the above technical solutions, the interconnections are used to connect the plurality of solar cells together to form the cell string, and the encapsulation layer is used to cover the surface of the cell string.

[0119] The photovoltaic module provided by the embodiment of the present application has the same beneficial effects as the solar cell described in the above technical solution, and thus will not be described herein.

[0120] In a third aspect, the present application further provides a method for manufacturing a solar cell. Figure 1 and Figure 2 The method for manufacturing a solar cell comprises the following steps.

[0121] Firstly, a semiconductor substrate 1 is provided; the semiconductor substrate 1 has a first surface 10 and a second surface 11 opposite to each other, and a plurality of side surfaces 12 between the first surface 10 and the second surface 11. The first surface 10 and the second surface 11 are subjected to a texturing treatment to form a first texture structure 102; the first surface 10 comprises a first electrode region 100 and a first non-electrode region 101;

[0122] The first texture structure 102 can trap light, reduce the reflection of sunlight by the solar cell, and improve the performance of the solar cell.

[0123] For example, the semiconductor substrate 1 is subjected to a cleaning treatment, and then the first surface 10 and the second surface are subjected to a texturing treatment by using an alkaline texturing solution. The specific cleaning steps and texturing methods can be referred to the prior art, and thus will not be limited herein. The shape, material, conductive type and light receiving aspect of the semiconductor substrate 1 have been described above, and thus will not be described herein.

[0124] Next, the first surface 10 of the semiconductor substrate 1 is subjected to a diffusion treatment to form a first doped layer and a first doped oxide layer formed on the first doped layer; the conductive type of the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 are opposite to each other, and at this time, the semiconductor substrate 1 and the first doped layer located in the first electrode region 100 form a PN junction.

[0125] For example, the diffusion treatment uses a group III source, such as a boron source, a gallium source, an indium source, etc.

[0126] In an optional manner, the group III source is a boron source, and the first doped oxide layer is a borosilicate glass layer. The borosilicate glass layer can play a protective role in the subsequent processing of the solar cell, reduce the risk of etching the first electrode region 100, and ensure the quality of the solar cell.

[0127] In some embodiments, the first surface 10 of the semiconductor substrate 1 can be subjected to a diffusion process to form a first doped layer and a first doped oxide layer on the first doped layer. The diffusion process can be performed by placing the semiconductor substrate 1 in a tube furnace and diffusing a boron source BCl3or BBr3in a nitrogen and oxygen atmosphere. The diffusion time and temperature can be set according to actual needs. In this way, the first doped layer (e.g., a P+ doped layer) and the first doped oxide layer (e.g., a borosilicate glass layer) are formed.

[0128] Next, the first doped oxide layer on the first non-electrode region 101 is removed.

[0129] The following describes the removal of the first doped oxide layer on the first non-electrode region 101 in two possible ways. It should be understood that the following description is for understanding only and is not used to specifically limit.

[0130] The first way is to use a first laser to irradiate the first doped oxide layer on the first non-electrode region 101.

[0131] Specifically, the first doped oxide layer on the first non-electrode region 101 is irradiated by a first laser process to remove the first doped oxide layer on the first non-electrode region 101. For example, the first laser irradiation destroys the borosilicate glass layer on the first non-electrode region 101, reducing the protective effect of the borosilicate glass layer on the first non-electrode region 101. The first laser can be any one of red light, green light, or violet light. The high-energy laser beam of a specific wavelength emitted by the laser acts on the borosilicate glass layer. The borosilicate glass layer absorbs the high-energy laser, causing the atoms in the borosilicate glass layer to vibrate, migrate, and other movements, destroying the chemical bonds between the atoms, thereby destroying the internal structure of the borosilicate glass layer and making the borosilicate glass layer loose. Alternatively, when the laser energy is very high, the borosilicate glass layer will melt and vaporize in a short time, and finally evaporate. Regardless of whether the borosilicate glass layer is removed or loose, its protective effect on the first non-electrode region 101 is significantly reduced. During subsequent alkali cleaning, the borosilicate glass layer is not sufficiently protected, allowing the alkali to corrode the semiconductor substrate 1.

[0132] It should be noted that after the first doped oxide layer subjected to the first laser irradiation process is loose, it can be immediately cleaned with a cleaning solution to remove the first doped oxide layer on the first non-electrode region 101. Alternatively, after the first doped oxide layer subjected to the first laser irradiation process is loose, it can be left untreated until the loose first doped oxide layer is removed when other film layers on the semiconductor substrate are cleaned later.

[0133] For example, the first laser wavelength in the first laser process is greater than or equal to 300 nm and less than or equal to 1200 nm. For example, the first laser wavelength can be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, or 1200 nm, etc.

[0134] The second way is to pattern the first doped oxide layer to remove the first doped oxide layer on the first non-electrode region 101. For example, a mask layer is formed on the first doped oxide layer in the first electrode region 100. The mask layer can resist acid corrosion, but can be easily removed by alkaline cleaning. Then, the first doped oxide layer in the first non-electrode region 101 is removed by using a first cleaning solution. For example, by using HF acid cleaning, the borosilicate glass layer in the first electrode region 100 is protected by the mask layer and is not affected. The borosilicate glass layer in the first non-electrode region 101 is removed by HF corrosion. At this time, the alkaline cleaning can corrode the semiconductor substrate 1 due to the loss of the borosilicate glass layer in the first non-electrode region 101. Then, the mask layer is removed by using a second cleaning solution. For example, the mask layer is removed by using an alkaline solution.

[0135] As a possible implementation, the width W1 of the first non-electrode region 101 is greater than or equal to 200 μm and less than or equal to 800 μm. For example, the width W1 of the first non-electrode region 101 can be 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, or 800 μm, etc.

[0136] Next, the first doped layer in the first non-electrode region 101 is etched to form a second doped layer, so that the doping concentration of the second doped layer is less than the doping concentration of the first doped layer.

[0137] The doping concentration of the first doped layer in the first electrode region 100 is greater than the doping concentration of the second doped layer in the first non-electrode region 101. By reducing the doping concentration of the first non-electrode region 101, the area of high concentration on the front surface of the solar cell is reduced, the problem of recombination on the surface of the semiconductor substrate 1 caused by high doping concentration is reduced, and the open circuit voltage of the cell is increased. At the same time, the first doped layer in the first electrode region 100 is retained to ensure that the contact resistance between the electrode and the first doped layer is small, the series resistance of the cell is reduced, the fill factor is improved, and the efficiency of the solar cell is improved.

[0138] For example, the first doped layer in the first non-electrode region 101 is etched away, and the remaining part of the first doped layer is the second doped layer, and the doping concentration of the second doped layer is less than that of the first doped layer. Alternatively, the first doped layer in the first non-electrode region 101 is etched away completely, and the doping concentration of the second doped layer in the first non-electrode region 101 is zero. That is, the PN junction in the first non-electrode region 101 is removed, which effectively reduces the recombination level of the first non-electrode region 101 in the first surface 10, improves the open circuit voltage of the solar cell, and allows high doping in the first electrode region 100, improves the contact resistance between the electrode and the first doped layer in the first electrode region 100, reduces the series resistance of the solar cell, improves the fill factor, and thus improves the efficiency of the solar cell.

[0139] In some embodiments, the first non-electrode region 101 is etched to a depth of greater than or equal to 1 μm and less than or equal to 5 μm. For example, the depth can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm, etc.

[0140] As a possible implementation, the method for manufacturing the solar cell further comprises the following steps: removing the first doped layer formed on the second surface 11 and the side surface 12 to remove the PN junction on the second surface 11 and the side surface 12. It should be noted that when the first surface 10 of the semiconductor substrate 1 is subjected to the diffusion treatment, the first doped layer and the first doped oxide layer will inevitably be formed on at least part of the second surface 11 and the side surface 12. At least part of the second surface 11 can be understood as the edge region of the second surface 11 close to the side surface 12, or the entire second surface 11.

[0141] For example, the second surface 11 (back surface) and the side surface 12 formed with the first doped layer are subjected to polishing treatment by using a chain machine and a slot machine to remove the PN junction on the second surface 11 and the side surface 12 of the semiconductor substrate 1, and to eliminate the leakage caused by the PN junction of the side surface 12. As for the specific process, the reagents used can refer to the prior art, and are not limited here. Further, while the PN junction of the second surface 11 and the side surface 12 is cleaned, the borosilicate glass layer remaining in the first non-electrode region 101 of the first surface 10 is also cleaned to facilitate subsequent secondary texturing treatment.

[0142] Next, the first doped oxide layer and the first doped layer on the second surface 11 and the part of the side surface 12 close to the second surface are removed, and a recessed region is formed on at least part of the side surface 12, and the bottom surface of the recessed region is lower than the surface of the side surface 12. As for the removal method, it is not limited here as long as it can meet the needs.

[0143] Next, referring to Figure 1 and Figure 2The tunneling layer 3 and the doped conductive layer 4 are deposited on the edge region of the first surface 10 and the second surface 11; wherein the semiconductor substrate 1 and the doped conductive layer 4 in the first electrode region 100 are of the same conductive type. For the first surface 10 of the semiconductor substrate 1, the tunneling layer 3 and the doped conductive layer 4 are disposed on the first doped layer or the second doped layer in the edge region.

[0144] For example, the tunneling layer 3 and the doped conductive layer 4 are sequentially grown on the second surface 11 after the polishing process, and the tunneling layer 3 and the doped conductive layer 4 will be plated around the edge region of the first surface 10. Alternatively, the tunneling layer 3 and the doped conductive layer 4 are sequentially grown on the edge region of the first surface 10 and on the second surface 11 after the polishing process. At the same time, a second doped oxide layer will be grown on the doped conductive layer 4. During the subsequent processing of the solar cell, the second doped oxide layer can play a protective role, reducing the risk of etching the second electrode region 110, to ensure the quality of the solar cell.

[0145] As a possible implementation, when depositing the doped conductive layer 4, there are three possible implementations, which are LPCVD (Low Pressure Chemical Vapor Deposition) double-sided deposition of the doped conductive layer, LPCVD single-sided deposition of the doped conductive layer, and PECVD (Plasma Enhanced Chemical Vapor Deposition) deposition of the doped conductive layer. Among them, the LPCVD double-sided deposition of the doped conductive layer and the PECVD deposition of the doped conductive layer 4 can make the doped conductive layer 4 formed on the first surface 10 and the second surface 11 consistent, and the first non-electrode region 101 and the second non-electrode region 111 can form a uniform and uniform texture structure during subsequent texturing. When the doped conductive layer is deposited on the second surface 11 using LPCVD, the first surface 10 is plated around, resulting in a plated region and a non-plated region on the first surface 10, which in turn causes the plated region and the non-plated region on the first surface 10 to have different reaction times during subsequent secondary texturing. By optimizing the additives and the formula, the plated region and the non-plated region can form a good texture structure, achieving the desired light trapping and passivation effect.

[0146] As to the material and thickness of the tunneling layer 3, they can be set according to actual conditions, and are not specifically limited herein. Exemplarily, the material of the tunneling layer 3 can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbon nitride, aluminum nitride, titanium nitride, titanium carbon nitride. The doped conductive layer 4 can be a doped polysilicon layer, which can be a phosphorus-doped polysilicon layer, and can also be doped with other substances, which are not specifically limited herein. The second doped oxide layer is a phosphorus-silicon glass layer.

[0147] At this time, the manufacturing method of the solar cell can be used to manufacture a tunneling oxide layer passivation contact cell to meet actual needs. Further, the chemical passivation of the tunneling layer 3 and the field passivation of the doped conductive layer 4 can significantly reduce the recombination degree of the surface of the semiconductor substrate 1. At the same time, the tunneling layer 3 can also ensure the effective tunneling of the majority carriers, and the doped conductive layer 4 can significantly improve the conduction performance of the photo-generated carriers, thereby improving the open-circuit voltage and the fill factor of the solar cell. When the second surface 11 is stacked with the tunneling layer 3 and the doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 form a passivation contact structure. The tunneling layer 3 allows the majority carriers to tunnel into the doped conductive layer 4 while blocking the recombination of the minority carriers, thereby allowing the majority carriers to be laterally transported in the doped conductive layer 4 to be collected by the metal, greatly reducing the metal contact recombination current, improving the open-circuit voltage and short-circuit current of the cell, and thereby improving the cell efficiency. When the edge region of the first surface 10 is stacked with the tunneling layer 3 and the doped conductive layer 4, the tunneling layer 3 and the doped conductive layer 4 can further passivate the edge region of the first surface 10 to improve the passivation performance of the edge region of the cell.

[0148] As a possible implementation, after the tunneling layer 3 and the doped conductive layer 4 are deposited on the edge region of the first surface 10 and the second surface 11, the manufacturing method of the solar cell further includes the following steps: using a second laser to irradiate the tunneling layer 3 and the doped conductive layer 4 on the second non-electrode area 111 to etch the tunneling layer 3 and the doped conductive layer 4 on the second non-electrode area 111.

[0149] For example, the second doped oxide layer in the second non-electrode region 111 is irradiated by the second laser process, i.e. the second doped oxide layer is laser patterned. The high-energy laser irradiation causes the phosphosilicate glass layer in the second non-electrode region 111 to be modified, loosened or vaporized in a short time, reducing the protection ability of the phosphosilicate glass layer in the second non-electrode region 111, ensuring the formation of a reaction rate gradient in the subsequent alkali corrosion process, and the second non-electrode region 111 can be corroded as required, while the second electrode region 110 is not affected due to the protection of the phosphosilicate glass layer. In the subsequent processing, the doped conductive layer in the second electrode region 110 is protected by the phosphosilicate glass layer and will not be corroded by the alkaline agent; since the phosphosilicate glass layer in the second non-electrode region 111 is damaged, the doped conductive layer in the second non-electrode region 111 is corroded by the alkaline agent, and the alkaline agent further corrodes the tunneling layer 3 and the semiconductor substrate 1 downward. At this time, the tunneling layer 3 and the doped conductive layer 4 in the second electrode region 110 form a conductive contact layer, which corresponds to an electrode one-to-one. The doped conductive layer 4 in the second non-electrode region 111 on the second surface 11 is removed, effectively reducing parasitic absorption and improving cell current, while the doped conductive layer 4 in the second electrode region 110 is retained, preventing the corrosion of the semiconductor substrate 1 by the paste during metallization, and improving the fill factor of the cell.

[0150] For example, the second laser wavelength in the second laser process is greater than or equal to 300 nm and less than or equal to 1200 nm, for example, the second laser wavelength can be 300 nm, 350 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm or 1200 nm, etc. The width W2 of the second non-electrode region 111 is greater than or equal to 250 μm and less than or equal to 800 μm, for example, the width W2 of the second non-electrode region 111 can be 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm or 800 μm, etc.

[0151] It should be noted that if the second surface 11 of the solar cell does not need to form the above-mentioned conductive contact layer corresponding to an electrode one-to-one, the second doped oxide layer does not need to be laser patterned, and at this time the tunneling layer and the doped conductive layer on the second surface are whole.

[0152] Next, part of the tunneling layer 3 and the doped conductive layer 4 on the edge region of the first surface 10 is removed;

[0153] For example, the chain-type acid cleaning uses an aqueous HF solution and removes the phosphosilicate glass layer at room temperature, the ratio of HF to water is greater than or equal to 1:15 and less than or equal to 1:3; for example, the ratio of HF to water can be 1:3, 2:15, 1:5, 4:15 or 1:15, etc. Further, the tunneling layer 3 and the doped conductive layer 4 on the edge region of the first surface 10 and the tunneling layer 3 and the doped conductive layer 4 on the side surface 12 are removed by using an alkaline solution. In this step, the alkaline solution further etches the side surface 12 of the semiconductor substrate 1 to form a groove 120. That is, the alkaline solution etches the bottom surface of the partially recessed region to form the groove 120. It should be noted that whether the semiconductor substrate 1 corresponding to the edge region of the first surface 1 is further etched downward is not specifically limited here and can be operated according to the actual situation.

[0154] Referring to Figure 1 and Figure 2 , a secondary texturing process is performed to form a texture structure (i.e., a second texture structure 103 and a third texture structure) on the first non-electrode region 101. For example, a mixed solution of sodium hydroxide solution and texturing additives is used to form the texture structure on the first non-electrode region 101. The second texture structure 103 is located in the middle region of the semiconductor substrate 1, and the third texture structure is located in the edge region of the semiconductor substrate 1; the third texture structure has a smaller degree of fluctuation than the second texture structure 103. The above-mentioned first surface 10 includes a middle region and an edge region, and the edge region refers to the region close to the four edges of the semiconductor substrate 1, and the edge region surrounds the middle region. In some embodiments, the width of the edge region is less than or equal to 3 mm, and the width of the edge region refers to the distance from the side of the edge region away from the edge of the semiconductor substrate 1 to the edge of the semiconductor substrate 1.

[0155] As a possible implementation, if the alkaline solution only removes part of the doped conductive layer 4 formed on the first surface 10 of the semiconductor substrate 1, the tunneling layer 3 and the doped conductive layer 4 are disposed on the first doped layer or the second doped layer located in the edge region.

[0156] It is worth noting that after the step of "removing the phosphosilicate glass layer around the first surface 10 (light receiving surface) of the semiconductor substrate 1 and the phosphosilicate glass layer around the side surface 12 of the semiconductor substrate 1 by using the chain single-sided cleaning device first", there may be residual phosphosilicate glass layer on the first surface 10, or there may be no residual phosphosilicate glass layer. Therefore, when the subsequent secondary texturing step is performed, the morphology of the third texture structure near the edge region of the semiconductor substrate 1 is various. In some embodiments, the third texture structure includes one or more of a tower base structure, a prismatic structure, an inverted pyramid structure, a prismatic structure, or a pyramid structure.

[0157] As a possible implementation, in combination with the foregoing description, see Figures 1 to 5 and Figures 1 to 5 Since the phosphosilicate glass layer located in the second non-electrode area 111 is damaged, the doped conductive layer 4 located in the second non-electrode area 111 is corroded by the alkaline solution, and the alkaline solution further corrodes the tunneling layer 3 and the semiconductor substrate 1 downward.

[0158] In the secondary texturing processing step, a fourth texture structure 112 is also formed in the second non-electrode area 111. Compared with the second non-electrode area 111 being a polished surface, the reflectivity of the second non-electrode area 111 is significantly reduced, and the cell efficiency is not affected in cooperation with the optimization of the passivation process, thereby improving the double-sided rate of the cell.

[0159] It can be understood that a texturing additive can be directly added to the alkaline solution for removing the tunneling layer 3 and the doped conductive layer 4 on the edge region of the first surface 10 and the tunneling layer 3 and the doped conductive layer 4 on the side surface 12 to form a texture structure on the first non-electrode area 101, or a separate texturing alkaline solution can be directly used to etch the first non-electrode area 101 to form a texture structure.

[0160] In combination with the foregoing description, see Figure 1 and Figure 2 In this application, the bottom surface of the partially recessed area is etched to form a groove 120. When the doped conductive layer 4 is formed on the second surface 11, the doped conductive layer 4 will also be formed around the first electrode area 100 of the first surface 10 and the side surface 12 of the semiconductor substrate 1. The groove 120 provided on at least part of the side surface 12 separates the doped conductive layer 4 on the first surface 10 and the second surface 11, avoiding the occurrence of short circuit and edge leakage of the solar cell; the groove 120 can also increase the distance between the first surface 10 and the second surface 11, and increase the difficulty of the doped conductive layer 4 on the first surface 10 and the second surface 11 being overlapped on the side surface 12. In the preparation process, part of the semiconductor substrate 1 on the side surface 12 of the cell is etched to remove the inner expansion layer formed in the semiconductor substrate 1 during the formation of the doped conductive layer 4, thereby reducing the possibility of short circuit caused by contact between the doped conductive layers 4 with opposite polarities.

[0161] In some embodiments, referring to Figure 2 When the solar cell is a whole solar cell, the recess 120 can be provided on each of the four side surfaces 12 of the semiconductor substrate 1, or the recess 120 can be provided on at least one of the side surfaces 12.

[0162] Referring to Figure 2 When the solar cell is a split solar cell, the recess 120 can be provided on each of the three side surfaces 12 of the semiconductor substrate 1 except for the split side surface, or the recess 120 can be provided on at least one of the side surfaces 12 except for the split side surface.

[0163] In some embodiments, referring to Figure 1 and Figure 2 the surface of the side surface 12 includes a surface close to the first surface 10 and a surface close to the second surface 11, the bottom of the recess 120 is lower than the surface of the side surface 12, and the height difference (H1 and H2 in Figure 1 ) between the bottom of the recess 120 and the surface of the side surface 12 is greater than or equal to 0.5 μm and less than or equal to 7 μm. In the thickness direction of the semiconductor substrate 1, the width of the recess 120 is greater than or equal to 0.5 μm and less than or equal to 7 μm. For example, the height difference can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm, etc.

[0164] Referring to Figure 2If the height difference between the groove bottom of the groove 120 and the surface of the side surface 12 is less than 0.5 μm, the depth of the groove 120 is shallow, and the groove 120 provided on the side surface 12 cannot effectively isolate the doped conductive layer 4 on the first surface 10 and the second surface 11, and cannot ensure that the inner extension layer of the side surface of the battery is completely removed, which increases the probability of short circuit and edge leakage of the solar cell. If the height difference between the groove bottom of the groove 120 and the surface of the side surface 12 is greater than 7 μm, the depth of the groove 120 is deep, and the side surface 12 of the semiconductor substrate 1 is removed more, which reduces the mechanical strength of the whole battery piece. The solar cell generates electricity by separating electrons and holes from the semiconductor substrate 1 under light, and if the semiconductor substrate 1 is removed too much, the light absorption rate of the semiconductor substrate 1 is reduced, which reduces the number of photo-generated carriers, i.e. holes and electrons, generated on the semiconductor substrate 1, and further reduces the photoelectric conversion rate of the solar cell. In summary of the above two aspects, the height difference between the surface of the groove 120 and the surface of the side surface 12 is set within a reasonable range, which avoids short circuit and edge leakage of the solar cell, ensures a high light absorption rate of the semiconductor substrate 1, does not reduce the photoelectric conversion rate of the solar cell, and also ensures that the battery piece has sufficient mechanical strength.

[0165] In some embodiments, referring to Figure 1 and Figure 2 , the surface of the side surface 12 includes a surface close to the first surface 10 and a surface close to the second surface 11, and the distance H1 between the groove bottom of the groove 120 and the surface close to the first surface 10 of the surface of the side surface 12 is greater than the distance H2 between the groove bottom of the groove 120 and the surface close to the second surface 11 of the surface of the side surface 12. Since H1 and H2 are not formed in the same process step, H2 is set to be less than H1, which reduces the etching depth of the side surface 12 of the solar cell and ensures the mechanical strength of the solar cell.

[0166] Referring to Figure 1 and Figure 1The second texture structure 103 and the third texture structure located on the first surface 10 are beneficial to increase the surface area of the semiconductor substrate 1, improve the light trapping effect of the semiconductor substrate 1, and are beneficial to more light being refracted into the semiconductor substrate 1 through the area where the second texture structure 103 and the third texture structure are located and being utilized by the semiconductor substrate 1, so that the solar cell has a higher photoelectric conversion efficiency. The first non-electrode area 101 focuses on the light trapping effect and passivation performance of the front surface of the cell sheet due to the absence of the shielding of the grid lines, the first electrode area 100 focuses on the contact performance and passivation performance, and based on the functional difference between the first electrode area 100 and the first non-electrode area 101, the first non-electrode area 101 needs to take into account the light trapping effect and the passivation performance of the passivation layer film. In the present application, the first non-electrode area 101 has the second texture structure 103 located in the middle region of the semiconductor substrate 1 and the third texture structure located in the edge region of the semiconductor substrate 1, and the third texture structure has a smaller fluctuation degree than the second texture structure 103. That is, in the present application, the first non-electrode area 101 extending to the edge region of the semiconductor substrate 1 has the third texture structure with a relatively flat fluctuation degree, which can provide a good surface for the subsequent passivation layer coverage, and the small fluctuation degree means that the specific surface area of the semiconductor substrate 1 located in the edge region is small, and in the same plating process, a thicker passivation layer can be formed to meet the passivation performance of the edge of the solar cell and ensure the efficiency of the solar cell.

[0167] In combination with the foregoing description, reference is made to Figure 2 and Figure 1 Due to the downward corrosion of the semiconductor substrate 1 located in the second non-electrode area 111 by the alkaline solution, the semiconductor substrate 1 located in the second non-electrode area 111 is removed by a portion, and at this time, along the thickness direction A of the semiconductor substrate 1, the surface of the second non-electrode area 111 is higher than the surface of the second electrode area 110.

[0168] In some embodiments, along the thickness direction A of the semiconductor substrate 1, the distance L2 between the top surface of the second electrode area 110 and the top surface of the second non-electrode area 111 is greater than or equal to 2 μm and less than or equal to 6 μm. For example, the distance L2 between the top surface of the second electrode area 110 and the top surface of the second non-electrode area 111 can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm, etc.

[0169] It should be noted that the top surface of the second non-electrode region 111 is composed of the top points of the plurality of fourth texture structures 112, and the top surface of the second non-electrode region 111 is a plane composed of the top points of the majority of the fourth texture structures 112 on the second non-electrode region 111, and the proportion of the majority of the fourth texture structures 112 in the second non-electrode region 111 can be flexibly selected according to actual conditions.

[0170] As a possible implementation, in the secondary texturing process, the volume ratio of the alkali to the additive in the alkali texturing tank is greater than or equal to 2:1 and less than or equal to 8:1, the temperature of the alkali tank is greater than or equal to 60°C and less than or equal to 85°C, and the time is greater than or equal to 2 min and less than or equal to 8 min. For example, the volume ratio of the alkali to the additive in the alkali texturing tank can be 2:1, 3:1, 4:1, 5:1, 6:1, 7:1 or 8:1, etc. The temperature of the alkali tank can be 60°C, 65°C, 70°C, 75°C, 80°C, 82°C or 85°C, etc. The time can be 2 min, 3 min, 3.5 min, 4 min, 4.5 min, 5 min, 5.5 min, 6 min, 6.5 min, 7 min, 7.5 min or 8 min, etc. It should be noted that the related parameters when forming the texture structure on the first non-electrode region 101 and the related parameters when forming the fourth texture structure 112 on the second non-electrode region 111 can be the same or different, as long as they meet the above ranges.

[0171] As a possible implementation, refer to Figure 2 and Figure 2 , the first texture structure 102 and / or the second texture structure 103 is a pyramid structure.

[0172] In an optional manner, refer to Figure 3, the first texture structure 102 (and / or the second texture structure 103) is a pyramid structure, the height of the pyramid of the first texture structure 102 (and / or the second texture structure 103) is greater than or equal to 1 μm and less than or equal to 4 μm, and the base size of the first texture structure 102 (and / or the second texture structure 103) is greater than or equal to 1 μm and less than or equal to 5 μm. The base of the first texture structure 102 can be square, rhombic, rectangular, parallelogram, approximately rhombic or approximately rectangular, and the base size of the first texture structure 102 can be the length, the short side, the diagonal or the farthest distance between two endpoints of the base shape. The height of the pyramid and the base size of the first texture structure 102 can be the height of the pyramid or the base size of a single texture structure, or the average of the height of the pyramid or the base size of the first texture structure 102 in a certain area; the same applies to the second texture structure 103. For example, in the range of 1 μm x 1 μm, the height of the pyramid can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm, etc. The base size can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm, etc. The height of the pyramid or the base size of the first texture structure 102 and the second texture structure 103 can be equal or not equal.

[0173] As a possible implementation, see Figure 1 and Figure 2 In forming the second texture structure 103, the intermediate region of the semiconductor substrate 1 is etched by the alkaline texturing solution, and at this time, along the thickness direction A of the semiconductor substrate 1, the first electrode region 100 is higher than the first non-electrode region 101.

[0174] In some embodiments, see Figure 1 and Figure 2 Along the thickness direction of the semiconductor substrate 1, the distance L1 between the first electrode region 100 and the first non-electrode region 101 is greater than or equal to 2 μm and less than or equal to 7 μm. See Figure 1 and Figure 2 The distance L1 between the first electrode region 100 and the first non-electrode region 101 can be the distance between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101, or the distance between the bottom surface of the first electrode region 100 and the top surface of the first non-electrode region 101, or the distance between the top surface of the first electrode region 100 and the bottom surface of the first non-electrode region 101. For example, the distance L1 between the top surface of the first electrode region 100 and the top surface of the first non-electrode region 101 can be 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm or 7 μm, etc.

[0175] It is worth noting that, referring to Figure 1 and Figure 2 , the top surface of the first electrode region 100 is composed of the top points of the plurality of first texture structures 102, and the top surface is a plane composed of the top points of the majority of the first texture structures 102 on the first electrode region 100, and the proportion of the majority of the first texture structures 102 in the first electrode region 100 can be flexibly selected according to actual conditions. Similarly, the top surface of the first non-electrode region 101 is composed of the top points of the plurality of second texture structures 103.

[0176] Next, referring to Figure 1 and Figure 2 , the passivation layer 5 is formed on the doped conductive layer 4 and on the first surface 10 and the second surface 11 of the semiconductor substrate 1.

[0177] As for the material and thickness of the passivation layer 5, they can be set according to actual conditions and are not specifically limited here. For example, the material of the passivation layer can include one or more of silicon nitride, hydrogen-containing silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, zinc oxide, and hafnium dioxide.

[0178] As a possible implementation, referring to Figure 1 and Figure 2 , the passivation layer 5 can be a single-layer film, such as a single layer of silicon nitride, or a multilayer film stack, such as a stack of an aluminum oxide layer and a silicon nitride layer, or a silicon nitride stack structure, etc.

[0179] In some embodiments, referring to Figure 1 and Figure 2 , an atomic layer deposition method is used to grow an aluminum oxide passivation layer 50 on the doped conductive layer 4 and on the first surface 10 and the second surface 11 of the semiconductor substrate 1, and then a plasma enhanced chemical vapor deposition (PECVD) device is used to deposit a silicon nitride passivation layer 51 on the aluminum oxide passivation layer 50 on the doped conductive layer 4 and on the first surface 10 and the second surface 11.

[0180] The passivation layer 5 can perform passivation treatment on the surface of the semiconductor substrate 1, reduce surface recombination, improve open-circuit voltage and fill factor, and the silicon nitride passivation layer 51 can protect the semiconductor substrate 1 and reduce pollution and mechanical damage.

[0181] Next, referring to ​ and ​An electrode is formed on the passivation layer 5, and the electrode is located in the first electrode area 100 and the second electrode area 110, respectively. That is, the first electrode 6 is prepared in the first electrode area 100 of the first surface 10 of the semiconductor substrate 1 by a printing device, and the second electrode 7 is prepared in the second electrode area 110 of the second surface 11 of the semiconductor substrate 1.

[0182] For example, referring to ​ and ​ The semiconductor substrate 1 is metallized, and the electrode is formed by screen printing or electroplating. The paste for preparing the first electrode 6 and the second electrode 7 can be silver alloy, silver-copper alloy, copper alloy, nickel alloy, etc. The paste is solidified by a low-temperature sintering process, and then the hydrogen passivation effect is improved by light injection. Finally, a good ohmic contact is formed by laser-assisted sintering contact technology (LECO), and the production of the solar cell is completed.

[0183] For example, referring to ​ and ​ The semiconductor substrate 1 is metallized, and the electrode is formed by screen printing or electroplating. The paste for preparing the first electrode 6 and the second electrode 7 can be silver alloy, silver-copper alloy, copper alloy, nickel alloy, etc. The paste is solidified by a low-temperature sintering process, and then the hydrogen passivation effect is improved by light injection. Finally, a good ohmic contact is formed by laser-assisted sintering contact technology (LECO), and the production of the solar cell is completed.

[0184] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner. The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A solar cell, characterized by, Comprise: a semiconductor substrate comprising a first surface and a second surface opposite to each other; the first surface is a light-receiving surface, and the second surface is a back surface; the first surface comprises a first electrode region and a first non-electrode region; the surface of the first electrode region has a first texture structure; the first non-electrode region has a second texture structure and a third texture structure, the second texture structure is located in the middle region of the semiconductor substrate, and the third texture structure is located in the edge region of the semiconductor substrate, the width of the edge region is less than or equal to 3 mm; the third texture structure has a smaller fluctuation degree than the second texture structure; a first doped layer disposed in the first electrode region; a second doped layer disposed in the first non-electrode region; the doping concentration of the first doped layer is greater than that of the second doped layer; a passivation layer formed on the side of the first doped layer and the second doped layer away from the semiconductor substrate; the second surface comprises a second electrode region and a second non-electrode region; the second electrode region and the second non-electrode region are arranged alternately on the second surface; the second non-electrode region has a fourth texture structure; the fourth texture structure has a lower size consistency than the first texture structure; and / or, the second texture structure has a greater size consistency than the fourth texture structure.

2. The solar cell according to claim 1, characterized in that, The third texture structure comprises one or more of a tower base structure, a prismatic structure, an inverted pyramid structure, a prismatic-pyramid structure, or a pyramid structure.

3. The solar cell according to claim 1, characterized in that, The first texture structure and / or the second texture structure is a pyramid structure.

4. The solar cell according to claim 1 or 3, characterized in that, The reflectivity of the first electrode region where the first texture structure is located is greater than the reflectivity of the first non-electrode region where the second texture structure is located.

5. The solar cell of claim 1, wherein Part of the edge region has a tunneling layer and / or a doped conductive layer; The tunneling layer and the doped conductive layer are disposed on the first doped layer and / or the second doped layer; The doping type of the first doped layer and the second doped layer is the same, and the doping type of the doped conductive layer is opposite to that of the first doped layer and the second doped layer.

6. The solar cell according to claim 1 or 5, characterized in that, The semiconductor substrate further comprises a plurality of side surfaces between the first surface and the second surface; At least part of the side surfaces is provided with a groove, the bottom of the groove is lower than the surface of the side surface; the height difference between the bottom of the groove and the surface of the side surface is greater than or equal to 0.5 μm and less than or equal to 7 μm.

7. The solar cell according to claim 6, characterized in that The surface of the side surface comprises a surface close to the first surface and a surface close to the second surface; The distance between the bottom of the groove and the surface of the side surface close to the first surface is greater than the distance between the bottom of the groove and the surface of the side surface close to the second surface.

8. The solar cell of claim 1, wherein, In the thickness direction of the semiconductor substrate, the first electrode region is higher than the first non-electrode region; The distance between the first electrode region and the first non-electrode region ranges from greater than or equal to 2 μm to less than or equal to 7 μm.

9. The solar cell of claim 1, wherein: a tunneling layer disposed on the surface of the second electrode region; a doped conductive layer disposed on the second electrode region and located on a side of the tunneling layer away from the semiconductor substrate; the second electrode region is higher than the second non-electrode region along the thickness direction of the semiconductor substrate; the distance between the second electrode region and the second non-electrode region is greater than or equal to 2 μm and less than or equal to 6 μm; alternatively, the projection of the first non-electrode region on the first surface and the projection of the second non-electrode region on the first surface at least partially overlap along the thickness direction of the semiconductor substrate.

10. A photovoltaic module, characterized by, The photovoltaic module comprises: a cell string comprising a plurality of interconnects and a plurality of solar cells according to any one of claims 1 to 9; the interconnects are used to connect the plurality of solar cells together in series to form the cell string; an encapsulation layer used to cover the surface of the cell string.

11. A method for manufacturing a solar cell, characterized in that, comprising: providing a semiconductor substrate; the semiconductor substrate has opposite first and second surfaces; the first surface is a light-receiving surface, and the second surface is a back surface; texturing the first and second surfaces to form a first texture structure; the first surface includes a first electrode region and a first non-electrode region; diffusing the first surface of the semiconductor substrate to form a first doped layer and a first doped oxide layer formed on the first doped layer; removing the first doped oxide layer on the first non-electrode region; etching the first doped layer in the first non-electrode region to form a second doped layer, such that the doping concentration of the second doped layer is less than the doping concentration of the first doped layer; depositing a tunneling layer and a doped conductive layer on the edge region of the first surface and the second surface, and removing part of the tunneling layer and the doped conductive layer on the edge region of the first surface; after removing part of the tunneling layer and the doped conductive layer on the edge region of the first surface, performing a secondary texturing process to form a texture structure on the first non-electrode region; the texture structure includes a second texture structure and a third texture structure, the second texture structure is located in the middle region of the semiconductor substrate, and the third texture structure is located in the edge region of the semiconductor substrate, the width of the edge region is less than or equal to 3 mm; the third texture structure has a smaller degree of fluctuation than the second texture structure; the second surface includes a second electrode region and a second non-electrode region; during the secondary texturing process, a fourth texture structure is also formed on the second non-electrode region; the fourth texture structure has a lower dimensional consistency than the first texture structure; and / or, the second texture structure has a higher dimensional consistency than the fourth texture structure; after the secondary texturing process, the method for manufacturing a solar cell further comprises: forming a passivation layer on the doped conductive layer and on the first and second surfaces of the semiconductor substrate.

12. The method for manufacturing a solar cell according to claim 11, wherein, Before removing the tunneling layer and the doped conductive layer on the edge region of the first surface and the second surface, the method for manufacturing the solar cell further comprises: irradiating the tunneling layer and the doped conductive layer on the second non-electrode region by using a second laser, and etching the tunneling layer and the doped conductive layer on the second non-electrode region.

13. The method of producing a solar cell according to claim 11 or 12, wherein The semiconductor substrate comprises a plurality of side surfaces between the first surface and the second surface; Before depositing the tunneling layer and the doped conductive layer on the edge region of the first surface and the second surface, the method for manufacturing the solar cell further comprises: The first doped oxide layer and the first doped layer on the second surface and the part of the side surface close to the second surface are removed, and a recessed region is formed on at least part of the side surface, the bottom surface of the recessed region being lower than the surface of the side surface; While removing the tunneling layer and the doped conductive layer on the edge region of the first surface, the method for manufacturing the solar cell further comprises: The bottom surface of part of the recessed region is etched to form a groove; The surface of the side surface comprises a surface close to the first surface and a surface close to the second surface, the distance between the bottom of the groove and the surface close to the first surface is greater than the distance between the bottom of the groove and the surface close to the second surface.

14. The method of producing a solar cell according to claim 12, wherein After the secondary texturing process, the method for manufacturing the solar cell further comprises: An electrode is formed on the passivation layer, the electrode being located in the first electrode region and the second electrode region respectively. An electrode is formed on the passivation layer, the electrode being located in the first electrode region and the second electrode region respectively.

Images