Power amplification system, power amplification method, and digital pre-distortion circuit

Abstract

A power amplification system (7) is provided with: power amplifiers (2A, 2B); a switched capacitor circuit (20) configured so as to generate a plurality of discrete voltages on the basis of the regulated voltage supplied from the preregulator circuit (10); an output switching circuit (30) configured to selectively output at least one of the plurality of discrete voltages to the power amplifier (2A); and a DPD circuit (71) configured to predistort the high-frequency signals (RF1 and RF2), the preregulator circuit (10) configured to convert an input voltage into a regulated voltage, output the regulated voltage to the switched capacitor circuit (20), and output the regulated voltage to the power amplifier (2B) without passing through the switched capacitor circuit (20), and the DPD circuit (71) predistorts the high-frequency signal (RF1) using a first mathematical model, and outputs the predistorted high-frequency signal (RF2) using a second mathematical model. And pre-distorting the high-frequency signal (RF2) using a second mathematical model, or not pre-distorting the high-frequency signal (RF2).

Description

Technical Field

[0001] The invention relates to a power amplification system, a power amplification method and a digital predistortion circuit. Background Art

[0002] In recent years, improvements in power added efficiency have been achieved by applying tracking technology to power amplifier circuits. Patent Document 1 discloses a tracker module for digital envelope tracking (D-ET) that supplies a power supply voltage that varies over time at multiple discrete levels (hereinafter referred to as multiple discrete voltages). Furthermore, Patent Document 2 discloses a tracker module for symbol power tracking (SPT) that supplies multiple discrete voltages.

[0003] Patent Document 1: U.S. Patent No. 8,829,993

[0004] Patent Document 2: U.S. Patent No. 10,686,407

[0005] When supplying multiple discrete voltages to a power amplifier, digital pre-distortion (DPD) is sometimes used to reduce the nonlinear distortion caused by the power amplifier operating in a nonlinear region. DPD predistorts the input signal to the power amplifier to cancel the nonlinear distortion generated by the power amplifier. In this case, the parameters of the mathematical model used for DPD (hereinafter referred to as DPD parameters) are stored in memory for each power amplifier, increasing the storage capacity.

[0006] Therefore, the present invention provides a power amplification system, a power amplification method, and a digital predistortion circuit capable of effectively improving the quality of a transmission signal while suppressing an increase in the amount of memory used for DPD parameters. Summary of the Invention

[0007] A power amplifier system according to one embodiment of the present invention comprises: a first power amplifier configured to amplify a first high-frequency signal; a second power amplifier configured to amplify a second high-frequency signal; a switched capacitor circuit configured to generate a plurality of discrete voltages based on an adjustment voltage supplied from a pre-regulator circuit; an output switching circuit configured to selectively output at least one of the plurality of discrete voltages to the first power amplifier; and a digital pre-distortion circuit configured to pre-distort the first high-frequency signal and the second high-frequency signal, the pre-regulator circuit configured to convert an input voltage into an adjustment voltage and output the adjustment voltage to the switched capacitor circuit, and output the adjustment voltage to the second power amplifier without passing through the switched capacitor circuit, the digital pre-distortion circuit using a first mathematical model for digital pre-distortion to pre-distort the first high-frequency signal and using a second mathematical model for digital pre-distortion to pre-distort the second high-frequency signal or not pre-distort the second high-frequency signal.

[0008] A power amplification method according to one embodiment of the present invention converts an input voltage into an adjustment voltage, generates a plurality of discrete voltages based on the adjustment voltage, selectively supplies at least one of the plurality of discrete voltages to a first power amplifier, predistorts a first input signal of the first power amplifier using a first mathematical model, amplifies the predistorted first input signal, skips the generation of the plurality of discrete voltages, supplies the adjustment voltage to a second power amplifier, predistorts a second input signal of the second power amplifier using a second mathematical model, and amplifies the predistorted second input signal.

[0009] A digital predistortion circuit according to one embodiment of the present invention predistorts a first input signal of a first power amplifier selectively supplied with at least one of a plurality of discrete voltages generated based on an adjustment voltage using a first mathematical model, and predistorts a second input signal of a second power amplifier supplied with the adjustment voltage using a second mathematical model.

[0010] According to the power amplification system and the like according to one aspect of the present invention, it is possible to effectively improve the quality of a transmission signal while suppressing an increase in the amount of memory used for DPD parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A This is a graph showing an example of the transition of the power supply voltage in the APT (Average Power Tracking) mode.

[0012] Figure 1B This is a graph showing an example of the transition of the power supply voltage in the A-ET (Analog Envelope Tracking) mode.

[0013] Figure 1C This is a graph showing an example of the transition of the power supply voltage in the D-ET mode.

[0014] Figure 2 It is a circuit configuration diagram of a communication device according to an embodiment.

[0015] Figure 3 FIG. 1 is a circuit diagram of a tracker module according to an embodiment.

[0016] Figure 4 1 is a flowchart showing a power amplification method according to an embodiment.

[0017] Figure 5 It is a component configuration diagram of a communication device according to an embodiment. DETAILED DESCRIPTION

[0018] The following describes embodiments of the present invention in detail using the accompanying drawings. The embodiments described below are generally or specifically examples. The values, shapes, materials, components, configurations of components, and connection methods shown in the following embodiments are examples and do not limit the present invention.

[0019] In addition, the figures are schematic diagrams that have been appropriately emphasized, omitted, or adjusted in ratio to illustrate the present invention, and are not necessarily strictly illustrated. Actual shapes, positional relationships, and ratios may differ. In the figures, substantially identical structures may be denoted by the same reference numerals, and repeated descriptions may be omitted or simplified.

[0020] In the following figures, the x-axis and y-axis are axes perpendicular to each other on a plane parallel to the main surface of the motherboard. Specifically, when the motherboard has a rectangular shape when viewed from above, the x-axis is parallel to the first side of the motherboard, and the y-axis is parallel to the second side of the motherboard, which is perpendicular to the first side. Furthermore, the z-axis is perpendicular to the main surface of the motherboard, with its positive direction indicating upward and its negative direction indicating downward.

[0021] In the circuit structure of the present invention, "connection" includes not only direct connection via connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Direct connection" means direct connection via connection terminals and / or wiring conductors without passing through other circuit elements. "C is connected between A and B" means that one end of C is connected to A, and the other end of C is connected to B, and is connected in series on the path connecting A and B. "The path connecting A and B" means the path formed by the conductor that electrically connects A and B.

[0022] In the following description, a "terminal" refers to a point where a conductor within an element ends. Furthermore, if the resistance of the conductor between elements is sufficiently low, a terminal can be interpreted not only as a single point but also as any point on the conductor between elements or as the entire conductor.

[0023] In the component arrangement of the present invention, "C is closer to A than B" means that the distance between A and C is shorter than the distance between A and B. Here, "the distance between A and B" refers to the shortest distance between A and B. In other words, "the distance between A and B" refers to the length of the shortest line segment among a plurality of line segments connecting an arbitrary point on the surface of A and an arbitrary point on the surface of B.

[0024] In addition, statements such as "parallel" and "perpendicular" that indicate the relationship between elements, statements such as "rectangular" that indicate the shape of elements, and numerical ranges do not only have strict meanings, but also include substantially equivalent ranges, such as errors of several percent.

[0025] First, as a technology for efficiently amplifying high-frequency signals, we will explain the tracking mode, which dynamically adjusts the power supply voltage applied to the power amplifier circuit based on the passage of high-frequency signals over time. Tracking mode refers to a mode that dynamically adjusts the power supply voltage applied to the power amplifier circuit. There are several types of tracking modes, but here, we will refer to Figure 1A Figure 1 illustrates the CAPT mode, A-ET mode, and D-ET mode. Figures 1A to 1C In FIG, the horizontal axis represents time and the vertical axis represents voltage. In addition, the thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation wave.

[0026] Figure 1A This graph shows an example of the power supply voltage transition in APT mode. In APT mode, the power supply voltage is varied to multiple discrete voltage levels per frame based on average power. As a result, the power supply voltage signal forms a rectangular wave.

[0027] A frame is the unit that makes up a high-frequency signal (modulated wave). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame consists of ten subframes, each of which contains multiple time slots, each of which consists of multiple symbols. A subframe is 1ms long, and a frame is 10ms long.

[0028] Furthermore, a mode that varies the voltage level in units of one frame or larger based on average power is called an APT mode, distinguishing it from a mode that varies the voltage level in units smaller than a frame (e.g., a subframe, time slot, or symbol). For example, a mode that varies the voltage level in units of a symbol is called a symbol power tracking (SPT) mode, distinguishing it from the APT mode.

[0029] Figure 1BThis is a graph showing an example of the transition of the power supply voltage in the A-ET mode. In the A-ET mode, the power supply voltage is continuously varied based on the envelope signal to track the envelope of the modulation wave.

[0030] The envelope signal is a signal representing the envelope of the modulated wave. The envelope value is, for example, represented by (I 2 +Q 2 ). Here, (I, Q) represents a constellation point. A constellation point is a point on a constellation diagram that represents a digitally modulated signal. For example, (I, Q) is determined by a BBIC (Baseband Integrated Circuit) based on transmission information.

[0031] Figure 1C This graph shows an example of the power supply voltage transition in D-ET mode. In D-ET mode, the power supply voltage is varied to multiple discrete voltage levels within a frame based on an envelope signal, tracking the envelope of the modulated wave. As a result, the power supply voltage signal forms a rectangular wave.

[0032] (Implementation Method)

[0033] Hereinafter, embodiments will be described.

[0034] [1.1 Circuit Structure of Communication Device 6]

[0035] First, refer to Figure 2 The circuit configuration of the communication device 6 according to this embodiment will be described. Figure 2 It is a circuit configuration diagram of the communication device 6 according to this embodiment.

[0036] also, Figure 2 This is an exemplary circuit configuration, and the communication device 6 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the communication device 6 should not be interpreted in a limiting sense.

[0037] The communication device 6 in this embodiment corresponds to a user equipment (UE) in a cellular network, typically a mobile phone, smartphone, tablet computer, wearable device, etc. Alternatively, the communication device 6 may be an IoT (Internet of Things) sensor device, medical / healthcare equipment, a car, an unmanned aerial vehicle (UAV), or an automated guided vehicle (AGV). Furthermore, the communication device 6 may function as a base station (BS) in a cellular network.

[0038] like Figure 2 As shown, the communication device 6 includes a tracker module 1, power amplifiers 2A and 2B, an RFIC (Radio Frequency Integrated Circuit) 3, a BBIC 4, and antennas 5A and 5B. Furthermore, the power amplification system 7 includes the tracker module 1, power amplifiers 2A and 2B, and an RFIC 3.

[0039] The tracker module 1 can supply a plurality of discrete voltages as the power supply voltage Vcc1 to the power amplifier 2A in the D-ET mode, and can supply an adjusted voltage as the power supply voltage Vcc2 to the power amplifier 2B in the APT mode.

[0040] Power amplifier 2A is connected between RFIC 3 and antenna 5A. Furthermore, power amplifier 2A is connected to tracker module 1. Power amplifier 2A amplifies high-frequency signal RF1 received from RFIC 3 using power supply voltage Vcc1 supplied by tracker module 1. High-frequency signal RF1 is a signal of a first communication system constructed using radio access technology (RAT). Examples of the first communication system include 5GNR (5th Generation New Radio) and 4GLTE (4th Generation Long Term Evolution), but the first communication system is not limited to these systems.

[0041] Power amplifier 2B is connected between RFIC 3 and antenna 5B. Furthermore, power amplifier 2B is connected to tracker module 1. Power amplifier 2B uses power supply voltage Vcc2 supplied by tracker module 1 to amplify high-frequency signal RF2 received from RFIC 3. High-frequency signal RF2 is a signal of a second communication system established using a RAT. This second communication system is different from the first communication system. An example of the second communication system is the 2G (2nd Generation) communication system, but this is not limited to this system.

[0042] RFIC3 is an example of a signal processing circuit that processes high-frequency signals. RFIC3 can receive digital IQ signals from BBIC4 and supply high-frequency signals RF1 and RF2 to power amplifiers 2A and 2B, respectively. The internal structure of RFIC3 will be described later.

[0043] BBIC4 is a baseband signal processing circuit that performs signal processing using a frequency band lower than that of high-frequency signals RF1 and RF2. BBIC4 digitally modulates bit sequences representing, for example, image signals for display and / or audio signals for communication via a speaker, to generate digital IQ signals. These generated digital IQ signals are supplied to RFIC3. BBIC4 may not be included in communication device 6.

[0044] Antenna 5A transmits high-frequency signal RF1 amplified by power amplifier 2A to the outside of communication device 6. Furthermore, antenna 5B transmits high-frequency signal RF2 amplified by power amplifier 2B to the outside of communication device 6. Alternatively, one of antennas 5A and 5B may transmit both high-frequency signals RF1 and RF2. In this case, the other of antennas 5A and 5B may not be included in communication device 6. Furthermore, both antennas 5A and 5B may not be included in communication device 6. In this case, communication device 6 may be connected to an external antenna.

[0045] [1.2 Internal structure of RFIC3]

[0046] Reference Figure 2 The internal structure of RFIC 3 is described below. RFIC 3 includes a DPD circuit 71, a digital-to-analog converter (DAC) 72, and a quadrature modulator 73. RFIC 3 may also include a control unit (not shown) for controlling the tracker module 1. Furthermore, some or all of the functions of RFIC 3's control unit may be implemented externally to RFIC 3.

[0047] The DPD circuit 71 can predistort the digital IQ signal supplied from the BBIC 4 using a mathematical model for DPD. For example, the DPD circuit 71 can generate a predistorted digital IQ signal based on the digital IQ signal. The predistorted digital IQ signal is supplied to the DAC 72. Alternatively, the DPD circuit 71 can skip the DPD process. In this case, the DPD circuit 71 can supply the digital IQ signal supplied from the BBIC 4 (i.e., the non-predistorted digital IQ signal) to the DAC 72.

[0048] The DAC 72 can convert the digital IQ signal supplied from the DPD circuit 71 into an analog IQ signal. The converted analog IQ signal is supplied to the quadrature modulator 73. A conventional DAC can be used as the DAC 72, and there is no particular limitation.

[0049] The quadrature modulator 73 can generate a high-frequency signal RF by performing quadrature modulation and up-conversion on the analog IQ signal supplied from the DAC 72. The generated high-frequency signal RF is supplied to the power amplifier 2. A conventional quadrature modulator can be used as the quadrature modulator 73, and there is no particular limitation.

[0050] also, Figure 2 The circuit configuration of the RFIC 3 shown is an example and is not limited thereto. For example, some or all of the DPD circuit 71, DAC 72, and quadrature modulator 73 may not be included in the RFIC 3. For example, the DPD circuit 71 may not be included in the BBIC 4.

[0051] Here, a description is given of a mathematical model used for DPD in the DPD circuit 71. In this embodiment, as the mathematical model used for DPD, a first mathematical model having a memory effect or a second mathematical model having no memory effect can be used.

[0052] The memory effect is defined as the change in distortion of a power amplifier due to past input signals. Therefore, the first mathematical model models not only the distortion due to the current input signal but also the change in distortion due to past input signals. As a result, the first mathematical model can reduce nonlinear distortion compared to the second mathematical model, but at the expense of an increased computational load.

[0053] Therefore, in this embodiment, to effectively reduce nonlinear distortion with less memory, power amplifiers 2A and 2B use different mathematical models for DPD. Specifically, the input signal to power amplifier 2A is predistorted using a first mathematical model, while the input signal to power amplifier 2B is either predistorted or not predistorted using a second mathematical model.

[0054] Here, a specific example of the second mathematical model without the memory effect will be described.

[0055] [Number 1]

[0056]

[0057] x[n]:predistorted signal

[0058] r[n]:original input signal

[0059] c i :DPD coefficients

[0060] N:polynomial order

[0061] The above formula (1) is an example of a polynomial used in the second mathematical model. The mathematical model using formula (1) is called a memoryless polynomial model. In formula (1), for the current input signal r[n], the input signal is multiplied by the exponential input signal. The polynomial order N and the DPD coefficient c i These are parameters of the memoryless polynomial model and can be predetermined through experiments and / or experience, and stored in advance in a memory (not shown) included in the RFIC 3 , for example.

[0062] In equation (1), increasing the polynomial order N can be expected to reduce nonlinear distortion, but there is a concern that the computational load will increase. In addition, since equation (1) does not take into account the memory effect, the reduction of nonlinear distortion in the memoryless polynomial model is limited.

[0063] Next, a specific example of setting the first mathematical model of the memory effect will be described.

[0064] [Number 2]

[0065]

[0066] x[n]:predistorted signal

[0067] r[n]:original input signal

[0068] c qi :DPD coefficients

[0069] Q: memory depth

[0070] N:polynomial order

[0071] The above equation (2) is an example of a polynomial used in the first mathematical model. The mathematical model using equation (2) is called a memory polynomial model (MPM). In equation (2), for each input signal r[n-q] from the past Q to the current 0, the input signal is multiplied by the exponential input signal. The polynomial order N, the memory depth Q, and the DPD coefficient c are qi These are parameters of the MPM and can be predetermined through experiments and / or experience, and stored in advance in, for example, a memory (not shown) included in the RFIC 3 .

[0072] In formula (2), if the polynomial order N and the memory depth Q increase, it is expected that the nonlinear distortion will be reduced, but there will be an increase in the number of parameters, an increase in the computational load, and a decrease in the DPD coefficient c. qi There is concern about decreased convergence during decision making.

[0073] [Number 3]

[0074]

[0075] x[n]:predistorted signal

[0076] r[n]:original input signal

[0077] c qi ,d qmi ,e qmi :DPD coefficients

[0078] Q:sync memory depth

[0079] N:sync order

[0080] Q d :lag memory depth

[0081] M d :maximum lag

[0082] N d :lag order

[0083] Q e :lead memory depth

[0084] M e :maximum lead

[0085] N e :lead order

[0086] The above formula (3) is an example of a polynomial used in the first mathematical model. The mathematical model using formula (3) is called a generalized memory polynomial model (GMP). In formula (3), the sync term (3-1) is combined with the Lag term (3-2) and the Lead term (3-3). The sync term (3-1) is the same as the term in formula (2) used for MPM. In the Lag term (3-2), the input signal is multiplied by the exponential past input signal. In the Lead term (3-3), the input signal is multiplied by the exponential future input signal. The order N, N of each term is d and N e , memory depth Q, and DPD coefficient c qi d qmi and e qmi These are parameters of GMP and can be determined in advance through experiments and / or experience, and stored in advance in a memory (not shown) included in the RFIC 3 , for example.

[0087] In formula (3), if the memory depth of each item is Q, Q d , Q e and cross width M d 、M e If the value is increased, the nonlinear distortion can be expected to decrease, but the number of parameters increases, the calculation load increases, and the DPD coefficient c increases. qi d qmi and e qmi There is concern about decreased convergence during decision making.

[0088] The effect of reducing nonlinear distortion increases in the order of the memoryless polynomial model, MPM, and GMP, but the number of parameters increases, and the computational load (i.e., power consumption) also increases. In other words, the GMP model reduces nonlinear distortion compared to the MPM and the memoryless polynomial model, while the MPM reduces nonlinear distortion compared to the memoryless polynomial model. Conversely, the memoryless polynomial model reduces the computational load compared to the MPM and GMP, while the MPM reduces the computational load compared to the GMP. Furthermore, the memoryless polynomial model reduces the amount of memory required to store parameters compared to the MPM and GMP, while the MPM reduces the amount of memory required to store parameters compared to the GMP.

[0089] Furthermore, the first mathematical model is not limited to MPM and GMP. In other words, the first mathematical model may use formulas different from equations (2) and (3). Furthermore, the second mathematical model is not limited to a memoryless polynomial model. In other words, the second mathematical model may use a formula different from equation (1).

[0090] [1.3 Circuit Structure of Tracker Module 1]

[0091] Next, refer to Figure 2 The circuit configuration of the tracker module 1 will be described. The tracker module 1 includes a pre-regulator circuit 10 , a switched capacitor circuit 20 , an output switch circuit 30 , a first filter circuit 41 , a second filter circuit 42 , switches S56 and S57 , and a digital control circuit 60 .

[0092] The pre-regulator circuit 10 can use a power inductor to convert the input voltage supplied from a DC power supply (not shown) into an adjustment voltage. The pre-regulator circuit 10 can supply the adjustment voltage to the switched capacitor circuit 20, and can also supply the adjustment voltage to the power amplifier 2B without passing through the switched capacitor circuit 20. The pre-regulator circuit 10 includes a power inductor and a switch. A power inductor refers to an inductor used for stepping up and / or stepping down a DC (Direct Current) voltage. The power inductor is configured in series on the DC path. In addition, the power inductor can also be connected between the DC path and the ground (in other words, configured in parallel with the DC path). Such a pre-regulator circuit 10 is also called a magnetic regulator or a DC / DC converter.

[0093] The switched capacitor circuit 20 includes a plurality of capacitors and a plurality of switches, and can generate a plurality of discrete voltages each having a plurality of discrete voltage levels based on the voltage supplied from the pre-regulator circuit 10. The switched capacitor circuit 20 is also sometimes called a switched-capacitor voltage balancer.

[0094] The output switch circuit 30 can selectively output at least one of the plurality of discrete voltages generated by the switched capacitor circuit 20 to the power amplifier 2A.

[0095] The first filter circuit 41 and the second filter circuit 42 can attenuate noise from a plurality of discrete voltages supplied to the power amplifier 2A. The first filter circuit 41 and the second filter circuit 42 are sometimes called pulse shaping filters or transition shaping filters.

[0096] Switches S56 and S57 are on / off switches for the first filter circuit 41 and the second filter circuit 42, respectively. Switch S56 is connected between the output switch circuit 30 and the first filter circuit 41. Switch S57 is connected between the output switch circuit 30 and the second filter circuit 42.

[0097] The digital control circuit 60 can control the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , and the switches S56 and S57 based on the digital control signal from the RFIC 3 .

[0098] Furthermore, the tracker module 1 may not include the pre-regulator circuit 10, the switched capacitor circuit 20, the output switch circuit 30, the first filter circuit 41, the second filter circuit 42, the switches S56 and S57, and part of the digital control circuit 60. For example, the tracker module 1 may not include the pre-regulator circuit 10. For another example, the tracker module 1 may not include the first filter circuit 41, the second filter circuit 42, and the switches S56 and S57. Furthermore, any combination of the pre-regulator circuit 10, the switched capacitor circuit 20, the output switch circuit 30, the first filter circuit 41, the second filter circuit 42, and the switches S56 and S57 may be integrated into a single circuit. Furthermore, the tracker module 1 may include multiple voltage supply circuits instead of the pre-regulator circuit 10 and the switched capacitor circuit 20, as described in Patent Document 2. In this case, the output switch circuit 30 may be configured to select at least one of the multiple voltage supply circuits.

[0099] Next, refer to Figure 3 The circuit configuration of each circuit included in the tracker module 1 will be described. Figure 3 2 is a circuit configuration diagram of the tracker module 1 according to this embodiment.

[0100] also, Figure 3 This is an exemplary circuit configuration, and the tracker module 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the description of the tracker module 1 provided below should not be interpreted in a limiting sense.

[0101] [1.3.1 Circuit Structure of Switched Capacitor Circuit 20]

[0102] First, the circuit structure of the switched capacitor circuit 20 is described. Figure 3 As shown, the switched capacitor circuit 20 includes capacitors C11 to C16, capacitors C10, C20, C30, and C40, and switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44. Energy and charge are input from the pre-regulator circuit 10 to the switched capacitor circuit 20 at nodes N1 to N4, and are then extracted from the switched capacitor circuit 20 to the output switch circuit 30 at nodes N1 to N4.

[0103] Capacitors C11-C16 each function as a flying capacitor (also sometimes called a flyby capacitor). In other words, each capacitor C11-C16 is used to boost or buck the regulated voltage supplied from the pre-regulator circuit 10. More specifically, capacitors C11-C16 transfer charge between capacitors C11-C16 and nodes N1-N4 to maintain voltages V1-V4 (relative to ground potential) at the four nodes N1-N4, satisfying the relationship V1:V2:V3:V4 = 1:2:3:4. These voltages V1-V4 correspond to multiple discrete voltages, each having multiple discrete voltage levels.

[0104] Capacitor C11 has two electrodes. One of the two electrodes of capacitor C11 is connected to one end of switch S11 and one end of switch S12. The other of the two electrodes of capacitor C11 is connected to one end of switch S21 and one end of switch S22.

[0105] Capacitor C12 has two electrodes. One of the two electrodes of capacitor C12 is connected to one end of switch S21 and one end of switch S22. The other of the two electrodes of capacitor C12 is connected to one end of switch S31 and one end of switch S32.

[0106] The capacitor C13 has two electrodes. One of the two electrodes of the capacitor C13 is connected to one end of the switch S31 and one end of the switch S32. The other of the two electrodes of the capacitor C13 is connected to one end of the switch S41 and one end of the switch S42.

[0107] Capacitor C14 has two electrodes. One of the two electrodes of capacitor C14 is connected to one end of switch S13 and one end of switch S14. The other of the two electrodes of capacitor C14 is connected to one end of switch S23 and one end of switch S24.

[0108] Capacitor C15 has two electrodes. One of the two electrodes of capacitor C15 is connected to one end of switch S23 and one end of switch S24. The other of the two electrodes of capacitor C15 is connected to one end of switch S33 and one end of switch S34.

[0109] Capacitor C16 has two electrodes. One of the two electrodes of capacitor C16 is connected to one end of switch S33 and one end of switch S34. The other of the two electrodes of capacitor C16 is connected to one end of switch S43 and one end of switch S44.

[0110] The group of capacitors C11 and C14 , the group of capacitors C12 and C15 , and the group of capacitors C13 and C16 can be complementarily charged and discharged by repeating the first stage and the second stage.

[0111] Specifically, in the first phase, switches S12, S13, S22, S23, S32, S33, S42, and S43 are turned on. Consequently, for example, one of the two electrodes of capacitor C12 is connected to node N3, the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C15 are connected to node N2, and the other of the two electrodes of capacitor C15 is connected to node N1.

[0112] On the other hand, in the second phase, switches S11, S14, S21, S24, S31, S34, S41, and S44 are turned on. Consequently, for example, one of the two electrodes of capacitor C15 is connected to node N3, the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C12 are connected to node N2, and the other of the two electrodes of capacitor C12 is connected to node N1.

[0113] By repeating the first and second stages, for example, when one of capacitors C12 and C15 is charged by node N2, the other of capacitors C12 and C15 can be discharged to capacitor C30. In other words, capacitors C12 and C15 can be charged and discharged in a complementary manner.

[0114] The group of capacitors C11 and C14 and the group of capacitors C13 and C16 can also be charged and discharged complementarily in the same manner as the group of capacitors C12 and C15 by repeating the first stage and the second stage.

[0115] The capacitors C10 , C20 , C30 , and C40 each function as a smoothing capacitor. In other words, the capacitors C10 , C20 , C30 , and C40 are used to hold and smooth the voltages V1 to V4 at the nodes N1 to N4 , respectively.

[0116] Capacitor C10 is connected between node N1 and the ground. Specifically, one of the two electrodes of capacitor C10 is connected to node N1, while the other of the two electrodes of capacitor C10 is connected to the ground.

[0117] Capacitor C20 is connected between nodes N2 and N1. Specifically, one of the two electrodes of capacitor C20 is connected to node N2. On the other hand, the other of the two electrodes of capacitor C20 is connected to node N1.

[0118] Capacitor C30 is connected between nodes N3 and N2. Specifically, one of the two electrodes of capacitor C30 is connected to node N3. On the other hand, the other of the two electrodes of capacitor C30 is connected to node N2.

[0119] Capacitor C40 is connected between nodes N4 and N3. Specifically, one of the two electrodes of capacitor C40 is connected to node N4. On the other hand, the other of the two electrodes of capacitor C40 is connected to node N3.

[0120] The switch S11 is connected between one of the two electrodes of the capacitor C11 and the node N3. Specifically, one end of the switch S11 is connected to one of the two electrodes of the capacitor C11. On the other hand, the other end of the switch S11 is connected to the node N3.

[0121] The switch S12 is connected between one of the two electrodes of the capacitor C11 and the node N4. Specifically, one end of the switch S12 is connected to one of the two electrodes of the capacitor C11. On the other hand, the other end of the switch S12 is connected to the node N4.

[0122] Switch S21 is connected between one of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S21 is connected to one of the two electrodes of capacitor C12 and the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S21 is connected to node N2.

[0123] Switch S22 is connected between one of the two electrodes of capacitor C12 and node N3. Specifically, one end of switch S22 is connected to one of the two electrodes of capacitor C12 and the other of the two electrodes of capacitor C11. On the other hand, the other end of switch S22 is connected to node N3.

[0124] Switch S31 is connected between the other of the two electrodes of capacitor C12 and node N1. Specifically, one end of switch S31 is connected to the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C13. On the other hand, the other end of switch S31 is connected to node N1.

[0125] Switch S32 is connected between the other of the two electrodes of capacitor C12 and node N2. Specifically, one end of switch S32 is connected to the other of the two electrodes of capacitor C12 and one of the two electrodes of capacitor C13. Meanwhile, the other end of switch S32 is connected to node N2. In other words, the other end of switch S32 is connected to the other end of switch S21.

[0126] The switch S41 is connected between the other of the two electrodes of the capacitor C13 and the ground. Specifically, one end of the switch S41 is connected to the other of the two electrodes of the capacitor C13. On the other hand, the other end of the switch S41 is connected to the ground.

[0127] Switch S42 is connected between the other of the two electrodes of capacitor C13 and node N1. Specifically, one end of switch S42 is connected to the other of the two electrodes of capacitor C13. On the other hand, the other end of switch S42 is connected to node N1. In other words, the other end of switch S42 is connected to the other end of switch S31.

[0128] Switch S13 is connected between one of the two electrodes of capacitor C14 and node N3. Specifically, one end of switch S13 is connected to one of the two electrodes of capacitor C14. The other end of switch S13 is connected to node N3. In other words, the other end of switch S13 is connected to the other end of switch S11 and the other end of switch S22.

[0129] Switch S14 is connected between one of the two electrodes of capacitor C14 and node N4. Specifically, one end of switch S14 is connected to one of the two electrodes of capacitor C14. On the other hand, the other end of switch S14 is connected to node N4. In other words, the other end of switch S14 is connected to the other end of switch S12.

[0130] Switch S23 is connected between one of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S23 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. On the other hand, the other end of switch S23 is connected to node N2. In other words, the other end of switch S23 is connected to the other end of switch S21 and the other end of switch S32.

[0131] Switch S24 is connected between one of the two electrodes of capacitor C15 and node N3. Specifically, one end of switch S24 is connected to one of the two electrodes of capacitor C15 and the other of the two electrodes of capacitor C14. On the other hand, the other end of switch S24 is connected to node N3. In other words, the other end of switch S24 is connected to the other end of switch S11, the other end of switch S22, and the other end of switch S13.

[0132] Switch S33 is connected between the other of the two electrodes of capacitor C15 and node N1. Specifically, one end of switch S33 is connected to the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C16. Meanwhile, the other end of switch S33 is connected to node N1. In other words, the other end of switch S33 is connected to the other end of switch S31 and the other end of switch S42.

[0133] Switch S34 is connected between the other of the two electrodes of capacitor C15 and node N2. Specifically, one end of switch S34 is connected to the other of the two electrodes of capacitor C15 and one of the two electrodes of capacitor C16. On the other hand, the other end of switch S34 is connected to node N2. In other words, the other end of switch S34 is connected to the other end of switch S21, the other end of switch S32, and the other end of switch S23.

[0134] The switch S43 is connected between the other of the two electrodes of the capacitor C16 and the ground line. Specifically, one end of the switch S43 is connected to the other of the two electrodes of the capacitor C16. On the other hand, the other end of the switch S43 is connected to the ground line.

[0135] Switch S44 is connected between the other of the two electrodes of capacitor C16 and node N1. Specifically, one end of switch S44 is connected to the other of the two electrodes of capacitor C16. Meanwhile, the other end of switch S44 is connected to node N1. In other words, the other end of switch S44 is connected to the other end of switch S31, the other end of switch S42, and the other end of switch S33.

[0136] A first group of switches, including switches S12, S13, S22, S23, S32, S33, S42, and S43, and a second group of switches, including switches S11, S14, S21, S24, S31, S34, S41, and S44, are complementarily switched on and off based on a control signal S2. Specifically, in the first phase, the switches of the first group are turned on, while the switches of the second group are turned off. Conversely, in the second phase, the switches of the first group are turned off, while the switches of the second group are turned on.

[0137] For example, in one of the first and second phases, capacitors C11 to C13 are charged to capacitors C10 to C40, and in the other of the first and second phases, capacitors C14 to C16 are charged to capacitors C10 to C40. In other words, capacitors C11 to C13 or capacitors C14 to C16 are always charged to capacitors C10 to C40. Therefore, even if current flows rapidly from nodes N1 to N4 to the output switch circuit 30, nodes N1 to N4 can be replenished with charge at high speed, thereby suppressing fluctuations in the potential of nodes N1 to N4.

[0138] By operating in this manner, switched capacitor circuit 20 is able to maintain approximately equal voltages across capacitors C10, C20, C30, and C40. Specifically, at the four nodes labeled V1 to V4, voltages V1 to V4 (relative to ground potential) are maintained in the order V1:V2:V3:V4 = 1:2:3:4. The voltage levels of voltages V1 to V4 correspond to the multiple discrete voltage levels that can be supplied to output switch circuit 30 via switched capacitor circuit 20.

[0139] Furthermore, the voltage ratio (V1:V2:V3:V4) is not limited to (1:2:3:4). For example, the voltage ratio (V1:V2:V3:V4) may be (1:2:4:8).

[0140] in addition, Figure 3 The structure of the switched capacitor circuit 20 shown is an example and is not limited thereto. Figure 3 In the embodiment, the switched capacitor circuit 20 is configured to supply four discrete voltages, but the number of discrete voltages is not limited to this. The switched capacitor circuit 20 can also be configured to supply any number of discrete voltages, two or more. For example, when supplying two discrete voltages, the switched capacitor circuit 20 only needs to include capacitors C12 and C15, and switches S21 to S24, and S31 to S34.

[0141] [1.3.2 Circuit Structure of Output Switch Circuit 30]

[0142] Next, refer to Figure 3 , the circuit structure of the output switch circuit 30 is described. Figure 3 As shown, the output switch circuit 30 includes input terminals 131 to 134 , switches S51 to S54 , and an output terminal 130 .

[0143] The output terminal 130 is connected to the first filter circuit 41 and the second filter circuit 42. The output terminal 130 is a terminal for supplying a power supply voltage selected from the voltages V1 to V4 to the power amplifier 2A via the first filter circuit 41 and / or the second filter circuit 42.

[0144] Input terminals 131 to 134 are respectively connected to nodes N4 to N1 of the switched capacitor circuit 20 . Input terminals 131 to 134 are terminals for receiving voltages V4 to V1 from the switched capacitor circuit 20 .

[0145] The switch S51 is connected between the input terminal 131 and the output terminal 130. Specifically, the switch S51 has a terminal connected to the input terminal 131 and a terminal connected to the output terminal 130. In this connection configuration, the switch S51 can switch between connection and disconnection between the input terminal 131 and the output terminal 130 by switching on / off according to the control signal S3.

[0146] The switch S52 is connected between the input terminal 132 and the output terminal 130. Specifically, the switch S52 has a terminal connected to the input terminal 132 and a terminal connected to the output terminal 130. In this connection configuration, the switch S52 can switch between connection and disconnection between the input terminal 132 and the output terminal 130 by switching on / off according to the control signal S3.

[0147] The switch S53 is connected between the input terminal 133 and the output terminal 130. Specifically, the switch S53 has a terminal connected to the input terminal 133 and a terminal connected to the output terminal 130. In this connection structure, the switch S53 can switch between connection and disconnection between the input terminal 133 and the output terminal 130 by switching on / off according to the control signal S3.

[0148] The switch S54 is connected between the input terminal 134 and the output terminal 130. Specifically, the switch S54 has a terminal connected to the input terminal 134 and a terminal connected to the output terminal 130. In this connection configuration, the switch S54 can switch between connection and disconnection between the input terminal 134 and the output terminal 130 by switching on / off according to the control signal S3.

[0149] These switches S51 to S54 are controlled to be exclusively turned on. In other words, only one of the switches S51 to S54 is turned on, while the remaining switches S51 to S54 are turned off. This allows the output switch circuit 30 to output a voltage selected from the voltages V1 to V4.

[0150] also, Figure 3 The illustrated structure of the output switch circuit 30 is an example and is not limited thereto. In particular, switches S51-S54 may have any configuration as long as they can selectively connect at least one of the four input terminals 131-134 to the output terminal 130. For example, the output switch circuit 30 may further include a switch connected between switches S51-S53, switch S54, and the output terminal 130. Furthermore, for example, the output switch circuit 30 may further include a switch connected between switches S51 and S52, switches S53 and S54, and the output terminal 130.

[0151] Furthermore, when voltages of two discrete voltage levels are supplied from the switched capacitor circuit 20 , the output switch circuit 30 only needs to include at least two of the switches S51 to S54 .

[0152] [1.3.3 Circuit Structure of Pre-regulator Circuit 10]

[0153] Next, refer to Figure 3 , the structure of the pre-regulator circuit 10 is described. Figure 3 As shown, the pre-regulator circuit 10 includes an input terminal 110 , output terminals 111 to 114 , switches S61 to S63 , S71 to S73 , a power inductor L71 , and capacitors C61 to C64 .

[0154] The input terminal 110 is a terminal for inputting a DC voltage. In other words, the input terminal 110 is a terminal for receiving an input voltage from the DC power supply 50 .

[0155] Output terminal 111 is an output terminal for voltage V4. In other words, output terminal 111 is a terminal for supplying voltage V4 to switched capacitor circuit 20. Output terminal 111 is connected to node N4 of switched capacitor circuit 20.

[0156] Output terminal 112 is an output terminal for voltage V3. In other words, output terminal 112 is a terminal for supplying voltage V3 to switched capacitor circuit 20, and is also a terminal for supplying voltage V3 as power supply voltage Vcc2 to power amplifier 2B. Output terminal 112 is connected to node N3 of switched capacitor circuit 20 and to power amplifier 2B.

[0157] Output terminal 113 is an output terminal for voltage V2. In other words, output terminal 113 is a terminal for supplying voltage V2 to switched capacitor circuit 20. Output terminal 113 is connected to node N2 of switched capacitor circuit 20.

[0158] Output terminal 114 is an output terminal for voltage V1. In other words, output terminal 114 is a terminal for supplying voltage V1 to switched capacitor circuit 20. Output terminal 114 is connected to node N1 of switched capacitor circuit 20.

[0159] Switch S71 is connected between input terminal 110 and one end of power inductor L71. Specifically, switch S71 has a terminal connected to input terminal 110 and a terminal connected to one end of power inductor L71. In this connection structure, switch S71 can switch between connection and disconnection between input terminal 110 and one end of power inductor L71 by switching on and off based on control signal S1.

[0160] Switch S72 is connected between one end of the power inductor L71 and the ground line. Specifically, switch S72 has a terminal connected to one end of the power inductor L71 and a terminal connected to the ground line. In this connection structure, switch S72 can switch between connecting and disconnecting one end of the power inductor L71 and the ground line by switching on and off based on control signal S1.

[0161] Switch S73 is connected between input terminal 110 and power amplifier 2B. Specifically, switch S73 includes a terminal connected to input terminal 110 and a terminal connected to power amplifier 2B. In this connection configuration, switch S73 can switch between connection and disconnection between input terminal 110 and power amplifier 2B by switching on and off based on control signal S1. In other words, switch S73 can switch between supplying and not supplying the input voltage of pre-regulator circuit 10 to power amplifier 2B.

[0162] The switch S61 is connected between the other end of the power inductor L71 and the output terminal 111. Specifically, the switch S61 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 111. In this connection structure, the switch S61 can switch between connection and disconnection between the other end of the power inductor L71 and the output terminal 111 by switching on and off based on the control signal S1.

[0163] The switch S62 is connected between the other end of the power inductor L71 and the output terminal 112. Specifically, the switch S62 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 112. In this connection structure, the switch S62 can switch between connection and disconnection between the other end of the power inductor L71 and the output terminal 112 by switching on and off based on the control signal S1.

[0164] The switch S63 is connected between the other end of the power inductor L71 and the output terminal 113. Specifically, the switch S63 has a terminal connected to the other end of the power inductor L71 and a terminal connected to the output terminal 113. In this connection structure, the switch S63 can switch between connection and disconnection between the other end of the power inductor L71 and the output terminal 113 by switching on and off based on the control signal S1.

[0165] One of the two electrodes of the capacitor C61 is connected to the switch S61 and the output terminal 111. The other of the two electrodes of the capacitor C61 is connected to the switch S62, the output terminal 112, and one of the two electrodes of the capacitor C62.

[0166] One of the two electrodes of capacitor C62 is connected to switch S62, output terminal 112, and the other of the two electrodes of capacitor C61. The other of the two electrodes of capacitor C62 is connected to a path connecting switch S63, output terminal 113, and one of the two electrodes of capacitor C63.

[0167] One of the two electrodes of capacitor C63 is connected to switch S63, output terminal 113, and the other of the two electrodes of capacitor C62. The other of the two electrodes of capacitor C63 is connected to output terminal 114 and one of the two electrodes of capacitor C64.

[0168] One of the two electrodes of the capacitor C64 is connected to the output terminal 114 and the other of the two electrodes of the capacitor C63 , and the other of the two electrodes of the capacitor C64 is grounded.

[0169] Switches S61-S63 are controlled to be exclusively turned on. In other words, only one of switches S61-S63 is turned on, while the remaining switches S61-S63 are turned off. By turning on only one of switches S61-S63, pre-regulator circuit 10 can change the voltage supplied to switched capacitor circuit 20 to a voltage level of voltages V2-V4.

[0170] The pre-regulator circuit 10 configured in this manner can supply charge to the switched capacitor circuit 20 via at least one of the output terminals 111 to 114 .

[0171] Furthermore, when the input voltage only needs to be converted into one regulated voltage, the pre-regulator circuit 10 only needs to include at least the switches S71 and S72 and the power inductor L71 .

[0172] [1.3.4 Circuit Structure of the First Filter Circuit 41 and the Second Filter Circuit 42]

[0173] Next, refer to Figure 3 , the circuit configurations of the first filter circuit 41 and the second filter circuit 42 of this embodiment will be described.

[0174] The first filter circuit 41 includes a parallel circuit (LC parallel circuit) of an inductor L51 and a capacitor C51. One end of the parallel circuit is connected to a switch S56, and the other end of the parallel circuit is connected to the power amplifier 2A.

[0175] The second filter circuit 42 includes a parallel circuit of an inductor L52 and a capacitor C52. One end of the parallel circuit of the inductor L52 and the capacitor C52 is connected to a switch S57, and the other end of the parallel circuit of the inductor L52 and the capacitor C52 is connected to the power amplifier 2A.

[0176] The first filter circuit 41 and the second filter circuit 42 connected in this manner are switched on / off by switches S56 and S57. Thus, the first filter circuit 41 and the second filter circuit 42 can switch on / off the band-stop filter for removing noise from a plurality of discrete voltages. For example, by controlling the opening and closing of switches S56 and S57, the following three band-stop filters (1) to (3) can be realized.

[0177] (1) By closing switch S56 and opening switch S57, the first filter circuit 41 is connected between the output switch circuit 30 and the power amplifier 2A, while the second filter circuit 42 is not connected. As a result, the first filter circuit 41 functions as a band-stop filter, while the second filter circuit 42 does not function as a band-stop filter.

[0178] (2) By opening switch S56 and closing switch S57, the second filter circuit 42 is connected between the output switch circuit 30 and the power amplifier 2A, and the first filter circuit 41 is disconnected. As a result, the second filter circuit 42 functions as a band-stop filter, and the first filter circuit 41 does not function as a band-stop filter.

[0179] (3) By closing the switch S56 and the switch S57, the first filter circuit 41 and the second filter circuit 42 are connected between the output switch circuit 30 and the power amplifier 2A. Thus, the first filter circuit 41 and the second filter circuit 42 function as band-stop filters.

[0180] For example, the opening and closing of switches S56 and S57 can be controlled based on the channel bandwidth (i.e., modulation bandwidth) of high-frequency signal RF1. Furthermore, if power amplifier 2A is capable of amplifying transmission signals in multiple frequency bands, the opening and closing of switches S56 and S57 can also be controlled based on the frequency band of the transmission signal amplified by power amplifier 2A. The opening and closing control of switches S56 and S57 is not limited to the above.

[0181] Figure 3The circuit configurations of the first filter circuit 41 and the second filter circuit 42 are shown as examples and are not limited thereto. For example, the first filter circuit 41 and / or the second filter circuit 42 may also be a series circuit (LC series circuit) of an inductor and a capacitor. In this case, the LC series circuit may be connected between the path connecting the output switch circuit 30 and the power amplifier 2A and the ground line.

[0182] [1.3.5 Circuit Structure of Digital Control Circuit 60]

[0183] Next, the circuit structure of the digital control circuit 60 will be described. Figure 3 As shown, the digital control circuit 60 includes a first controller 61 and a second controller 62 .

[0184] The first controller 61 can generate control signals S1 to S4 by processing a serial data signal (DATA) based on a clock signal (CLK) supplied from the RFIC 3. Here, the serial data signal refers to a data signal transmitted bit by bit through a signal line or a circuit.

[0185] Control signal S1 is a signal for controlling the opening and closing of switches S61 to S63 and S71 to S73 included in pre-regulator circuit 10. Control signal S2 is a signal for controlling the opening and closing of switches S11 to S14, S21 to S24, S31 to S34, and S41 to S44 included in switched capacitor circuit 20. Control signal S3 is a signal for controlling the opening and closing of switches S51 to S54 included in output switch circuit 30 when power amplifier 2A is in APT mode. Control signal S4 is a signal for controlling the opening and closing of switches S56 and S57 used in first filter circuit 41 and second filter circuit 42.

[0186] The clock signal used to process the serial data signal in the first controller 61 uses a signal line different from the serial data signal, but the present invention is not limited thereto. For example, the clock signal may be transmitted via the same signal line as the serial data signal.

[0187] In addition, in this embodiment, one serial data signal is used to control the pre-regulator circuit 10 , the switched capacitor circuit 20 , the output switch circuit 30 , and the switches S56 and S57 , but a plurality of serial data signals may be used.

[0188] The second controller 62 can process the digital control logic (DCL) signals (DCL1, DCL2) supplied from the RFIC 3 to generate the control signal S5. The DCL signal is an example of a parallel data signal. Here, a parallel data signal refers to a data signal that is transmitted simultaneously and in parallel through multiple signal lines or circuits.

[0189] When the power amplifier 2A is in D-ET mode, RFIC 3 generates DCL signals (DCL1, DCL2) based on the envelope signal of the high-frequency signal. Therefore, when the power amplifier 2A is in D-ET mode, control signal S5 is a signal for controlling the opening and closing of switches S51 to S54 included in the output switch circuit 30.

[0190] Each DCL signal (DCL1, DCL2) is a single-bit signal. Voltages V1 to V4 are represented by a combination of two single-bit signals. For example, "00," "01," "10," and "11" represent V1, V2, V3, and V4, respectively. Gray code can also be used to represent voltage levels.

[0191] Furthermore, while this embodiment uses two DCL signals to control the output switch circuit 30 in D-ET mode, the number of DCL signals is not limited to this. For example, an arbitrary number of DCL signals, from one to three or more, may be used, depending on the number of voltage levels selectable by each output switch circuit 30. Furthermore, the digital control signals used to control the output switch circuit 30 are not limited to DCL signals.

[0192] [1.4 Power Amplification Method]

[0193] Next, refer to Figure 4 The power amplification method of this embodiment will be described. Figure 4 1 is a flowchart showing the power amplification method according to this embodiment.

[0194] First, pre-regulator circuit 10 converts the input voltage supplied from the DC power supply into a regulated voltage (S10). Next, it determines which power amplifier 2A or 2B to use (S20). In other words, it determines whether power amplifier 2A should amplify high-frequency signal RF1 or power amplifier 2B should amplify high-frequency signal RF2.

[0195] Here, when using power amplifier 2A (2A in S20), switched capacitor circuit 20 generates multiple discrete voltages based on the adjustment voltage (S30). Output switch circuit 30 selectively supplies at least one of the multiple discrete voltages to power amplifier 2A (S40). Thus, power amplifier 2A applies the D-ET mode. RFIC3 predistorts the input signal (high-frequency signal RF1) of power amplifier 2A using the first mathematical model that accounts for the memory effect (S50). Power amplifier 2A amplifies the predistorted input signal (high-frequency signal RF1) (S60).

[0196] On the other hand, when power amplifier 2B is used (2B in S20), pre-regulator circuit 10 supplies the regulated voltage to power amplifier 2B (S70). In other words, the generation of the discrete voltage is skipped. Thus, power amplifier 2B is in APT mode. RFIC 3 predistorts the input signal (high-frequency signal RF2) to power amplifier 2B using a second mathematical model that does not incorporate memory effects (S80). Power amplifier 2B amplifies the predistorted input signal (high-frequency signal RF2) (S90).

[0197] also, Figure 4 The power amplification method shown is an example and is not limited thereto. For example, in step S80, RFIC 3 may not predistort the input signal of power amplifier 2B. In this case, in step S90, power amplifier 2B amplifies the non-predistorted input signal.

[0198] [1.5 Component Configuration of Communication Device 6]

[0199] Next, refer to Figure 5 The component configuration of the communication device 6 will be described. Figure 5 : is a component configuration diagram of the communication device 6 of this embodiment. Specifically, Figure 5 1 is a top view of the motherboard 1000 and the antennas 5A and 5B. Figure 5 In order to make the configuration relationship of each component easier to understand, characters representing the components (such as "PA1" etc.) are added to each component, but in practice, such characters do not need to be added to each component.

[0200] Antenna 5A (ANT1) and antenna 5B (ANT2) are arranged near motherboard 1000. On motherboard 1000, tracker module 1 (TM), power amplifier 2A (PA1), power amplifier 2B (PA2), RFIC 3, and BBIC 4 are arranged.

[0201] The power amplifier 2A is arranged closer to the tracker module 1 than the power amplifier 2B. In other words, the distance D1 between the power amplifier 2A and the tracker module 1 is shorter than the distance D2 between the power amplifier 2B and the tracker module 1.

[0202] Furthermore, the power amplifier 2A is arranged closer to the RFIC 3 than the power amplifier 2B. In other words, the distance D3 between the power amplifier 2A and the RFIC 3 is shorter than the distance D4 between the power amplifier 2B and the RFIC 3.

[0203] [1.6 Effects, etc.]

[0204] As described above, the power amplification system 7 of this embodiment includes: a power amplifier 2A configured to amplify a high-frequency signal RF1; a power amplifier 2B configured to amplify a high-frequency signal RF2; a switched capacitor circuit 20 configured to generate a plurality of discrete voltages based on a regulated voltage supplied from a pre-regulator circuit 10; an output switch circuit 30 configured to selectively output at least one of the plurality of discrete voltages to the power amplifier 2A; and a DPD circuit 71 configured to pre-distort the high-frequency signals RF1 and RF2. The pre-regulator circuit 10 is configured to convert an input voltage into a regulated voltage and output the regulated voltage to the switched capacitor circuit 20, and output the regulated voltage to the power amplifier 2B without passing through the switched capacitor circuit 20. The DPD circuit 71 pre-distorts the high-frequency signal RF1 using a first mathematical model for DPD and pre-distorts the high-frequency signal RF2 using a second mathematical model for DPD, or does not pre-distort the high-frequency signal RF2.

[0205] In addition, the power amplification method of this embodiment converts an input voltage into an adjustment voltage (S10), generates multiple discrete voltages based on the adjustment voltage (S30), selectively supplies at least one of the multiple discrete voltages to power amplifier 2A (S40), predistorts a first input signal of power amplifier 2A using a first mathematical model (S50), amplifies the predistorted first input signal (S60), skips the generation of the multiple discrete voltages, supplies the adjustment voltage to power amplifier 2B (S70), predistorts a second input signal of power amplifier 2B using a second mathematical model (S80), and amplifies the predistorted second input signal (S90).

[0206] Furthermore, the DPD circuit 71 of this embodiment predistorts a first input signal of the power amplifier 2A, which selectively receives at least one of a plurality of discrete voltages generated based on the adjustment voltage, using a first mathematical model, and predistorts a second input signal of the power amplifier 2B, which receives the adjustment voltage, using a second mathematical model.

[0207] Thus, DPD based on a first mathematical model is applied to the input signal of power amplifier 2A, which selectively supplies at least one of multiple discrete voltages, while DPD based on a second mathematical model is applied to the input signal of power amplifier 2B, which supplies a regulated voltage, or DPD is not applied. Supplying multiple discrete voltages may more actively utilize the nonlinear region of the power amplifier to improve power efficiency than supplying a regulated voltage, which in turn increases nonlinear distortion. Therefore, by applying the first mathematical model to the input signal of power amplifier 2A, reducing nonlinear distortion prioritizes improving transmit signal quality. On the other hand, by applying the second mathematical model to the input signal of power amplifier 2B, or by not applying DPD, reducing the amount of DPD parameters stored in power amplifier 2B prioritizes reducing the amount of DPD parameters stored in power amplifier 2B. This effectively improves transmit signal quality while suppressing an increase in the amount of DPD parameter storage.

[0208] For example, in the power amplification system 7, the power amplification method or the DPD circuit 71 of this embodiment, the memory effect of the power amplifier 2A may be set in the first mathematical model, and the memory effect of the power amplifier 2B may not be set in the second mathematical model.

[0209] According to this, by also predistorting the input signal using the first mathematical model, the quality of the transmission signal can be further improved, and by predistorting the input signal using the second mathematical model, the amount of memory can be further reduced.

[0210] For example, in the power amplification system 7 , the power amplification method, or the DPD circuit 71 of the present embodiment, the DET mode may be applied to the power amplifier 2A, and the APT mode may be applied to the power amplifier 2B.

[0211] Thus, power amplifier 2A in D-ET mode uses the first mathematical model, while power amplifier 2B in APT mode uses the second mathematical model, or does not apply DPD. D-ET mode utilizes the nonlinear region of the power amplifier compared to APT mode, resulting in increased nonlinear distortion. Therefore, by improving transmit signal quality in D-ET mode and reducing the amount of DPD parameter storage in APT mode, transmit signal quality can be effectively improved while suppressing an increase in the amount of DPD parameter storage.

[0212] For example, in the power amplification system 7 of the present embodiment, the power amplifier 2A may be arranged closer to the tracker module 1 including the output switch circuit 30 than the power amplifier 2B.

[0213] This shortens the voltage supply path between power amplifier 2A and tracker module 1. Since the power supply voltage Vcc1 supplied to power amplifier 2A varies discretely at shorter intervals than the power supply voltage Vcc2 supplied to power amplifier 2B, degradation in the voltage supply path is greater. Therefore, shortening the voltage supply path between power amplifier 2A and RFIC 3 significantly suppresses degradation in power supply voltage Vcc1. Furthermore, since the voltage supply path between power amplifier 2B and tracker module 1 can be lengthened, the flexibility in the configuration of power amplifier 2B is increased.

[0214] For example, in the power amplification system 7 of the present embodiment, the power amplifier 2A may be arranged closer to the RFIC 3 including the DPD circuit 71 than the power amplifier 2B.

[0215] This shortens the transmission path of high-frequency signal RF1 between power amplifier 2A and RFIC 3, suppresses degradation of the input signal (high-frequency signal RF1) to power amplifier 2A, and reduces nonlinear distortion of the output signal of power amplifier 2A. Furthermore, since the transmission path of high-frequency signal RF2 between power amplifier 2B and RFIC 3 can be lengthened, the flexibility in the configuration of power amplifier 2B can be increased.

[0216] (Other Embodiments)

[0217] While the power amplification system and power amplification method of the present invention have been described above based on the embodiments, the power amplification system and power amplification method of the present invention are not limited to the aforementioned embodiments. Other embodiments achieved by combining arbitrary components of the aforementioned embodiments, modifications of the aforementioned embodiments that occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the aforementioned power amplification system are also encompassed by the present invention.

[0218] For example, in the circuit configurations of the various circuits of the above-described embodiments, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, a filter may be inserted between the DAC 72 and the orthogonal modulator 73. Furthermore, for example, a filter may be inserted between the power amplifier 2A and the antenna 5A, and / or between the power amplifier 2B and the antenna 5B.

[0219] Furthermore, in the above embodiment, multiple discrete voltages are supplied to the output switch circuit from a switched capacitor circuit, but this is not limiting. For example, multiple voltages may be supplied from multiple DC-DC converters. Furthermore, when the voltage levels of the multiple discrete voltages are evenly spaced, using a switched capacitor circuit is preferred, as it effectively reduces the size of the tracker module.

[0220] Furthermore, in the above embodiment, four discrete voltages are supplied to the power amplifier. However, the number of discrete voltages is not limited to four. For example, as long as the plurality of discrete voltages includes at least a voltage corresponding to the maximum output power and a voltage corresponding to the output power with the highest generation frequency, the power added efficiency can be improved.

[0221] The present invention can be widely used in communication equipment such as mobile phones as a power amplification system for amplifying high-frequency signals.

[0222] Description of Reference Numerals

[0223] 1…tracker module, 2A, 2B…power amplifier, 3…RFIC, 4…BBIC, 5A, 5B…antenna, 6…communication device, 7…power amplification system, 10…pre-regulator circuit, 20…switched capacitor circuit, 30…output switch circuit, 41…first filter circuit, 42…second filter circuit, 60…digital control circuit, 61…first controller, 62…second controller, 71…DPD circuit, 72…DAC, 73…quadrature modulator, 1000…motherboard.

Claims

1. A power amplification system, wherein: have: a first power amplifier configured to amplify a first high frequency signal; a second power amplifier configured to amplify a second high frequency signal; a switched capacitor circuit configured to generate a plurality of discrete voltages based on a regulation voltage supplied from the pre-regulator circuit; an output switching circuit configured to selectively output at least one of the plurality of discrete voltages to the first power amplifier; as well as The digital predistortion circuit is configured to predistort the first high-frequency signal and the second high-frequency signal. The pre-regulator circuit is configured to convert the input voltage into the adjustment voltage and output the voltage to the switched capacitor circuit, and output the adjustment voltage to the second power amplifier without passing through the switched capacitor circuit. The digital predistortion circuit predistorts the first high frequency signal using a first mathematical model for digital predistortion and predistorts the second high frequency signal using a second mathematical model for digital predistortion, or does not predistort the second high frequency signal.

2. The power amplification system according to claim 1, wherein: The memory effect of the first power amplifier is set in the first mathematical model. The second mathematical model does not include the memory effect of the second power amplifier.

3. The power amplification system according to claim 1 or 2, wherein: The D-ET (Digital Envelope Tracking) mode is applied to the first power amplifier. The second power amplifier is operated in an APT (Average Power Tracking) mode.

4. The power amplification system according to claim 3, wherein: The first power amplifier is arranged closer to the tracker module including the output switch circuit than the second power amplifier.

5. The power amplification system according to claim 3 or 4, wherein: The first power amplifier is arranged closer to the integrated circuit including the digital predistortion circuit than the second power amplifier.

6. A power amplification method, wherein: Converts the input voltage into a regulated voltage, Generate multiple discrete voltages based on the above adjustment voltage, selectively supplying at least one of the plurality of discrete voltages to the first power amplifier, predistorting a first input signal of the first power amplifier using a first mathematical model, amplifying the predistorted first input signal, skipping the generation of the plurality of discrete voltages and supplying the adjusted voltage to the second power amplifier, predistorting a second input signal of the second power amplifier using a second mathematical model, The predistorted second input signal is amplified.

7. The power amplification method according to claim 6, wherein: The memory effect of the first power amplifier is set in the first mathematical model. The second mathematical model does not include the memory effect of the second power amplifier.

8. The power amplification method according to claim 6 or 7, wherein: The DET mode is applied to the first power amplifier. The APT mode is applied to the second power amplifier.

9. A digital predistortion circuit, wherein: predistorting a first input signal of a first power amplifier selectively supplied to at least one of a plurality of discrete voltages generated based on the adjustment voltage using a first mathematical model, A second input signal of a second power amplifier supplied with the adjustment voltage is predistorted using a second mathematical model.

10. The digital predistortion circuit according to claim 9, wherein: The memory effect of the first power amplifier is set in the first mathematical model. The second mathematical model does not include the memory effect of the second power amplifier.

11. The digital predistortion circuit according to claim 9 or 10, wherein: The DET mode is applied to the first power amplifier. The APT mode is applied to the second power amplifier.

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