Wide load capacitance low dropout linear regulator circuit, power supply device and electronic equipment

Abstract

The invention is suitable for the technical field of electronic circuits, and provides a wide-load-capacitance low-dropout linear regulator circuit, a power supply device and electronic equipment. The wide load capacitance low dropout linear regulator circuit comprises a bias module, a first operational amplifier module, a second operational amplifier module, a third operational amplifier module, a first compensation module and a second compensation module, and the first operational amplifier module is electrically connected with the bias module, the second operational amplifier module and the first compensation module. The third operational amplifier module is electrically connected with the second operational amplifier module, the second compensation module and the first operational amplifier module. A first zero point generated by the first compensation module is used for compensating the second pole, and a second zero point generated by the second compensation module is used for compensating the third pole. Therefore, according to the design architecture of the wide-load-capacitance low-dropout linear voltage regulator circuit provided by the embodiment of the invention, the two zero points effectively compensate the corresponding poles, the phase margin of the circuit is remarkably improved under the wide-range load capacitance, and the stability of the circuit is enhanced.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a wide load capacitance low voltage drop linear regulator circuit, a power supply device, and an electronic device. Background Art

[0002] Low-dropout linear regulators (LDOs) are widely used in portable electronic devices, IoT terminals, mobile power supplies, and other fields due to their significant advantages, including simple structure, low cost, low power consumption, and small size. In LDO circuit design, a multi-stage operational amplifier cascade architecture is often used to meet high gain requirements to improve output accuracy and load capacity. However, multi-stage amplifier cascades introduce multiple poles, which exacerbate system phase lag. The position of the output poles varies significantly over a wide range of load capacitance, resulting in low phase margin in existing LDO circuits and poor stability. Summary of the Invention

[0003] The embodiments of the present application provide a wide-load-capacitance low-dropout linear regulator circuit, a power supply device, and an electronic device, which can solve the problem that the existing wide-load-capacitance low-dropout linear regulator circuit generally has a low phase margin under a wide range of load capacitance, thereby causing the problem of poor stability of the LDO circuit.

[0004] In a first aspect, an embodiment of the present application provides a wide load capacitance low voltage dropout linear regulator circuit, comprising a first operational amplifier module, a second operational amplifier module, a third operational amplifier module, a first compensation module, and a second compensation module, wherein the first operational amplifier module is electrically connected to the bias module, the second operational amplifier module, and the first compensation module, respectively, and the third operational amplifier module is electrically connected to the second operational amplifier module, the second compensation module, and the first operational amplifier module, respectively; The bias module is used to receive a first reference current and a second reference current, and generate a bias current based on the first reference current and the second reference current; the first operational amplifier module is used to output a first voltage signal to the second operational amplifier module based on the bias current, feedback voltage and reference voltage, and generate a first pole at the common end of the first operational amplifier module and the second operational amplifier module; the second operational amplifier module is used to output a second voltage signal to the third operational amplifier module based on the first voltage signal, and generate a second pole at the common end of the second operational amplifier module and the third operational amplifier module; the third operational amplifier module is used to output a target voltage and the feedback voltage based on the second voltage signal; the first compensation module is used to generate a first zero point, and the first zero point is used to compensate for the second pole; the second compensation module is used to generate a second zero point, and the second zero point is used to compensate for the third pole generated at the common end of the second compensation module and the third operational amplifier module.

[0005] In a possible implementation of the first aspect, the bias module includes a first transistor and a second transistor, the gate of the first transistor being electrically connected to the drain of the first transistor and the first operational amplifier module, respectively, for receiving the first reference current, the source of the first transistor and the source of the second transistor being electrically connected to a first power supply, and the gate of the second transistor being electrically connected to the drain of the second transistor and the first operational amplifier module, respectively, for receiving the second reference current. In a possible implementation of the first aspect, the first operational amplifier module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the gate of the third transistor and the gate of the fourth transistor are both electrically connected to the bias module, the source of the third transistor is used to be electrically connected to the first power supply, the drain of the third transistor is electrically connected to the source of the fourth transistor, the gate of the fifth transistor is used to receive the reference voltage, the source of the fifth transistor is respectively electrically connected to the drain of the fourth transistor and the source of the sixth transistor, the drain of the fifth transistor is respectively electrically connected to the drain of the seventh transistor, the gate of the seventh transistor, and the gate of the eighth transistor, the gate of the sixth transistor is used to receive the feedback voltage, the drain of the sixth transistor is respectively electrically connected to the drain of the eighth transistor, the first compensation module, and the second operational amplifier module, and the source of the seventh transistor and the source of the eighth transistor are both grounded. In a possible implementation of the first aspect, the first compensation module includes a first resistor and a first capacitor, the first end of the first resistor is electrically connected to the first op amp module and the second op amp module respectively, the second end of the first resistor is electrically connected to the first end of the first capacitor, and the second end of the first capacitor is grounded. In a possible implementation of the first aspect, the second operational amplifier module includes a ninth transistor, a tenth transistor, an eleventh transistor, a second resistor, and a third resistor; the gate of the ninth transistor is electrically connected to the first operational amplifier module and the first compensation module, respectively; the drain of the ninth transistor is electrically connected to the second end of the second resistor; the source of the ninth transistor is grounded; the gate of the tenth transistor is used to receive a gate drive signal; the source of the tenth transistor is electrically connected to the first end of the second resistor; the drain of the tenth transistor is electrically connected to the gate of the eleventh transistor, the drain of the eleventh transistor, and the third operational amplifier module, respectively; the first ends of the three resistors are used to be electrically connected to a second power supply; and the second end of the third resistor is electrically connected to the source of the eleventh transistor. In a possible implementation of the first aspect, the third operational amplifier module includes a twelfth transistor, a thirteenth transistor, a fourth resistor and a fifth resistor, the source of the twelfth transistor and the source of the thirteenth transistor are both used to be electrically connected to the second power supply, the gate of the twelfth transistor is electrically connected to the gate of the thirteenth transistor, the drain of the twelfth transistor is electrically connected to the second compensation module, the drain of the thirteenth transistor is electrically connected to the first end of the fourth resistor, the first end of the fifth resistor is electrically connected to the second end of the fourth resistor and the first operational amplifier module respectively, and the second end of the fifth resistor is grounded.

[0006] In a possible implementation of the first aspect, the second compensation module includes a sixth resistor and a load capacitor, the first end of the sixth resistor is electrically connected to the third operational amplifier module, the second end of the sixth resistor is electrically connected to the first end of the load capacitor and the third operational amplifier module, respectively, and the second end of the load capacitor is grounded.

[0007] In a possible implementation of the first aspect, the wide load capacitance low voltage difference linear regulator circuit also includes a seventh resistor, a first end of the seventh resistor is used to be electrically connected to the second power supply, and a second end of the seventh resistor is electrically connected to the second operational amplifier module and the second compensation module respectively. In a second aspect, an embodiment of the present application provides a power supply device, comprising the wide load capacitance low voltage dropout linear regulator circuit described in any one of the first aspects.

[0008] In a third aspect, an embodiment of the present application provides an electronic device comprising the power supply device described in the second aspect.

[0009] Compared with the prior art, the embodiments of the present application have the following beneficial effects: The wide load capacitance low voltage difference linear regulator circuit provided in an embodiment of the present application includes a bias module, a first operational amplifier module, a second operational amplifier module, a first compensation module, a second compensation module, and a third operational amplifier module. The bias module can generate a bias current based on a first reference current and a second reference current, and the first operational amplifier module outputs a first voltage signal based on the bias current, a reference voltage, and a feedback voltage output by the third operational amplifier module. The second operational amplifier module outputs a second voltage signal based on the first voltage signal, and the third operational amplifier module outputs a target voltage and a feedback voltage based on the second voltage signal. In the design of the wide load capacitance low voltage difference linear regulator circuit, a first pole is generated at the output end of the first operational amplifier module, a second pole is generated at the output end of the second operational amplifier module, and a third pole is generated at the output end of the wide load capacitance low voltage difference linear regulator circuit. Due to the presence of these three poles, two zero points need to be introduced for frequency compensation. The first zero point generated by the first compensation module is used to compensate for the second pole, and the second zero point generated by the second compensation module is used to compensate for the third pole. Therefore, the design architecture of the wide load capacitance low voltage difference linear regulator circuit provided in the embodiment of the present application has two zero points that effectively compensate for the corresponding poles, significantly improving the phase margin of the circuit and enhancing the stability of the circuit under a wide range of load capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 This is a typical application diagram of an existing wide load capacitance low voltage dropout linear regulator circuit; Figure 2 This is a principle block diagram of a wide load capacitance low voltage dropout linear regulator circuit provided by an embodiment of the present application; Figure 3 1 is a circuit connection diagram of a wide load capacitor low voltage dropout linear regulator circuit provided by an embodiment of the present application.

[0012] In the figure, 10 is a wide load capacitor low voltage difference linear regulator circuit; 101 is a bias module; 102 is a first operational amplifier module; 103 is a second operational amplifier module; 104 is a third operational amplifier module; 105 is a first compensation module; and 106 is a second compensation module. DETAILED DESCRIPTION

[0013] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0014] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0015] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0016] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0017] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0018] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0019] Low-dropout linear regulators (LDOs), with their significant advantages such as simple structure, low cost, low power consumption, and small size, have gained widespread application in portable electronic devices, IoT terminals, and mobile power supplies. In LDO circuit design, to meet high gain requirements, a multi-stage operational amplifier cascade architecture is often used to improve output accuracy and load capacity. However, this multi-stage amplifier cascade introduces multiple poles, which exacerbate system phase lag. This results in low phase margin in existing LDO circuits, which in turn leads to poor stability.

[0020] For example, Figure 1 As shown in the figure, the LDO circuit mainly consists of an error amplifier EA, a PMOS power transistor PM1, and a voltage divider resistor. Among them, VREF is the reference voltage, RL is the load resistor, CL is the load capacitor, VREG is the output voltage, R1 and R2 divide the output voltage and transmit the feedback voltage VFB to the input of the error amplifier EA.

[0021] Based on the above problems, the wide load capacitance low voltage difference linear regulator circuit provided by the embodiment of the present application includes a bias module, a first op amp module, a second op amp module, a first compensation module, a second compensation module and a third op amp module. Among them, the bias module can generate a bias current based on the first reference current and the second reference current, and the first op amp module outputs a first voltage signal based on the bias current, the reference voltage and the feedback voltage output by the third op amp module. The second op amp module outputs a second voltage signal based on the first voltage signal, and the third op amp module outputs a target voltage and a feedback voltage based on the second voltage signal. In the design of the wide load capacitance low voltage difference linear regulator circuit, a first pole is generated at the output end of the first op amp module, a second pole is generated at the output end of the second op amp module, and a third pole is generated at the output end of the wide load capacitance low voltage difference linear regulator circuit. Due to the existence of these three poles, two zero points need to be introduced for frequency compensation. Among them, the first zero point generated by the first compensation module is used to compensate for the second pole, and the second zero point generated by the second compensation module is used to compensate for the third pole. Therefore, the design architecture of the wide load capacitance low voltage difference linear regulator circuit provided in the embodiment of the present application has two zero points that effectively compensate for the corresponding poles, significantly improving the phase margin of the circuit and enhancing the stability of the circuit under a wide range of load capacitance.

[0022] In order to illustrate the technical solution described in this application, specific embodiments are provided below.

[0023] Figure 2 FIG1 shows a principle block diagram of a wide load capacitance low voltage drop linear regulator circuit 10 provided by an embodiment of the present application. Figure 2As shown, the wide load capacitance low voltage difference linear regulator circuit 10 includes a bias module 101, a first operational amplifier module 102, a second operational amplifier module 103, a third operational amplifier module 104, a first compensation module 105 and a second compensation module 106. The first operational amplifier module 102 is electrically connected to the bias module 101, the second operational amplifier module 103 and the first compensation module 105 respectively, and the third operational amplifier module 104 is electrically connected to the second operational amplifier module 103, the second compensation module 106 and the first operational amplifier module 102 respectively.

[0024] Specifically, the bias module 101 can generate a bias current based on a first reference current IBIAS1 and a second reference current IBIAS2. The first op amp module 102 outputs a first voltage signal based on the bias current, a reference voltage, and a feedback voltage VFB output by the third op amp module 104. The second op amp module 103 outputs a second voltage signal based on the first voltage signal, and the third op amp module 104 outputs a target voltage and a feedback voltage VFB based on the second voltage signal. In the design of the wide-load-capacitor low-voltage-dropout linear regulator circuit 10, a first pole is generated at the output of the first op amp module 102, a second pole is generated at the output of the second op amp module 103, and a third pole is generated at the output of the wide-load-capacitor low-voltage-dropout linear regulator circuit 10. Due to the presence of these three poles, two zeros are required for frequency compensation. The first zero generated by the first compensation module 105 is used to compensate for the second pole, and the second zero generated by the second compensation module 106 is used to compensate for the third pole. Therefore, in the design architecture of the wide load capacitance low voltage difference linear regulator circuit 10 provided in the embodiment of the present application, the two zero points effectively compensate for the corresponding poles, significantly improving the phase margin of the circuit (for example, ensuring that the phase margin is above 60°) under a wide range of load capacitance, thereby enhancing the stability of the circuit.

[0025] In one embodiment of the present application, Figure 3 As shown, the bias module 101 includes a first transistor MP1 and a second transistor MP2, the gate of the first transistor MP1 is electrically connected to the drain of the first transistor MP1 and the first operational amplifier module 102, respectively, for receiving a first reference current IBIAS1, the source of the first transistor MP1 and the source of the second transistor MP2 are electrically connected to a first power supply VPP, and the gate of the second transistor MP2 is electrically connected to the drain of the second transistor MP2 and the first operational amplifier module 102, respectively, for receiving a second reference current IBIAS2.

[0026] Specifically, the first transistor MP1 determines the current flowing through the first transistor MP1 based on the first reference current IBIAS1, and the second transistor MP2 determines the current flowing through the second transistor MP2 based on the second reference current IBIAS2. Furthermore, the second reference current IBIAS2 generates a first bias voltage VB1 through the second transistor MP2, and the first reference current IBIAS1 generates a second bias voltage VB2 through the first transistor MP1. Thus, the first operational amplifier module 102 is provided with the first bias voltage VB1, the second bias voltage VB2, and the bias currents (the current flowing through the first transistor MP1 and the current flowing through the second transistor MP2).

[0027] It should be noted that both the first reference current IBIAS1 and the second reference current IBIAS2 can be generated by a bandgap reference module.

[0028] Exemplarily, the first power supply VPP may be a low voltage power supply with a power supply voltage of 2V to 5.5V.

[0029] For example, designers can select the types of the first transistor MP1 and the second transistor MP2 according to actual conditions, that is, both can use fully controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors. For example, the first transistor MP1 and the second transistor MP2 can be both PMOS transistors.

[0030] It should be noted that the embodiments provided herein only illustrate one circuit structure as the bias module 101, and do not mean that this is the only circuit structure that can implement the function of the bias module 101. Other circuit structures that can implement this function may also be substituted, and the present invention is not limited thereto.

[0031] In one embodiment of the present application, Figure 3As shown, the first operational amplifier module 102 includes a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MP6, a seventh transistor MN1, and an eighth transistor MN2. The gate of the third transistor MP3 and the gate of the fourth transistor MP4 are both electrically connected to the bias module 101. The source of the third transistor MP3 is electrically connected to the first power supply VPP. The drain of the third transistor MP3 is electrically connected to the source of the fourth transistor MP4. The gate of the fifth transistor MP5 is used to receive the reference voltage VREF. The source of the fifth transistor MP5 is electrically connected to the drain of the fourth transistor MP4 and the source of the sixth transistor MP6, respectively. The drain of the fifth transistor MP5 is electrically connected to the drain of the seventh transistor MN1, the gate of the seventh transistor MN1, and the gate of the eighth transistor MN2, respectively. The gate of the sixth transistor MP6 is used to receive the feedback voltage VFB. The drain of the sixth transistor MP6 is electrically connected to the drain of the eighth transistor MN2, the first compensation module 105, and the second operational amplifier module 103, respectively. The source of the seventh transistor MN1 and the source of the eighth transistor MN2 are both grounded.

[0032] Specifically, the third transistor MP3 and the second transistor MP2 form a current mirror, and the fourth transistor MP4 and the first transistor MP1 form a current mirror. Therefore, the current flowing through the third transistor MP3 is proportional to the current flowing through the second transistor MP2, and the current flowing through the fourth transistor MP4 is proportional to the current flowing through the first transistor MP1. The third and fourth transistors MP3 and MP4 form a cascode structure, which ensures that the current mirrored by the third transistor MP3 is more accurate and reduces the influence of the input to the transistor source on the current flowing through the third transistor MP3. The third transistor MP3, the fourth transistor MP4, the fifth transistor MP5, the sixth transistor MP6, the seventh transistor MN1, and the eighth transistor MN2 collectively constitute a first-stage operational amplifier, which serves as the first stage of the LDO circuit and provides the main gain. The first input (positive input) of the first-stage operational amplifier is used to receive a reference voltage VREF, and the second input (negative input) of the first-stage operational amplifier is used to receive a feedback voltage VFB. The output of the first-stage operational amplifier is electrically connected to the second operational amplifier module 103 for outputting a first voltage signal to the second operational amplifier module 103. When the LDO circuit is first powered on, because the feedback voltage VFB is less than the reference voltage VREF, the first voltage signal is a high-level signal. The combined action of the second and third op amp modules 103, 104 ultimately increases the output current, thereby increasing the feedback voltage VFB. When the feedback voltage VFB is greater than or equal to the reference voltage VREF, the first voltage signal is a low-level signal. The combined action of the second and third op amp modules 103, 104 ultimately decreases the output current, thereby decreasing the feedback voltage VFB. This ultimately stabilizes the output voltage VOUT at a preset voltage.

[0033] For example, designers can select the types of the third transistor MP3, the fourth transistor MP4, the fifth transistor MP5, the sixth transistor MP6, the seventh transistor MN1, and the eighth transistor MN2 according to actual conditions. That is, they can all use fully-controlled power devices such as metal oxide field-effect transistors or insulated gate bipolar transistors. For example, the third transistor MP3, the fourth transistor MP4, the fifth transistor MP5, and the sixth transistor MP6 can all be PMOS transistors, and the seventh transistor MN1 and the eighth transistor MN2 can both be NMOS transistors.

[0034] It should be noted that the embodiments provided in this application only show one circuit structure as the first operational amplifier module 102, which does not mean that only this circuit structure can realize the function of the first operational amplifier module 102. Other circuit structures that can realize this function can also be replaced, and the present invention is not limited to this.

[0035] In one embodiment of the present application, Figure 3 As shown, the first compensation module 105 includes a first resistor R1 and a first capacitor C1, the first end of the first resistor R1 is electrically connected to the first operational amplifier module 102 and the second operational amplifier module 103 respectively, the second end of the first resistor R1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is grounded.

[0036] Specifically, the first resistor R1 and the first capacitor C1 within the first compensation module 105 form an RC series zero-point compensation network, the core function of which is to generate a fixed first zero point to compensate for the second pole at the output of the second op amp module 103. Specifically, the frequency characteristics of the RC network generate a leading phase at a specific frequency, which can offset the lagging phase caused by the second pole. When the second pole at the output of the second op amp module 103 exacerbates the system phase lag, the first zero point generated by the RC network provides a leading phase near the corresponding frequency, effectively improving the phase margin and ensuring the phase stability of the loop at the gain crossover frequency, thereby maintaining stable operation of the LDO and optimizing the system's dynamic performance in conjunction with other compensation mechanisms.

[0037] It should be noted that the embodiments provided in this application only show one circuit structure as the first compensation module 105, which does not mean that only this circuit structure can realize the function of the first compensation module 105. Other circuit structures that can realize this function can also be replaced, and are not limited to this.

[0038] In one embodiment of the present application, Figure 3As shown, the second operational amplifier module 103 includes a ninth transistor MN3, a tenth transistor HMN1, an eleventh transistor HMP1, a second resistor R2, and a third resistor R3. The gate of the ninth transistor MN3 is electrically connected to the first operational amplifier module 102 and the first compensation module 105, respectively. The drain of the ninth transistor MN3 is electrically connected to the second end of the second resistor R2. The source of the ninth transistor MN3 is grounded. The gate of the tenth transistor HMN1 is used to receive a gate drive signal VB3. The source of the tenth transistor HMN1 is electrically connected to the first end of the second resistor R2. The drain of the tenth transistor HMN1 is electrically connected to the gate of the eleventh transistor HMP1, the drain of the eleventh transistor HMP1, and the third operational amplifier module 104, respectively. The first ends of the three resistors are used to be electrically connected to the second power supply VIN. The second end of the third resistor R3 is electrically connected to the source of the eleventh transistor HMP1.

[0039] Specifically, the ninth transistor MN3, the tenth transistor HMN1, the eleventh transistor HMP1, the second resistor R2, and the third resistor R3 collectively constitute a first-stage common-source amplifier, serving as the second-stage operational amplifier of the LDO circuit, for expanding the bandwidth of the LDO circuit. The ninth transistor MN3 is turned on or off in response to a first voltage signal, and the tenth transistor HMN1 is turned on or off in response to a gate drive signal VB3. When the ninth transistor MN3 is turned on in response to the first voltage signal and the tenth transistor HMN1 is turned on in response to the gate drive signal VB3, the gate of the eleventh transistor HMP1 is pulled low, turning on the eleventh transistor HMP1. This causes current to flow from the second power supply VIN, through the third resistor R3, the eleventh transistor HMP1, the tenth transistor HMN1, the second resistor R2, and the ninth transistor MN3, and to ground, forming a loop.

[0040] Exemplarily, the first power supply VPP may be a high voltage power supply, and the power supply voltage may be as high as 10V.

[0041] For example, designers can select the types of the ninth transistor MN3, the tenth transistor HMN1, and the eleventh transistor HMP1 based on actual circumstances. Specifically, they can all employ fully-controlled power devices such as metal oxide field-effect transistors (MOS FETs) or insulated gate bipolar transistors (IGBTs). For example, the ninth transistor MN3 can be an NMOS transistor, and the tenth transistor HMN1 and the eleventh transistor HMP1 can both be PMOS transistors. Furthermore, the tenth transistor HMN1 and the eleventh transistor HMP1 are both high-voltage transistors, primarily designed to withstand high voltages and protect low-voltage components.

[0042] It should be noted that the embodiments provided in this application only show one circuit structure as the second operational amplifier module 103, which does not mean that only this circuit structure can realize the function of the second operational amplifier module 103. Other circuit structures that can realize this function can also be replaced, and are not limited to this.

[0043] In one embodiment of the present application, Figure 3 As shown, the third operational amplifier module 104 includes a twelfth transistor HMP2, a thirteenth transistor HMP3, a fourth resistor R4, and a fifth resistor R5. The source of the twelfth transistor HMP2 and the source of the thirteenth transistor HMP3 are both used to be electrically connected to the second power supply VIN, the gate of the twelfth transistor HMP2 is electrically connected to the gate of the thirteenth transistor HMP3, the drain of the twelfth transistor HMP2 is electrically connected to the second compensation module 106, the drain of the thirteenth transistor HMP3 is electrically connected to the first end of the fourth resistor R4, the first end of the fifth resistor R5 is electrically connected to the second end of the fourth resistor R4 and the first operational amplifier module 102, respectively, and the second end of the fifth resistor R5 is grounded.

[0044] Specifically, the sources of the twelfth transistor HMP2 and the thirteenth transistor HMP3 are commonly connected to the second power supply VIN, and their gates are interconnected to form a current mirror structure, which dynamically adjusts the current based on the circuit input signal, thereby controlling the output voltage. The fourth resistor R4 and the fifth resistor R5 form a stable voltage divider network through series voltage division, which is used to divide the target voltage. Based on the voltage distribution principle of a series circuit, the target voltage is distributed across the two resistors in proportion to their resistance values, ultimately generating a stable feedback voltage VFB at the connection node between the fourth resistor R4 and the fifth resistor R5. This feedback voltage VFB serves as the voltage reference for the first-stage op amp, providing a stable reference for the final output of the target voltage, ensuring the accuracy and stability of the output voltage VOUT.

[0045] It should be noted that when the feedback voltage VFB is less than the reference voltage VREF, the first voltage signal is a high-level signal, and the gate voltage of the thirteenth transistor HMP3 decreases, ultimately increasing the output current and, in turn, increasing the feedback voltage VFB. When the feedback voltage VFB is greater than or equal to the reference voltage VREF, the first voltage signal is a low-level signal, and the gate voltage of the thirteenth transistor HMP3 increases, ultimately decreasing the output current and, in turn, decreasing the feedback voltage VFB. This ultimately stabilizes the output voltage VOUT at a predetermined voltage.

[0046] For example, designers can select the type of the twelfth transistor HMP2 and the thirteenth transistor HMP3 based on actual conditions. Specifically, both transistors can be fully controlled power devices, such as metal oxide field-effect transistors (MOS FETs) or insulated gate bipolar transistors (IGBTs). For example, both the twelfth transistor HMP2 and the thirteenth transistor HMP3 can be PMOS transistors. Furthermore, both the twelfth transistor HMP2 and the thirteenth transistor HMP3 are high-voltage transistors, primarily designed to withstand high voltages and protect low-voltage components.

[0047] For example, the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 are not limited here. For example, the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 can be fixed or variable. In addition, in addition to using one fourth resistor R4 and one fifth resistor R5, designers can also use other numbers of fourth resistors R4 and fifth resistors R5. For example, two or three fourth resistors R4 can be connected in series and parallel, and two or three fifth resistors R5 can be connected in series and parallel. Figure 3 Only a circuit structure is shown in which the third operational amplifier module 104 includes a fourth resistor R4 with a fixed resistance and a fifth resistor R5 with a fixed resistance connected in series. Resistors of different numbers, types or connection relationships can be used to replace the fourth resistor R4 and the fifth resistor R5. The basic working principles are similar and will not be described in detail here.

[0048] For example, the resistance ratio between the fourth resistor R4 and the fifth resistor R5 can be selected. For example, the resistance ratio of the fourth resistor R4 to the fifth resistor R5 is 4:1. At this time, through the joint action of the first operational amplifier module 102, the first compensation module 105, the second operational amplifier module 103, the third operational amplifier module 104 and the second compensation module 106, the output voltage VOUT can finally be stabilized at 5 times the reference voltage VREF.

[0049] It should be noted that the embodiment provided in this application only shows one circuit structure as the second compensation module 106, which does not mean that only this circuit structure can realize the function of the second compensation module 106. Other circuit structures that can realize this function can also be replaced, and are not limited to this.

[0050] In one embodiment of the present application, Figure 3 As shown, the second compensation module 106 includes a sixth resistor R6 and a load capacitor RL, the first end of the sixth resistor R6 is electrically connected to the third operational amplifier module 104, the second end of the sixth resistor R6 is electrically connected to the first end of the load capacitor RL and the third operational amplifier module 104, respectively, and the second end of the load capacitor RL is grounded.

[0051] Specifically, the core technology of the second compensation module 106 is the pseudo-ESR (Equivalent Series Resistance) compensation network. In the LDO circuit, the pseudo-ESR compensation technology compensates for the pole offset caused by the change of the load capacitance RL by introducing a zero point related to the equivalent series resistance, thereby improving the stability of the system over a wide load capacitance range.

[0052] It should be noted that because the load capacitance RL typically varies within a preset range (e.g., 1uF to 20uF), the third pole at the output of the LDO circuit varies significantly, sometimes coming close to the first pole. This phenomenon can easily lead to increased phase lag, threatening system stability. To address this issue, the circuit is designed with a dynamically adjustable second zero point. That is, the second zero point can track changes in the load capacitance in real time and accurately compensate for the phase influence of the third pole. Therefore, the LDO circuit of the present application is applicable to a wide range of load capacitance variations. That is, the present application can have a high phase margin within a wide range of load capacitance variations, significantly improving the stability and adaptability of the circuit under complex operating conditions.

[0053] It should be noted that the embodiment provided in this application only shows one circuit structure as the second compensation module 106, which does not mean that only this circuit structure can realize the function of the second compensation module 106. Other circuit structures that can realize this function can also be replaced, and are not limited to this.

[0054] In one embodiment of the present application, Figure 3 As shown, the wide load capacitance low voltage difference linear regulator circuit 10 further includes a seventh resistor R7, a first end of the seventh resistor R7 is used to be electrically connected to the second power supply VIN, and a second end of the seventh resistor R7 is electrically connected to the second operational amplifier module 103 and the second compensation module 106 respectively.

[0055] Specifically, the seventh resistor R7 is used to provide a path from the second power supply VIN to ground when the eleventh transistor HMP1 is in the off state. The seventh resistor R7 also acts as a current limiter to reduce the static power consumption of the LDO. In addition, the seventh resistor R7 can also dynamically adjust the pole frequency, allowing the second pole to enter or exit the bandwidth.

[0056] In one embodiment of the present application, Figure 3 As shown, the wide load capacitance low voltage difference linear regulator circuit 10 further includes a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the first end of the sixth resistor R6, and a second end of the second capacitor C2 is electrically connected to the second end of the fourth resistor R4 and the first end of the fifth resistor R5 respectively.

[0057] Specifically, the second capacitor C2 and the fourth resistor R4 generate a zero point, and the second capacitor C2, the fourth resistor R4, and the fifth resistor R5 generate a pole point, and the above zero point and pole point will cancel each other out.

[0058] The following combination Figure 3 The working principle of the LDO circuit of the present application and how the LDO circuit has high phase margin, fast transient response and low static power consumption in a wide load capacitance range are described in detail.

[0059] Under heavy or full load conditions, i.e., when the output current is high, the VGS of the thirteenth transistor HMP3 is low, and the eleventh transistor HMP1 is turned on. At this point, the third resistor R3, the eleventh transistor HMP1, the tenth transistor HMN1, the second resistor R2, and the ninth transistor MN3 form a path from the second power supply VIN to ground. The first pole is the primary pole, the third pole is the secondary pole, and the second pole is located at a high frequency. To increase the loop bandwidth, the second pole needs to be brought into the bandwidth, increasing the loop bandwidth and thus enabling a fast transient response of the LDO circuit. Furthermore, the first compensation module 105 and the second compensation module 106 can compensate for the poles, thereby improving the phase margin and stability of the LDO circuit.

[0060] Under heavy or full load conditions, the value of the dominant pole is:

[0061] Among them, r p6 is the small signal resistance of MP6; r n2 is the small signal resistance of MN2; C j1 It is the parasitic capacitance of the output node of the first stage op amp.

[0062] The value of the secondary dominant pole is:

[0063] Among them, r Hp3 is the small signal resistance of HMP3; RL is the load resistance; R5 and R6 are the voltage divider resistances; CL is the load capacitance.

[0064] The value of the second pole is:

[0065] Where gm is the transconductance of HMP1, C j2 is the parasitic capacitance of the output node of the second-stage operational amplifier; R3 is the resistance value of the third resistor R3.

[0066] In addition, to keep the LDO circuit at a high loop bandwidth, a frequency compensation scheme is developed. That is, when the loop bandwidth is at its maximum under heavy or full load, the second pole is placed within the bandwidth to increase the loop bandwidth. Since there are three poles within the bandwidth, two zeros are required for frequency compensation. Since the load capacitance varies between 1uF and 20uF, the third pole at the output of the LDO circuit varies greatly, and there are situations where the primary and secondary poles are close to each other. A zero is required to follow the load capacitance changes and track and compensate for the third pole at the LDO output. Therefore, a pseudo-ESR compensation technique (second compensation module 106) is adopted, and its zero position is:

[0067] Among them, gmp3 refers to the transconductance of HMP3; gmp2 refers to the transconductance of HMP2; among them, gmp2 is much smaller than gmp3.

[0068] To keep the high-frequency second pole within the bandwidth, a zero is required to ensure the loop phase margin is above 60°. Therefore, a series RC connection (first compensation module 105) is required to create this zero. Under no-load conditions, the primary pole is at the LDO output, while the secondary pole is located at the output of the first op amp. Keeping both the secondary pole and the second pole outside the bandwidth ensures LDO system stability.

[0069] Under no-load conditions, that is, when the output current is low, the VGS of the thirteenth transistor HMP3 is high, and the eleventh transistor HMP1 is off. At this point, the seventh resistor R7, the tenth transistor HMN1, the second resistor R2, and the ninth transistor MN3 form a path from the second power supply VIN to ground. The third pole is the primary pole, and the first pole is the secondary pole. Because the secondary pole is closer to the second pole and the second pole's frequency is lower, the static power consumption of the LDO circuit can be effectively reduced. In this case, the secondary pole and the second pole need to be placed outside the bandwidth to ensure loop stability.

[0070] Under no-load conditions, the value of the dominant pole is:

[0071] The value of the secondary dominant pole is:

[0072] The value of the second pole is:

[0073] It should be noted that Miller compensation is a commonly used frequency compensation method in the prior art. Its working principle is to shift the main pole toward low frequencies and the secondary pole toward high frequencies. Zero-point compensation is then performed based on the number of poles. Generally, zero-point compensation uses a resistor and capacitor in series to provide a zero point. This combination of two frequency compensations can stabilize the LDO system. However, this method is not suitable for a wide range of load capacitance variations. Existing frequency compensation schemes, such as pseudo-ESR compensation, create two poles within the bandwidth and compensate for one zero point using pseudo-ESR, which can stabilize the LDO system over a wide range. However, the bandwidth of this LDO is relatively small. An improvement is proposed here, namely, adding a buffer structure to the output of the first-stage op amp to increase the loop bandwidth. However, this structure reduces the gate input voltage range of the power tube, requiring a larger area to drive the same current, and also increases power consumption.

[0074] In summary, the problem of LDO stability over a wide load capacitance range, fast transient response, and low static power consumption cannot be achieved simultaneously requires compromise. The LDO circuit of this application, by combining frequency compensation and dynamic bias technology, enables the LDO to have high robustness, high dynamic characteristics, and low static power consumption over a wide load capacitance and load range. This avoids improving transient characteristics by increasing power consumption and adding a loop, simplifies the complexity of the design, reduces the area, and reduces production costs. This structure has a wide range of peripheral capacitor selectivity, strong driving capability, and a wide range of user applications.

[0075] The present application also discloses a power supply device, which adopts the above-mentioned wide load capacitance low voltage difference linear regulator circuit 10. By virtue of the high phase margin and stability design of the wide load capacitance low voltage difference linear regulator circuit 10 under a wide load capacitance range, the output voltage fluctuation can be effectively suppressed. At the same time, low static power consumption and fast transient response are achieved through dynamic bias technology, thereby enabling the power supply device to have wide load adaptability, high-precision voltage regulation performance and low power consumption advantages, and is suitable for electronic equipment scenarios with high requirements on power supply stability, power consumption and dynamic response.

[0076] This application also discloses an electronic device comprising the aforementioned power supply device. The electronic device employing the aforementioned power supply device can provide the electronic device with strong power adaptability, long battery life, excellent anti-interference performance, and high operational stability. The device is suitable for use in applications such as portable terminals and IoT devices that have strict requirements on power reliability and power consumption.

[0077] Since the processing and functions implemented by the power supply device and the electronic device in this embodiment basically correspond to the embodiments, principles and examples of the aforementioned wide load capacitance low voltage difference linear regulator circuit, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments and will not be repeated here.

[0078] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A wide load capacitance low voltage dropout linear regulator circuit, characterized in that: The device comprises a bias module, a first operational amplifier module, a second operational amplifier module, a third operational amplifier module, a first compensation module, and a second compensation module, wherein the first operational amplifier module is electrically connected to the bias module, the second operational amplifier module, and the first compensation module respectively, and the third operational amplifier module is electrically connected to the second operational amplifier module, the second compensation module, and the first operational amplifier module respectively; The bias module is used to receive a first reference current and a second reference current, and generate a bias current according to the first reference current and the second reference current; The first operational amplifier module is used to output a first voltage signal to the second operational amplifier module according to the bias current, feedback voltage and reference voltage, and generate a first pole at the common end of the first operational amplifier module and the second operational amplifier module; the second operational amplifier module is used to output a second voltage signal to the third operational amplifier module according to the first voltage signal, and generate a second pole at the common end of the second operational amplifier module and the third operational amplifier module; the third operational amplifier module is used to output a target voltage and the feedback voltage according to the second voltage signal; the first compensation module is used to generate a first zero point, and the first zero point is used to compensate for the second pole; the second compensation module is used to generate a second zero point, and the second zero point is used to compensate for the third pole generated at the common end of the second compensation module and the third operational amplifier module.

2. The wide load capacitance low voltage dropout linear regulator circuit according to claim 1, characterized in that: The bias module includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the drain of the first transistor and the first operational amplifier module, respectively, for receiving the first reference current, the source of the first transistor and the source of the second transistor are electrically connected to a first power supply, and the gate of the second transistor is electrically connected to the drain of the second transistor and the first operational amplifier module, respectively, for receiving the second reference current.

3. The wide load capacitance low voltage dropout linear regulator circuit according to claim 1, characterized in that: The first operational amplifier module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. The gate of the third transistor and the gate of the fourth transistor are both electrically connected to the bias module. The source of the third transistor is used to be electrically connected to the first power supply. The drain of the third transistor is electrically connected to the source of the fourth transistor. The gate of the fifth transistor is used to receive the reference voltage. The source of the fifth transistor is respectively electrically connected to the drain of the fourth transistor and the source of the sixth transistor. The drain of the fifth transistor is respectively electrically connected to the drain of the seventh transistor, the gate of the seventh transistor and the gate of the eighth transistor. The gate of the sixth transistor is used to receive the feedback voltage. The drain of the sixth transistor is respectively electrically connected to the drain of the eighth transistor, the first compensation module and the second operational amplifier module. The source of the seventh transistor and the source of the eighth transistor are both grounded.

4. The wide load capacitance low voltage dropout linear regulator circuit according to claim 1, characterized in that: The first compensation module includes a first resistor and a first capacitor, the first end of the first resistor is electrically connected to the first operational amplifier module and the second operational amplifier module respectively, the second end of the first resistor is electrically connected to the first end of the first capacitor, and the second end of the first capacitor is grounded.

5. The wide load capacitance low voltage dropout linear regulator circuit according to claim 1, characterized in that: The second operational amplifier module includes a ninth transistor, a tenth transistor, an eleventh transistor, a second resistor and a third resistor. The gate of the ninth transistor is electrically connected to the first operational amplifier module and the first compensation module, respectively. The drain of the ninth transistor is electrically connected to the second end of the second resistor. The source of the ninth transistor is grounded. The gate of the tenth transistor is used to receive a gate drive signal. The source of the tenth transistor is electrically connected to the first end of the second resistor. The drain of the tenth transistor is electrically connected to the gate of the eleventh transistor, the drain of the eleventh transistor and the third operational amplifier module, respectively. The first ends of the three resistors are used to be electrically connected to a second power supply. The second end of the third resistor is electrically connected to the source of the eleventh transistor.

6. The wide load capacitance low voltage dropout linear regulator circuit according to claim 1, characterized in that: The third operational amplifier module includes a twelfth transistor, a thirteenth transistor, a fourth resistor and a fifth resistor. The source of the twelfth transistor and the source of the thirteenth transistor are both used to be electrically connected to the second power supply, the gate of the twelfth transistor is electrically connected to the gate of the thirteenth transistor, the drain of the twelfth transistor is electrically connected to the second compensation module, the drain of the thirteenth transistor is electrically connected to the first end of the fourth resistor, the first end of the fifth resistor is electrically connected to the second end of the fourth resistor and the first operational amplifier module respectively, and the second end of the fifth resistor is grounded.

7. The wide load capacitance low voltage dropout linear regulator circuit according to claim 1, characterized in that: The second compensation module includes a sixth resistor and a load capacitor, the first end of the sixth resistor is electrically connected to the third operational amplifier module, the second end of the sixth resistor is electrically connected to the first end of the load capacitor and the third operational amplifier module respectively, and the second end of the load capacitor is grounded.

8. The wide load capacitance low voltage dropout linear regulator circuit according to any one of claims 1 to 7, characterized in that: The wide load capacitance low voltage difference linear regulator circuit further includes a seventh resistor, a first end of the seventh resistor being electrically connected to the second power supply, and a second end of the seventh resistor being electrically connected to the second operational amplifier module and the second compensation module respectively.

9. A power supply device, characterized in that: The invention comprises the wide load capacitance low voltage drop linear regulator circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Includes the power supply device according to claim 9.

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