Field sequential display pixel potential monitoring circuit and compensation method

Abstract

The invention discloses a field sequential display pixel potential monitoring compensation method, which comprises the following steps of: respectively applying a first square wave and a second square wave to a pre-storage capacitor and a pixel capacitor through a compensation signal and a pixel signal line, and collecting electric leakage data under different target gray scales; constructing an electric leakage index relationship based on the electric leakage data; acquiring the pixel voltage of the Nth frame; a first compensation amount is obtained based on the pixel voltage and the electric leakage index relation, so that the pre-stored voltage is preset pre-stored voltage in the (N + 1) th frame; obtaining a pre-stored voltage of the (N + 2) th frame and a pixel voltage of the (N + 1) th frame; obtaining a second compensation amount based on the electric leakage index relationship, the pre-stored voltage of the (N + 2) th frame and the pixel voltage of the (N + 1) th frame; and obtaining the compensation voltage of the Nth frame of the compensation circuit based on the first compensation amount and the second compensation amount. The beneficial effects of the invention are that the voltage writing size of the data signal is adjusted by monitoring the electric leakage condition of the voltage, so that electric leakage compensation is carried out, and the precise control of the voltage brightness and the picture uniformity are realized.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a field sequential display pixel potential monitoring circuit and compensation method. Background Art

[0002] Field-sequential or color-sequential display driver technology exploits the residual effect of human visual pauses to directly mix the RGB light sources to achieve full-color display. This eliminates the need for color filters, improving light source utilization while reducing power consumption. The backlight can only be activated after all screen data has been written and the liquid crystal deflection has reached a stable state. Otherwise, the image will be distorted, requiring a significant amount of time for the liquid crystal deflection to complete before the backlight is activated. This makes it difficult to achieve high brightness and high-frequency display over an average timeframe, while also increasing backlight brightness specifications and lifespan requirements, driving up costs.

[0003] When using the method of pre-storing the relevant signals of the next frame by means of in-pixel capacitance, a shorter lighting time is achieved by second-order programming through charge sharing. However, in high-PPI products such as VR glasses, 4K projectors, etc., the pre-stored voltage potential and the pixel voltage potential are inaccurate due to reasons such as small storage capacitance and device leakage. Whether it is the pre-stored voltage or the pixel voltage, in the off state, when the drain-source voltage at both ends of the transistor is large, due to leakage current, the low grayscale potential will leak to the high grayscale, and the high grayscale potential will leak to the low grayscale. Therefore, for the pixel voltages of the first and last rows of the row n pixel circuit, the same pixel voltage Vpixel after sharing in a sub-frame period, since Vpixel_0ms≠Vpixel_4ms, when the target voltage is Vpixel_0ms, the overall picture deviates from the target grayscale, making the low grayscale brighter and the high grayscale darker.

[0004] Furthermore, for the pre-stored voltages of the first and last rows of n rows of pixel circuits, if the same pre-stored voltage is written, the storage time for the first row is 4ms, while the storage time for the last row is assumed to be 0ms. When the next frame is shared, Vpre_0ms ≠ Vpre_4ms, resulting in different pixel voltages Vpixel after sharing the same target voltage. Due to this issue, high-PPI (Pixels Per Inch) product applications with intra-pixel capacitance require not only improved device off-state performance but also appropriate compensation methods to reduce deviations caused by leakage.

[0005] Therefore, the present invention proposes a field sequential display pixel potential monitoring circuit and compensation method to eliminate the influence of leakage, thereby avoiding the influence of abnormal image display. Summary of the Invention

[0006] The purpose of the present invention is to provide a field sequential display pixel potential monitoring circuit and compensation method, thereby eliminating the influence of leakage.

[0007] The purpose of the present invention is to realize a method for monitoring and compensating pixel potential of field sequential display through the following technical solutions, including: Based on the monitoring circuit, leakage data of the pre-storage capacitor and the pixel capacitor within a unit sub-frame time is collected at different target gray levels; Construct leakage index relationship based on leakage data; Obtaining a first target pixel voltage at a second time node in an Nth frame of the circuit to be compensated; Obtaining a first compensation amount based on the first target pixel voltage and the leakage index relationship to eliminate leakage effects of the pre-storage capacitor when the data signal voltage of the Nth frame is written into the display of the N+1th frame; Obtaining a pre-written pre-stored voltage at a first time node of the N+2th frame and a second target pixel voltage at a first time node of the N+1th frame of the circuit to be compensated; Obtaining a second compensation amount based on the leakage index relationship, the pre-written pre-stored voltage, and the second target pixel voltage to eliminate leakage effects of the pixel capacitor during the period from the display time of the N+1 frame to the writing of the data of the N+2 frame; Obtaining a compensation voltage of the circuit to be compensated in the Nth frame based on the first compensation amount and the second compensation amount; Performing voltage compensation on the nth row of circuits to be compensated based on the compensation voltage and the leakage time of the nth row of circuits to be compensated; The time interval between the first time node and the second time node is a unit subframe time of the circuit to be compensated; The first time node is the starting time 0ms of the unit subframe time, and the second time node is the ending time of the subframe time.

[0008] Furthermore, the expression for obtaining the first compensation amount is: ; in, V1 is the first compensation amount; Vpre_N+1 is the pre-stored voltage at the first time node in the N+1th frame or the pre-stored voltage at the second time node in the Nth frame; Vpixel_N is the first target pixel voltage at the second time node in the Nth frame; Vdata is the data signal voltage; when the Nth frame is a positive frame, Vdata=5V; when the Nth frame is a negative frame, Vdata=-5V.

[0009] Furthermore, the expression for obtaining the second compensation amount is: ; in, V2 is the second compensation amount; Vpre_N+2 is the pre-write and pre-storage voltage at the first time node in the N+2th frame; Vpixel_N+1 is the second target pixel voltage at the second time node in the N+1th frame.

[0010] Furthermore, the compensation voltage expression of the compensation circuit in the Nth frame obtained based on the first compensation amount and the second compensation amount is: ; Wherein, V is the compensation voltage; Based on the charge sharing principle, the relationship between the pixel voltage and the pre-stored voltage before and after sharing is obtained, that is, , for The inverse function of .

[0011] Furthermore, performing voltage compensation on the n-th row of circuits to be compensated based on the compensation voltage and the leakage time of the n-th row of circuits to be compensated includes: The leakage time t of the n-row pixel circuit in a sub-frame period is: ; Where N is the total number of sub-pixel rows, is the subframe period.

[0012] Furthermore, when the monitoring circuit collects different target grayscales, the leakage data of the pre-storage capacitor and the pixel capacitor within a unit sub-frame time includes: Input a first square wave and a second square wave to the input pre-storage capacitor and the pixel capacitor through the compensation signal line and the pixel signal line respectively; After the pre-storage capacitor and the pixel capacitor are pre-charged; the compensation signal line and the pixel signal line stop inputting the first square wave and the second square wave respectively, and the data signal line continues to input the data signal voltage corresponding to the target grayscale, and records the pixel voltage when it changes from the minimum grayscale corresponding voltage to the maximum grayscale corresponding voltage at the first time node, that is, when it changes from 0V to 5V, the voltage changes of the pre-storage capacitor and the pixel capacitor in unit subframe time under different pre-storage voltages, and obtains leakage data based on the changed pre-storage voltage and the corresponding pixel voltage.

[0013] Furthermore, the voltage range of the first square wave pulse is (-5V+Vcom, +5V+Vcom); the voltage range of the second square wave pulse is (-5V+Vcom, +5V+Vcom), and Vcom is a common voltage.

[0014] Furthermore, the method adopts a sub-frame column inversion driving mode and gives priority to compensating for potential deviations in low grayscale areas.

[0015] Furthermore, the monitoring circuit includes: a pre-storage unit and a driving unit; The pre-storage unit includes a first transistor and a pre-storage capacitor; The gate of the first transistor is coupled to the row gate signal line, the first source and drain of the first transistor are coupled to the data signal line, the second source and drain of the first transistor are coupled to one end of a pre-storage capacitor, one end of the pre-storage capacitor is also coupled to the compensation signal line; the other end of the pre-storage capacitor is coupled to the common signal line; The driving unit includes a second transistor, a pixel capacitor and a holding capacitor; The first source and drain of the second transistor are coupled to the second source and drain of the first transistor, the gate of the second transistor is coupled to the transfer signal line, the second source and drain of the second transistor are coupled to one end of the holding capacitor and one end of the pixel capacitor, the other ends of the holding capacitor and the pixel capacitor are coupled to the common signal line; the holding capacitor is also coupled to the pixel signal line.

[0016] Furthermore, the monitoring circuit also includes: a reset unit; the reset unit includes a third transistor, the first source and drain of the third transistor are coupled to the second source and drain of the second transistor, the gate of the third transistor is coupled to the reset signal line, and the second source and drain of the third transistor is coupled to the reference signal line.

[0017] Furthermore, the timing of the monitoring circuit is configured as follows: Leakage data acquisition stage: The row gate signal line jumps to a high level, turning on the first transistor; the data signal line inputs a preset voltage, and the compensation signal line inputs a first square wave to the pre-storage capacitor. The first square wave changes according to a preset step size, and the potential of the pre-stored voltage at the first time node and the second time node within the unit subframe time is obtained; The row gate signal line jumps to a low level, the first transistor is turned off, the transfer signal line jumps to a high level, and the second transistor is turned on; the compensation signal line inputs a first square wave of a fixed size, and the pixel signal line inputs a second square wave to the pixel capacitor. The second square wave changes according to a preset step size, and the potential of the pixel voltage at the second time node of the current frame and the first time node of the next frame are obtained; obtaining leakage data based on a pre-stored voltage and a pixel voltage; Obtaining a leakage index relationship based on leakage data; During the backlight on phase: The row gate signal line jumps to a high level, and the first transistor is turned on; the data signal line pre-writes a compensation voltage into the pre-storage capacitor through the first transistor; After the pre-writing is completed, the row gate signal line jumps to a low level and the first transistor is turned off; During the backlight off phase: The reset signal line jumps to a high level, and the third transistor is turned on; the reference signal line jumps to a common voltage, so that the pixel capacitor is reset through the third transistor; After the reset is completed, the level of the reference signal line jumps to a low level, and the third transistor is turned off; the transfer signal line jumps to a high level, the second transistor is turned on, and the pre-storage capacitor transfers the data signal voltage to the holding capacitor and the pixel capacitor through the second transistor.

[0018] The present invention has the following advantages: The present invention monitors the changes in the pre-stored voltage and the pixel voltage within the pixel to obtain a mapping relationship between the pixel voltage and the pre-stored voltage, i.e., a leakage index relationship constructed using leakage data. This method performs two compensations for the pixel circuit within the unit subframe time, i.e., the 0ms and last bit time of the subframe cycle, when V_0ms≠V_4ms due to transistor leakage. The first compensation is for the pre-stored voltage. Based on the leakage index relationship, it can be determined what Vpre_0ms is when Vpre_4ms is required to be the preset voltage in the case of leakage, i.e., what the input data signal voltage is at that time. This value is the first compensation amount, ensuring that the pre-stored voltage is at the preset voltage at the second time node of the sub-frame period, thereby ensuring that the pixel voltage transferred to the pixel capacitor is at the preset voltage. This eliminates the effect of leakage from the first transistor when the data signal voltage of the Nth frame is written to the display of the N+1th frame. The second compensation is to compensate for the pixel voltage. When writing the next frame, the pixel voltage leakage caused by the pre-stored voltage of the next frame written in the first row is compensated to eliminate the leakage effect caused by the second transistor of the pixel capacitor from the display time of the N+1 frame to the writing of the data of the N+2 frame. The total compensation voltage is obtained based on the two compensation amounts; at the same time, the entire panel is written from the first row to the last row within a cycle. The different writing time of each row leads to different leakage time of each row. According to the opening time of the row gate signal line of each row, which is also the writing time of the data signal voltage, leakage compensation is performed on each row in a partition, so that the pixel voltage of each row in a sub-frame cycle does not deviate, so that the overall picture will not deviate from the target grayscale, thereby realizing precise control of voltage brightness and picture uniformity, which is conducive to the industrialization of high PPI products. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A diagram showing the steps of the method of the present invention; Figure 2 Schematic diagram of pixel circuit leakage deviation; Figure 3 Schematic diagram of pixel voltage integration; Figure 4This is a graph showing the variation of the low grayscale compensation voltage of the present invention; Figure 5 A circuit diagram of the present invention; Figure 6 This is a timing diagram of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0021] It should be noted that the directions or positional relationships indicated by "left" and "right" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is typically placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. Such terms are intended only to facilitate the description of the present invention and simplify the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present invention. It should be noted that the embodiments of the present invention and the features and technical solutions in the embodiments can be combined with each other unless there is a conflict.

[0022] Example 1 like Figure 2 As shown, within a subframe period, the unit subframe time is 4ms. When there is device leakage, the pre-stored voltage of the first row pixel circuit and the pre-stored voltage of the last row pixel circuit in the entire panel are not equal, that is, Vpre_0ms≠Vpre_4ms; at this time, after charge sharing, the pixel voltage Vpixe in the pixel capacitor Clc of some rows cannot reach the expected target value; because the second transistor T2 also has leakage, when the shared Vpixel_0ms≠Vpixel_4ms, the panel display brightness also cannot reach the target value.

[0023] Therefore, we first obtain the leakage of the transistor in the circuit to be compensated, such as Figure 2 Leakage curve shown.

[0024] The pre-stored voltage Vpre is preset as a first voltage, and the first voltage steps from -5V to 5V with a step size of 2.5V; the data signal line Data inputs different potential voltages Vdata, Vdata is +5V or -5V, and the source-drain voltage of the second transistor T2 when the pixel voltage Vpixel changes is collected, and the leakage voltage of the second transistor is obtained based on the source-drain voltage, and the leakage voltage of the second transistor is obtained based on the leakage voltage change within the sub-frame period, such as Figure 2 The leakage curve shown in ; or The preset pixel voltage Vpixel is a second voltage, which steps from -5V to 5V with a step size of 2.5V. The data signal line Data continuously inputs the first data signal voltage Vdata, which is +5V or -5V, and collects the source-drain voltage of the first transistor T1 when the pre-stored voltage Vpre changes.

[0025] The linear relationship between the leakage voltage change ΔV and time t is: The leakage formula is: ΔV = k·t; Where k is the transistor leakage rate; Due to transistor leakage, the brightness decreases or becomes brighter during the leakage time, so the total brightness integral changes within the subframe period, making the overall brightness unexpected. Therefore, it is necessary to compensate for the brightness integral caused by leakage.

[0026] For this, see Figure 1 The present invention provides a method for monitoring and compensating pixel potentials in a field sequential display, the method comprising: S1, collecting leakage data of the pre-storage capacitor and the pixel capacitor within a unit sub-frame time at different target grayscales based on the monitoring circuit; S11. Apply a first square wave to the pre-storage capacitor Cst1 through the compensation signal line Pre to pre-charge the pre-storage capacitor Cst1. The voltage of the first square wave is 2.5V, and the voltage value range of the first square wave is (-5V+Vcom, +5V+Vcom). At the same time, apply a second square wave pulse to the pixel capacitor Clc through the pixel signal line Pixel to pre-charge the pixel capacitor Clc. The voltage of the second square wave is 5V, and the voltage value range of the second square wave is (-5V+Vcom, +5V+Vcom). Using the first square wave or the second square wave to pre-charge the capacitor can protect the device and improve the efficiency of subsequent voltage writing to the capacitor.

[0027] S12. After precharging is completed, the row gate signal line Scan jumps to a high level, and the first transistor T1 is turned on; the data signal line Data inputs a data signal voltage of 5V, and the compensation signal line Pre stops applying the first square wave to the pre-storage capacitor Cst1; the potentials of the pre-storage voltage at the first time node Vpre_0ms and the second time node Vpre_4ms of the sub-frame period are recorded; S13, the row gate signal line Scan jumps to a low level, the first transistor T1 is turned off, the transfer signal line Tran jumps to a high level, and the second transistor T2 is turned on; the compensation signal line Pre inputs a first square wave of a fixed size; the pixel signal line Pixel applies a second square wave to the pixel capacitor Clc; When the pixel voltage changes from the voltage corresponding to the minimum grayscale to the voltage corresponding to the maximum grayscale, that is, 0V to 5V, the voltage changes of the Nth frame pixel voltage Vpixel_N, the N+1th frame pixel voltage Vpixel_N+1_0ms and the Nth frame pre-stored voltage Vpre_N within the unit sub-frame time under different pre-stored voltages are recorded, and leakage data is obtained based on the potential of the changed pre-stored voltage Vpre and the pixel voltage Vpixel.

[0028] S2. Construct a leakage index relationship based on the leakage data.

[0029] S3, obtaining a first target pixel voltage Vpixel_N at a second time node in the Nth frame of the circuit to be compensated; S4. A first compensation amount V1 is obtained based on the relationship between the first target pixel voltage Vpixel_N and the leakage index to eliminate the leakage effect of the pre-storage capacitor Cst1 when the data signal voltage of the Nth frame is written to the display of the N+1th frame; so that after the unit sub-frame time, the pre-storage voltage has the same first time node potential and second time node potential, that is, Vpre_N+1_t1=Vpre_N_t2, that is, Vpre_N+1_0ms=Vpre_N_4ms=expected Vpre.

[0030] The expression for obtaining the first compensation amount is: ; in, V1 is the first compensation amount; Vpre_N+1 is the pre-stored voltage at the first time node in the N+1th frame or the pre-stored voltage at the second time node in the Nth frame; Vpixel_N is the first target pixel voltage at the second time node in the Nth frame; Vdata is the data signal voltage; when the Nth frame is a positive frame, Vdata=5V; when the Nth frame is a negative frame, Vdata=-5V.

[0031] The first compensation amount is the compensation for the pre-stored voltage Vpre. According to the pixel voltage Vpixel_N of the current frame, that is, the Nth frame, the data of the middle, high and low grayscales corresponding to the leakage index relationship Vpixel_N are queried, so as to achieve voltage consistency of the same grayscale Vpixel_N+1 in the next frame at 0ms.

[0032] S5, obtaining a pre-written pre-stored voltage Vpre_N+2 at the first time node of the N+2th frame and a second target pixel voltage Vpixel_N+1 at the first time node of the N+1th frame of the circuit to be compensated; S6. Obtain a second compensation amount V2 based on the leakage index relationship, the pre-write pre-storage voltage Vpre_N+2, and the second target pixel voltage Vpixel_N+1; The expression for obtaining the second compensation amount is: ; Where, V2 is the second compensation amount; Vpre_N+2 is the pre-write pre-storage voltage at the first time node within the (N + 2)-th frame; Vpixel_N+1 is the second target pixel voltage at the second time node within the (N + 1)-th frame; The second compensation amount V2 is the compensation for the pixel voltage Vpixel to eliminate the leakage effect of the pixel capacitance from the display time of the (N + 1)-th frame to the data writing time of the (N + 2)-th frame. At this time, for the entire panel pixel circuit, monitoring from the first row to the last row, compensating for the leakage amount of Vpixel_N+1 caused by the pre-stored signal Vpre_N+2 of the next frame written to the first row.

[0033] For the second compensation amount V2, select an equivalent display voltage, and use the average voltage of Vpixel_0ms and Vpixel_4ms as the equivalent display voltage. Using Vpixel_4ms as the reference, as Figure 3 described, for the voltage change situation without leakage as shown by the yellow line V1, V1_0ms = V1_4ms; when there is transistor leakage as shown by the black line V2, for the input voltage and the voltage without leakage, after the unit sub-frame time, V2_0ms ≠ V2_4ms and V2_4ms < V1_4ms; to solve this problem, change the magnitude of the input data signal voltage so that the voltage integrals of Vpixel_0ms and Vpixel_4ms in the case of leakage are equal to those without leakage; That is: .

[0034] Of course, we can also choose the brightness integral as the reference. For compensating the brightness integral, the second compensation amount corresponds to the time integral of the brightness value between the first time node t1 and the second time node t2; ; Where, L is the brightness integral; C is the brightness value without leakage; Q(t) is the relationship between the leakage brightness and time obtained after voltage and brightness integration in the case of leakage; specifically, leakage makes Vpixel_0ms and Vpixel_4ms unequal, and it is the relationship between the brightness and time in the case of leakage obtained after converting the equivalent voltage and brightness of Vpixel_0ms and Vpixel_4ms.

[0035] S7, obtaining a compensation voltage of the compensation circuit in the Nth frame based on the first compensation amount V1 and the second compensation amount V2. The compensation voltage V can be obtained by the compensation voltage V, and the compensation voltage V expression is: ; Wherein, V is the compensation voltage, which is the data signal voltage Vdata written into the data signal line Data; F3(x) is the implicit relationship between the pixel voltage Vpixel and the pre-stored voltage Vpre before and after sharing based on the charge sharing principle, that is: .

[0036] Because the second compensation amount V2 is directly compensated for the pixel voltage Vpixel, it is necessary to calculate the voltage that needs to be compensated for the corresponding pre-stored voltage Vpre in the relationship F3(x) of the charge sharing of the second compensation amount V2, that is, The two compensation amounts are written directly by adjusting the data signal voltage Vdata, and both are written into the pre-stored voltage Vpre.

[0037] The compensation voltage V can also be obtained by using the leakage index relationship and searching for a close voltage according to the conditions of the pixel voltage Vpixel and the pre-stored voltage Vpre.

[0038] S8. Perform voltage compensation on the nth row of circuits to be compensated based on the compensation voltage and the leakage time of the nth row of circuits to be compensated: The leakage time t of the circuit to be compensated in the nth row within the sub-frame period: ; Where N is the total number of rows, is the subframe period, It is the inverse of the refresh rate.

[0039] When writing to multiple rows of pixel circuits, the time difference between the first row and the last row is one sub-frame period. The earlier the row is written, the longer the leakage time. However, for the row where the pre-stored voltage Vpre_N+2 of the N+2 frame is not written, the pre-stored voltage Vpre=pixel voltage Vpixel at this time, so the leakage is negligible, resulting in uneven brightness of the upper and lower displays of the panel. Therefore, the leakage time t is calculated for each row, and the compensation voltage is adjusted according to the leakage time t to make the voltage within the surface uniform.

[0040] Furthermore, compensating for dark areas in displays is an industry concern, such as Figure 4 As shown in the figure, this figure shows low grayscale compensation. The method adopts the sub-frame column inversion driving mode and gives priority to compensating the potential deviation of the low grayscale area. After the second compensation, it can be seen that the data signal line Data can effectively compensate for the brightness within the leakage time t after inputting the second compensation amount.

[0041] The present invention monitors the changes in the pre-stored voltage Vpre and the pixel voltage Vpixel in the pixel to obtain the leakage condition of the pixel circuit; based on the leakage data, a mapping relationship between the pre-stored voltage Vpre and the pixel voltage Vpixel is obtained, and the pixel voltage Vpixel of each row of pixel circuits is compensated, so that the pixel voltage of each row within a sub-frame period does not deviate, so that the overall picture does not deviate from the target grayscale. Example

[0042] like Figure 5 As shown, the present invention also provides a field sequential display pixel potential monitoring circuit, which is suitable for the compensation method.

[0043] The monitoring circuit includes: a pre-storage unit, a driving unit and a reset unit; The pre-storage unit includes a first transistor T1 and a pre-storage capacitor Cst1; The gate of the first transistor T1 is coupled to the row gate signal line Scan, the first source and drain of the first transistor T1 are coupled to the data signal line Data, the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1, one end of the pre-storage capacitor Cst1 is also coupled to the compensation signal line Pre; the other end of the pre-storage capacitor Cs1 is coupled to the common signal line Com; The driving unit includes a second transistor T2, a pixel capacitor Clc and a holding capacitor Cst2; A first source and drain of the second transistor T2 is coupled to the second source and drain of the first transistor T1, a gate of the second transistor T2 is coupled to the transfer signal line Tran, a second source and drain of the second transistor T2 is coupled to one end of a holding capacitor Cst2 and one end of a pixel capacitor Clc, the other ends of the holding capacitor Cst2 and the pixel capacitor Clc are coupled to a common signal line Com; the holding capacitor Cst2 is also coupled to a pixel signal line Pixel; The reset unit includes a third transistor T3 , a first source and drain of the third transistor T3 coupled to the second source and drain of the second transistor T2 , a gate of the third transistor T3 coupled to the reset signal line Reset, and a second source and drain of the third transistor T3 coupled to the reference signal line Vref.

[0044] like Figure 6 As shown, the timing of the circuit is configured as follows: Leakage data acquisition stage: The row gate signal line Scan jumps to a high level, turning on the first transistor T1; the data signal line Data inputs a preset voltage, and the compensation signal line Pre inputs a first square wave to the pre-storage capacitor Cst1. The first square wave changes according to a preset step size, and the potential of the pre-stored voltage at the first time node and the second time node of the subframe period is obtained; The row gate signal line Scan jumps to a low level, the first transistor T1 is turned off, the transfer signal line Tran jumps to a high level, and the second transistor T2 is turned on; the compensation signal line Pre inputs a first square wave of a fixed magnitude, and the pixel signal line Pixel inputs a second square wave to the pixel capacitor Clc. The second square wave changes according to a preset step of 2.5V, and the potential of the pixel voltage at the second time node of the sub-frame period and the first time node of the next sub-frame period are obtained; obtaining leakage data based on a potential of a pre-stored voltage and a pixel voltage; Obtaining a leakage index relationship based on leakage data; In the backlight-on phase of frame N: The row gate signal line Scan jumps to a high level, and the first transistor T1 is turned on; Obtain a first compensation amount based on a relationship between a target grayscale and a leakage index, and obtain a second compensation amount based on the leakage index relationship and the first compensation amount; The data signal line Data pre-writes the second compensation value into the pre-storage capacitor Cst1 through the first transistor T1; After the pre-writing is completed, the row gate signal line Scan jumps to a low level, and the first transistor T1 is turned off; In the backlight off phase of frame N: The reset signal line Reset jumps to a high level, and the third transistor T3 is turned on; the reference signal line Vref jumps to a common voltage Vcom, so that the pixel capacitor Clc is reset through the third transistor T3; After the reset is completed, the level of the reference signal line Vref jumps to a low level, and the third transistor T3 is turned off; the transfer signal line Tran jumps to a high level, the second transistor T2 is turned on, and the pre-storage capacitor Cst1 transfers the data signal voltage to the holding capacitor Cst2 and the pixel capacitor Clc through the second transistor T2.

[0045] The first compensation amount and the second compensation amount are obtained according to the obtained leakage number index relationship, so that the total brightness integral of the pixel voltage Vpixel in the sub-frame period is not affected by the transistor leakage; thereby, the change of the source-drain voltage in the circuit to be compensated is obtained through the monitoring circuit, and then compensation is performed to achieve precise control of voltage brightness and ensure picture uniformity.

[0046] The above embodiments merely represent preferred implementations, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art will be able to make various modifications and improvements without departing from the present invention, and these modifications and improvements are all within the scope of protection of the present invention.

Claims

1. A method for monitoring and compensating pixel potential in a field sequential display, characterized by: include: Based on the monitoring circuit, leakage data of the pre-storage capacitor and the pixel capacitor within a unit sub-frame time is collected at different target gray levels; Construct leakage index relationship based on leakage data; Obtaining a first target pixel voltage at a second time node of the Nth frame of the circuit to be compensated; Obtaining a first compensation amount based on the first target pixel voltage and the leakage index relationship to eliminate leakage effects of the pre-storage capacitor when the data signal voltage of the Nth frame is written into the display of the N+1th frame; Obtaining a pre-written pre-stored voltage at a first time node of the N+2th frame and a second target pixel voltage at a first time node of the N+1th frame of the circuit to be compensated; Obtaining a second compensation amount based on the leakage index relationship, the pre-written pre-stored voltage, and the second target pixel voltage to eliminate leakage effects of the pixel capacitor during the period from the display time of the N+1 frame to the writing of the data of the N+2 frame; Obtaining a compensation voltage of the circuit to be compensated in the Nth frame based on the first compensation amount and the second compensation amount; Performing voltage compensation on the nth row of circuits to be compensated based on the compensation voltage and the leakage time of the nth row of circuits to be compensated; The time interval between the first time node and the second time node is a unit subframe time of the circuit to be compensated.

2. The method for monitoring and compensating pixel potential in field sequential display according to claim 1, wherein: The expression for obtaining the first compensation amount is: ； in, V1 is the first compensation amount; Vpre_N+1 is the pre-stored voltage of the first time node in the N+1th frame; Vpixel_N is the first target pixel voltage at the second time node in the Nth frame; Vdata is the data signal voltage.

3. The method for monitoring and compensating pixel potential in field sequential display according to claim 2, wherein: The expression for obtaining the second compensation amount is: ； in, V2 is the second compensation amount; Vpre_N+2 is the pre-write and pre-storage voltage at the first time node in the N+2th frame; Vpixel_N+1 is the second target pixel voltage at the second time node in the N+1th frame.

4. The method for monitoring and compensating pixel potential in field sequential display according to claim 3, wherein: The expression for obtaining the compensation voltage of the compensation circuit in the Nth frame based on the first compensation amount and the second compensation amount is: ; in, V is the compensation voltage; F3 is the relationship between the pixel voltage before and after sharing and the pre-stored voltage based on the charge sharing principle, that is, .

5. The method for monitoring and compensating pixel potential in field sequential display according to claim 1, wherein: The performing voltage compensation on the n-th row of circuits to be compensated based on the compensation voltage and the leakage time of the n-th row of circuits to be compensated comprises: The leakage time t of the pixel circuit in the nth row is: ； in, N is the total number of rows, is the subframe period.

6. The method for monitoring and compensating pixel potential in field sequential display according to claim 1, wherein: When collecting different target grayscales based on the monitoring circuit, the leakage data of the pre-storage capacitor and the pixel capacitor within a unit sub-frame time includes: Inputting a first square wave and a second square wave to the input pre-storage capacitor (Cst1) and the pixel capacitor (Clc) through the compensation signal line (Pre) and the pixel signal line (Pixel) respectively; After the pre-storage capacitor (Cst1) and the pixel capacitor (Clc) are pre-charged, the compensation signal line (Pre) and the pixel signal line (Pixel) stop inputting the first square wave and the second square wave respectively, and the data signal line (Data) continues to input the data signal voltage corresponding to the target grayscale. When the pixel voltage changes from the minimum grayscale corresponding voltage to the maximum grayscale corresponding voltage at the first time node, the voltage changes of the pre-storage capacitor and the pixel capacitor in the unit sub-frame time under different pre-storage voltages are recorded, and leakage data is obtained based on the changed pre-storage voltage and the corresponding pixel voltage.

7. The method for monitoring and compensating pixel potential in field sequential display according to claim 6, wherein: The voltage range of the first square wave is (-5V+Vcom, +5V+Vcom); the voltage range of the second square wave is (-5V+Vcom, +5V+Vcom), and Vcom is a common voltage.

8. A field sequential display pixel potential monitoring circuit, characterized in that: include: Pre-storage unit and drive unit; The pre-storage unit includes a first transistor (T1) and a pre-storage capacitor (Cst1); The gate of the first transistor (T1) is coupled to a row gate signal line (Scan), the first source and drain of the first transistor (T1) are coupled to a data signal line (Data), the second source and drain of the first transistor (T1) are coupled to one end of a pre-storage capacitor (Cs1), one end of the pre-storage capacitor (Cst1) is also coupled to a compensation signal line (Pre); the other end of the pre-storage capacitor (Cs1) is coupled to a common signal line (Com); The driving unit includes a second transistor (T2), a pixel capacitor (Clc) and a holding capacitor (Cst2); The first source and drain of the second transistor (T2) are coupled to the second source and drain of the first transistor (T1), the gate of the second transistor (T2) is coupled to the transfer signal line (Tran), the second source and drain of the second transistor (T2) are coupled to one end of a holding capacitor (Cst2) and one end of a pixel capacitor (Clc), the other ends of the holding capacitor (Cs2) and the pixel capacitor (Clc) are coupled to a common signal line (Com); the holding capacitor (Cst2) is also coupled to a pixel signal line (Pixel).

9. The field sequential display pixel potential monitoring circuit according to claim 8, further comprising: Reset unit; The reset unit includes a third transistor (T3), a first source and drain of the third transistor (T3) is coupled to the second source and drain of the second transistor (T2), a gate of the third transistor (T3) is coupled to a reset signal line (Reset), and a second source and drain of the third transistor (T3) is coupled to a reference signal line (Vref).

10. The field sequential display pixel potential monitoring circuit according to claim 9, characterized in that: The timing of the monitoring circuit is configured as follows: Leakage data acquisition stage: The row gate signal line (Scan) jumps to a high level, and the first transistor (T1) is turned on; the data signal line (Data) inputs a preset voltage, and the compensation signal line (Pre) inputs a first square wave to the pre-storage capacitor (Cst1), the first square wave changes according to a preset step size, and the potential of the pre-stored voltage at the first time node and the second time node of the subframe period is obtained; The row gate signal line (Scan) jumps to a low level, the first transistor (T1) is turned off, the transfer signal line (Tran) jumps to a high level, and the second transistor (T2) is turned on; the compensation signal line (Pre) inputs a first square wave of a fixed size, and the pixel signal line (Pixel) inputs a second square wave to the pixel capacitor (Clc), the second square wave changes according to a preset step size, and the potential of the pixel voltage at the second time node of the sub-frame period and the first time node of the next sub-frame period is obtained; obtaining leakage data based on a pre-stored voltage and a pixel voltage; Obtaining a leakage index relationship based on leakage data; During the backlight on phase: The row gate signal line (Scan) jumps to a high level, and the first transistor (T1) is turned on; Obtain a first compensation amount based on a relationship between a target grayscale and a leakage index, and obtain a second compensation amount based on the leakage index relationship and the first compensation amount; The data signal line (Data) pre-writes a second compensation value into the pre-storage capacitor (Cst1) through the first transistor (T1); After the pre-writing is completed, the row gate signal line (Scan) jumps to a low level, and the first transistor (T1) is turned off; During the backlight off phase: The reset signal line (Reset) jumps to a high level, and the third transistor (T3) is turned on; the reference signal line (Vref) jumps to a common voltage, so that the pixel capacitor (Clc) is reset through the third transistor (T3); After the reset is completed, the level of the reference signal line (Vref) jumps to a low level, and the third transistor (T3) is turned off; the transfer signal line (Tran) jumps to a high level, and the second transistor (T2) is turned on, and the pre-storage capacitor (Cst1) transfers the data signal voltage to the holding capacitor (Cst2) and the pixel capacitor (Clc) through the second transistor (T2).

Images