High-speed channel signal integrity chip evaluation method and system

Abstract

The invention discloses a high-speed channel signal integrity chip evaluation method and system, and the method comprises the steps: generating an excitation signal containing a plurality of frequency components and different amplitudes, and enabling the excitation signal to be used for simulating a complex signal scene in actual high-speed communication; inputting the excitation signal to a transmitting end of a to-be-evaluated signal integrity chip, and obtaining an actual transmitting signal output by the transmitting end of the chip; the actual transmitting signal is analyzed, characteristic parameters of the transmitting signal are obtained, and the characteristic parameters comprise overshoot, undershoot, rise time and fall time of the signal and spectrum distribution of the signal; the transmission process of the signal in different transmission environments is simulated through the transmission line model, the actual transmitting signal is input into the transmission line model to obtain the signal after simulation transmission, and the complex signal scene in actual high-speed communication can be simulated more truly by generating the excitation signal containing multiple frequency components and different amplitudes, so that the signal transmission efficiency is improved. Therefore, the signal integrity chip can be evaluated more comprehensively and accurately.

Description

Technical Field

[0001] The present invention relates to the technical field of chip evaluation, and in particular to a high-speed channel signal integrity chip evaluation method and system. Background Art

[0002] With the rapid development of information technology, high-speed communications have been widely used in various fields, such as data centers, 5G communications, and high-performance computing. In high-speed communication systems, signal integrity is crucial to ensure accurate and rapid data transmission. Signal integrity issues can lead to signal distortion, increased bit error rates, and even system failures.

[0003] Signal integrity chips are key components in high-speed communication systems, and their performance directly impacts the signal transmission quality of the entire system. Therefore, accurate and comprehensive evaluation of high-speed channel signal integrity chips is crucial. However, existing chip evaluation methods often fail to fully simulate the complex signal scenarios encountered in actual high-speed communications, resulting in inaccurate evaluation results and a lack of reliable evidence for chip design optimization and performance improvement.

[0004] In order to meet the growing demand for high-speed communications and improve the performance and reliability of signal integrity chips, it is necessary to develop a more complete and accurate high-speed channel signal integrity chip evaluation method and system. Summary of the Invention

[0005] The present invention aims to provide a high-speed channel signal integrity chip evaluation method and system. By generating excitation signals containing multiple frequency components and varying amplitudes, the system can more realistically simulate the complex signal scenarios encountered in actual high-speed communications, thereby enabling a more comprehensive and accurate evaluation of the signal integrity chip. The system utilizes a fast Fourier transform algorithm to perform spectrum analysis on the transmitted signal, constructs a transmission line model based on transmission line theory, and adjusts parameters based on the actual environment, thereby improving the accuracy and reliability of the evaluation. The system uses a pseudo-random binary sequence to calculate the bit error rate, and acquires signals using a high-speed oscilloscope and high-precision data acquisition equipment, ensuring the accuracy and validity of the test data. The modules in the evaluation system have clear divisions of labor and work collaboratively, enabling efficient evaluation of high-speed channel signal integrity chips. The system also presents the results in a visual manner through a data analysis and display module, facilitating user understanding and use.

[0006] A high-speed channel signal integrity chip evaluation method includes a stimulus signal generation step: generating a stimulus signal containing multiple frequency components and varying amplitudes. This stimulus signal is used to simulate the complex signal scenarios encountered in actual high-speed communications. In actual high-speed communications, signals often contain a wide range of frequency components and varying amplitudes. Generating such a stimulus signal can more realistically simulate the various conditions encountered during signal transmission.

[0007] Transmitter testing steps: Input the stimulus signal to the transmitter of the signal integrity chip to be evaluated and obtain the actual transmit signal output by the chip transmitter. Analyze the actual transmit signal to obtain characteristic parameters of the transmit signal, including overshoot, undershoot, rise time, fall time, and spectral distribution. By analyzing the characteristic parameters of the transmit signal, we can understand the chip transmitter's processing capability for the stimulus signal and the signal quality.

[0008] Transmission line simulation: A transmission line model is used to simulate the signal transmission process under different transmission environments. The actual transmitted signal is input into the transmission line model to obtain the simulated transmission signal. The transmission line model is constructed based on transmission line theory and takes into account the resistance, inductance, capacitance, and conductance parameters of the transmission line. These parameters can be adjusted according to the actual transmission environment to simulate different transmission losses and signal distortion conditions. The actual signal transmission environment is complex and changeable, and the transmission line model can accurately simulate these conditions, providing a more realistic signal for subsequent evaluation of the chip's receiving end performance.

[0009] Receiver testing steps: Input the simulated transmitted signal into the signal integrity chip's receiver and obtain the actual received signal output by the chip. This signal is then compared with the original stimulus signal, and receiver evaluation parameters such as the bit error rate and distortion are calculated. These parameters directly reflect the chip's ability to recover from the transmitted signal and the signal quality.

[0010] A further improvement involves spectrum analysis of the transmitted signal: During the step of analyzing the actual transmitted signal, a fast Fourier transform (FFT) algorithm is used to perform spectrum analysis on the actual transmitted signal to determine the amplitude and phase information of each frequency component in the signal, thereby obtaining the signal's spectral distribution. The FFT algorithm is an efficient spectrum analysis method that can quickly and accurately convert time-domain signals into frequency-domain signals, providing a powerful tool for analyzing the frequency characteristics of transmitted signals.

[0011] Transmission Line Model Construction: This transmission line model is based on transmission line theory, taking into account the resistance, inductance, capacitance, and conductance of the transmission line. These parameters can be adjusted based on the actual transmission environment to simulate different transmission losses and signal distortion conditions. By properly setting the transmission line model parameters, the signal transmission process in different transmission environments can be accurately simulated, improving the accuracy of the assessment.

[0012] BER calculation method: When calculating the BER of a signal, a pseudo-random binary sequence is used as the stimulus signal. By comparing the signal sequence recovered at the receiver with the original pseudo-random binary sequence, the number of bit errors is counted and the BER is calculated. Pseudo-random binary sequences have good randomness and periodicity, effectively simulating data signals used in actual communications. By comparing the received and original sequences, the BER can be accurately calculated.

[0013] Signal acquisition equipment: High-speed oscilloscopes and high-precision data acquisition equipment are used to acquire the actual transmitted signal from the chip's transmitter and the actual received signal from the chip's receiver, ensuring the acquired signals have high resolution and accuracy. High-speed oscilloscopes and high-precision data acquisition equipment can accurately capture the details of high-speed signals, providing reliable data support for subsequent signal analysis.

[0014] A high-speed channel signal integrity chip evaluation system includes a stimulus signal generation module, which generates stimulus signals containing multiple frequency components and varying amplitudes. This module includes a direct digital frequency synthesizer (DDS) and a signal amplitude modulator (AM), enabling precise control of the frequency and amplitude of the stimulus signal. The DDS rapidly generates high-precision frequency signals, while the AM precisely adjusts the signal amplitude to produce the desired stimulus signal.

[0015] Transmitter Test Module: Connected to the stimulus signal generation module, it is used to input the stimulus signal into the transmitter of the signal integrity chip to be evaluated, obtain the actual transmission signal output by the chip transmitter, and analyze the actual transmission signal to obtain the characteristic parameters of the transmission signal. This module includes a high-speed oscilloscope, a signal amplifier, and a signal analysis processor. The high-speed oscilloscope is used to collect the actual transmission signal, the signal amplifier is used to amplify the collected signal, and the signal analysis processor is used to analyze the characteristic parameters of the amplified signal. The high-speed oscilloscope can accurately collect high-speed transmission signals, the signal amplifier can enhance the signal strength to facilitate subsequent analysis, and the signal analysis processor can quickly and accurately extract the characteristic parameters of the transmission signal.

[0016] Transmission Line Simulation Module: Connected to the transmitter test module, this module simulates signal transmission under various transmission environments based on a transmission line model. The actual transmission signal obtained by the transmitter test module is input into this module to generate the simulated transmission signal. This module uses a field programmable gate array (FPGA) to implement the transmission line model algorithm, enabling rapid simulation of signal transmission under various transmission environments. The FPGA's high flexibility and fast computation speed allow for rapid adjustment of transmission line model parameters to suit different transmission environments, enabling efficient signal transmission simulation.

[0017] The receiving-end test module, connected to the transmission line simulation module, is used to input the simulated transmitted signal into the signal integrity chip's receiving end, obtain the actual received signal output by the chip's receiving end, compare the actual received signal with the original stimulus signal, and calculate receiver evaluation parameters such as the signal's bit error rate and distortion. This module includes a bit error rate tester, a signal comparator, and a distortion analyzer. The bit error rate tester calculates the signal's bit error rate, the signal comparator compares the actual received signal with the original stimulus signal, and the distortion analyzer calculates the signal's distortion. These devices accurately test and analyze the receiving-end signal, providing critical data for evaluating the chip's receiving-end performance.

[0018] The Data Analysis and Display Module, connected to the transmitter and receiver test modules, comprehensively analyzes the characteristic parameters of the transmitted signal and the receiver evaluation parameters, and visually displays the evaluation results. This comprehensive analysis of transmitter and receiver parameters allows for a comprehensive assessment of the chip's signal integrity performance, while the visual display facilitates an intuitive understanding of the evaluation results.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] By generating excitation signals containing multiple frequency components and different amplitudes, the present invention can more realistically simulate complex signal scenarios in actual high-speed communications, thereby performing a more comprehensive and accurate evaluation of signal integrity chips.

[0021] The fast Fourier transform algorithm is used to perform spectrum analysis on the transmitted signal, and a transmission line model is constructed based on transmission line theory, and parameters can be adjusted according to the actual environment, which improves the accuracy and reliability of the evaluation.

[0022] The use of pseudo-random binary sequences to calculate the bit error rate and the use of high-speed oscilloscopes and high-precision data acquisition equipment to acquire signals ensure the accuracy and effectiveness of the test data.

[0023] The modules in the evaluation system have clear divisions of labor and work together to efficiently complete the evaluation of high-speed channel signal integrity chips. The data analysis and display modules visualize the results for easy understanding and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the system block diagram of the patent of this invention. DETAILED DESCRIPTION

[0025] In order to make the technical means, creative features, objectives and effects achieved by the present invention easier to understand, the present invention is further described below in conjunction with specific implementation methods.

[0026] A high-speed channel signal integrity chip evaluation method includes: generating an excitation signal containing multiple frequency components and different amplitudes, wherein the excitation signal is used to simulate a complex signal scenario in actual high-speed communication;

[0027] Input the excitation signal to the transmitter of the signal integrity chip to be evaluated, and obtain the actual transmission signal output by the chip transmitter;

[0028] Analyze the actual transmission signal to obtain characteristic parameters of the transmission signal, wherein the characteristic parameters include overshoot, undershoot, rise time, fall time and spectrum distribution of the signal;

[0029] Simulating the transmission process of a signal under different transmission environments through a transmission line model, inputting the actual transmitted signal into the transmission line model to obtain a signal after simulated transmission;

[0030] Input the simulated transmitted signal to the receiving end of the signal integrity chip, and obtain the actual received signal output by the chip receiving end;

[0031] The actual received signal is compared with the original excitation signal, and receiving end evaluation parameters such as the signal bit error rate and the signal distortion degree are calculated.

[0032] Wherein, in the step of analyzing the actual transmitted signal, a fast Fourier transform algorithm is used to perform spectrum analysis on the actual transmitted signal to determine the amplitude and phase information of each frequency component in the signal, thereby obtaining the spectrum distribution of the signal.

[0033] The transmission line model is constructed based on transmission line theory, taking into account the resistance, inductance, capacitance and conductance parameters of the transmission line, and can adjust these parameters according to the actual transmission environment to simulate different transmission losses and signal distortion conditions.

[0034] When calculating the bit error rate of a signal, a pseudo-random binary sequence is used as an excitation signal. By comparing the signal sequence recovered by the receiving end with the original pseudo-random binary sequence, the number of bit errors is counted, and then the bit error rate is calculated.

[0035] Among them, when obtaining the actual transmission signal output by the chip transmitter and the actual reception signal output by the chip receiver, a high-speed oscilloscope and high-precision data acquisition equipment are used to ensure that the collected signals have high resolution and accuracy.

[0036] A high-speed channel signal integrity chip evaluation system includes: an excitation signal generation module for generating an excitation signal containing multiple frequency components and different amplitudes;

[0037] A transmitter testing module, connected to the stimulus signal generating module, configured to input a stimulus signal into the transmitter of the signal integrity chip to be evaluated, obtain an actual transmission signal output by the chip transmitter, and analyze the actual transmission signal to obtain characteristic parameters of the transmission signal;

[0038] A transmission line simulation module is connected to the transmitter test module, and simulates the transmission process of the signal under different transmission environments based on the transmission line model. The actual transmission signal obtained by the transmitter test module is input into the module to obtain the signal after simulated transmission;

[0039] A receiving end test module, connected to the transmission line simulation module, is used to input the simulated transmitted signal into the receiving end of the signal integrity chip, obtain the actual received signal output by the chip receiving end, compare the actual received signal with the original stimulus signal, and calculate the signal bit error rate, signal distortion degree and other receiving end evaluation parameters;

[0040] The data analysis and display module is connected to the transmitting end test module and the receiving end test module, and is used to comprehensively analyze the characteristic parameters of the transmitting signal and the receiving end evaluation parameters, and to display the evaluation results in a visual manner.

[0041] The excitation signal generation module includes a direct digital frequency synthesizer and a signal amplitude modulator, which can accurately control the frequency and amplitude of the excitation signal.

[0042] Among them, the transmitting end test module includes a high-speed oscilloscope, a signal amplifier and a signal analysis processor. The high-speed oscilloscope is used to collect the actual transmission signal, the signal amplifier is used to amplify the collected signal, and the signal analysis processor is used to analyze the characteristic parameters of the amplified signal.

[0043] The transmission line simulation module uses a field programmable gate array to implement the algorithm of the transmission line model, which can quickly simulate the transmission process of signals under different transmission environments.

[0044] Among them, the receiving end test module includes a bit error rate tester, a signal comparator and a distortion analyzer. The bit error rate tester is used to calculate the bit error rate of the signal, the signal comparator is used to compare the actual received signal with the original excitation signal, and the distortion analyzer is used to calculate the distortion degree of the signal.

[0045] Stimulus signal generation: A direct digital synthesizer (DDS) is used to generate an initial frequency signal. The DDS's frequency control word is programmed to output a signal containing multiple frequency components, such as those ranging from 1 GHz to 10 GHz. These frequency signals are then amplitude modulated using a signal amplitude modulator to achieve varying amplitudes. For example, the amplitude range can be set from 0.5 V to 2 V to simulate the amplitude variations experienced in actual high-speed communications. This generates a stimulus signal that simulates the complex signal scenarios found in real-world high-speed communications.

[0046] Transmitter Testing: The generated stimulus signal is appropriately amplified by a signal amplifier and then input to the transmitter of the signal integrity chip to be evaluated. A high-speed oscilloscope is connected to the chip's transmitter output pin to capture the actual transmit signal. The oscilloscope's sampling rate is set to a sufficiently high level, such as 50GSa / s, to accurately capture signal details. The captured signal is then transmitted to a signal analysis processor, which uses a fast Fourier transform algorithm to perform spectral analysis on the actual transmit signal. This spectral analysis determines the amplitude and phase of each frequency component in the signal, thereby determining the signal's spectral distribution. The signal analysis processor also calculates characteristic parameters such as overshoot, undershoot, rise time, and fall time. For example, analysis reveals a signal with an overshoot of 10%, an undershoot of 5%, a rise time of 50ps, and a fall time of 60ps.

[0047] Transmission line simulation: Based on transmission line theory, a field-programmable gate array (FPGA) is used to construct a transmission line model. An algorithm is written in the FPGA to set the transmission line resistance, inductance, capacitance, and conductance parameters. The transmission line model parameters are set based on the actual transmission environment, for example, a transmission line length of 10 cm, a line width of 0.1 mm, and a dielectric constant of 4. The actual transmission signal obtained from transmitter testing is input into the transmission line model. The FPGA runs the algorithm to simulate the signal's transmission along the transmission line, taking into account transmission losses and signal distortion, and then generates the simulated transmitted signal.

[0048] Receiver test: Input the simulated transmitted signal into the receiver of the signal integrity chip. Connect a bit error rate tester to the output pin of the chip's receiver, and also input the original stimulus signal into the tester. The tester uses a pseudo-random binary sequence as the stimulus signal. By comparing the signal sequence recovered by the receiver with the original pseudo-random binary sequence, it counts the number of bit errors and calculates the bit error rate. For example, if 100 bit errors are detected in 10^9 code elements, the bit error rate is 10^-7. At the same time, a signal comparator is used to compare the actual received signal with the original stimulus signal to obtain signal difference information. The distortion level of the signal is then calculated using a distortion analyzer. For example, the distortion level of the signal is 8%.

[0049] Excitation Signal Generation Module: This module uses the Analog Devices AD9910 direct digital frequency synthesizer, which boasts a maximum output frequency of 1 GHz and a frequency resolution of 1 MHz. The AD9910 is programmed via the SPI interface to set the frequency control word, generating signals with multiple frequency components. The signal amplitude modulator uses the AD835 analog multiplier, which multiplies the DDS output signal by an amplitude control signal to modulate the signal amplitude. The amplitude control signal is provided by a digital potentiometer, the X9C103, which is controlled by a microcontroller to precisely adjust the signal amplitude.

[0050] Transmitter test module: A high-speed oscilloscope with a sampling rate of up to 100GSa / s and a bandwidth of 7GHz accurately acquires high-speed transmitted signals. The acquired signal is amplified by an AD8066 low-noise amplifier with a 10x amplification factor. The amplified signal is then fed into a signal analysis processor, which uses a TI TMS320C6748 floating-point DSP chip. A corresponding algorithm is programmed to analyze the characteristic parameters of the transmitted signal.

[0051] The transmission line simulation module uses an XC7K325T FPGA as the hardware platform for the transmission line model. The transmission line model algorithm is written in the Vivado development environment using the Verilog hardware description language. By configuring the FPGA pins, the actual transmission signal from the transmitter test module is input into the FPGA. After processing by the transmission line model algorithm, the simulated transmission signal is generated and output through the FPGA's output pins.

[0052] Receiver Test Module: The bit error rate tester supports data rate testing up to 112 Gbps and accurately calculates the signal's bit error rate. The signal comparator uses the MAX900 comparator chip, comparing the actual received signal with the original stimulus signal and outputting the comparison result. The distortion analyzer uses the Analog Devices AD8363 chip, calculating the signal's distortion based on the comparator's output.

[0053] Data Analysis and Display Module: A PC serves as the data analysis and display platform. Data from the transmitter and receiver test modules are transferred to the PC via a USB interface. A data analysis and display program is written using LabVIEW software on the PC to perform a comprehensive analysis of the characteristic parameters of the transmitted signal and the receiver evaluation parameters, such as calculating comprehensive signal integrity indicators. The evaluation results are visualized in charts, such as bar charts and line graphs, allowing users to intuitively understand the chip's performance.

[0054] It should be noted that the present invention is a high-speed channel signal integrity chip evaluation method and system. The components in the present invention are all components known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.

[0055] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-speed channel signal integrity chip evaluation method, characterized in that: include: generating an excitation signal containing multiple frequency components and different amplitudes, wherein the excitation signal is used to simulate a complex signal scenario in actual high-speed communication; Input the excitation signal to the transmitter of the signal integrity chip to be evaluated, and obtain the actual transmission signal output by the chip transmitter; Analyze the actual transmission signal to obtain characteristic parameters of the transmission signal, wherein the characteristic parameters include overshoot, undershoot, rise time, fall time and spectrum distribution of the signal; Simulating the transmission process of a signal under different transmission environments through a transmission line model, inputting the actual transmitted signal into the transmission line model to obtain a signal after simulated transmission; Input the simulated transmitted signal to the receiving end of the signal integrity chip, and obtain the actual received signal output by the chip receiving end; The actual received signal is compared with the original excitation signal, and receiving end evaluation parameters such as the signal bit error rate and the signal distortion degree are calculated.

2. The high-speed channel signal integrity chip evaluation method according to claim 1, characterized in that: In the step of analyzing the actual transmitted signal, a fast Fourier transform algorithm is used to perform spectrum analysis on the actual transmitted signal to determine the amplitude and phase information of each frequency component in the signal, thereby obtaining the spectrum distribution of the signal.

3. The high-speed channel signal integrity chip evaluation method according to claim 1, characterized in that: The transmission line model is constructed based on transmission line theory, taking into account the resistance, inductance, capacitance and conductance parameters of the transmission line, and can adjust these parameters according to the actual transmission environment to simulate different transmission losses and signal distortion conditions.

4. The high-speed channel signal integrity chip evaluation method according to claim 1, characterized in that: When calculating the bit error rate of a signal, a pseudo-random binary sequence is used as the excitation signal. By comparing the signal sequence recovered by the receiving end with the original pseudo-random binary sequence, the number of bit errors is counted and the bit error rate is calculated.

5. The high-speed channel signal integrity chip evaluation method according to claim 1, characterized in that: When acquiring the actual transmitted signal output by the chip transmitter and the actual received signal output by the chip receiver, a high-speed oscilloscope and high-precision data acquisition equipment are used to ensure that the acquired signals have high resolution and accuracy.

6. A high-speed channel signal integrity chip evaluation system, characterized in that: include: An excitation signal generating module, used for generating an excitation signal containing multiple frequency components and different amplitudes; A transmitter testing module, connected to the stimulus signal generating module, configured to input a stimulus signal into the transmitter of the signal integrity chip to be evaluated, obtain an actual transmission signal output by the chip transmitter, and analyze the actual transmission signal to obtain characteristic parameters of the transmission signal; A transmission line simulation module is connected to the transmitter test module, and simulates the transmission process of the signal under different transmission environments based on the transmission line model. The actual transmission signal obtained by the transmitter test module is input into the module to obtain the signal after simulated transmission; A receiving end test module, connected to the transmission line simulation module, is used to input the simulated transmitted signal into the receiving end of the signal integrity chip, obtain the actual received signal output by the chip receiving end, compare the actual received signal with the original stimulus signal, and calculate the signal bit error rate, signal distortion degree and other receiving end evaluation parameters; The data analysis and display module is connected to the transmitting end test module and the receiving end test module, and is used to comprehensively analyze the characteristic parameters of the transmitting signal and the receiving end evaluation parameters, and to display the evaluation results in a visual manner.

7. The high-speed channel signal integrity chip evaluation system according to claim 6, characterized in that: The excitation signal generation module includes a direct digital frequency synthesizer and a signal amplitude modulator, and can accurately control the frequency and amplitude of the excitation signal.

8. The high-speed channel signal integrity chip evaluation system according to claim 6, characterized in that: The transmitter test module includes a high-speed oscilloscope, a signal amplifier and a signal analysis processor. The high-speed oscilloscope is used to collect the actual transmission signal, the signal amplifier is used to amplify the collected signal, and the signal analysis processor is used to analyze the characteristic parameters of the amplified signal.

9. The high-speed channel signal integrity chip evaluation system according to claim 6, characterized in that: The transmission line simulation module uses a field programmable gate array to implement the algorithm of the transmission line model, and can quickly simulate the transmission process of signals under different transmission environments.

10. The high-speed channel signal integrity chip evaluation system according to claim 6, characterized in that: The receiving end test module includes a bit error rate tester, a signal comparator and a distortion analyzer. The bit error rate tester is used to calculate the bit error rate of the signal, the signal comparator is used to compare the actual received signal with the original excitation signal, and the distortion analyzer is used to calculate the distortion degree of the signal.

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