LDO (Low Dropout Regulator) with load transient response enhancement circuit and electronic equipment

Abstract

The invention discloses an LDO (Low Dropout Regulator) with a load transient response enhancement circuit and electronic equipment, and belongs to the technical field of integrated circuits. The circuit comprises an error amplifier, a buffer, a power tube, a feedback circuit, a compensation circuit and an LTRE module. The output end EAO of the error amplifier is connected with the grid electrode of the power tube through the buffer, the error amplifier compares reference voltage with feedback voltage, an EAO signal adjusts the conduction degree of the power tube, and the output voltage of the LDO is kept stable; the compensation circuit comprises an NMOS tube and a capacitor. The grid of the NMOS tube is connected with the input end of the buffer, the drain is connected with one end of the capacitor, and the source is grounded; the other end of the capacitor is connected with the EAO; one end of a delay circuit in the LTRE module is connected with the input end of the buffer, and the other end of the delay circuit is connected with the grid electrode of the NMOS tube, so that the grid electrode voltage is delayed to rise when the buffer voltage rises. The circuit has the advantages of low working voltage, low voltage drop and low static power consumption, and the transient response can be enhanced when the load current is increased or decreased.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an LDO with a load transient response enhancement circuit and an electronic device. Background Art

[0002] With the development of systems-on-chip (SoCs) and high-performance computing devices, the load transient response (LTR) of low-dropout (LDO) devices has become a critical factor affecting system stability and reliability. When the load current suddenly changes, the LDO must quickly adjust its output voltage; otherwise, system performance may degrade or even fail. In high-performance computing, the dynamic power consumption of CPUs and GPUs fluctuates rapidly. Inadequate transient response can lead to insufficient power supply, impacting computing speed and stability. In wireless communications and radio frequency systems, rapid changes in power amplifier current can cause signal distortion and compromise communication quality. When digital circuits or radio frequency modules switch between different operating modes, the load current can fluctuate dramatically within nanoseconds, causing significant undershoot or overshoot in the LDO output voltage. These voltage fluctuations can cause logic errors, shorten system life, or even lead to device failure. Furthermore, in low-power embedded systems, good transient response reduces excess power consumption and improves energy efficiency. Technologies such as enhanced drive capability, fast charge and discharge circuits, and adaptive transient compensation can reduce transient overshoot and undershoot, improving system power integrity. Therefore, improving the LDO's load transient response is crucial for the stable operation of modern electronic devices.

[0003] In portable devices, communication systems, artificial intelligence acceleration chips, and other fields, LDOs need to achieve fast voltage regulation with low static power consumption to adapt to transient load changes. Traditional solutions often rely on large-capacity output capacitors to suppress voltage fluctuations, which not only increases system size and cost but also may affect power conversion efficiency.

[0004] In recent years, researchers have proposed a variety of methods to improve the transient response of LDO loads, including variable bias technology, transient-boost capacitance (TBC), asynchronous control, dynamic-replica regulation, and bulk modulation.

[0005] Dynamic biasing technology adjusts the error amplifier's bias current based on load conditions, temporarily increasing the amplifier's drive capability when a fast response is required. For example, during a heavy load transient, the error amplifier's tail current is increased, allowing it to more quickly charge and discharge the power transistor gate, accelerating output regulation. This method significantly improves slew rate and shortens recovery time during load transitions. To maintain high efficiency, designs typically ensure that the bias branch is closed under light loads, while also ensuring that the bias current is not excessively high under heavy loads, thereby avoiding excessively reducing the amplifier's gain and affecting steady-state accuracy. Dynamic biasing effectively strikes a balance between transient performance and static power consumption.

[0006] Transient-enhancing capacitors: This refers to adding a coupling capacitor or equivalent capacitive branch within the LDO to inject or drain charge into the control node when the output voltage changes rapidly, thereby accelerating the response. For example, some LDOs without external capacitors use an additional capacitor to detect output changes through high-pass filtering, instantaneously charging and discharging the power tube gate, which is equivalent to providing a transient-enhanced frequency compensation path. When the load current suddenly increases or decreases, this additional capacitor path can quickly drive the power tube gate voltage to change, thereby reducing the undershoot or overshoot of the output voltage. This method can achieve both transient compensation and frequency compensation, ensuring that the LDO remains stable over the full load range.

[0007] An asynchronous control path introduces an independent, auxiliary control path outside the main feedback loop, typically consisting of a comparator or detection circuit directly driving the power transistor. When a load transient is detected (such as a rapid drop or rise in the output voltage from a reference), the asynchronous path bypasses the error amplifier's bandwidth limitations and directly forces the gate of the power transistor to adjust. For example, an additional charge / discharge transistor can be turned on momentarily during a transient, providing a high-current charge / discharge path for the gate. This significantly improves response speed and reduces voltage overshoot / undershoot caused by the speed limitations of the main amplifier. However, the asynchronous path requires careful design to avoid competition with the main loop or causing instability.

[0008] Dynamic replica regulation: This approach uses an analog load or replica circuit to proactively sense load changes and pre-adjust the LDO control variable. When a load change occurs, the replica circuit generates a corresponding signal and injects it into the control node, achieving feedforward compensation. For example, a small portion of the load current is replicated to an internal sensing node. When the output current changes suddenly, this detection signal quickly reflects the change and drives the error amplifier or power transistor to pre-adjust the output. Dynamic replica regulation essentially forms a dual-channel control system: the main loop maintains steady-state accuracy, while the secondary loop instantaneously corrects deviations, thus achieving a balance between stability and transient response. The challenge lies in the replica's accuracy and speed, ensuring that the compensation amount is appropriate and coordinated with the main loop.

[0009] Body-effect modulation: Utilizing the body effect of MOS transistors (MOS transistors) to dynamically adjust the threshold voltage of power transistors to enhance drive capability and accelerate response. Specifically, in response to sudden load changes, the threshold voltage is adjusted by controlling the substrate potential of the power transistor, instantaneously increasing or decreasing the transistor's conduction capability. For example, a dual-error amplifier architecture is employed, with one controlling the gate and the other a high-speed amplifier controlling the substrate voltage. When a sudden increase in load current causes an output drop, the PMOS body voltage is rapidly reduced (or the NMOS body voltage is increased), effectively lowering the threshold. This allows the power transistor's source and drain to conduct greater current at low voltage drop, mitigating the voltage drop. Conversely, when the load decreases momentarily, the body voltage is increased to raise the threshold, rapidly reducing the on-state current and suppressing output overshoot. While improving transient drive, body-effect modulation also allows for the use of smaller power transistors (because the threshold can be dynamically lowered to meet peak current requirements), reduces gate capacitance, and increases system bandwidth. Its disadvantages are that implementation is complex, requiring process support for controllable substrate biasing, and the body effect's impact is limited at very low voltage drop. Furthermore, the need to prevent body diode conduction limits the body voltage range during design.

[0010] Each of these new technology solutions has its own principles and applicability: dynamic biasing and asynchronous paths focus on improving gate-drive current and slew rate, significantly shortening the LDO's response time to load steps; transient coupling capacitors and dynamic feedforward replicas provide additional compensation channels, suppressing voltage fluctuations and ensuring stability without adding significant output capacitance; and body-effect modulation expands the LDO's low-voltage drive capability through device-level control. However, the effectiveness of these solutions is limited under ultra-low voltage or very low voltage drop conditions (where the input voltage approaches the output voltage). This is because the error amplifier and power transistor lack sufficient voltage headroom to execute fast control actions, resulting in less room for increasing gate voltage / current and limiting the extent of transient improvement. Therefore, improving LDO transient response in low-dropout scenarios remains a challenging task, requiring continued exploration and optimization of circuit topology and device processes. Summary of the Invention

[0011] The present invention aims to provide an LDO and electronic device with a load transient response enhancement circuit, which has low operating voltage, low voltage drop, low static power consumption, and can enhance the transient response when the load current increases or decreases.

[0012] On the one hand, the present invention provides an LDO with a load transient response enhancement circuit, comprising an error amplifier, a buffer, a power tube, a feedback circuit, a compensation circuit, and an LTRE module; the error amplifier output terminal EAO is connected to the gate of the power tube through the buffer, and the error amplifier compares the reference voltage V REF and the feedback voltage V of the feedback circuit FB, the error amplifier output EAO signal adjusts the conduction degree of the power tube to maintain the LDO output voltage V OUT Stablize;

[0013] The compensation circuit includes an NMOS transistor N5 and a capacitor C1; the gate of the NMOS transistor N5 is connected to the buffer input terminal, and this connection point is defined as the VS point. The drain of the NMOS transistor N5 is connected to one end of the capacitor C1, the source of the NMOS transistor N5 is grounded, and the other end of the capacitor C1 is connected to the error amplifier output terminal EAO.

[0014] The LTRE module includes a delay circuit, one end of which is connected to the VS point, and the other end is connected to the gate of the NMOS transistor N5, so that the gate voltage of the NMOS transistor N5 is delayed to increase when the voltage at the VS point increases.

[0015] Furthermore, the buffer is a current multiplying buffer composed of a plurality of cascaded current mirrors, and the current gain of each current mirror is greater than 1.

[0016] Furthermore, the current multiplying buffer includes an NMOS transistor N0, an NMOS transistor N1, an NMOS transistor N2, a PMOS transistor P0, a PMOS transistor P1, and a PMOS transistor P2, wherein the PMOS transistors P0 and PMOS transistors P1 form a first current mirror, the NMOS transistors N1 and NMOS transistors N2 form a second current mirror, and the PMOS transistors P2 and PMOS transistors P3 form a third current mirror stage, wherein the PMOS transistor P3 is the power transistor;

[0017] The gate of the NMOS transistor N0 is connected to the error amplifier output terminal EAO, the drain of the NMOS transistor N0 is connected to the gate of the PMOS transistor P0, the drain of the PMOS transistor P0, and the gate of the PMOS transistor P1; the gate and drain of the PMOS transistor P2 are connected to the gate of the PMOS transistor P3;

[0018] The gate of the NMOS transistor N5 is connected to the drain of the NMOS transistor N1, and this connection point is defined as the VS point. The drain of the NMOS transistor N5 is connected to one end of the capacitor C1, the source of the NMOS transistor N5 is grounded, and the other end of the capacitor C1 is connected to the error amplifier output terminal EAO.

[0019] Furthermore, the delay circuit includes a resistor R0 and a capacitor C0; one end of the resistor R0 is connected to the VS point, and the other end is connected to the gate of the NMOS transistor N5 and one end of the capacitor C0, and the other end of the capacitor C0 is connected to the source of the NMOS transistor N5 and ground.

[0020] Furthermore, the LTRE module further includes a capacitor C2, a bias current source, an AC current sampling circuit, a reference current source, and an NMOS tube N6;

[0021] One end of capacitor C2 is connected to the LDO output voltage VOUT , the other end is connected to the bias current source and the input end of the AC current sampling circuit, and the output end of the AC current sampling circuit is connected to the reference current source and the gate of the NMOS tube N6; the drain of the NMOS tube N6 is connected to the VS point, and the source of the NMOS tube N6 is connected to the gate of the NMOS tube N5; the bias current source current is I0. When the circuit is working stably, the output current of the AC current sampling circuit is k*I0, k is the amplification factor of the AC current, and the reference current I1 of the reference current source is greater than k*I0; when the load current changes from large to small, the AC current generated by the capacitor C2 is amplified by the AC current sampling circuit and is greater than the reference current I1.

[0022] Furthermore, the AC current sampling circuit includes a fourth current mirror composed of NMOS transistors N7 and NMOS transistors N8, and a fifth current mirror composed of PMOS transistors P7 and PMOS transistors P8; one end of capacitor C2 is connected to the LDO output voltage V OUT The other end is connected to the bias current source, the drain of NMOS tube N7, the gate of NMOS tube N7, and the gate of NMOS tube N8; the source of NMOS tube N7, the source of NMOS tube N8, and the source of NMOS tube N9 are grounded; the drain of NMOS tube N8 is connected to the drain of PMOS tube P7, the gate of PMOS tube P7, and the gate of PMOS tube P8; the source of PMOS tube P7 and the source of PMOS tube P8 are connected to the power supply VDD; the reference current source uses NMOS tube N9, and the gate of NMOS tube N9 is connected to the bias voltage V BIAS The drain of the PMOS tube P8 is connected to the drain of the NMOS tube N9 and the gate of the NMOS tube N6; the drain of the NMOS tube N6 is connected to the VS point, and the source of the NMOS tube N6 is connected to the gate of the NMOS tube N5.

[0023] On the other hand, the present invention further provides an electronic device including the above-mentioned LDO with load transient response enhancement circuit.

[0024] The beneficial effects of the LDO and electronic device with a load transient response enhancement circuit of the present invention are as follows:

[0025] The LDO with load transient response enhancement circuit and electronic equipment of the present invention uses PMOS as the LDO power tube, which can more easily meet the requirements of low operating voltage, low voltage drop and low static power consumption.

[0026] When the load increases suddenly, the LDO output voltage VOUT will drop, and then through the feedback circuit, the output voltage EAO of the error amplifier will increase, and finally the current of the power tube P3 will increase, thereby reducing the output voltage V OUTHowever, the speed at which the EAO voltage rises will slow down as the equivalent on-resistance of the NMOS transistor N5 in the compensation circuit decreases. The present invention uses a delay circuit composed of a resistor R0 and a capacitor C0 to delay the increase of the gate voltage of the NMOS transistor N5 when the EAO voltage rises, thereby reducing the on-resistance of the NMOS transistor N5 and accelerating the speed at which the EAO voltage rises, thereby achieving the purpose of reducing the undershoot voltage.

[0027] When the load suddenly decreases from a large current, the gate voltage of the NMOS transistor N5 needs to change from high to low. If the speed of change is to be increased, the gate voltage of the NMOS transistor N5 needs to change to a low level quickly, and the influence of the above-mentioned delay circuit needs to be eliminated. To this end, the present invention also adds a circuit on the basis of the delay circuit to OUT When there is no change, the gate voltage of NMOS tube N6 is initially at zero potential; when the load current changes from large to small, the output voltage V OUT The AC current generated on the capacitor C2 is amplified to make it greater than the reference current I1, and the gate voltage signal of the NMOS tube N6 is increased. The NMOS tube N6 is turned on, which is similar to short-circuiting R0, so that the gate voltage of the NMOS tube N5 is quickly reduced. The speed of reduction is close to that without the delay circuit (R0 and C0), and the transient response capability is restored.

[0028] The LDO output pole varies widely with load. To simplify the design of the LDO compensation circuit and meet the LDO loop gain requirements, the gate pole of the PMOS transistor (the power transistor) needs to be raised outside the bandwidth. However, the low power supply operating voltage and the minimum gate voltage of the PMOS transistor (the power transistor) must be below 0.6V, which limits the implementation of the LDO control architecture. To address this, the present invention uses a current multiplying buffer composed of current mirrors to generate multiple poles. These poles increase with increasing load current and can be maintained outside the loop bandwidth under different loads. This improves loop gain while avoiding a reduction in phase margin.

[0029] Through simulation tests, it is shown that when the LTRE module of the LDO of the present invention adopts an AC current sampling circuit in addition to a delay circuit, the transient response when the load current increases or decreases is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is the LDO circuit schematic.

[0031] Figure 2 This is the schematic diagram of an LDO circuit using a current multiplying buffer.

[0032] Figure 3 FIG. 4 is a schematic diagram of an LDO circuit including an LTRE module according to an embodiment of the present invention.

[0033] Figure 4 FIG. 4 is a schematic diagram of an LDO circuit including an LTRE module and a current multiplying buffer according to an embodiment of the present invention.

[0034] Figure 5 This is a circuit schematic diagram of an LTRE module including only a delay circuit according to an embodiment of the present invention.

[0035] Figure 6 This is a circuit schematic diagram of an LTRE module with an additional delay elimination circuit according to an embodiment of the present invention.

[0036] Figure 7 This is the LDO load transient response simulation waveform without the LTRE module.

[0037] Figure 8 The figure shows the LDO load transient response simulation waveform when the LTRE module only contains the delay circuit.

[0038] Figure 9 This is the LDO load transient response simulation waveform after the LTRE module adds a delay elimination circuit. DETAILED DESCRIPTION

[0039] The present invention will be described in further detail below with reference to the embodiments and accompanying drawings.

[0040] An embodiment of the present invention is an LDO (Low Dropout Regulator) circuit with a load transient response enhancement circuit, which is used to improve the LDO load transient response and can be used for power management of various electronic devices.

[0041] Designing a circuit to improve load transient response requires targeting different LDO control architectures, and two factors need to be considered when selecting an LDO control architecture.

[0042] First, the LDO of the present invention is required to have a low operating voltage, low voltage drop, and low static power consumption. Therefore, the LDO using PMOS as the power tube is easier to meet the requirements of low operating voltage, low voltage drop, and low static power consumption than the LDO using charge pump voltage multiplication and NMOS power tube.

[0043] Secondly, the LDO of the present invention requires an operating voltage of only 1.6V, while the threshold voltage of a PMOS transistor is approximately 0.7V. Considering the effects of process corner deviation and temperature, the PMOS transistor's conduction threshold increases to approximately 1V. This requires that when the PMOS transistor is used as a power transistor, the gate control voltage must be lower than 0.6V to ensure that the power transistor turns on when the power supply voltage is 1.6V. However, for an LDO, simply turning on the PMOS transistor as a power transistor is far from sufficient. The degree of conduction of the power transistor directly determines the LDO's dropout voltage parameter. The larger the gate-source voltage difference, the more conductive the PMOS transistor is. The same PMOS size can achieve a lower voltage drop, so the gate voltage is preferably 0V.

[0044] like Figure 1 As shown in the figure, the LDO includes an error amplifier, a buffer, a power transistor (PMOS transistor P3), a feedback circuit, and a compensation circuit. The error amplifier output (Error Amplifier Output) EAO is connected to the gate of the power transistor P3 through the buffer. The error amplifier compares the reference voltage V REF And the feedback voltage V FB , which outputs the EAO signal to adjust the conduction level of the power tube P3 to maintain the output voltage V OUT Stable. The error amplifier output EAO is connected to a compensation circuit to ensure loop stability and prevent oscillation. The compensation circuit includes NMOS transistor N5 and capacitor C1. The gate of NMOS transistor N5 is connected to the buffer input, defined as point VS. The drain of NMOS transistor N5 is connected to one end of capacitor C1, the source of NMOS transistor N5 is grounded, and the other end of capacitor C1 is connected to the error amplifier output EAO. Bias voltage VBP1 provides bias voltage for the error amplifier.

[0045] The LDO output pole varies widely with load, with the output load resistance varying between 1MΩ and 4Ω, a difference of approximately 2 million times. At no load or light load, the output pole is primary, while at heavy load, it becomes secondary. To simplify the design of the LDO compensation circuit and meet the required loop gain, the gate pole of the PMOS transistor (the power transistor) must be raised outside the bandwidth. However, the low power supply operating voltage and the minimum gate voltage requirement of the PMOS transistor, which serves as the power transistor, below 0.6V, limit the implementation options for the LDO loop control circuit. Neither a differential pair buffer nor a PMOS source follower can be used as the buffer.

[0046] Preferably, in another embodiment of the present invention, the buffer is a current multiplying buffer (Current Multiplying Buffer) formed by a current mirror. Figure 2As shown, the current multiplying buffer consists of a cascade of a first current mirror consisting of PMOS transistors P0 and P1, a second current mirror consisting of NMOS transistors N1 and N2, and a third current mirror consisting of PMOS transistors P2 and P3. PMOS transistor P3 is the power transistor of the LDO. The current gain of the first current mirror is K1, the current gain of the second current mirror is K2, and the current gain of the third current mirror is K3. K1, K2, and K3 are all greater than 1, acting as current multipliers. This cascaded current mirror arrangement generates multiple poles, but these poles increase in size as the load current increases. They remain outside the loop bandwidth under varying loads, thus improving loop gain while avoiding a reduction in phase margin.

[0047] like Figure 2 As shown, the compensation circuit includes NMOS transistor N5 and capacitor C1. The gate of NMOS transistor N5 is connected to the drain of NMOS transistor N1, and this connection point is defined as VS. The drain of NMOS transistor N5 is connected to one end of capacitor C1. The source of NMOS transistor N5 is grounded, and the other end of capacitor C1 is connected to the error amplifier output EAO. Because the current of NMOS transistor N1 is proportional to the output current of the LDO, the voltage at VS also reflects the magnitude of the LDO output current, increasing as the LDO output current increases.

[0048] When the load suddenly increases, the LDO output voltage V OUT It will drop, and then pass through the feedback circuit (resistor voltage divider) to the gate of the error amplifier input pair tube P5. At this time, the gate voltage of the error amplifier input pair tube P5 also decreases, and the differential pair (NMOS tubes N3 and N4) generates an output current, which increases the output EAO voltage of the error amplifier, and finally increases the current of the power tube P3, thereby reducing the output voltage V OUT However, the rate of increase of the EAO voltage will slow down as the equivalent on-resistance of the NMOS tube N5 in the compensation circuit decreases. At the beginning, the gate voltage of the NMOS tube N5 is low and the equivalent impedance is large, much larger than the capacitor impedance, so the EAO voltage rises quickly; but as the EAO voltage increases, the voltage at the VS point also increases, causing the on-resistance of the NMOS tube N5 to decrease, and the rate of increase of the EAO voltage begins to slow down.

[0049] In order to solve this problem, the LDO of the present invention further includes a LTRE (Load Transient Response Enhancement) module, such as Figure 3 and Figure 4As shown in the red box, the LTRE module is used to improve transient response speed and reduce output voltage overshoot and undershoot. The LTRE module includes a delay circuit, one end of which is connected to the VS point and the other end to the gate of NMOS transistor N5 in the compensation circuit. This delays the increase in the gate voltage of NMOS transistor N5 when the voltage at VS increases. This delay circuit prevents undershoot.

[0050] Preferably, in another embodiment, Figure 5 As shown in Figure 1, the delay circuit includes resistor R0 and capacitor C0. One end of resistor R0 is connected to point VS, and the other end is connected to the gate of NMOS transistor N5 and one end of capacitor C0. The other end of capacitor C0 is connected to the source of NMOS transistor N5 and ground. When the voltage at point VS increases, the gate voltage of NMOS transistor N5 increases with a delay, which in turn reduces the on-resistance of NMOS transistor N5, thereby accelerating the rise of EAO voltage and reducing undershoot voltage.

[0051] When the load suddenly decreases from a large current, the gate voltage of the NMOS transistor N5 needs to change from high to low. If the speed of change is to be increased, the gate voltage of the NMOS transistor N5 needs to change to a low level quickly, and the influence of the above-mentioned delay circuit needs to be eliminated. In order to achieve this need, in another embodiment, the LTRE module further includes the following Figure 6 The circuit in the blue dotted box. The LTRE module also includes capacitor C2, bias current source, AC current sampling circuit, reference current source, and NMOS tube N6. One end of capacitor C2 is connected to the LDO output voltage V OUT The other end is connected to the bias current source and the input end of the AC current sampling circuit. The output end of the AC current sampling circuit is connected to the reference current source and the gate of the NMOS tube N6. The drain of the NMOS tube N6 is connected to the VS point, and the source of the NMOS tube N6 is connected to the gate of the NMOS tube N5. The bias current source current is I0. When the circuit is working stably, the output current of the AC current sampling circuit is k*I0, where k is the amplification factor of the AC current. The reference current I1 of the reference current source is greater than k*I0, so that the output voltage V OUT When there is no change, the gate voltage V RCTRL is zero potential, so the initial state of the gate voltage of NMOS tube N6 is zero potential. When the load current changes from large to small, the output voltage V OUT will increase, so the capacitor C2 will generate an AC current. After being amplified by the AC current sampling circuit, the output current will be greater than the reference current I1, so the gate voltage V RCTRLbecomes high, the on-resistance of the NMOS tube N6 decreases, the NMOS tube N6 is turned on, and then R0 is approximately short-circuited, so that the gate voltage of the NMOS tube N5 decreases rapidly. The speed of decrease is close to that when there is no delay circuit (R0 and C0), and the transient response capability is restored.

[0052] Preferably, if Figure 6 As shown, the AC current sampling circuit includes a fourth current mirror composed of NMOS transistors N7 and NMOS transistors N8, and a fifth current mirror composed of PMOS transistors P7 and PMOS transistors P8. One end of capacitor C2 is connected to the LDO output voltage V OUT The other end is connected to the bias current source, the drain of NMOS transistor N7, the gate of NMOS transistor N7, and the gate of NMOS transistor N8. The source of NMOS transistor N7, the source of NMOS transistor N8, and the source of NMOS transistor N9 are grounded. The drain of NMOS transistor N8 is connected to the drain of PMOS transistor P7, the gate of PMOS transistor P7, and the gate of PMOS transistor P8; the source of PMOS transistor P7 and the source of PMOS transistor P8 are connected to VDD. The reference current source uses NMOS transistor N9, and the gate of NMOS transistor N9 is connected to the bias voltage V BIAS The drain of the PMOS tube P8 is connected to the drain of the NMOS tube N9 and the gate of the NMOS tube N6; the drain of the NMOS tube N6 is connected to the VS point, and the source of the NMOS tube N6 is connected to the gate of the NMOS tube N5.

[0053] When the circuit is working stably, the current flowing through the NMOS tube N7 is I0, and the current flowing through the PMOS tube P8 is k*I0, where k is the amplification factor of the AC current. The current capacity I1 of the NMOS tube N9 is configured to be greater than k*I0, so that the output voltage V OUT When there is no change, the gate voltage V RCTRL is zero potential, so the initial state of the gate voltage of NMOS tube N6 is zero potential. When the load current changes from large to small, the output voltage V OUT will increase, so the capacitor C2 will generate an AC current, which will be amplified by the fourth current mirror composed of NMOS tubes N7 and N8, and the fifth current mirror composed of PMOS tubes P7 and P8, and will be greater than the current of NMOS tube N9. Therefore, the gate voltage V RCTRL becomes high, the on-resistance of the NMOS tube N6 decreases, the NMOS tube N6 is turned on, and then R0 is approximately short-circuited, so that the gate voltage of the NMOS tube N5 decreases rapidly. The speed of decrease is close to that when there is no delay circuit (R0 and C0), and the transient response capability is restored.

[0054] Those skilled in the art will appreciate that the AC current sampling circuit in this embodiment may be implemented using other circuit structures (such as a source amplifier, etc.).

[0055] The overshoot and undershoot values ​​of the LDO load transient response are closely related to the size of the output capacitor and the rate of change of the load current. Figures 7-9 The simulation results shown are obtained under the same simulation test conditions: the output capacitance value is 1uF, the output load current change time is 1us, it changes between 1mA and 300mA, and the power supply input voltage is 4.3V.

[0056] The output voltage and current of the LDO without LTRE module are as follows: Figure 7 As shown, when the load current suddenly increases, the output voltage V OUT The drop change (dy) is 278 mV (V OUT From 3.322028V to 3.042275V); when the load current suddenly decreases, the output voltage V OUT The increase in change (dy) is 147 mV (V OUT from 3.305818V to 3.453337V).

[0057] like Figure 8 As shown in the figure, when only the delay circuit consisting of resistor R0 and capacitor C0 is used in the LTRE module of the LDO loop control circuit, when the load current suddenly increases, the output voltage V OUT The drop change (dy) becomes 164 mV (V OUT from 3.322V to 3.158V), and Figure 7 Compared with the above, the decrease in the amount of change is significantly reduced. Figure 8 It can be seen that the delay circuit composed of R0 and C0 will also bring negative effects. When the load current decreases, the output voltage V OUT The increase in change (dy) is 155 mV (V OUT from 3.306V to 3.461V), which is greater than that of Figure 7 147 mV in.

[0058] like Figure 9 As shown in Figure 1, when the LTRE module uses an AC current sampling circuit in addition to the delay circuit, the transient response when the load current increases or decreases is enhanced. OUT When the output voltage V OUT The drop change (dy) is 165 mV (V OUT From 3.322026V to 3.15693V); load current I OUT When the output voltage V OUT Increases, the gate voltage V RCTRLThe voltage rises from zero potential, making NMOS tube N6 conduct, which is similar to short-circuiting R0, so that the gate voltage of NMOS tube N5 decreases rapidly. The speed of decrease is almost the same as when there is no delay circuit (R0 and C0). The output voltage V OUT The increase in change (dy) is 147 mV (V OUT from 3.305818V to 3.453152V).

[0059] The LDO with a load transient response enhancement circuit of the present invention uses a PMOS as a power tube, which can more easily meet the requirements of low operating voltage, low voltage drop, and low static power consumption.

[0060] When the load suddenly increases, the LDO output voltage V OUT It will drop, and then pass through the feedback circuit to increase the output voltage EAO of the error amplifier, and finally increase the current of the power tube P3, thereby reducing the output voltage V OUT However, the speed at which the EAO voltage rises will slow down as the equivalent on-resistance of the NMOS transistor N5 in the compensation circuit decreases. The present invention uses a delay circuit composed of a resistor R0 and a capacitor C0 to delay the increase of the gate voltage of the NMOS transistor N5 when the EAO voltage rises, thereby reducing the on-resistance of the NMOS transistor N5 and accelerating the speed at which the EAO voltage rises, thereby achieving the purpose of reducing the undershoot voltage.

[0061] When the load suddenly decreases from a large current, the gate voltage of the NMOS transistor N5 needs to change from high to low. If the speed of change is to be increased, the gate voltage of the NMOS transistor N5 needs to change to a low level quickly, and the influence of the above-mentioned delay circuit needs to be eliminated. To this end, the present invention also adds a circuit on the basis of the delay circuit to OUT When there is no change, the gate voltage of NMOS tube N6 is initially at zero potential; when the load current changes from large to small, the output voltage V OUT The AC current generated on the capacitor C2 is amplified to make it greater than the reference current I1, and the gate voltage signal of the NMOS tube N6 is increased. The NMOS tube N6 is turned on, which is similar to short-circuiting R0, so that the gate voltage of the NMOS tube N5 is quickly reduced. The speed of reduction is close to that without the delay circuit (R0 and C0), and the transient response capability is restored.

[0062] The LDO output pole varies widely with load. To simplify the design of the LDO compensation circuit and meet the LDO loop gain requirements, the gate pole of the PMOS transistor (the power transistor) needs to be raised outside the bandwidth. However, the low power supply operating voltage and the minimum gate voltage of the PMOS transistor (the power transistor) must be below 0.6V, which limits the implementation of the LDO control architecture. To address this, the present invention uses a current multiplying buffer composed of current mirrors to generate multiple poles. These poles increase with increasing load current and can be maintained outside the loop bandwidth under different loads. This improves loop gain while avoiding a reduction in phase margin.

[0063] Through simulation tests, it is shown that when the LTRE module of the LDO of the present invention adopts an AC current sampling circuit in addition to a delay circuit, the transient response when the load current increases or decreases is enhanced.

[0064] Although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. Any equivalent changes or modifications made without departing from the spirit and scope of the present invention are also within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the content defined in the claims of this application.

Claims

1. An LDO with a load transient response enhancement circuit, characterized in that: It includes an error amplifier, a buffer, a power tube, a feedback circuit, a compensation circuit, and an LTRE module; the error amplifier output terminal EAO is connected to the gate of the power tube through the buffer, and the error amplifier compares the reference voltage V REF and the feedback voltage V of the feedback circuit FB , the error amplifier output EAO signal adjusts the conduction degree of the power tube to maintain the LDO output voltage V OUT Stablize; The compensation circuit includes an NMOS transistor N5 and a capacitor C1; the gate of the NMOS transistor N5 is connected to the buffer input terminal, and this connection point is defined as the VS point. The drain of the NMOS transistor N5 is connected to one end of the capacitor C1, the source of the NMOS transistor N5 is grounded, and the other end of the capacitor C1 is connected to the error amplifier output terminal EAO. The LTRE module includes a delay circuit, one end of which is connected to the VS point, and the other end is connected to the gate of the NMOS transistor N5, so that the gate voltage of the NMOS transistor N5 is delayed to increase when the voltage at the VS point increases.

2. The LDO with load transient response enhancement circuit according to claim 1, characterized in that: The buffer is a current multiplying buffer composed of a plurality of cascaded current mirrors, and the current gain of each current mirror is greater than 1.

3. The LDO with load transient response enhancement circuit according to claim 2, characterized in that: The current multiplying buffer includes an NMOS transistor N0, an NMOS transistor N1, an NMOS transistor N2, a PMOS transistor P0, a PMOS transistor P1, and a PMOS transistor P2. The PMOS transistors P0 and PMOS transistors P1 form a first current mirror, the NMOS transistors N1 and NMOS transistors N2 form a second current mirror, and the PMOS transistors P2 and PMOS transistors P3 form a third current mirror stage. The PMOS transistor P3 is the power transistor. The gate of the NMOS transistor N0 is connected to the error amplifier output terminal EAO, the drain of the NMOS transistor N0 is connected to the gate of the PMOS transistor P0, the drain of the PMOS transistor P0, and the gate of the PMOS transistor P1; the gate and drain of the PMOS transistor P2 are connected to the gate of the PMOS transistor P3; The gate of the NMOS transistor N5 is connected to the drain of the NMOS transistor N1, and this connection point is defined as the VS point. The drain of the NMOS transistor N5 is connected to one end of the capacitor C1, the source of the NMOS transistor N5 is grounded, and the other end of the capacitor C1 is connected to the error amplifier output terminal EAO.

4. The LDO with a load transient response enhancement circuit according to any one of claims 1 to 3, characterized in that: The delay circuit includes a resistor R0 and a capacitor C0; one end of the resistor R0 is connected to the VS point, and the other end is connected to the gate of the NMOS transistor N5 and one end of the capacitor C0, and the other end of the capacitor C0 is connected to the source of the NMOS transistor N5 and ground.

5. The LDO with load transient response enhancement circuit according to claim 4, characterized in that: The LTRE module also includes a capacitor C2, a bias current source, an AC current sampling circuit, a reference current source, and an NMOS tube N6; One end of capacitor C2 is connected to the LDO output voltage V OUT , the other end is connected to the bias current source and the input end of the AC current sampling circuit, and the output end of the AC current sampling circuit is connected to the reference current source and the gate of the NMOS tube N6; the drain of the NMOS tube N6 is connected to the VS point, and the source of the NMOS tube N6 is connected to the gate of the NMOS tube N5; the bias current source current is I0. When the circuit is working stably, the output current of the AC current sampling circuit is k*I0, k is the amplification factor of the AC current, and the reference current I1 of the reference current source is greater than k*I0; when the load current changes from large to small, the AC current generated by the capacitor C2 is amplified by the AC current sampling circuit and is greater than the reference current I1.

6. The LDO with load transient response enhancement circuit according to claim 5, characterized in that: The AC current sampling circuit includes a fourth current mirror composed of NMOS transistors N7 and NMOS transistors N8, and a fifth current mirror composed of PMOS transistors P7 and PMOS transistors P8; one end of capacitor C2 is connected to the LDO output voltage V OUT The other end is connected to the bias current source, the drain of NMOS tube N7, the gate of NMOS tube N7, and the gate of NMOS tube N8; the source of NMOS tube N7, the source of NMOS tube N8, and the source of NMOS tube N9 are grounded; the drain of NMOS tube N8 is connected to the drain of PMOS tube P7, the gate of PMOS tube P7, and the gate of PMOS tube P8; the source of PMOS tube P7 and the source of PMOS tube P8 are connected to the power supply VDD; the reference current source uses NMOS tube N9, and the gate of NMOS tube N9 is connected to the bias voltage V BIAS The drain of the PMOS tube P8 is connected to the drain of the NMOS tube N9 and the gate of the NMOS tube N6; the drain of the NMOS tube N6 is connected to the VS point, and the source of the NMOS tube N6 is connected to the gate of the NMOS tube N5.

7. An electronic device, characterized in that: The invention comprises an LDO with a load transient response enhancement circuit according to any one of claims 1 to 6.

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