Multi-core Interlaken architecture and method based on resource sharing

Abstract

The invention relates to the technical field of data transmission, and discloses a multi-core Interlaken architecture and method based on resource sharing. The architecture comprises a Memory resource pool used for centrally managing memory access requests of each core; the first mapping module is used for mapping the memory access bus bandwidth of each core to a Memory resource pool according to the configuration state of each core; the PCS resource pool is used for centrally managing PCS channel resources of each core in a SerDes channel pooling mode; and the second mapping module is used for mapping the SerDes channel connection relation of each core to the PCS resource pool according to the configuration state of each core. According to the architecture provided by the embodiment of the invention, through centralized management of the Memory resource pool and the PCS resource pool, the limitation that each core exclusively occupies a memory channel and a SerDes channel in the related technology is broken through, and the resource utilization rate is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data transmission, and in particular to a multi-core Interlaken architecture and method based on resource sharing. Background Art

[0002] Interlaken is a high-speed interconnect interface protocol that supports high-bandwidth and highly reliable data packet transmission. However, related technologies often suffer from resource sharing issues within multi-core Interlaken architectures, resulting in low resource utilization. Therefore, how to achieve resource sharing within a multi-core Interlaken architecture and improve resource utilization has become a pressing issue. Summary of the Invention

[0003] In view of this, the present disclosure provides a multi-core Interlaken architecture and method based on resource sharing to solve the problem of how to implement resource sharing in the multi-core Interlaken architecture, thereby improving resource utilization.

[0004] On the one hand, the present disclosure provides a multi-core Interlaken architecture based on resource sharing, which includes: multiple cores, each of the multiple cores is used to independently execute Interlaken protocol processing tasks; a memory resource pool, which is used to centrally manage the memory access requests of each core in a bus bandwidth pooling manner; a first mapping module, which is used to map the memory access bus bandwidth of each core to the memory resource pool according to the configuration status of each core, so as to realize memory resource sharing among multiple cores; a PCS resource pool, which is used to centrally manage the PCS channel resources of each core in a SerDes channel pooling manner; and a second mapping module, which is used to map the SerDes channel connection relationship of each core to the PCS resource pool according to the configuration status of each core, so as to realize PCS processing resource sharing among multiple cores.

[0005] On the other hand, the present disclosure also provides a resource sharing method for a multi-core Interlaken architecture, which is applied to the above-mentioned multi-core Interlaken architecture based on resource sharing. The method includes: independently executing Interlaken protocol processing tasks through each core of a plurality of cores; centrally managing the memory access request of each core in a bus bandwidth pooling manner through a Memory resource pool; mapping the memory access bus bandwidth of each core to the Memory resource pool through a first mapping module according to the configuration status of each core to realize memory resource sharing among multiple cores; centrally managing the PCS channel resources of each core in a SerDes channel pooling manner through a PCS resource pool; and mapping the SerDes channel connection relationship of each core to the PCS resource pool through a second mapping module according to the configuration status of each core to realize PCS processing resource sharing among multiple cores.

[0006] On the other hand, the present disclosure further provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned multi-core Interlaken architecture resource sharing method when executing the computer program.

[0007] On the other hand, the present disclosure further provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to implement the above-mentioned resource sharing method of the multi-core Interlaken architecture.

[0008] Another aspect of the present disclosure further provides a computer program product, including computer instructions, which are used to enable a computer to execute the above-mentioned resource sharing method of the multi-core Interlaken architecture.

[0009] Through the resource-sharing multi-core Interlaken architecture and method of the above-mentioned embodiments of the present disclosure, through the centralized management of the Memory resource pool and the PCS resource pool, the limitation of each core monopolizing the memory channel and SerDes channel in the related art is broken, thereby improving resource utilization.

[0010] In addition, the first mapping module and the second mapping module can increase the flexibility of resource utilization by respectively mapping the bus bandwidth of the core and the connection relationship of the SerDes channel according to the configuration status of the core. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 An exemplary schematic diagram showing the architecture of a multi-core Interlaken interface of the related art;

[0013] Figure 2 An exemplary schematic diagram of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0014] Figure 3 An exemplary schematic diagram showing a core structure of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0015] Figure 4aAn exemplary schematic diagram of configuring a large core using a first mapping module in a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0016] Figure 4b An exemplary schematic diagram of a core in a first mapping module configuration of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0017] Figure 4c An exemplary schematic diagram of configuring a small core in a first mapping module of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0018] Figure 5a An exemplary schematic diagram of configuring a large core using a second mapping module in a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0019] Figure 5b An exemplary schematic diagram of a core in a second mapping module configuration of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0020] Figure 5c An exemplary schematic diagram of configuring a small core using a second mapping module in a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure is shown;

[0021] Figure 6 A schematic diagram of a multi-core Interlaken architecture resource sharing method provided by an embodiment of the present disclosure is shown;

[0022] Figure 7 A schematic structural diagram of another multi-core Interlaken architecture based on resource sharing provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The Interlaken protocol is a high-speed serial interface protocol designed for high-bandwidth, high-reliability data transmission. It is widely used in network chips, switching equipment, and data center chips for efficient data exchange between the Media Access Control (MAC) layer and the physical layer. Its core goal is to maximize bandwidth utilization within limited serializer / deserializer (SerDes) channels while providing excellent reliability and low-latency transmission capabilities.

[0024] like Figure 1As shown in the figure, in the related multi-core Interlaken interface architecture, the system typically allocates a fixed cache (memory) access bandwidth and a fixed number of SerDes channel resources to each core. Each core independently completes the complete Interlaken protocol processing flow, including functional modules such as MAC processing and physical coding sublayer (PCS) processing.

[0025] Although the methods of related technologies have certain parallelism, they also have the following significant defects: the interfaces are independent of each other and resources cannot be shared, resulting in low resource utilization and low system flexibility.

[0026] To solve the above problems, various embodiments of the present disclosure provide a multi-core Interlaken architecture based on resource sharing, which includes: multiple cores, each of the multiple cores is used to independently execute Interlaken protocol processing tasks; a memory resource pool, which is used to centrally manage the memory access requests of each core in a bus bandwidth pooling manner; a first mapping module, which is used to map the memory access bus bandwidth of each core to the memory resource pool according to the configuration status of each core, so as to realize memory resource sharing among multiple cores; a PCS resource pool, which is used to centrally manage the PCS channel resources of each core in a SerDes channel pooling manner; a second mapping module, which is used to map the SerDes channel connection relationship of each core to the PCS resource pool according to the configuration status of each core, so as to realize PCS processing resource sharing among multiple cores.

[0027] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present disclosure.

[0028] Please refer to Figure 2 , Figure 2 FIG. 1 shows an exemplary schematic diagram of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 2 As shown, the architecture may include: multiple cores, a memory resource pool, a first mapping module, a PCS resource pool and a second mapping module.

[0029] Multiple cores, each of the multiple cores is used to independently execute Interlaken protocol processing tasks.

[0030] In this embodiment, the core refers to a hardware processing unit or logic module dedicated to executing Interlaken protocol processing tasks, rather than a central processing unit (CPU) core.

[0031] Here, the architecture includes multiple cores, each of which can independently process a complete Interlaken data flow task.

[0032] Exemplarily, the architecture may include n cores, specifically core0 to coren-1.

[0033] The memory resource pool is used to centrally manage the memory access requests of each core in a bus bandwidth pooling manner.

[0034] In this embodiment, the Memory resource pool may be a memory collection in the architecture used for data interaction, caching, or temporary storage, and may be a resource pool formed by the collection of memories used by n cores.

[0035] For example, assuming that the bus bandwidth of each core accessing Memory at the minimum specification is m bits, and the bus bandwidth of n cores accessing Memory at the minimum specification is n*mbit, the n*mbit bus bandwidth can be pooled to build a Memory resource pool.

[0036] The pooled memory resource pool can centrally manage the memory access interfaces of each core and allocate bus bandwidth on demand.

[0037] Here, bus bandwidth can refer to the interface width and throughput capability of the core accessing memory resources.

[0038] The first mapping module is used to map the memory access bus bandwidth of each core to the memory resource pool according to the configuration status of each core, so as to realize memory resource sharing among multiple cores.

[0039] In this embodiment, the first mapping module may be a resource scheduling and bandwidth allocation control module, which may determine how much bus bandwidth of the memory resource each core can obtain.

[0040] The core configuration state can be used to represent the resource scheduling priority of the core to obtain bus bandwidth.

[0041] Furthermore, the first mapping module is used to establish a data transmission path between each core and the Memory resource pool according to the configuration status of each core, and allocate bus bandwidth to each core on demand so that each core can access the Memory resource pool.

[0042] The PCS resource pool is used to centrally manage the PCS channel resources of each core in a SerDes channel pooling manner.

[0043] In this embodiment, the PCS resource pool may be a resource pooling structure that uniformly manages PCS-related functional modules and corresponding PCS channel resources in the architecture.

[0044] For example, assuming that each core is allocated p SerDes lanes under the minimum specification, and n cores are allocated n*p SerDes lanes under the minimum specification, the n*p SerDes lanes can be pooled to build a PCS resource pool.

[0045] The pooled PCS resource pool can uniformly manage the PCS resources of each core and allocate SerDes channels on demand.

[0046] The second mapping module is used to map the SerDes channel connection relationship of each core to the PCS resource pool according to the configuration status of each core, so as to realize the sharing of PCS processing resources among multiple cores.

[0047] In this embodiment, the second mapping module may be a resource scheduling and SerDes channel allocation control module, which may determine how many SerDes channels of PCS resources each core can obtain.

[0048] The core configuration status can also be used to represent the resource scheduling priority of the core to obtain the SerDes channel.

[0049] Furthermore, the second mapping module is used to establish a data transmission path between each core and the PCS resource pool according to the configuration status of each core, and allocate a SerDes channel to each core for use by the core as needed.

[0050] The resource-sharing multi-core Interlaken architecture and method of the above-mentioned embodiments of the present disclosure, through the centralized management of the memory resource pool and the PCS resource pool, overcomes the limitation of each core in the related art of exclusive memory channels and SerDes channels, thereby improving resource utilization. The first mapping module and the second mapping module respectively map the core bus bandwidth and SerDes channel connection relationship according to the core configuration status, thereby increasing resource utilization flexibility.

[0051] In a possible implementation of the above embodiment, please refer to Figure 3 , Figure 3 FIG1 shows an exemplary schematic diagram of a core structure of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 3 As shown, each core includes: a MAC processing module and a multi-lane data synchronization correction unit, where:

[0052] The MAC processing module is used to perform at least one of the following: control and data processing on the Interlaken data channel side, packaging and distributing data in a specified format and receiving data, and managing the status and traffic of the data channel.

[0053] The multi-lane data synchronization correction unit can specifically refer to the multi-lanesalign&deskew unit. Here, multi-lanesalign can be used to perform frame-level alignment or codeword boundary alignment on the data streams in multiple SerDes channels at the transmitting end to ensure that the data is sent synchronously on multiple physical channels; deskew can be used to perform delay compensation on the data on multiple SerDes channels at the receiving end to eliminate the timing offset caused by transmission path differences between channels.

[0054] Furthermore, the multi-lane data synchronization correction unit can also be used for PCS processing, wherein the PCS processing may include but is not limited to at least one of the following: encoder / decoder, frame identifier / frame extractor, error detection and correction unit, etc.

[0055] Furthermore, the MAC processing module is connected to the Memory resource pool via a data bus, is used to perform framing and deframing operations of data frames, and accesses the Memory resource pool via the bus bandwidth allocated by the first mapping module during data reading and writing.

[0056] In this embodiment, a MAC processing module is integrated in each core. The MAC processing module can be used to frame / deframe data frames when receiving / sending Interlaken data. However, when performing frame data operations, the Memory resource pool must be read or written as a buffer area or transfer station.

[0057] At this time, the first mapping module is used to allocate the bus bandwidth corresponding to the MAC processing module in each core, and the MAC processing module accesses the Memory resource pool based on the allocated bus bandwidth.

[0058] The multi-lane data synchronization correction unit is connected to the memory resource pool through the first mapping module, and is used to write alignment information to the memory resource pool when aligning multi-channel data at the sending end, and read the alignment information from the memory resource pool at the receiving end to correct the phase deviation of the multi-channel data.

[0059] In this embodiment, a multi-lane data synchronization correction unit (multi-lanes align&deskew unit) is used to write alignment information to the Memory resource pool when aligning multi-channel data at the sending end, and read the alignment information from the Memory resource pool at the receiving end to correct the phase deviation of the multi-channel data.

[0060] At this time, the first mapping module is used to allocate the bus bandwidth corresponding to the multi-lanes align&deskew unit in each core, and the multi-lanes align&deskew unit accesses the memory resource pool based on the allocated bus bandwidth.

[0061] Here, since the multi-lanes align&deskew unit acts on multiple SerDes channels and needs to coordinate timing, sequence, and alignment information between different channels, the multi-lanes align&deskew unit needs to access the Memory resource pool.

[0062] Furthermore, the multi-lanes align&deskew unit can also act on a single SerDes channel. Therefore, the multi-lanes align&deskew unit does not need to access the Memory resource pool, but the PCS resource pool.

[0063] The multi-lanes align&deskew unit interacts with the physical layer links of the PCS resource pool through the SerDes channels allocated by the second mapping module.

[0064] In this embodiment, the second mapping module is responsible for dynamically allocating the connection requirements of multiple core SerDe channels to the actual PCS resource pool to achieve resource reuse or bandwidth scheduling.

[0065] Through the multi-core Interlaken architecture and method based on resource sharing of the above-mentioned embodiments of the present invention, through the centralized design of the Memory resource pool and the PCS resource pool, the memory bandwidth and SerDes channel resources originally bound to each core are pooled, so that the system can dynamically allocate resources according to the actual load requirements of each core during operation, avoid resource waste or inefficient use, and improve resource utilization. Each core has a complete MAC and PCS processing module, which can independently execute Interlaken protocol stack tasks while sharing underlying resources, so that the system has better elasticity and load balancing capabilities when supporting concurrent processing of multiple business flows, thereby improving concurrent processing efficiency. By introducing the Memory resource pool interaction mechanism in the multi-lanesalign&deskew unit, the alignment information of multiple channels can be uniformly managed, ensuring that the frame-level synchronization and the phase correction of the receiving end are more accurate and the latency is more controllable.

[0066] In a possible implementation of the above embodiment, the configuration state of each core includes one of the following: a large core configuration state, a medium core configuration state, or a small core configuration state.

[0067] In this embodiment, the configuration state may refer to the resource demand state of the core in different working states. For example, different working states may include but are not limited to: current task complexity, data flow, processing priority, etc.

[0068] Furthermore, the large core configuration state may refer to the current core undertaking the main processing tasks or processing high-throughput business flows. Therefore, the core in the large core configuration state requires the largest bus bandwidth and the largest number of SerDes channels; the medium core configuration state may refer to the current core being in a secondary or medium load state. Therefore, the core in the medium core configuration state requires a medium bus bandwidth and a medium number of SerDes channels; the small core configuration state may refer to the current core being in an idle, low-load or standby state. Therefore, the core in the small core configuration state only requires basic bandwidth resources or the minimum number of SerDes channels.

[0069] For example, the large core can be allocated n*m bits of bus bandwidth and n*p SerDes channels, the medium core can be allocated n / 2*m bits of bus bandwidth and n / 2*p SerDes channels, and the small core can be allocated m bits of bus bandwidth and p SerDes channels.

[0070] It is worth noting that the large cores, medium cores and small cores among multiple cores are relative. In theory, the distinction and allocation of cores can be expanded infinitely, such as "core#(maximum bandwidth of memory access bus, maximum number of serdes lanes connected by PCS)".

[0071] Exemplarily, the allocation form among multiple cores can be as follows: core0(n*m bit,n*p lanes), core1(n / 2*m bit,n / 2*p lanes), core2(n / 4*m bit,n / 4*p lanes), core3(n / 4*m bit,n / 4*planes), core4(n / 8*m bit,n / 8*p lanes), core5(n / 8*m bit,n / 8*p lanes), ..., coren / 2(m bit,p lanes), ..., core n-1(m bit,p lanes).

[0072] Through the multi-core Interlaken architecture and method based on resource sharing of the above-mentioned embodiments of the present disclosure, by introducing the configuration state system of "large core, medium core, small core", and based on the resource requirements corresponding to each state, different bus bandwidths and numbers of SerDes channels are allocated respectively, so that on-demand dynamic allocation and flexible scheduling of multi-core resources can be achieved. Compared with the traditional fixed allocation method, the present invention can dynamically adjust the core state and reallocate resources when the core processing load changes, significantly reducing the redundant occupation or waste of memory bandwidth or PCS link resources, and avoiding idle or wasted resources. The configuration method that supports scalable core number and multi-level state subdivision can enhance the system expansion capability and multi-core collaboration capability.

[0073] In a possible implementation of the above embodiment, the first mapping module is specifically configured to perform one of the following:

[0074] If the target core among multiple cores is in the large core configuration state, the entire bus bandwidth of the memory resource pool is mapped to the target core, and no memory bandwidth is allocated to other cores in the multiple cores.

[0075] If the target core among the multiple cores is in the medium core configuration state and the multiple cores do not have the large core configuration state, half of the bus bandwidth of the memory resource pool is mapped to the target core, and the remaining half of the bus bandwidth is evenly mapped to the other cores among the multiple cores;

[0076] If the configuration states of multiple cores are all small core configuration states, the entire bus bandwidth of the memory resource pool is evenly mapped to the multiple cores.

[0077] In this embodiment, if a target core among multiple cores is configured as a large core, indicating that the target core is processing a high-priority or high-throughput task, the first mapping module, after identifying the large core, allocates the entire bus bandwidth of the memory resource pool to the large core to ensure unobstructed access to the memory resource pool and maximize data channel throughput. Simultaneously, the first mapping module temporarily suspends access to the memory resource pool by other cores.

[0078] For example, please refer to Figure 4a , Figure 4a FIG2 shows an exemplary schematic diagram of configuring a large core using a first mapping module of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 4a As shown, among the multiple cores, core0 is a large core and core1 is a medium core. The first mapping module configures the bus bandwidth of core0 to n*m bits and allocates all bus bandwidth of the memory resource pool to the large core.

[0079] If the configuration state of the target core among the multiple cores is the medium core configuration state and there is no large core configuration state among the configuration states of the multiple cores, indicating that there is at least one medium load state among the multiple cores, the first mapping module allocates half of the bus bandwidth to the medium core and distributes the remaining part evenly among the other cores.

[0080] For example, please refer to Figure 4b , Figure 4b FIG. 1 shows an exemplary schematic diagram of a core in a first mapping module configuration of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 4b As shown, among the multiple cores, core0 is a large core and core1 is a medium core. The first mapping module downgrades the large core of core0 to a medium core and allocates a bus bandwidth of n / 2*m bits to core0, and runs the medium core of core1 at full specifications and allocates a bus bandwidth of n / 2*m bits to core1.

[0081] If the configuration states of multiple cores are all small core configuration states, indicating that all cores are currently idle, low-loaded, or only executing light tasks, the first mapping module no longer has priority restrictions when allocating bus bandwidth, but allocates it evenly to each core.

[0082] For example, please refer to Figure 4c , Figure 4c FIG. 1 shows an exemplary schematic diagram of configuring a small core in a first mapping module of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 4c As shown, each core is a small core, and mbit of bus bandwidth is evenly allocated to each core.

[0083] The resource-sharing multi-core Interlaken architecture and method described in the above-mentioned embodiments of this disclosure automatically adjusts configuration states based on the core's current load, eliminating the need for manual intervention. This enables adaptive scheduling in a multi-tasking environment and improves the architecture's operational flexibility. The number of cores, core capabilities, and bandwidth specifications can be expanded as needed, resulting in excellent modularity and deployability.

[0084] In a possible implementation of the above embodiment, the second mapping module is specifically configured to perform one of the following:

[0085] If the configuration state of the target core among the multiple cores is the large core configuration state, all SerDes channel connection relationships in the PCS resource pool are mapped to the target core, and no SerDes channel connection relationships are allocated to other cores among the multiple cores;

[0086] If the configuration state of a target core among the multiple cores is a medium core configuration state and the configuration states of the multiple cores do not exist in a large core configuration state, half of the SerDes channel connection relationship of the PCS resource pool is mapped to the target core, and the remaining half of the SerDes channel connection relationship is evenly mapped to other cores among the multiple cores;

[0087] If the configuration states of multiple cores are all small core configuration states, all SerDes channel connection relationships in the PCS resource pool are evenly mapped to the multiple cores.

[0088] In this embodiment, if a target core among multiple cores is configured as a large core, indicating that the target core is processing a high-priority or high-throughput task, the second mapping module, after identifying the large core, allocates all SerDes channels in the PCS resource pool to the large core to ensure unobstructed access to the PCS resource pool. Simultaneously, the second mapping module temporarily suspends access to the PCS resource pool by other cores.

[0089] For example, please refer to Figure 5a , Figure 5a FIG2 shows an exemplary schematic diagram of configuring a large core using a second mapping module of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 5a As shown, core0 is a large core and core1 is a medium core among the multiple cores. The second mapping module configures the SerDes channel of core0 as p*mlanes and allocates all SerDes channels of the PCS resource pool to the large core.

[0090] If the configuration state of the target core among multiple cores is the medium core configuration state and there is no large core configuration state among the configuration states of multiple cores, it indicates that there is at least one medium load state among the multiple cores. The second mapping module allocates half of the SerDes channels to the medium core and distributes the remaining half of the SerDes channels evenly among the other cores.

[0091] For example, please refer to Figure 5b , Figure 5b FIG. 1 shows an exemplary schematic diagram of a core in a second mapping module configuration of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 5b As shown, among the multiple cores, core0 is a large core and core1 is a medium core. The second mapping module downgrades the large core of core0 to a medium core, allocates p / 2*mlanes SerDes channels to core0, and runs the medium core of core1 at full specifications, and allocates p / 2*mlanes SerDes channels to core1.

[0092] If the configuration states of multiple cores are all small core configuration states, indicating that all cores are currently idle, low-loaded, or only performing light tasks, the second mapping module no longer has priority restrictions when allocating SerDes channels, but allocates them evenly to each core.

[0093] For example, please refer to Figure 5c , Figure 5c FIG2 shows an exemplary schematic diagram of configuring a small core in a second mapping module of a multi-core Interlaken architecture based on resource sharing according to an embodiment of the present disclosure. Figure 5c As shown, each core is a small core, and p lanes of SerDes channels are evenly allocated to each core.

[0094] The resource-sharing multi-core Interlaken architecture and method described in the above-mentioned embodiments of this disclosure automatically adjusts configuration states based on the core's current load, eliminating the need for manual intervention. This enables adaptive scheduling in a multi-tasking environment and improves the architecture's operational flexibility. The number of cores, core capabilities, and bandwidth specifications can be expanded as needed, resulting in excellent modularity and deployability.

[0095] Further references Figure 6 , Figure 6 A schematic diagram of a resource sharing method for a multi-core Interlaken architecture provided by an embodiment of the present disclosure is shown, which is applied to the above Figure 1 -The multi-core Interlaken architecture based on resource sharing as shown in any one of the items 5, the process of the method may include the following steps:

[0096] Step S601, independently executing an Interlaken protocol processing task by each of the multiple cores;

[0097] Step S602: centrally manage the memory access requests of each core through the memory resource pool in a bus bandwidth pooling manner;

[0098] Step S603: Mapping the memory access bus bandwidth of each core to the memory resource pool according to the configuration status of each core through the first mapping module to achieve memory resource sharing among multiple cores;

[0099] Step S604: Centrally manage the PCS channel resources of each core in a SerDes channel pooling manner through the PCS resource pool;

[0100] Step S605 : Mapping the SerDes channel connection relationship of each core to the PCS resource pool according to the configuration status of each core through the second mapping module to achieve PCS processing resource sharing among multiple cores.

[0101] In a possible implementation of the above embodiment, each core includes: a MAC processing module and a multi-lane data synchronization correction unit, wherein:

[0102] The MAC processing module performs data frame framing and deframing operations, and accesses the memory resource pool through the bus bandwidth allocated by the first mapping module during data reading and writing;

[0103] Through the multi-lane data synchronization correction unit, the transmitter writes alignment information to the memory resource pool when aligning multi-channel data, and the receiver reads the alignment information from the memory resource pool to correct the phase deviation of the multi-channel data;

[0104] Through the multi-lane data synchronization correction unit, the SerDes channel allocated by the second mapping module interacts with the physical layer link of the PCS resource pool.

[0105] In a possible implementation of the above embodiment, the configuration state of each core includes one of the following: a large core configuration state, a medium core configuration state, or a small core configuration state.

[0106] Through the multi-core Interlaken architecture and method based on resource sharing in the above embodiments of the present disclosure,

[0107] In a possible implementation of the above embodiment, the first mapping module maps the memory access bus bandwidth of each core to the memory resource pool according to the configuration status of each core to achieve memory resource sharing among multiple cores, including one of the following:

[0108] If the target core among multiple cores is in the large core configuration state, the entire bus bandwidth of the memory resource pool is mapped to the target core, and no memory bandwidth is allocated to other cores in the multiple cores.

[0109] If the target core among the multiple cores is in the medium core configuration state and the multiple cores do not have the large core configuration state, half of the bus bandwidth of the memory resource pool is mapped to the target core, and the remaining half of the bus bandwidth is evenly mapped to the other cores among the multiple cores;

[0110] If the configuration states of multiple cores are all small core configuration states, the entire bus bandwidth of the memory resource pool is evenly mapped to the multiple cores.

[0111] In a possible implementation of the above embodiment, the second mapping module maps the SerDes channel connection relationship of each core to the PCS resource pool according to the configuration status of each core to achieve PCS processing resource sharing among multiple cores, including one of the following:

[0112] If the configuration state of the target core among the multiple cores is the large core configuration state, all SerDes channel connection relationships in the PCS resource pool are mapped to the target core, and no SerDes channel connection relationships are allocated to other cores among the multiple cores;

[0113] If the configuration state of a target core among the multiple cores is a medium core configuration state and the configuration states of the multiple cores do not exist in a large core configuration state, half of the SerDes channel connection relationship of the PCS resource pool is mapped to the target core, and the remaining half of the SerDes channel connection relationship is evenly mapped to other cores among the multiple cores;

[0114] If the configuration states of multiple cores are all small core configuration states, all SerDes channel connection relationships in the PCS resource pool are evenly mapped to the multiple cores.

[0115] The present disclosure also provides an electronic device having the above Figure 1 -5 A multi-core Interlaken architecture based on resource sharing as shown in any one of the above.

[0116] See also Figure 7 , Figure 7 FIG. 4 shows a schematic diagram of a multi-core Interlaken architecture based on resource sharing provided by an embodiment of the present disclosure. Figure 7As shown, the electronic device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0117] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0118] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to execute the method shown in the above embodiment.

[0119] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0120] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0121] The electronic device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The bus connection is taken as an example.

[0122] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the electronic device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0123] The electronic device also includes a communication interface for the electronic device to communicate with other devices or a communication network.

[0124] The embodiments of the present disclosure also provide a computer-readable storage medium. The above-mentioned method according to the embodiments of the present disclosure can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0125] A portion of the present disclosure may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present disclosure through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes but is not limited to a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0126] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A multi-core Interlaken architecture based on resource sharing, characterized in that: The architecture includes: Multiple cores, each of the multiple cores is used to independently execute Interlaken protocol processing tasks; A memory resource pool is used to centrally manage the memory access requests of each core in a bus bandwidth pooling manner; A first mapping module is used to map the memory access bus bandwidth of each core to the memory resource pool according to the configuration status of each core, so as to realize memory resource sharing among multiple cores; A PCS resource pool, configured to centrally manage the PCS channel resources of each core in a SerDes channel pooling manner; The second mapping module is used to map the SerDes channel connection relationship of each core to the PCS resource pool according to the configuration status of each core, so as to realize the sharing of PCS processing resources among multiple cores.

2. The architecture according to claim 1, wherein: Each of the cores includes: a MAC processing module and a multi-lane data synchronization correction unit, wherein: The MAC processing module is connected to the Memory resource pool via a data bus, is used to perform framing and deframing operations of data frames, and access the Memory resource pool through the bus bandwidth allocated by the first mapping module during data reading and writing; The multi-lane data synchronization correction unit is connected to the memory resource pool through the first mapping module, and is used to use the memory resource pool to perform data transmission alignment on the multi-channel data at the sending end, and to use the memory resource pool to correct the phase deviation of the multi-channel data at the receiving end; The multi-lane data synchronization correction unit interacts with the physical layer link of the PCS resource pool through the SerDes channel allocated by the second mapping module.

3. The architecture according to claim 2, characterized in that The configuration state of each core includes one of the following: a large core configuration state, a medium core configuration state, or a small core configuration state.

4. The architecture according to claim 3, characterized in that The first mapping module is specifically configured to perform one of the following: If the configuration state of a target core among the multiple cores is a large core configuration state, all bus bandwidths of the memory resource pool are mapped to the target core, and no memory bandwidth is allocated to other cores among the multiple cores; If the configuration state of a target core among the multiple cores is a medium core configuration state and the configuration states of the multiple cores do not exist in a large core configuration state, half of the bus bandwidth of the memory resource pool is mapped to the target core, and the remaining half of the bus bandwidth is evenly mapped to other cores among the multiple cores; If the configuration states of the multiple cores are all small core configuration states, all bus bandwidths of the Memory resource pool are evenly mapped to the multiple cores.

5. The architecture according to claim 3, wherein: The second mapping module is specifically configured to perform one of the following: If the configuration state of a target core among the multiple cores is a large core configuration state, all SerDes channel connection relationships of the PCS resource pool are mapped to the target core, and no SerDes channel connection relationships are allocated to other cores among the multiple cores; If the configuration state of a target core among the multiple cores is a medium core configuration state and the configuration states of the multiple cores do not include a large core configuration state, mapping half of the SerDes channel connection relationship of the PCS resource pool to the target core, and mapping the remaining half of the SerDes channel connection relationship evenly to other cores among the multiple cores; If the configuration states of the multiple cores are all small core configuration states, all SerDes channel connection relationships of the PCS resource pool are evenly mapped to the multiple cores.

6. A resource sharing method for a multi-core Interlaken architecture, characterized in that: Applied to the multi-core Interlaken architecture based on resource sharing according to any one of claims 1 to 5, the method comprises: Independently execute Interlaken protocol processing tasks through each of the multiple cores; Through the memory resource pool, the memory access request of each core is centrally managed in a bus bandwidth pooling manner; By means of a first mapping module, the memory access bus bandwidth of each core is mapped to the memory resource pool according to the configuration status of each core, so as to realize memory resource sharing among multiple cores; Centrally manage the PCS channel resources of each core in a SerDes channel pooling manner through the PCS resource pool; Through the second mapping module, the SerDes channel connection relationship of each core is mapped to the PCS resource pool according to the configuration status of each core, so as to realize the sharing of PCS processing resources among multiple cores.

7. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the multi-core Interlaken architecture resource sharing method as claimed in claim 6 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the resource sharing method of the multi-core Interlaken architecture according to claim 6.

9. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the resource sharing method of the multi-core Interlaken architecture according to claim 6.

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