Retimer controller data path switching method and Retimer chip

Abstract

The invention discloses a data path switching method of a Retimer controller and a Retimer chip, and belongs to the field of communication. In order to reduce the risk of timeout of RC and EP in a balance stage, the method for switching the data path of the Retimer controller comprises the following steps: when the Retimer controller simultaneously meets the condition that any channel of an uplink pseudo port and a downlink pseudo port respectively detects eight continuous TS2 sequences with speed fields of 1, the public maximum rate is PCIe Gen6 and is greater than the current rate, and the Retimer controller is in an FLIT mode and a stateful state, setting the start field to 1. And after the negotiation is completed, the RC controller, the EP controller and the Regimer controller enter a recovery. Speed state to switch the speed, and the switching from PCIe Gen5 to Gen6 is completed. And after switching, the Retimer and the EP are switched to a recovery. Phase0 state, the RC is switched to a recovery. Phase1 state, and when the Retimer controller is in the recovery. Phase0 state, a code stream generation module generates a TS0 sequence and sends the TS0 sequence to the RC and the EP. The method is applied to the PCIe field, and the robustness of RC and EP in the balancing process is improved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a retimer controller data path switching method and a retimer chip. Background Art

[0002] As data rates continue to increase, such as with the evolution from Gen5 to Gen6 in the high-speed Peripheral Component Interconnect Express (PCIe) protocol, signal attenuation and interference during transmission are becoming increasingly severe. These issues directly impact signal quality at the receiver, making the eye diagram difficult to meet normal communication requirements. To address this issue, the industry has introduced various equalization techniques into transmission protocols to compensate for channel loss and improve signal integrity.

[0003] Retimer chips, as key components in high-speed signal transmission, are widely used in PCIe links to extend transmission distances and optimize signal quality. On the receiving end (RX), retimer chips typically support continuous time linear equalization (CTLE) and decision feedback equalization (DFE) technologies to enhance the signal's high-frequency components and correct distortion. On the transmitting end (TX), they optimize the output signal through specific equalization techniques, effectively compensating for channel losses and improving signal integrity. During the equalization process, retimer chips are typically configured with two pseudo ports, which complete the equalization operation by switching internal data paths to communicate with the root complex (RC) and endpoint device (EP).

[0004] In PCIe links supporting rates up to PCIe Gen6, the link establishment (link training) process involves the coordinated work of the RC, EP, and Retimer chips. Specifically, after the link rate switches from PCIe Gen5 to PCIe Gen6 (referred to as speed switching), the Retimer chip must quickly adjust the data path, switching from forwarding data path mode to execution data path mode to output data directly at the transmitter. This design decouples the clock data recovery (CDR) locking function of the receiver from the data output function of the transmitter, allowing the transmitter to send data without waiting for the CDR lock of the receiver's physical layer (PHY layer) or the completion of link data processing by the controller. As a result, the Retimer chip can more efficiently utilize the timers in Phase 0 and Phase 1 specified by the PCIe protocol, accelerating the data locking process of the RC and EP, avoiding excessive locking time or equalization failure caused by insufficient PHY layer performance, and significantly improving link stability. This optimization solution is particularly effective in multi-level Retimer cascade scenarios.

[0005] However, the existing technology has the following defects when implementing the above functions:

[0006] (1) Low link establishment efficiency and high failure probability: The data path switching mechanism of existing retimer chips typically requires the receiver to complete data processing before switching to the execution data path. This causes the RC to remain in Phase 1 and the EP to remain in Phase 0 for an extended period of time. When the PHY layer performance of the device in the link is poor, timer timeout may cause the physical layer link establishment to fail, and the probability of failure is particularly prominent.

[0007] (2) Complex circuit implementation and low reliability: Existing technologies usually require additional code stream modification functions and data alignment operations between the forwarding data path and the execution data path when switching data paths. This increases the complexity of circuit design, not only without obvious performance benefits, but also easily introduces errors and reduces system reliability.

[0008] To address these issues, existing technical solutions struggle to balance link establishment efficiency, circuit simplicity, and system stability in high-speed PCIe links. Therefore, a new technical solution is urgently needed that optimizes the data path switching mechanism of the retimer chip, simplifies circuit design, and improves link establishment efficiency and stability to meet the requirements of PCIe Gen6 and future higher-speed PCIe links. Summary of the Invention

[0009] In order to alleviate or partially alleviate the above technical problems, the solutions of the present invention are as follows:

[0010] A method for switching data paths of a retimer controller includes the following steps:

[0011] If the Retimer controller meets the following conditions at the same time: (1) when 8 consecutive TS2 sequences with the speed_change field being 1 are detected from any channel of the upstream pseudo port of the Retimer controller; (2) 8 TS2 sequences with the speed_change field being 1 are detected from any channel of the downstream pseudo port of the Retimer controller; (3) the public maximum rate is PCIe Gen6 and is greater than the current communication rate; (4) it is in FLIT mode; (5) it is in state_forwarding state; the start_equalization_w_preset field is set to 1; after the data transmission rate switching negotiation is completed, the RC, EP and Retimer controller enter the recovery.speed state and perform the data transmission rate switching operation, completing the data transmission rate switching of the PCIe link from PCIe Gen5 to PCIe Gen6; After the retimer controller completes the data transmission rate switch, it exits the recovery.speed state and immediately switches to the recovery.phase0 state; the EP switches to the recovery.phase0 state, and the RC switches to the recovery.phase1 state; After the retimer controller switches to the recovery.phase0 state, the stream generation module immediately starts generating the TS0 sequence and sends it to the RC and EP.

[0012] Furthermore, the RC in the recovery.phase1 state sends the TS0 sequence to the Retimer controller, and the EP in the recovery.phase0 state sends the TS0 sequence to the Retimer controller.

[0013] Furthermore, before the EP switches to the recovery.phase0 state, it first enters the recovery.rcvrlock state; before the RC switches to the recovery.phase1 state, it first enters the recovery.rcvrlock state.

[0014] Furthermore, when detecting the TS2 sequence in the Retimer controller, in addition to detecting whether the speed_change field is 1, it also detects whether the date rate identifier field is 10111b.

[0015] Furthermore, the data transmission path between the RC and the EP passes through multiple Retimer controllers.

[0016] Furthermore, at the beginning of the data path switch, the RC and EP are placed in the recovery.rcvrcfg state, and the Retimer controller is placed in the state_forwarding state.

[0017] Furthermore, after the data transmission rate of the PCIe link is switched from PCIe Gen5 to PCIe Gen6, the Retimer controller immediately switches the data path from the forwarding data path mode to the execution data path mode.

[0018] Furthermore, the RC, the Retimer controller and the EP all include LTSSM.

[0019] Furthermore, the bitstream generation module and the bitstream modification module in the retimer controller serve as optional input modules of the multiplexer. The multiplexer selects the bitstream generation module or the bitstream modification module as the actual input module according to the selection signal output by the LTSSM in the retimer controller.

[0020] A retimer chip includes a retimer controller, the retimer controller including two multiplexers, two bitstream modification modules, and two bitstream generation modules; the retimer controller also includes an LTSSM for sending a selection signal to the multiplexer; the retimer controller also includes a physical layer (PHY) for performing data transmission with an RC and an electronic programmable logic controller (EP), respectively; the multiplexer receives a sequence output by the bitstream modification module or the two bitstream generation modules; the bitstream modification module receives a bitstream output by the PHY layer; and the retimer controller is configured to execute a data path switching method for a retimer controller according to any of the preceding items.

[0021] Furthermore, a data connection is established between the two serially connected Retimer controllers via a PHY layer, and the two Retimer controllers respectively transmit data to the RC and the EP.

[0022] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0023] (1) In the technical solution of the present invention, once the rate cut operation is completed, the system immediately switches to the execution data path. Due to this feature, the data at the receiving end is not forwarded to the output end of another pseudo port. Based on this, the present invention does not require the development of additional stream modification functions, thus reducing the engineering workload.

[0024] (2) Since the switching is performed immediately after the speed cut is completed, the data alignment operation between the forwarding path and the execution path is avoided, and direct switching can be achieved, which greatly simplifies the switching process of the data path, that is, greatly simplifies the circuit implementation, and saves circuit resources.

[0025] (3) Reduces various boundary scenarios of circuit timing, making the system more stable and reliable.

[0026] (4) The robustness of RC and EP in the balancing process is improved, and the risk of RC and EP timeout in the balancing stage is reduced.

[0027] From the perspective of overall circuit implementation, the present invention combines simplicity with high reliability, which is of great significance for complex system engineering.

[0028] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the circuit structure of the Retimer controller switching data path in a single Retimer scenario in the present invention;

[0030] Figure 2 This is a flow chart of the control plane when the Retimer controller switches the data path in the present invention;

[0031] Figure 3 Schematic diagram of the circuit structure of the Retimer controller switching data path in the cascaded Retimer scenario of the present invention. DETAILED DESCRIPTION

[0032] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0033] To facilitate a clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish between identical or similar items having substantially the same functions and effects. Those skilled in the art will appreciate that terms such as "first" and "second" do not limit the quantity or order of execution.

[0034] The present invention involves a variety of professional terms in this field. The meanings of these terms or symbols are explained as follows:

[0035] RC: The root complex of a PCIe system, typically located on a motherboard or within a CPU, is the starting point of the PCIe topology. It manages PCIe bus communications, connecting the CPU, memory, and PCIe devices (such as EP).

[0036] EP: refers to the endpoint device in the PCIe link, usually a functional device such as a graphics processor, network card, storage controller, etc. These devices communicate with the system through the PCIe bus and are responsible for performing specific functional tasks.

[0037] FLIT: Flow Control Unit (FLIT) mode is a new data transmission mode introduced in the PCIe 6.0 specification. As a fixed-size data unit, FLIT plays a key role in flow control and efficient data transmission.

[0038] PHY layer: The physical layer in the retimer controller is mainly used to lock the receiving end data and convert serial data into parallel data when working at the receiving end; and to send data and convert parallel data into serial data.

[0039] LTSSM: Link Training and Status State Machine (LTSSM), responsible for managing the status of the entire link and generating control signals for data path switching. The RC, retimer controller, and EP all include the LTSSM.

[0040] Multiplexer: A data path switching module that determines which path to output data from by selecting a signal.

[0041] OS_MOD: Stream modification module, which can modify the content of the forwarded data stream and forward it to the other end.

[0042] OS_GEN: code stream generation module, which can generate data.

[0043] TS0 / TS1 / TS2: These are different types of training sequences (TS) defined in the PCIe specification. These sequences are used to ensure correct synchronization and configuration between the transmitter and receiver, and are used for link initialization, training, and negotiation. TS1 is used for initialization synchronization, and TS2 is used for link parameter optimization. TS0 was added to PCIe 6.0 and is used together with the previous TS1 and TS2 for link initialization, training, and negotiation.

[0044] EIOSQ: Electrical Idle Ordered Set Sequence (EIOSQ) is an ordered set sequence that must be sent before the link enters the electrical idle state. It is used to inform the link partner that it is about to enter or has entered the electrical idle state. After receiving the EIOSQ, the receiver adjusts its state accordingly to match the electrical idle state.

[0045] recovery.rcvrcfg: This state is used to restore the receiver's configuration when a PCIe link anomaly occurs. In the PCIe protocol, recovery.rcvrcfg is primarily related to receiver configuration recovery. When a PCIe link anomaly occurs, such as signal loss, high bit error rate, or link training failure, the recovery state is entered. recovery.rcvrcfg is a substate within the recovery process, primarily used to reconfigure receiver parameters.

[0046] recovery.speed: This is a sub-state of the PCIe link in the recovery state. The recovery state is entered when a link failure occurs or when the link rate needs to be renegotiated. recovery.speed is mainly used to renegotiate the link transmission rate.

[0047] recovery.rcvrlock: This is a substate of the PCIe link recovery state. Its primary purpose is to resynchronize the clock signals between the transmitter and receiver. After entering the recovery.rcvrlock state, the device uses a specific training sequence and algorithm to readjust the clock phase and frequency, enabling the receiver to accurately sample the data sent by the transmitter, ensuring accurate data transmission.

[0048] recovery.phase0: This is the initial phase of the link recovery process. When a PCIe link loses synchronization or fails due to various reasons (such as signal interference, high bit error rate, power supply fluctuations, etc.), it enters the recovery state. Recovery.phase0 is the first step in the recovery process, primarily initializing the electrical layer, sending idle signals, and preparing for clock synchronization.

[0049] recovery.phase1: This phase follows recovery.phase0. Its main purpose is to further negotiate link configuration parameters based on the recovery.phase0 phase, gradually restoring the link to normal working conditions.

[0050] state_forwarding: This is the data forwarding state when the PCIe link is in normal working order. This state is entered when the link successfully completes the training process and establishes a stable communication connection.

[0051] PCIe Gen5 / PCIe Gen6: These are different generations of the Peripheral Component Interconnect Express (PCIe) standard, and are also used in this document to refer to the data rates of the corresponding versions. PCIe Gen5 has a maximum theoretical bandwidth of 32 GT / s (Gigatransfers per second) per lane, or approximately 4 GB / s per lane in each direction. PCIe Gen6 doubles the data rate to 64 GT / s per lane, or approximately 8 GB / s per lane in each direction.

[0052] The present invention can be applied to single Retimer scenarios and cascaded Retimer scenarios. First, the present invention takes the simplest single Retimer scenario as an example to introduce the Retimer controller data path switching method of the present invention, which is applied to Retimers.

[0053] Figure 1 Schematic diagram of the circuit structure of the Retimer controller switching data path in a single Retimer scenario in the present invention.

[0054] Data transmission between RC and EP can be achieved through the Retimer chip. The Retimer chip includes a Retimer controller.

[0055] The retimer controller includes the PHY layer and performs data transmission with the RC and EP respectively. The RC, EP, and retimer controller each include their own LTSSM: RC LTSSM, EP LTSSM, and Retimer LTSSM.

[0056] For example, the RC and EP can transfer data to and from the PHY layer in the retimer controller. One data transmission path is the RC, PHY, OS_MOD, multiplexer, PHY, and EP. The other data transmission path in the opposite direction is the EP, PHY, OS_MOD, multiplexer, PHY, and RC. The OS_MOD and multiplexer in both transmission paths are independent and distinct modules.

[0057] Furthermore, the bitstream modification module (OS_MOD) and bitstream generation module (OS_GEN) can serve as inputs to the multiplexer, and the selection signal from the Retimer LTSSM determines which input is output. For the different data transmission paths mentioned above, the OS_MOS here are also independent and different.

[0058] Taking the example of RC sending data and forwarding it to EP via the Retimer chip, the following symbols regarding the time required for data transmission in the present invention have the following meanings:

[0059] T0: is the link transmission delay from RC to the upstream pseudo port.

[0060] T1: The time it takes for the PHY layer in the Retimer controller to lock data.

[0061] T2: Data processing time at the receiving end of the Retimer controller.

[0062] T3: Path delay from the stream modification module to the multiplexer.

[0063] T4: Path delay from the bitstream generation module to the multiplexer.

[0064] T5: The time it takes for the sender to process data.

[0065] T6: Transmission delay of the link from the downstream pseudo port to the EP.

[0066] T7: The data lock time of the EP's own PHY layer.

[0067] T8: Data processing time of the receiving link.

[0068] In the existing technical solution, the data processing time at the receiving end of the retimer controller, that is, T2, is the inevitable duration, and T2 is the part with the highest proportion in the entire data transmission path.

[0069] Figure 2 This is a flow chart of the control plane when the Retimer controller switches data paths in the present invention. Figure 2 The terms used in the specification follow those in the PCIe specification. For details, please refer to the explanation of the meaning of the terms in the present invention. Figure 2 The timing of data processing or transmission between the above-mentioned RCLTSSM, EP LTSSM and Retimer LTSSM, as well as the state changes of the RC, EP and Retimer controllers are shown.

[0070] In order to switch the data transmission rate of the PCIe link from PCIe Gen5 to PCIe Gen6, at the beginning of the data path switching, the RC and EP are placed in the recovery.rcvrcfg state, and the Retimer controller is placed in the state_forwarding state.

[0071] If the Retimer controller meets the following conditions at the same time:

[0072] (1) When eight consecutive TS2 sequences with the speed_change field set to 1 are detected from any channel of the upstream pseudo-port of the retimer controller;

[0073] (2) 8 TS2 sequences with the speed_change field set to 1 are detected from any channel of the downstream pseudo port of the retimer controller;

[0074] (3) The public maximum rate is PCIe Gen6, which is greater than the current communication rate;

[0075] (4) in FLIT mode;

[0076] (5) In state_forwarding state;

[0077] Then, set the start_equalization_w_preset field to 1.

[0078] Then, the upstream pseudo port of the retimer controller and the downstream pseudo port of the retimer controller receive the EIOSQ from the RC and EP respectively.

[0079] At this point, the data transmission rate switching negotiation is completed, the RC, EP, and Retimer controllers enter the recovery.speed state and perform data transmission rate switching, completing the data transmission rate switch of the PCIe link from PCIe Gen5 to PCIe Gen6 target.

[0080] After the retimer controller completes the data transmission rate switch, it exits the recovery.speed state and immediately switches to the recovery.phase0 state; the EP also switches to the recovery.phase0 state, and the RC switches to the recovery.phase1 state.

[0081] After the Retimer controller switches to the recovery.phase0 state, the bitstream generation module (OS_GEN) starts working immediately and generates the TS0 sequence.

[0082] Then, the Retimer controller switches the data path from the forwarding data path mode to the execution data path mode, and sends the TS0 sequence generated by the bit stream generation module to the RC and EP.

[0083] Furthermore, the RC in the recovery.phase1 state sends the TS0 sequence to the Retimer controller, and the EP in the recovery.phase0 state sends the TS0 sequence to the Retimer controller.

[0084] Furthermore, before the EP switches to the recovery.phase0 state, it first enters the recovery.rcvrlock state, and before the RC switches to the recovery.phase1 state, it first enters the recovery.rcvrlock state.

[0085] Furthermore, when detecting the TS2 sequence in the Retimer controller, in addition to detecting whether the speed_change field is 1, it also detects whether the date rate identifier field is 10111b.

[0086] According to the above-described embodiment of the present invention, in a single-retimer scenario, the present invention directly sends data after switching the speed, eliminating the time consumed by the retimer chip itself in receiving and processing data. The EP also does not need to wait for the retimer chip to complete data processing before receiving the data. Therefore, the time consumption of the present invention in a single-retimer scenario can be roughly described as T4 + T5 + T6 + T7 + T8.

[0087] Figure 3 Schematic diagram of the circuit structure of the Retimer controller switching data path in the cascade Retimer scenario of the present invention. This example is a two-level Retimer cascade scenario. The time consumption of the present invention can also be approximately described as T4+T5+T6+T7+T8.

[0088] In the cascaded retimer scenario, the data transmission path between the RC and the EP passes through multiple retimer controllers.

[0089] In other words, whether in a multi-stage cascaded Retimer scenario or a single Retimer scenario, the present invention reduces overall processing time compared to existing solutions by eliminating the time consumed by the Retimer chip itself in receiving and processing data. Furthermore, the present invention offers at least the following advantages: it avoids data alignment between the forwarding path and the execution path, enabling direct switching, significantly simplifying the data path switching process, and improving the efficiency and stability of link establishment.

[0090] To better illustrate the present invention, numerous specific details are provided in the detailed description above. Those skilled in the art will appreciate that the present invention can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main purpose of the present invention.

[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for switching data paths of a retimer controller, characterized in that: The steps include: If the Retimer controller meets the following conditions simultaneously: (1) when eight consecutive TS2 sequences with the speed_change field set to 1 are detected from any channel of the upstream pseudo port of the Retimer controller; (2) when eight TS2 sequences with the speed_change field set to 1 are detected from any channel of the downstream pseudo port of the Retimer controller; (3) the public maximum rate is PCIe Gen6 and is greater than the current communication rate; (4) it is in FLIT mode; (5) it is in state_forwarding state; set the start_equalization_w_preset field to 1; After the data rate switching negotiation is complete, the RC, EP, and Retimer controllers enter the recovery.speed state and perform the data rate switching operation, completing the switch of the PCIe link data rate from PCIe Gen5 to PCIe Gen6. After the retimer controller completes the data transmission rate switch, it exits the recovery.speed state and immediately switches to the recovery.phase0 state; the EP switches to the recovery.phase0 state, and the RC switches to the recovery.phase1 state; After the Retimer controller switches to the recovery.phase0 state, the stream generation module immediately starts generating the TS0 sequence and sends it to the RC and EP.

2. The method for switching data paths of a retimer controller according to claim 1, wherein: The RC in the recovery.phase1 state sends the TS0 sequence to the Retimer controller, and the EP in the recovery.phase0 state sends the TS0 sequence to the Retimer controller.

3. The method for switching data paths of a retimer controller according to claim 2, wherein: Before EP switches to the recovery.phase0 state, it first enters the recovery.rcvrlock state; Before RC switches to the recovery.phase1 state, it first enters the recovery.rcvrlock state.

4. The method for switching data paths of a retimer controller according to claim 3, wherein: When detecting the TS2 sequence in the Retimer controller, in addition to detecting whether the speed_change field is 1, it also detects whether the date rate identifier field is 10111b.

5. The method for switching data paths of a retimer controller according to claim 4, wherein: The data transmission path between RC and EP passes through multiple Retimer controllers.

6. The method for switching data paths of a retimer controller according to claim 5, wherein: At the beginning of the data path switch, the RC and EP are placed in the recovery.rcvrcfg state, and the Retimer controller is placed in the state_forwarding state.

7. The method for switching data paths of a retimer controller according to claim 6, wherein: When the data transmission rate of the PCIe link switches from PCIe Gen5 to PCIe Gen6, the retimer controller immediately switches the data path from the forwarding data path mode to the execution data path mode.

8. The method for switching data paths of a retimer controller according to claim 7, wherein: The RC, Retimer controller and EP all include LTSSM; The bitstream generation module and the bitstream modification module in the retimer controller serve as optional input modules of the multiplexer. The multiplexer selects the bitstream generation module or the bitstream modification module as the actual input module according to the selection signal output by the LTSSM in the retimer controller.

9. A retimer chip, comprising a retimer controller, characterized in that: The Retimer controller includes two multiplexers, two bitstream modification modules, and two bitstream generation modules; The retimer controller further includes an LTSSM for sending a selection signal to the multiplexer; The Retimer controller also includes a PHY layer, and performs data transmission with the RC and EP respectively; The multiplexer receives the sequences output by the code stream modification module or the two code stream generation modules; The bit stream modification module receives the bit stream output by the PHY layer; and, The retimer controller is configured to execute the retimer controller data path switching method according to any one of claims 1 to 8.

10. The retimer chip according to claim 9, wherein: A data connection is established between the two serially connected Retimer controllers via the PHY layer, and the two Retimer controllers transmit data to the RC and the EP respectively.

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