A built-in self-test architecture, system and method for in-memory compute macrocells

Abstract

The application relates to a built-in self-test method, architecture and system of an in-memory computing macro unit, comprising the following steps: performing a first test mode: inserting a computing activation vector and a computing enabling instruction in an MBIST test algorithm to perform a computing test after a read operation to detect coupling faults between a storage array and bit multiplication logic; and judging whether storage read results and computing results are correct, if yes, entering a second test mode or judging that self-test is correct and detection is completed, otherwise diagnosing a fault position based on a detection result. The test method provided by the application inserts a computing enabling instruction and a computing activation vector in a traditional MBIST algorithm, verifies an additional multiply-accumulate computing operation after a read operation, and can further effectively detect data coupling between a storage unit and a computing unit under the premise of covering traditional storage fault types, so that the fault coverage is improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically to a built-in self-test architecture, system, and method for in-memory computing macrocells. Background Technology

[0002] With the rapid development of artificial intelligence algorithms and deep neural networks (DNNs), the "memory wall" problem in traditional computing hardware has become increasingly prominent. In-memory computing (CIM) technology, by integrating computing power into memory, effectively reduces data migration costs and power consumption, becoming one of the key technologies for solving this problem.

[0003] In-memory computation macros (DCIMs) are widely deployed in AI chips as computing IPs providing computing power and partial storage. The large number of on-chip DCIMs requires robustness and self-testing capabilities to ensure system-level reliability and testability. Furthermore, as technology scales down and design complexity increases, the probability of chip failure also rises. Therefore, the reliability and testability of DCIMs must be carefully ensured before mass production.

[0004] For traditional memory IP, Built-in Self-Test (BIST) is an effective and fast method to verify its functionality and enhance its reliability in chip design. On-chip BIST enables autonomous and efficient self-testing, reducing reliance on expensive Automated Test Equipment (ATE). BIST has been widely used in SRAM memory, and dedicated memory BIST (MBIST) algorithms, such as MSCAN and Checkerboard, have been developed.

[0005] However, the tight integration of storage units and computational logic in DCIM presents new challenges for chip testing. Because DCIM couples SRAM storage with logic, in addition to the inherent faults in SRAM and computational logic, coupling faults between the two can also cause circuit failures. This is a unique fault characteristic of DCIM. Furthermore, in traditional memory-based BIST, since the read and write data are consistent—that is, the test vector (written data) and the result to be verified (read data) are the same—the result comparison circuit can simply use an XOR structure. However, for DCIM, the calculation result is the multiplication-and-accumulation (MAC) result of the weighted data read from multiple rows of SRAM and the input data. This MAC result is completely different from the input data. For a set of test vectors, the ideal calculation result is called the Golden Result. Generating the Golden Result of the DCIM MAC result requires either additional storage (ROM) or an additional set of equivalent computational circuitry, both of which incur significant area overhead. Moreover, after the MAC operation, the fault location is difficult to pinpoint directly and accurately. Because the input-to-output mapping is many-to-one (i.e., different inputs may produce the same output), traditional memory-based BIST (MBIST) schemes, such as the March algorithm, are insufficient to meet the testing requirements of DCIM (Distributed Memory Imaging Information). This is because they cannot cover computationally coupled faults, resulting in low test coverage and impacting the system reliability and yield of AI chips.

[0006] Currently, most CIM testing uses FPGAs to apply test stress. This testing method is only suitable for testing a small number of chips or single chips, making it difficult to automate and unsuitable for mass production scenarios (rapid screening of large batches of chips is required, and testing each chip individually would consume enormous amounts of time and manpower). Furthermore, this method can only apply test stress from the top layer of the AI ​​chip; for chips integrating multiple CIMs, it is difficult to test and locate faults in each CIM individually.

[0007] Existing technologies have also designed self-test circuits for CIM, but their test vectors / instructions are all generated randomly and do not analyze and cover the fault types specific to in-memory computing, resulting in low test fault coverage.

[0008] Therefore, it is necessary to improve the existing testing architecture and methods for in-memory computing macrocells. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention provides a high-efficiency, low-overhead, and high-fault-coverage built-in self-test architecture for in-memory computing macrocells, comprising: a built-in self-test method for in-memory computing macrocells, characterized by including executing a first test mode:

[0010] The MBIST test algorithm incorporates computation activation vectors and computation enable instructions to perform computational tests after read operations to detect coupling faults between the memory array and its bit multiplication logic; and

[0011] Determine whether the storage read results and calculation results are correct. If so, enter the second test mode or determine that the self-test is correct and complete the test. Otherwise, diagnose the fault location based on the test results.

[0012] The testing method provided in this application, by verifying the insertion computation enable and computation activation vector in the traditional MBIST algorithm after the read operation through the additional multiply-accumulate computation operation, can further effectively detect the unique fault of data coupling between memory cells and computation cells while covering traditional memory fault types, thereby improving fault coverage.

[0013] Optionally, the built-in self-test method for in-memory computing macrocells provided in this application also includes executing a second test mode:

[0014] An automatic test vector is generated using ATPG. The automatic test vector and its corresponding activation vector are then iterated through and multiplied / accumulated to test the computational logic.

[0015] Determine if the calculation result is correct. If not, diagnose the fault location. If yes, determine that the self-test is correct and complete the test.

[0016] The second test mode, as a supplement to the first test mode, constitutes a multi-mode joint test system, which improves the integrity, robustness and reliability of the overall test of the in-memory computing unit. The second test mode automatically generates input modes with high fault coverage through ATPG, thereby improving test efficiency and coverage.

[0017] Optionally, the built-in self-test method for in-memory computing macrocells provided in this application further includes the following steps:

[0018] The mode selection step involves selecting the corresponding test mode based on the test requirements. The test modes include the first test mode, the second test mode, and the sequential test mode.

[0019] If only storage testing is required, execute the first test mode;

[0020] If only computational testing is required, then execute the second test mode; and

[0021] If both storage and computation tests are required, execute the sequential test mode: first execute the first test mode, then execute the second test mode.

[0022] This implementation supports multiple test modes, including storage, computing, and combinations thereof, enabling flexible adaptation to different testing needs and enhancing the versatility and configurability of the test solution. Furthermore, its mode selection mechanism's configuration logic improves the intelligence and automation of the test process, simplifying the test control flow. Finally, on-demand calling avoids redundant testing, improves testing efficiency, shortens testing time, and reduces resource consumption.

[0023] Optionally, the built-in self-testing method for in-memory computing macrocells provided in this application includes the following first test modes:

[0024] Weight writing steps: Sequentially output ascending addresses to the test address channel, and write test data to each row of the storage array through the test weight channel within the corresponding period of each address. This writing operation is synchronously controlled by controlling the "CIM write enable" signal to ensure that all physical addresses of the storage array are loaded with uniform known data, providing a known weight benchmark for subsequent tests.

[0025] Calculation activation step: Re-traverse the address range of the weight writing step, load the test input channel as the activation vector, and pull up the "CIM calculation enable" signal and "CIM read enable" signal to trigger the linked start of the storage array reading and multiplication accumulation calculation path. In each cycle, the storage array reads the weight of the corresponding row and performs parallel bitwise multiplication with the input activation value. Then, it completes the accumulation through the addition tree and outputs the calculation result.

[0026] Result judgment and error detection steps: If the calculation result is consistent with the expected value, the system will proceed to the next test mode or output "BIST correct" as high to complete the test; otherwise, the system will output "BIST correct" as low and proceed to the diagnostic process.

[0027] First, a unified known weight writing mechanism can ensure the predictability of subsequent calculation outputs, provide ideal reference values ​​for fault detection, and improve the controllability and accuracy of testing.

[0028] Secondly, the synchronous control mechanism of CIM write enable and calculation / read enable signals can achieve precise control of the write and calculation process, avoid timing misalignment or test distortion, and enhance test stability.

[0029] Optionally, the built-in self-test method for in-memory computing macrocells provided in this application includes the following second test mode:

[0030] Test vector weight loading steps: Write the automatic test vectors generated by ATPG into the corresponding storage array address row, and control the writing timing through the "CIM write enable" signal to ensure that the automatic test vector data is correctly configured;

[0031] Activation vector loading and calculation triggering steps: After the automatic test vector is written, the system synchronously loads the corresponding activation vector to the calculation path, and at the same time raises "CIM calculation enable" to start the multiply-accumulate operation;

[0032] Result judgment steps: Compare the test results with adjacent columns. If all automatic test vectors pass the test, raise the "BIST test passed" signal and issue the "BIST end" command. If any automatic test vector fails the test, record the error location information and output it.

[0033] The main technical effects of this design include:

[0034] Improve the accuracy of computation path testing: The diverse test vectors generated by ATPG can accurately cover corner errors and interconnection anomalies in complex computation paths.

[0035] Reduce test dependencies: The self-comparison mechanism eliminates the need for a reference golden value, reducing test storage costs and external control complexity.

[0036] Improve timing control stability: Ensure the synchronization and consistency of the testing process through fine control signals such as "CIM write enable" and "CIM calculation enable".

[0037] Automatic diagnosis and feedback mechanism: Once a fault is detected, the system can automatically record the location of the error and output it, enhancing the efficiency of fault location and debugging.

[0038] Highly scalable: Supports expansion to multiple vector tests or different activation combinations, improving the overall flexibility of BIST.

[0039] To achieve the above-mentioned objectives, this application provides a built-in self-test architecture for in-memory computing macrocells, comprising:

[0040] The MBIST module is configured to generate test addresses and test weights for testing the memory array of the in-memory computing macrocells in a first test mode.

[0041] The LBIST module is configured to generate test inputs for detecting coupling faults between the storage array and its bit multiplication logic in a first test mode, and to provide automatic test vectors for testing the computational logic of the in-memory computation macrocells in a second test mode.

[0042] The BIST controller is connected to the MBIST module and the LBIST module and is used to control the operation of the MBIST module and the LBIST module.

[0043] A multiplexer network, connected between the BIST controller, the MBIST module, the LBIST module, and the in-memory computation macrocell, is used to switch the input corresponding to the mode between functional mode and test mode; and

[0044] The diagnostic unit, connected to the BIST controller, is used to analyze and output the fault location based on test feedback information.

[0045] Optionally, the MBIST module includes:

[0046] The storage decoder is used to generate test weights; and

[0047] A storage counter, connected to the storage decoder, is used to generate test addresses.

[0048] Optionally, the LBIST module includes:

[0049] A logic decoder is used to generate test inputs and automatic test vectors; and

[0050] A logic counter, connected to the logic decoder, is used to control the timing of the automatic test vectors.

[0051] To achieve the aforementioned objectives, this application provides a built-in self-test system for in-memory computing macrocells, comprising the built-in self-test architecture for in-memory computing macrocells described above, and further comprising:

[0052] In-memory computing macrounits are connected to the built-in self-test architecture; and

[0053] The comparison unit, connected to the in-memory computing macro unit and the diagnostic unit, is capable of comparing the storage test results and / or calculation test results of the in-memory computing macro unit with preset values, and sending storage error information and / or logic error information to the diagnostic unit.

[0054] Optionally, the comparison unit includes a logic comparator and a storage comparator, which are used to calculate the test result comparison and store the test result comparison, respectively. The logic comparator determines whether the calculation result is correct based on the consistency of the calculation results of two adjacent columns. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of a typical fault model for an in-memory computing array.

[0056] Figure 2This is a schematic diagram of the built-in self-test system for in-memory computing macrocells provided by an embodiment of the present invention.

[0057] Figure 3 yes Figure 2 A schematic diagram of the structure of a logic comparator.

[0058] Figure 4 This is a flowchart illustrating the first test mode in the built-in self-test method for in-memory computing macrocells provided by an embodiment of the present invention.

[0059] Figure 5 This is a flowchart illustrating the second test mode in the built-in self-test method for in-memory computing macrocells provided by an embodiment of the present invention.

[0060] Figure 6 This is a timing diagram of the built-in self-test method for in-memory computing macrocells provided by an embodiment of the present invention.

[0061] Figure 7 This is a schematic diagram illustrating the steps of a built-in self-test method for in-memory computing macrocells provided by an embodiment of the present invention.

[0062] Figure 8 This is a schematic diagram illustrating the steps of a built-in self-test method for in-memory computing macrocells provided by an embodiment of the present invention.

[0063] Figure 9 This is a schematic diagram illustrating the steps of a built-in self-test method for in-memory computing macrocells provided by an embodiment of the present invention. Detailed Implementation

[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0065] Figure 1 This diagram illustrates an in-memory computing array and two typical failure models. The in-memory computing array is used to perform the following operations:

[0066] Vector-matrix multiplication (VMM) or matrix-matrix multiplication (MMM), i.e., Y = W × A;

[0067] Where A is the input vector or input matrix, which is input through address lines A0, A1, ..., AM; W is the weight matrix, which is stored in memory cells; and Y is the output vector or matrix, representing the result after weighted calculation.

[0068] Continue to refer to Figure 1 The weight storage unit W{i,j} is responsible for storing the weight value of the i-th row and j-th column, and is generally implemented using technologies such as SRAM, RRAM and FeRAM.

[0069] The bitwise multiplication unit, also known as the multiplier ×, receives the corresponding input Ai in each row and performs parallel multiplication with the weights of each column: W{i,j}*Ai.

[0070] An adder array accumulates the multiplication results of all rows in the same column to achieve vector dot product.

[0071] The multi-column calculation structure selects different column results and outputs them to Y{0,0} to Y{0,N}.

[0072] Of the two typical fault models, the first is the weight-input coupling fault. The fault is located between the input signal and the weight storage unit. There is electrical coupling between the input and the weight, which may cause voltage disturbances, leading to instability when reading the stored weight. The input signal may also affect the stability of the storage unit, causing errors in the read weight, ultimately resulting in incorrect weight values ​​in the multiplication calculation. Even if the input is correct, it may still lead to incorrect results.

[0073] The second type is the weight-bit multiplication result coupling fault, which is located between the weight storage unit and the multiplication result output terminal. The stored weight value affects the multiplier result output line during the output process. It may cause the weight to change, resulting in the output multiplication result being contaminated. It may also cause the original result to be interfered with by the bypass signal in the output stage. Ultimately, even if the input and weight are correct, the final result may be wrong due to the weight affecting the output path.

[0074] Because DCIM couples SRAM storage with logic, in addition to the inherent failures of SRAM and computation logic, failures in this coupling can also cause circuit failures. This is a unique fault characteristic of DCIM. After discovering this unique fault caused by the characteristics of in-memory computation, the applicant has proposed a highly efficient, low-overhead, and high-fault-coverage built-in self-test architecture 100 for in-memory computation macrocells, such as... Figure 2 As shown, it includes:

[0075] MBIST module 10 is used to generate test stimuli for the storage path in the in-memory computing macrocell 200. Specifically, MBIST module is configured to generate test addresses and test weights for testing the storage array of the in-memory computing macrocell in a first test mode. MBIST module 10 includes: storage decoder 11, used to generate test weights and decode them into control signals; and storage counter 12, connected to storage decoder 11, used to generate test addresses.

[0076] The LBIST module 20 is used to generate test stimuli for the computation path in the in-memory computation macrocell 200. Specifically, it is configured to generate test inputs for detecting coupling faults between the memory array and its bit multiplication logic in a first test mode, and to provide automatic test vectors for testing the computation logic of the in-memory computation macrocell 200 in a second test mode. The LBIST module 20 includes: a logic decoder 21 for generating test inputs and automatic test vectors for logic functional units; and a logic counter 22 connected to the logic decoder 21 for controlling the timing of the automatic test vectors.

[0077] BIST controller 30 is connected to MBIST module 10 and LBIST module 20 and is used to control the operation of MBIST module 10 and LBIST module 20.

[0078] A multiplexer network 40, connected between the BIST controller 30, the MBIST module 10, the LBIST module 20, and the in-memory computation macrounit 200, is capable of switching between functional and test modes and selecting inputs corresponding to the mode; and

[0079] The diagnostic unit 50, connected to the BIST controller 30, is used to analyze and output the fault location and / or fault type based on test feedback information.

[0080] Specifically, the multiplexer network 40 includes: a weight selector 41 for selectively inputting test weights or functional weights, an input selector 42 for selectively inputting test inputs or functional inputs (matrix or vector), an address selector 43 for selectively inputting test addresses or logic counter outputs, and a control signal selector 44 for selectively inputting test control signals or control signals. The input of each selector is determined by the output instructions of the BIST controller 30. In other words, each selector selectively operates in test mode or functional mode under the control of the BIST controller 30.

[0081] Specifically, the logic decoder 21 is configured to integrate an ATPG for generating test vectors. The ATPG is an automated tool used to generate test vectors for digital circuits. Its goal is to detect specific types of faults (such as open circuits, short circuits, coupling, delays, etc.) to verify whether the chip has manufacturing defects or functional failures. In some implementations, the ATPG can be set separately from the logic decoder 21 and connected to the logic decoder.

[0082] Continue to refer to Figure 2 This embodiment also provides a built-in self-test system for an in-memory computing macrocell, including an in-memory computing macrocell built-in self-test architecture 100, an in-memory computing macrocell 200, and a comparison unit 300.

[0083] Optionally, the comparison unit 300 includes a logic comparator 310 and a storage comparator 320, used for calculating test result comparison and storing test result comparison, respectively. More specifically, the logic comparator 310 determines whether the calculation result is correct based on the consistency of the calculation results of two adjacent columns, such as... Figure 3 As shown, in this embodiment, since a self-comparison method is used, there is no need to generate an additional ideal reference calculation result. The calculation can be judged as correct by inputting the same activation and weight in each column and further by comparing the consistency of the calculation results between adjacent columns, which greatly reduces the additional hardware overhead.

[0084] The in-memory computing macro unit 200 is connected to the built-in self-test architecture 100. The comparison unit 300 is connected to the in-memory computing macro unit 200 and the diagnostic unit 50. It can compare the storage test results and / or computing test results of the in-memory computing macro unit 200 with preset values ​​and send storage error information and / or logic error information to the diagnostic unit 50.

[0085] This embodiment also provides a built-in self-testing method for in-memory computing macrocells, which includes a first test mode and a second test mode. Figure 4 The flowchart for the first test mode is as follows: After the first test mode starts, a basic memory is selected to test the algorithm. The test algorithm is executed, and computation enable and computation activation vectors are inserted to perform computation testing after the read operation. The correctness of the memory read result and computation result is determined. If not, the error location is diagnosed. If so, it is further determined whether it is the last step of the algorithm. If so, the BIST is output as correct. If not, the process returns to the step of executing the test algorithm and inserting computation enable and computation activation vectors to perform computation testing after the read operation.

[0086] Figure 5 This is a flowchart of the second test mode. After the second test mode starts, the ATPG test vector is traversed to determine whether the calculation result is correct. If not, the error location is diagnosed. If yes, it is further determined whether it is the last test vector. If yes, the BIST is output as correct. If not, it returns to traversing the ATPG test vector.

[0087] The following is combined with Figure 6 right Figure 2 The working principle of the built-in self-test architecture 100 of the in-memory computing macrocell shown in the figure is explained. After receiving the BIST enable signal, the BIST controller 30 uses the multiplexer network 40 to select the test control signal, test weight, test input, and test address. If the test instruction requires both the storage function and the computing function to be tested:

[0088] First, the first test mode is executed: MBIST (Memory Built-In Self-Test) module 10, which is the built-in memory self-test module, based on the traditional MBIST algorithm, such as March C. - Algorithm; then execute address traversal and weight writing steps: BIST controller 30 sequentially outputs ascending addresses (0~511) to the test address channel. In each address corresponding period, all-1 test data is written to each row of SRAM through the test weight channel. This write operation is synchronously controlled by controlling the "CIM write enable" signal. The purpose is to ensure that all physical addresses of SRAM are loaded with uniform known data, so as to provide a known weight benchmark for subsequent tests.

[0089] After the write operation is complete, the calculation activation step is executed: the BIST controller 30 retraces the address range (0~511). During this stage, the test input (also known as input activation) channel is loaded as a 32-bit all-one activation vector (i.e., 32'hffffffff), and the "CIM Calculation Enable" signal and the "CIM Read Enable" signal are pulled high to trigger the simultaneous start of SRAM read and multiply-accumulate calculation paths. In each cycle, the SRAM reads the all-one weight of the corresponding row and performs a parallel bitwise multiplication operation with the input activation value. Then, the accumulation is completed through the addition tree, and the calculation result is output.

[0090] After the calculation is completed, the system will proceed to the result judgment and error detection steps: The expected output of the system is the sum of the product of the 32-bit all-1 weight and the 32-bit all-1 activation, i.e., a fixed value. This calculation output will be sent to the logic comparator for result judgment. If the calculated value matches the expected value, the system will proceed to the next test mode; otherwise, the system will output "BIST correct" as low and proceed to the diagnostic process.

[0091] In this testing phase, the logic comparator is used to compare whether the final accumulated result is the expected value. Since the intermediate paths (read, calculation, and storage) all participate in data transfer, it effectively covers SRAM bitcell faults, read path errors, partial faults of multipliers / adders, and coupling defects in the data path.

[0092] It should be noted that the test input of all 1s is only for illustrative purposes. Different test inputs can be selected for different basic MBIST algorithms and different steps of the same MBIST algorithm to test the corresponding algorithm.

[0093] The testing method provided in this embodiment, by verifying the insertion calculation enable and calculation activation vector in the traditional MBIST algorithm after the read operation through the additional multiply-accumulate calculation operation, can further effectively detect the unique fault of data coupling between memory cells and computing cells while covering traditional memory fault types, thus improving fault coverage.

[0094] If the settlement value executed in the first test mode is consistent with the expected value, then the second test mode (also known as entering the second test phase) is executed. This phase mainly targets the coverage test of complex combinational logic structures such as multipliers and addition trees in the CIM structure, using stimulus and expectation pairs generated in advance by the Automatic Test Vector Generation Tool (ATPG).

[0095] The second testing mode includes the following steps:

[0096] Test vector weight loading steps: The BIST controller 30 writes the weight vectors (W0, W1, ... W31) generated by ATPG (Automatic Test Pattern Generation) sequentially into the corresponding SRAM address rows in ascending order. The weight data width is 256 bits, and each group of weights corresponds to a specific activation vector used to combine test calculation paths. During the loading process, the "CIM write enable" signal controls the write timing to ensure that the weight data is configured correctly.

[0097] Activation vector loading and calculation triggering steps: After the weights are written, the system synchronously loads the corresponding activation vectors (A0, A1, ... Ai) into the calculation path, and simultaneously raises the "CIM calculation enable" to start the multiply-accumulate operation. During this process, the multiplier output will be compared and judged again by the self-comparison module to verify its functional correctness.

[0098] Result determination steps: After all ATPG vector tests pass, the BIST controller raises the BIST pass indicator and issues a "BIST end" command, completing the entire BIST process. If any test fails, the BIST controller 30 records the error location information and outputs the error location information through the diagnostic unit.

[0099] It should be noted that the BIST test is considered passed only when both BIST values ​​are correct and the end value of BIST is 1.

[0100] Optionally, if only the storage function needs to be tested, only the steps of the first test mode can be executed; similarly, if only the logical function needs to be tested, only the steps of the second test mode can be executed. Specifically, such as Figure 4 As shown, a built-in self-testing method for an in-memory computing macrocell also includes a mode selection step. If only storage testing is required, the first test mode is entered; if only computing / logic testing is required, the second test mode is entered; if both storage and computing testing are required, the sequential test mode is executed, that is, the relevant steps of the first test mode are executed first, and then the relevant steps of the second test mode are executed.

[0101] Optionally, such as Figure 7As shown, this embodiment provides a built-in self-test method for in-memory computing macrocells, including the following steps:

[0102] The MBIST test algorithm incorporates computation activation vectors and computation enable instructions to perform computational tests after read operations to detect coupling faults between the memory array and its bit multiplication logic; and

[0103] Determine whether the storage read results and calculation results are correct. If so, enter the second test mode or determine that the self-test is correct and complete the test. Otherwise, diagnose the fault location based on the test results.

[0104] Optionally, such as Figure 8 As shown, the built-in self-testing method for an in-memory computing macrocell provided in this embodiment further includes executing a second test mode:

[0105] An automatic test vector is generated using ATPG. The automatic test vector and its corresponding activation vector are then iterated through and multiplied / accumulated to test the computational logic.

[0106] Determine whether the stored read results and calculation results are correct. If not, diagnose the fault location. If yes, determine that the self-test is correct and complete the test.

[0107] Optionally, such as Figure 9 As shown, the built-in self-test method for in-memory computing macrocells provided in this embodiment further includes the following steps:

[0108] The test mode selection process involves choosing the appropriate test mode based on the test requirements. Test modes include the first test mode, the second test mode, and the sequential test mode.

[0109] If only storage testing is required, execute the first test mode;

[0110] If only computational testing is required, then execute the second test mode; and

[0111] If both storage and computation tests are required, execute the sequential test mode: first execute the first test mode, then execute the second test mode.

[0112] Optionally, the first test mode includes:

[0113] Weight writing steps: Sequentially output ascending addresses to the test address channel, and write test data to each row of the storage array through the test weight channel within the corresponding period of each address. This writing operation is synchronously controlled by controlling the "CIM write enable" signal to ensure that all physical addresses of the storage array are loaded with uniform known data, providing a known weight benchmark for subsequent tests.

[0114] Calculation activation step: Retrace the address range of the weight writing step, load the test input channel as the activation vector, pull up the "CIM calculation enable" signal and the "CIM read enable" signal to trigger the linked start of the storage array reading and multiplication accumulation calculation path. In each cycle, the storage array reads the weight of the corresponding row and performs parallel bitwise multiplication with the input activation value. Then, it completes the accumulation through the addition tree and outputs the calculation result.

[0115] Result judgment and error detection steps: If the calculation result is consistent with the expected value, the system will proceed to the next test mode or output "BIST Correct" as high to complete the test; otherwise, the system will output "BIST Correct" as low to perform error diagnosis.

[0116] Optionally, the second test mode includes:

[0117] Test vector weight loading steps: Write the automatic test vectors generated by ATPG into the corresponding storage array address row, and control the writing timing through the "CIM write enable" signal to ensure that the automatic test vector data is correctly configured;

[0118] Activation vector loading and calculation triggering steps: After the automatic test vector is written, the system synchronously loads the corresponding activation vector into the calculation path, raises the "CIM calculation enable" and starts the multiply-accumulate operation;

[0119] Result judgment steps: Compare the test results with adjacent columns. If all automatic test vectors pass the test, raise the "BIST Correct" signal and issue the "BIST End" command. If any automatic test vector fails the test, record the error location information and output it.

[0120] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A built-in self-test method for in-memory computing macrocells, characterized in that, Including executing the first test mode: The MBIST test algorithm inserts computation activation vectors and computation enable instructions to perform computation tests after read operations to detect faults in the memory array and its coupling with bit multiplication logic. as well as Determine whether the storage read result and calculation result are correct. If so, enter the second test mode or determine that the self-test is correct and complete the test. Otherwise, diagnose the fault location based on the test result. The second test mode includes: Test vector weight loading steps: Write the automatic test vectors generated by ATPG into the corresponding storage array address row, and control the writing timing through the "CIM write enable" signal to ensure that the automatic test vector data is correctly configured; Activation vector loading and calculation triggering steps: After the automatic test vector is written, the system synchronously loads the corresponding activation vector to the calculation path, and at the same time raises "CIM calculation enable" to start the multiply-accumulate operation; Result judgment steps: Compare the test results with adjacent columns. If all automatic test vectors pass the test, raise the "BIST test passed" signal and issue the "BIST end" command. If any automatic test vector fails the test, record the error location information and output it.

2. The built-in self-test method for in-memory computing macrocells according to claim 1, characterized in that, This also includes executing a second test mode: An automatic test vector is generated using ATPG. The automatic test vector and its corresponding activation vector are then iterated through and multiplied / accumulated to test the computational logic. Determine if the calculation result is correct. If not, diagnose the fault location. If yes, determine that the self-test is correct and complete the test.

3. The built-in self-test method for in-memory computing macrocells according to claim 2, characterized in that, It also includes the following steps: The mode selection step involves selecting the corresponding test mode based on the test requirements. The test modes include the first test mode, the second test mode, and the sequential test mode. If only storage testing is required, then execute the first test mode; If only computational testing is required, then execute the second test mode; as well as If both storage and computation tests are required, execute the sequential test mode: first execute the first test mode, then execute the second test mode.

4. The built-in self-test method for in-memory computing macrocells according to claim 3, characterized in that, The first test mode includes: Weight writing steps: Sequentially output ascending addresses to the test address channel, and write test data to each row of the storage array through the test weight channel within the corresponding period of each address. This writing operation is synchronously controlled by controlling the "CIM write enable" signal to ensure that all physical addresses of the storage array are loaded with uniform known data, providing a known weight benchmark for subsequent tests. Calculation activation step: Re-traverse the address range of the weight writing step, load the test input channel as the activation vector, pull up the "CIM calculation enable" signal and the "CIM read enable" signal to trigger the linked start of the storage array reading and multiplication accumulation calculation path. In each cycle, the storage array reads the weight of the corresponding row and performs parallel bitwise multiplication with the input activation value. Then, it completes the accumulation through the addition tree and outputs the calculation result. Result judgment and error detection steps: If the calculation result is consistent with the expected value, the system will proceed to the next test mode or output "BIST correct" as high to complete the test; otherwise, the system will output "BIST correct" as low and proceed to the diagnostic process.

5. A built-in self-test architecture for in-memory computing macrocells, employing the built-in self-test method for in-memory computing macrocells as described in any one of claims 1-4, characterized in that, include: The MBIST module is configured to generate test addresses and test weights for testing the memory array of the in-memory computing macrocells in a first test mode. The LBIST module is configured to generate test inputs for detecting coupling faults between the storage array and its bit multiplication logic in a first test mode, and to provide automatic test vectors for testing the computational logic of the in-memory computation macrocells in a second test mode. The BIST controller is connected to the MBIST module and the LBIST module and is used to control the operation of the MBIST module and the LBIST module. A multiplexer network, connected between the BIST controller, the MBIST module, the LBIST module, and the in-memory computing macrocell, is used to switch the input corresponding to the mode between the functional mode and the test mode; as well as The diagnostic unit, connected to the BIST controller, is used to analyze and output the fault location based on test feedback information.

6. The built-in self-test architecture for in-memory computing macrocells according to claim 5, characterized in that, The MBIST module includes: The storage decoder is used to generate test weights; and A storage counter, connected to the storage decoder, is used to generate test addresses.

7. The built-in self-test architecture for in-memory computing macrocells according to claim 5, characterized in that, The LBIST module includes: A logic decoder is used to generate test inputs and automatic test vectors; and A logic counter, connected to the logic decoder, is used to control the timing of the automatic test vectors.

8. A built-in self-test system for in-memory computing macrocells, comprising the built-in self-test architecture for in-memory computing macrocells as described in any one of claims 5-7, characterized in that, Also includes: The in-memory computing macrounit is connected to the built-in self-test architecture; as well as The comparison unit, connected to the in-memory computing macro unit and the diagnostic unit, is capable of comparing the storage test results and / or calculation test results of the in-memory computing macro unit with preset values, and sending storage error information and / or logic error information to the diagnostic unit.

9. The built-in self-test system for in-memory computing macrocells according to claim 8, characterized in that, The comparison unit includes a logic comparator and a storage comparator, which are used to calculate test result comparison and store test result comparison, respectively. The logic comparator determines whether the calculation result is correct based on the consistency of the calculation results of two adjacent columns.

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