Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises a first reset signal network. The first reset signal network includes a plurality of first reset signal lines and a plurality of first rings interconnected together. Each of the plurality of first rings is connected to two adjacent first reset signal lines of the plurality of first reset signal lines, respectively. Each of the plurality of first reset signal lines is connected to the two first rings, respectively. The two first rings are located in the two adjacent rows of sub-pixels respectively.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light-emitting diode (OLED) displays are one of the hot topics in the field of flat panel display research today. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. The OLED display panel includes a plurality of pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied from the data line to the driving transistor via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the Invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising a first reset signal network; wherein the first reset signal network comprises a plurality of first reset signal lines and a plurality of first rings interconnected together; each first ring in the plurality of first rings is respectively connected to two adjacent first reset signal lines in the plurality of first reset signal lines; each first reset signal line in the plurality of first reset signal lines is respectively connected to two first rings; the two first rings are respectively located in two adjacent rows of sub-pixels.

[0004] Optionally, each of the first reset signal lines includes a first body and a plurality of first branches connected to the first body; the first body extends along a first direction; each of the plurality of first branches extends along a second direction; the first direction and the second direction are different from each other; and each of the first branches is respectively connected to two first rings.

[0005] Optionally, the plurality of first rings are located in a different layer from the plurality of first reset signal lines; and each of the first reset signal lines is connected to a corresponding first ring through a via extending through at least one layer comprising insulating material.

[0006] Optionally, the plurality of first rings are located in the third gate metal layer; the plurality of first reset signal lines are located in the first signal line layer; and each first reset signal line is connected to a corresponding first ring through a via extending through the passivation layer.

[0007] Optionally, the array substrate includes a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits includes a first reset transistor; the first electrodes of the two first reset transistors in two adjacent pixel driving circuits in the same row are part of the overall structure; and the respective first reset signal lines are connected to the overall structure including the first electrodes of the two first reset transistors in the two adjacent pixel driving circuits in the same row through a first single via.

[0008] Optionally, the overall structure also includes the active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row; and the orthographic projections of the respective first reset signal lines on the substrate at least partially overlap with the orthographic projections of the active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row on the substrate.

[0009] Optionally, the array substrate includes a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits includes a data writing transistor, a compensation transistor, a first light emitting control transistor and a driving transistor; the positive projection of each first branch on the substrate separates the positive projections of two adjacent integral structures from two adjacent pixel driving circuits on the substrate; and each integral structure in the two adjacent integral structures includes the second electrode of the data writing transistor, the second electrode of the first light emitting control transistor and at least part of the first electrode of the driving transistor.

[0010] Optionally, the array substrate includes a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits includes a compensation transistor, a driving transistor, a third reset transistor and a third node connection line; the third node connection line is connected to the first electrode of the compensation transistor through a first via, is connected to the second electrode of the third reset transistor through a second via, and is connected to the second electrode of the driving transistor through a third via.

[0011] Optionally, the orthographic projections of the first branches on the base substrate separate the orthographic projections of two adjacent third node connection lines from two adjacent pixel driving circuits on the array substrate.

[0012] Optionally, the array substrate further includes a plurality of first gate lines; wherein the orthographic projections of the third node lines on the base substrate partially overlap with the orthographic projections of the corresponding first gate lines on the base substrate.

[0013] Optionally, the array substrate further includes a plurality of second gate lines; wherein the orthographic projections of the third node lines on the base substrate partially overlap with the orthographic projections of the corresponding second gate lines on the base substrate.

[0014] Optionally, the array substrate further includes a plurality of data lines; wherein the orthographic projections of the respective first branches on the base substrate separate the orthographic projections of two adjacent data lines among the plurality of data lines on the base substrate.

[0015] Optionally, the array substrate further includes a second reset signal network; wherein the second reset signal network includes a plurality of second reset signal lines and a plurality of second rings interconnected together; each second ring in the plurality of second rings is respectively connected to two adjacent second reset signal lines in the plurality of second reset signal lines; each second reset signal line in the plurality of second reset signal lines is respectively connected to two second rings; and the two second rings are respectively located in two adjacent rows of sub-pixels.

[0016] Optionally, each of the second reset signal lines includes a second body and a plurality of second branches connected to the second body; the second body extends along a first direction; each of the plurality of second branches extends along a second direction; the first direction and the second direction are different from each other; and each of the second branches is respectively connected to two second rings.

[0017] Optionally, the plurality of second rings are located in a different layer from the plurality of second reset signal lines; and each of the second reset signal lines is connected to a corresponding second ring through a via extending through at least one layer comprising insulating material.

[0018] Optionally, the plurality of second rings are located in the third gate metal layer; the plurality of second reset signal lines are located in the first signal line layer; and each second reset signal line is connected to a corresponding second ring through a via extending through the passivation layer.

[0019] Optionally, the array substrate includes a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits includes a second reset transistor; the first electrodes of the two second reset transistors in two adjacent pixel driving circuits in the same row are part of the overall structure; and the respective second reset signal lines are connected to the overall structure including the first electrodes of the two second reset transistors in the two adjacent pixel driving circuits in the same row through a second single via.

[0020] Optionally, the overall structure also includes the active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row; and the positive projections of the respective second reset signal lines on the substrate at least partially overlap with the positive projections of the active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row on the substrate.

[0021] Optionally, each of the first rings surrounds a window area in the array substrate, wherein accessories are installed in the window area.

[0022] On the other hand, the present disclosure provides an array substrate, including a second reset signal network; wherein the second reset signal network includes a plurality of second reset signal lines and a plurality of second rings interconnected together; each second ring in the plurality of second rings is respectively connected to two adjacent second reset signal lines in the plurality of second reset signal lines; each second reset signal line in the plurality of second reset signal lines is respectively connected to two second rings; and the two second rings are respectively located in two adjacent rows of sub-pixels.

[0023] In another aspect, the present disclosure provides a display device comprising the array substrate described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings are examples for illustration purposes only, in accordance with various disclosed embodiments, and are not intended to limit the scope of the invention.

[0025] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0026] Figure 2A is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 2B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0028] Figure 3A is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0029] Figure 3B It shows Figure 3A Schematic diagram of the arrangement of pixel driving circuits in the array substrate depicted in FIG.

[0030] Figure 3C It shows Figure 3A Schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG.

[0031] Figure 3D It shows Figure 3A Schematic diagram of the structure of the first gate metal layer in the array substrate depicted in FIG.

[0032] Figure 3E It shows Figure 3A Schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG.

[0033] Figure 3F It shows Figure 3A Schematic diagram of a via extending through the first interlayer dielectric layer in an array substrate depicted in FIG.

[0034] Figure 3G It shows Figure 3A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in .

[0035] Figure 3H It shows Figure 3A Schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate depicted in FIG.

[0036] Figure 3I It shows Figure 3A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG.

[0037] Figure 3J It shows Figure 3A Schematic diagram of a via extending through a passivation layer in an array substrate is depicted in FIG.

[0038] Figure 3K It shows Figure 3A Schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0039] Figure 3L It shows Figure 3A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG.

[0040] Figure 3M It shows Figure 3A Schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0041] Figure 3N It shows Figure 3A Schematic diagram of a via extending through the second planarization layer in an array substrate depicted in FIG.

[0042] Figure 3O It shows Figure 3A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0043] Figure 3P It shows Figures 3C to 3M Schematic diagram of the superposition structure.

[0044] Figure 3Q It shows Figures 3C to 3K Schematic diagram of the superposition structure.

[0045] Figure 4 It is along Figure 3A Cross-sectional view along line AA'.

[0046] Figure 5 is a schematic diagram illustrating a first reset signal network in an array substrate according to some embodiments of the present disclosure.

[0047] Figure 6 is a schematic diagram illustrating a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0048] Figure 7 is a schematic diagram illustrating a plurality of first reset signal lines and a plurality of data lines in an array substrate according to some embodiments of the present disclosure.

[0049] Figure 8A is a circuit diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 8B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. DETAILED DESCRIPTION

[0051] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise forms disclosed.

[0052] The present disclosure particularly provides an array substrate and a display device that substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a first reset signal network. Optionally, the first reset signal network includes a plurality of first reset signal lines and a plurality of first rings interconnected together. Optionally, each first ring in the plurality of first rings is respectively connected to two adjacent first reset signal lines in the plurality of first reset signal lines. Optionally, each first reset signal line in the plurality of first reset signal lines is respectively connected to two first rings. Optionally, the two first rings are respectively located in two adjacent rows of sub-pixels.

[0053] Various suitable pixel drive circuits can be used in this array substrate. Examples of suitable drive circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each of the multiple pixel drive circuits is an 8T1C drive circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0054] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of voltage supply lines Vdd, and respective second voltage supply lines (for example, a low voltage supply line Vss). The light emission of each sub-pixel Sp is driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (for example, a VDD signal) is input to a corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through each high voltage supply line among the plurality of voltage supply lines Vdd; a low voltage signal (for example, a VSS signal) is input to the cathode of the light-emitting element through the low voltage supply line. The voltage difference between the high voltage signal (for example, the VDD signal) and the low voltage signal (for example, the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0055] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to the first electrode of a third reset transistor Tr3; a third reset transistor Tr3 having a gate connected to a corresponding second gate line among a plurality of second gate lines GL2, a first electrode connected to the second electrode of the second reset transistor Tr2, and a second electrode connected to the second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines, a first electrode connected to the second electrode of the driving transistor The first and second electrodes of the first transistor T1 and the second transistor T2 are connected to the first and second electrodes of the first and second transistors T3. The first and second transistors T3 have a gate connected to a corresponding light emitting control signal line em among a plurality of light emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the drive transistor Td and the second electrode of the first transistor T1. The fourth transistor T4 has a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to the second electrode of the drive transistor Td and the first electrode of the second transistor T2, and a second electrode connected to the anode of the light emitting element LE. The first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0056] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0057] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the third reset transistor Tr3. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0058] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in an S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents a corresponding first subpixel of a first color, C2 represents a corresponding second subpixel of a second color, C3 represents a corresponding third subpixel of a third color, and C2' represents a corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is an RGBG format, where a corresponding first subpixel is a red subpixel, a corresponding second subpixel is a green subpixel, a corresponding third subpixel is a blue subpixel, and a corresponding fourth subpixel is a green subpixel.

[0059] In some embodiments, a minimum repeating unit of a plurality of sub-pixels of an array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td.

[0060] The present disclosure may be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Figure 2A, the second transistor T2 and the fourth transistor T4 are n-type transistors, such as metal oxide transistors, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the valid control signal (e.g., the on control signal) is a low voltage signal, while the invalid control signal (e.g., the off control signal) is a high voltage signal. For n-type transistors, the valid control signal (e.g., the on control signal) is a high voltage signal, while the invalid control signal (e.g., the off control signal) is a low voltage signal.

[0061] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0062] Figure 2B 1 is a timing diagram illustrating the operation of the pixel driving circuit in some embodiments of the present disclosure. Figure 2A and Figure 2B During one frame of image, the operation of the pixel driving circuit includes a first sub-phase t1, a second sub-phase t2, a third sub-phase t3, a fourth sub-phase t4, a fifth sub-phase t5, a sixth sub-phase t6 and a seventh sub-phase t7.

[0063] In the first sub-phase t1, a reset control signal is supplied to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, thereby turning on the first reset transistor Tr1. This causes the initialization voltage signal from the corresponding first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1 and further to the fourth node N4. The anode of the light-emitting element LE is initialized. A reset control signal is supplied to the gate of the second reset transistor Tr2 via a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, thereby turning on the second reset transistor Tr2. A reset control signal for the third reset transistor Tr3 is supplied to the gate of the third reset transistor Tr3 via a corresponding second gate line GL2 among a plurality of second gate lines, thereby turning on the third reset transistor Tr3. This causes the initialization voltage signal from the corresponding second reset signal line Vint2 among a plurality of second reset signal lines to be transmitted through the second and third reset transistors Tr2 and Tr3 and further to the third node N3. The second electrode of the drive transistor Td is initialized. In the first sub-phase t1, a turn-off control signal for the second transistor T2 is provided to the gate of the second transistor T2 via each of the plurality of second gate lines GL2, thereby turning off the second transistor T2. In the first sub-phase t1, a turn-off reset control signal for the fourth transistor T4 is provided to the gate of the fourth transistor T4 via a corresponding second reset control signal line rst2 from the plurality of second reset control signal lines, thereby turning off the fourth transistor T4.

[0064] In the second sub-phase t2, a reset control signal is provided to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among the plurality of first reset control signal lines, thereby turning on the first reset transistor Tr1. A reset control signal for the fourth transistor T4 is provided to the gate of the fourth transistor T4 via a corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, thereby turning on the fourth transistor T4. A control signal for the second transistor T2 is provided to the gate of the second transistor T2 via a corresponding second gate line GL2 among the plurality of second gate lines, thereby turning on the second transistor T2. The initialization voltage signal from the corresponding first reset signal line Vint1 passes through the first reset transistor Tr1, the fourth transistor T4, and the second transistor T2, and is then transferred to the first capacitor electrode Ce1 and the gate of the drive transistor Td. The gate of the drive transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the second sub-phase t2. In the second sub-phase t2, the first gate line GL1 is provided with a cutoff signal, so the first transistor T1 is turned off, and the light emitting control signal line em is provided with a high voltage signal, so that the third transistor T3 is turned off.

[0065] In the third sub-stage t3, a cut-off control signal is provided to the gate of the first transistor T1 through the corresponding first gate line GL1 among the multiple first gate lines, so as to cut off the first transistor T1; a cut-off control signal for the second transistor T2 is provided to the gate of the second transistor T2 through the corresponding second gate line GL2 among the multiple second gate lines, so as to cut off the second transistor T2; a cut-off reset control signal is provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1 among the multiple first reset control signal lines, so as to cut off the first reset transistor Tr1; a cut-off reset control signal for the second reset transistor Tr2 is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 among the multiple second reset control signal lines, so as to cut off the second reset transistor Tr2.

[0066] In the fourth sub-phase t4, a turn-on control signal is provided to the gate of the first transistor T1 via a corresponding first gate line GL1 among the plurality of first gate lines, thereby turning on the first transistor T1. A turn-on control signal for the second transistor T2 is provided to the gate of the second transistor T2 via a corresponding second gate line GL2 among the plurality of second gate lines, thereby turning on the second transistor T2. A turn-off control signal for the third reset transistor Tr3 is provided to the gate of the third reset transistor Tr3 via a corresponding second gate line GL2 among the plurality of second gate lines, thereby turning off the third reset transistor Tr3. The second electrode of the drive transistor Td is connected to the first electrode of the second transistor T2. The gate of the drive transistor Td is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on in the fourth sub-phase t4, the gate and the second electrode of the drive transistor Td are connected and short-circuited, leaving only the PN junction between the gate and the first electrode of the drive transistor Td active, thereby placing the drive transistor Td in a diode connection mode. The first transistor T1 is turned on in the fourth sub-phase t4. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate and the first electrode of the driving transistor Td is active, the voltage level at the first node N1 gradually rises to (Vdata + Vth) during the fourth sub-phase t4, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. During the fourth sub-phase t4, the corresponding emission control signal line em is provided with a high voltage signal, turning off the third transistor T3. During the fourth sub-phase t4, a turn-off reset control signal for the fourth transistor T4 is provided to the gate of the fourth transistor T4 via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, turning off the fourth transistor T4.

[0067] In the fifth sub-phase t5 , a turn-off control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among the plurality of first gate lines, so as to turn off the first transistor T1 .

[0068] The sixth sub-phase t6 is an on-bias sub-phase serving as a stabilization period, during which no significant signal changes occur, thereby ensuring that the circuit maintains its state before emitting light. In the sixth sub-phase t6, a turn-off control signal for the second transistor T2 is provided to the gate of the second transistor T2 via a corresponding second gate line GL2 among the plurality of second gate lines, thereby turning off the second transistor T2.

[0069] In the seventh sub-phase t7, the cutoff reset control signal is again provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, turning off the second reset transistor Tr2. The corresponding first gate line GL1 is provided with a cutoff signal, turning off the first transistor T1. In the seventh sub-phase t7, the cutoff control signal for the second transistor T2 is provided to the gate of the second transistor T2 via the corresponding second gate line GL2 among the plurality of second gate lines, turning off the second transistor T2. A low voltage signal is provided to the corresponding light-emitting control signal line em among the plurality of light-emitting control signal lines, turning on the third transistor T3. The turn-on control signal for the fourth transistor T4 is provided to the gate of the fourth transistor T4 via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, turning on the fourth transistor T4. The voltage level at the first node N1 is maintained at (Vdata + Vth) in the seventh sub-phase t7. This voltage level turns on the drive transistor Td and operates in the saturation region. This forms a path to the light-emitting element LE via the third transistor T3, the drive transistor Td, and the fourth transistor T4. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. The voltage level at the third node N3 connected to the second electrode of the driving transistor Td is equal to the light emitting voltage of the light emitting element LE.

[0070] Figure 3A is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B It shows Figure 3A Schematic diagram of the arrangement of pixel driving circuits in the array substrate depicted in FIG. Figure 3C It shows Figure 3A Schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG. Figure 3D It shows Figure 3A Schematic diagram of the structure of the first gate metal layer in the array substrate depicted in FIG. Figure 3E It shows Figure 3A Schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG.

[0071] Figure 3F It shows Figure 3ASchematic diagram of a via extending through the first interlayer dielectric layer in an array substrate depicted in FIG. Figure 3G It shows Figure 3A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in . Figure 3H It shows Figure 3A Schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate depicted in FIG. Figure 3I It shows Figure 3A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG. Figure 3J It shows Figure 3A Schematic diagram of a via extending through a passivation layer in an array substrate is depicted in FIG. Figure 3K It shows Figure 3A Schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 3L It shows Figure 3A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG. Figure 3M It shows Figure 3A Schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Figure 3N It shows Figure 3A Schematic diagram of a via extending through the second planarization layer in an array substrate depicted in FIG. Figure 3O It shows Figure 3A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Figure 3P It shows Figures 3C to 3M Schematic diagram of the superposition structure. Figure 3Q It shows Figures 3C to 3K Schematic diagram of the superposition structure. Figure 4 It is along Figure 3A Cross-sectional view along line AA'. Figures 3A to 3Q A portion of an array substrate having four adjacent pixel driving circuits (including PDC1 , PDC2 , PDC3 , and PDC4 ) is depicted.

[0072] Reference Figures 3A to 3Q as well as Figure 4In some embodiments, the array substrate includes: a base substrate BS; a buffer layer BUF, which is located on the base substrate BS; a first semiconductor material layer SML1, which is located on a side of the buffer layer BUF away from the base substrate BS; a gate insulating layer GI, which is located on a side of the first semiconductor material layer SML1 away from the base substrate BS; a first gate metal layer Gate1, which is located on a side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN, which is located on a side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2, which is located on a side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1, which is located on a side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2, which is located on a side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2; a second interlayer dielectric Layer ILD2, which is located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1; the third gate metal layer Gate3, which is located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX, which is located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1, which is located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1, which is located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second planarization layer SD2, which is located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; the second planarization layer PLN2, which is located on the side of the second signal line layer SD2 away from the first planarization layer PLN1; and the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SD2.

[0073] Reference Figure 2A 、 Figure 3A 、 Figure 3C ,and Figure 4In some embodiments, the first semiconductor material layer SML1 includes at least the active layer of multiple transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Optionally, the first semiconductor material layer SML1 also includes at least the corresponding portion of the first electrodes of the multiple transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Optionally, the first semiconductor material layer SML1 also includes at least the corresponding portion of the second electrodes of the multiple transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Optionally, the first semiconductor material layer SML1 includes the active layer, the first electrode, and the second electrode of the multiple transistors of the pixel driving circuit (including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td). Various suitable semiconductor materials can be used to manufacture the first semiconductor material layer SML1. Examples of semiconductor materials used to manufacture the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, single crystal silicon, and amorphous silicon.

[0074] exist Figure 3C In the figure, the corresponding Figure 3B 1. The pixel driving circuit of PDC2 in FIG. 1 is shown in FIG. 1 , and reference numerals represent components of each of the multiple transistors (T1, T3, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The drive transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0075] Optionally, the active layers (ACT1, ACT3, ACTr1, ACTr2, ACTr3 and ACTd), the first electrodes (S1, S3, Sr1, Sr2, Sr3 and Sd) and the second electrodes (D1, D3, Dr1, Dr2, Dr3 and Dd) of each transistor (T1, T3, Tr1, Tr2, Tr3 and Td) are located on the same layer.

[0076] Reference Figure 2A 、 Figure 3A 、 Figure 3D and Figure 4 In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., individual first gate lines GL1), a plurality of light-emitting control signal lines (e.g., individual light-emitting control signal lines em), at least a portion of a plurality of second gate lines (e.g., individual second gate line first branches GL2-1), a plurality of first reset control signal lines (e.g., individual first reset control signal lines rst1), at least a portion of a plurality of second reset control signal lines (e.g., individual second reset control signal lines first branches rst2-1), and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first gate metal layer Gate1. For example, the conductive material can be deposited on a substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, the plurality of first gate lines, the plurality of light emission control signal lines, at least part of the plurality of second gate lines, the plurality of first reset control signal lines, at least part of the plurality of second reset control signal lines, and the first capacitor electrode Ce1 are located in the same layer.

[0077] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of first gate lines and a first capacitor electrode Ce1 are formed as a result of one or more steps of the same patterning process performed in the same material layer, the plurality of first gate lines and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the steps of forming a plurality of first gate lines and forming the first capacitor electrode Ce1, a plurality of first gate lines and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0078] Reference Figure 2A 、 Figure 3A 、 Figure 3E and Figure 4In some embodiments, the second gate metal layer Gate2 includes at least a portion of a plurality of second gate lines (e.g., the corresponding second gate line second branches GL2-2), at least a portion of a plurality of second reset control signal lines (e.g., the corresponding second reset control signal line second branches rst2-2), and the second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second gate metal layer Gate2. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the corresponding second gate line second branch GL2-2, the corresponding second reset control signal line second branch rst2-2, and the second capacitor electrode are located on the same layer.

[0079] In some embodiments, a portion of the second capacitor electrode Ce2 is not present in the hole region H. Alternatively, except for the hole region H where the portion of the second capacitor electrode Ce2 is not present, an orthographic projection of the second capacitor electrode Ce2 on the base substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and extends beyond an orthographic projection of the first capacitor electrode Ce1 on the base substrate BS. Alternatively, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the hole region H, and the insulating layer IN.

[0080] Figure 3F , a via extending through the first interlayer dielectric layer ILD1 is depicted.

[0081] Reference Figure 2A 、 Figure 3A 、 Figure 3G as well as Figure 4In some embodiments, the second semiconductor material layer SML2 includes at least the active layer of the second transistor T2 and at least the active layer of the fourth transistor T4. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode of the second transistor T2. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode of the second transistor T2. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode of the fourth transistor T4. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode of the fourth transistor T4. Optionally, the second semiconductor material layer SML2 includes the active layer, first electrode, and second electrode of the second transistor T2. Optionally, the second semiconductor material layer SML2 includes the active layer, first electrode, and second electrode of the fourth transistor T4. In this array substrate, at least the active layers of the second transistor T2 and the fourth transistor T4 are located in a layer different from at least the active layers of other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to manufacture the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (eg, indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (eg, zinc oxynitride).

[0082] exist Figure 3G In, corresponding to Figure 3B The pixel driving circuit of PDC2 in FIG. 1 is labeled with reference numbers, which indicate the components of the second transistor T2 and the fourth transistor T4 in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2; the fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2 are located on the same layer. Optionally, the active layer ACT4, the first electrode S4, and the second electrode D4 of the fourth transistor T4 are located on the same layer.

[0083] Figure 3H , a via extending through the second interlayer dielectric layer ILD2 is depicted.

[0084] Reference Figure 2A 、 Figure 3A 、 Figure 3I 、 Figure 4In some embodiments, the third gate metal layer Gate3 includes at least a portion of a plurality of second gate lines (e.g., corresponding second gate line third branches GL2-3), at least a portion of a plurality of second reset control signal lines (e.g., corresponding second reset control signal third branches rst2-3), a plurality of first rings (e.g., each first ring LP1) and a plurality of second rings (e.g., each second ring LP2). Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the third gate metal layer Gate3. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0085] Figure 3J A via extending through the passivation layer PVX is depicted in FIG.

[0086] Reference Figure 2A 、 Figure 3A 、 Figure 3K ,and Figure 4 In some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines (e.g., each first reset signal line Vint1), a plurality of second reset signal lines (e.g., each second reset signal line Vint2), a first node connection line Cln1, a third node connection line Cln3, a fourth node connection line Cln4, a voltage connection pad VCP, and a data connection pad DCP. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer SD1. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of first reset signal lines, the plurality of second reset signal lines, the first node connection line Cln1, the third node connection line Cln3, the fourth node connection line Cln4, the voltage connection pad VCP, and the data connection pad DCP are located on the same layer.

[0087] In some embodiments, each first reset signal line includes a plurality of first branches (eg, corresponding first branches BR1 ). In some embodiments, each second reset signal line includes a plurality of second branches (eg, corresponding second branches BR2 ).

[0088] In some embodiments, the first node connection line Cln1 is connected to the first capacitor electrode Ce1 and to the second electrode D2 of the second transistor T2 .

[0089] In some embodiments, the third node connection line Cln3 is connected to the first electrode S2 of the second transistor T2 through a first via v1, to the second electrode Dr3 of the third reset transistor Tr3 through a second via v2, and to the second electrode Dd of the drive transistor Td through a third via v3. Optionally, the first via v1 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2. Optionally, the second via v2 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. Optionally, the third via v3 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0090] In some embodiments, the third node connection line Cln3 spans the corresponding first gate line GL1 and the corresponding second gate line. In some embodiments, the third node connection line Cln3 spans the corresponding first gate line GL1, the corresponding second gate line first branch GL2-1, the corresponding second gate line second branch GL2-2, and the corresponding second gate line third branch GL2-3. In some embodiments, the orthographic projection of the third node connection line Cln3 on the substrate substrate BS partially overlaps with the orthographic projection of the corresponding first gate line GL1 on the substrate substrate BS, partially overlaps with the orthographic projection of the corresponding second gate line first branch GL2-1 on the substrate substrate BS, partially overlaps with the orthographic projection of the corresponding second gate line second branch GL2-2 on the substrate substrate BS, and partially overlaps with the orthographic projection of the corresponding second gate line third branch GL2-3 on the substrate substrate BS.

[0091] In some embodiments, the fourth node connection line Cln4 is connected to the second electrode Dr1 of the first reset transistor Tr1 and to the second electrode D4 of the fourth transistor T4 .

[0092] Figure 3L A via extending through the first planarization layer PLN1 is depicted in FIG.

[0093] Reference Figure 2A 、 Figure 3A 、 Figure 3M and Figure 4In some embodiments, the second signal line layer SD2 includes a plurality of voltage supply lines (e.g., individual voltage supply lines Vdd), a plurality of data lines (e.g., individual data lines DL), and an anode contact pad ACP. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer SD2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, and the like. Optionally, the plurality of voltage supply lines (e.g., individual voltage supply lines Vdd), the plurality of data lines (e.g., individual data lines DL), and the anode contact pad ACP are located on the same layer.

[0094] In some embodiments, each second gate line GL2 includes a plurality of branches respectively located in different layers. In some embodiments, each second gate line GL2 includes a corresponding second gate line first branch GL2-1, a corresponding second gate line second branch GL2-2, and a corresponding second gate line third branch GL2-3 located in three different layers. Optionally, the corresponding second gate line first branch GL2-1 is located in the first gate metal layer Gate1, the corresponding second gate line second branch GL2-2 is located in the second gate metal layer Gate2, and the corresponding second gate line third branch GL2-3 is located in the third gate metal layer Gate3. In some embodiments, the orthographic projection of the corresponding second gate line first branch GL2-1 on the substrate substrate BS at least partially overlaps with the orthographic projection of the corresponding second gate line second branch GL2-2 on the substrate substrate BS, and at least partially overlaps with the orthographic projection of the corresponding second gate line third branch GL2-3 on the substrate substrate BS. Optionally, the corresponding second gate line first branch GL2-1, the corresponding second gate line second branch GL2-2, and the corresponding second gate line third branch GL2-3 are configured to be provided with the same gate scan signal.

[0095] In some embodiments, each second reset control signal line rst2 includes multiple branches located in different layers. In some embodiments, each second reset control signal line rst2 includes a corresponding second reset control signal line first branch rst2-1, a corresponding second reset control signal line second branch rst2-2, and a corresponding second reset control signal line third branch rst2-3. Optionally, the corresponding second reset control signal line first branch rst2-1 is located in the first gate metal layer Gate1, the corresponding second reset control signal line second branch rst2-2 is located in the second gate metal layer Gate2, and the corresponding second reset control signal line third branch rst2-3 is located in the third gate metal layer Gate3. In some embodiments, the orthographic projection of the corresponding second reset control signal line first branch rst2-1 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding second reset control signal line second branch rst2-2 on the substrate BS, and at least partially overlaps with the orthographic projection of the corresponding second reset control signal line third branch rst2-3 on the substrate BS. Optionally, the corresponding second reset control signal line first branch rst2 - 1 , the corresponding second reset control signal line second branch rst2 - 2 , and the corresponding second reset control signal line third branch rst2 - 3 are configured to be provided with the same reset control signal.

[0096] Figure 5 Schematic diagram showing a first reset signal network in an array substrate according to some embodiments of the present disclosure. Figures 3A to 3Q 、 Figure 4 and Figure 5 In some embodiments, the array substrate includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of interconnected first reset signal lines and a plurality of first rings. In some embodiments, each first ring LP1 in the plurality of first rings is connected to two adjacent first reset signal lines in the plurality of first reset signal lines. In some embodiments, each first reset signal line Vint1 in the plurality of first reset signal lines is connected to two first rings, where the two first rings are located in two adjacent rows of sub-pixels.

[0097] In some embodiments, each first reset signal line Vint1 includes a first main body MB1 and a plurality of first branches connected to the first main body MB1. In some embodiments, the first main body MB1 extends along a first direction DR1, and each of the plurality of first branches BR1 extends along a second direction DR2, where the first direction DR1 and the second direction DR2 are different. In one specific example, the first direction DR1 is perpendicular to the second direction DR2. In some embodiments, each first branch BR1 is connected to two first rings, where the two first rings are located in two adjacent rows of sub-pixels.

[0098] In some embodiments, each first ring LP1 surrounds a window area in the array substrate, wherein accessories are mounted in the window area. Examples of accessories include a photoelectric sensor, a fingerprint sensor, and a camera.

[0099] In some embodiments, a plurality of first rings are located in the third gate metal layer Gate3, and a plurality of first reset signal lines are located in the first signal line layer SL1. In some embodiments, each first reset signal line Vint1 is connected to a corresponding first ring LP1 through a via extending through the passivation layer PVX.

[0100] In some embodiments, two adjacent pixel driving circuits in the same row (eg, Figure 3B PDC1 and PDC2 in, or Figure 3B The first electrodes of the two first reset transistors in PDC3 and PDC4 are part of the overall structure. In some embodiments, each first reset signal line Vint1 is connected to the overall structure including the first electrodes of the two first reset transistors in two adjacent pixel drive circuits in the same row through a first single via sv1. Optionally, the first single via sv1 extends through the passivation layer PVX, the second interlayer dielectric layer IL2, the first interlayer dielectric layer IL1, the insulating layer IN, and the gate insulating layer GI.

[0101] In some embodiments, the overall structure further includes active layers of two first reset transistors in two adjacent pixel driving circuits in the same row. In some embodiments, the overall structure further includes second electrodes of two first reset transistors in two adjacent pixel driving circuits in the same row.

[0102] In some embodiments, an orthographic projection of each first reset signal line Vint1 on the base substrate BS at least partially overlaps with an orthographic projection of active layers of two first reset transistors in two adjacent pixel driving circuits in the same row on the base substrate BS.

[0103] The inventors of the present disclosure have discovered that the structure of the first reset signal network can achieve a symmetrical layout, a more uniform electrical environment, and a flatter anode layer.

[0104] In some embodiments, the orthographic projections of corresponding first branches BR1 on the substrate BS separate the orthographic projections of two adjacent integral structures from two adjacent pixel driver circuits on the substrate BS, where each of the two adjacent integral structures includes the second electrode D1 of the first transistor T1, the second electrode D3 of the third transistor T3, and at least a portion of the first electrode Sd of the driver transistor Td. The inventors of the present disclosure have discovered that the structure of the first reset signal network can effectively prevent interference between the two adjacent integral structures from the two adjacent pixel driver circuits. In some embodiments, each of the two adjacent integral structures corresponds to the second node N2.

[0105] Figure 6 is a schematic diagram showing a second reset signal network in an array substrate according to some embodiments of the present disclosure. Figures 3A to 3Q 、 Figure 4 and Figure 6 In some embodiments, the array substrate includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of interconnected second reset signal lines and a plurality of second rings. In some embodiments, each second ring LP2 in the plurality of second rings is connected to two adjacent second reset signal lines in the plurality of second reset signal lines. In some embodiments, each second reset signal line Vint2 in the plurality of second reset signal lines is connected to two second rings, where the two second rings are located in two adjacent rows of sub-pixels.

[0106] In some embodiments, each second reset signal line Vint2 includes a second main body MB2 and multiple second branches connected to the second main body MB2. In some embodiments, the second main body MB2 extends along a first direction DR1, and each of the multiple second branches BR2 extends along a second direction DR2, where the first direction DR1 and the second direction DR2 are different. In one specific example, the first direction DR1 is perpendicular to the second direction DR2. In some embodiments, each second branch BR2 is connected to two second rings, where the two second rings are located in two adjacent rows of sub-pixels.

[0107] In some embodiments, the plurality of second rings are located in the third gate metal layer Gate3, and the plurality of second reset signal lines are located in the first signal line layer SL1. In some embodiments, each second reset signal line Vint2 is connected to a corresponding second ring LP2 through a via extending through the passivation layer PVX.

[0108] In some embodiments, two adjacent pixel driving circuits in the same row (eg, Figure 3B PDC1 and PDC2 in, or Figure 3BThe first electrodes of the two second reset transistors in PDC3 and PDC4 (in the pixel driver circuits) are part of the overall structure. In some embodiments, each second reset signal line Vint2 is connected to the overall structure including the first electrodes of the two second reset transistors in two adjacent pixel driver circuits in the same row through a second single via sv2. Optionally, the second single via sv2 extends through the passivation layer PVX, the second interlayer dielectric layer IL2, the first interlayer dielectric layer IL1, the insulating layer IN, and the gate insulating layer GI.

[0109] In some embodiments, the overall structure further includes active layers of two second reset transistors in two adjacent pixel driving circuits in the same row. In some embodiments, the overall structure further includes second electrodes of two second reset transistors in two adjacent pixel driving circuits in the same row.

[0110] In some embodiments, an orthographic projection of each second reset signal line Vint2 on the base substrate BS at least partially overlaps with an orthographic projection of active layers of two second reset transistors in two adjacent pixel driving circuits in the same row on the base substrate BS.

[0111] The inventors of the present disclosure have discovered that the structure of the second reset signal network can achieve a symmetrical layout, a more uniform electrical environment, and a flatter anode layer.

[0112] In some embodiments, the orthographic projections of each second branch BR2 on the substrate BS separate the orthographic projections of two adjacent third node connection lines (e.g., Cln3) from two adjacent pixel drive circuits on the substrate BS. The inventors of the present disclosure have discovered that the structure of the second reset signal network can effectively prevent interference between two adjacent third node connection lines from two adjacent pixel drive circuits. In some embodiments, each of the two adjacent third node connection lines corresponds to a third node N3.

[0113] Figure 7 Schematic diagram showing a plurality of first reset signal lines and a plurality of data lines in an array substrate according to some embodiments of the present disclosure. Figure 7 In some embodiments, the orthographic projections of the first branches BR1 on the substrate BS separate the orthographic projections of two adjacent data lines among the plurality of data lines on the substrate BS. The inventors of the present disclosure have found that this layout can effectively prevent interference between the two adjacent data lines.

[0114] Reference Figure 3Q 、 Figure 3K and Figure 3CThe second electrodes of the third reset transistor Tr3 and the drive transistor Td are located in the semiconductor material layer SML, and the third reset transistor Tr3 and the second electrodes of the drive transistor Td are separated from each other in the semiconductor material layer SML. In some embodiments, the array substrate further includes a third node connection line Cln3 located in a layer different from the second electrodes of the third reset transistor Tr3 and the drive transistor Td. In some embodiments, the third node connection line Cln3 is connected to the second electrode Dr3 of the third reset transistor Tr3 and to the second electrode Dd of the drive transistor Td, thereby electrically connecting the third reset transistor Tr3 and the second electrode of the drive transistor Td. In one example, the third node connection line Cln3 is located in the first signal line layer.

[0115] In some embodiments, the third node connection line Cln3 crosses over a corresponding first gate line GL1 among the plurality of first gate lines. In some embodiments, an orthographic projection of the third node connection line Cln3 on the substrate partially overlaps an orthographic projection of the corresponding first gate line GL1 on the substrate.

[0116] In some embodiments, the third node connection line Cln3 also spans the corresponding second gate line. In some embodiments, the third node connection line Cln3 also spans the corresponding second gate line first branch GL2-1, the corresponding second gate line second branch GL2-2, and the corresponding second gate line third branch GL2-3. In some embodiments, the orthographic projection of the third node connection line Cln3 on the substrate substrate partially overlaps with the orthographic projection of the corresponding second gate line on the substrate substrate. In some embodiments, the orthographic projection of the third node connection line Cln3 on the substrate substrate partially overlaps with the orthographic projection of the corresponding second gate line first branch GL2-1 on the substrate substrate, partially overlaps with the orthographic projection of the corresponding second gate line second branch GL2-2 on the substrate substrate, and partially overlaps with the orthographic projection of the corresponding second gate line third branch GL2-3 on the substrate substrate.

[0117] Various alternative embodiments may be practiced in the present disclosure. Figure 8A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 8AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to the second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines, a first electrode connected to the second electrode of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light emitting control signal line em among a plurality of light emitting control signal lines, a first electrode connected to a corresponding voltage supply line V among a plurality of voltage supply lines A first electrode of the first transistor T4 is connected to a first electrode of the first reset control signal line rst1, a first electrode connected to a first reset signal line Vint1, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE; and a third reset transistor Tr3 is connected to a first electrode of the third reset control signal line rst3, a first electrode connected to a third reset signal line Vint1, and a second electrode connected to the first electrode of the second transistor T2, the second electrode of the driving transistor Td, the second electrode of the second reset transistor Tr2, and the first electrode of the fourth transistor T4. A second capacitor electrode Ce2 is connected to a corresponding voltage supply line and the first electrode of the third transistor T3.

[0118] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, the second electrode of the third reset transistor Tr3, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0119] The present disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Figure 8A , the second transistor T2 and the fourth transistor T4 are n-type transistors, such as metal oxide transistors, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the valid control signal (e.g., the on control signal) is a low voltage signal, while the invalid control signal (e.g., the off control signal) is a high voltage signal. For n-type transistors, the valid control signal (e.g., the on control signal) is a high voltage signal, while the invalid control signal (e.g., the off control signal) is a low voltage signal.

[0120] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0121] Figure 8B 1 is a timing diagram illustrating the operation of the pixel driving circuit in some embodiments of the present disclosure. Figure 8A and Figure 8B During one frame of image, the operation of the pixel driving circuit includes a first sub-phase t1, a second sub-phase t2, a third sub-phase t3, a fourth sub-phase t4, a fifth sub-phase t6, and a seventh sub-phase t7.

[0122] During the first sub-phase t1, an on-reset control signal is provided to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, thereby turning on the first reset transistor Tr1. This causes the initialization voltage signal from the corresponding first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1 and further to the fourth node N4. The anode of the light-emitting element LE is initialized. An on-reset control signal is provided to the gate of the second reset transistor Tr2 via a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, thereby turning on the second reset transistor Tr2. This causes the initialization voltage signal from the corresponding second reset signal line Vint2 among a plurality of second reset signal lines to be transmitted through the second reset transistor Tr2 and further to the second node N2. The second electrode of the drive transistor Td is initialized. During the first sub-phase t1, an off-control signal is provided to the gate of the second transistor T2 via a corresponding second gate line GL2 among a plurality of second gate lines, thereby turning off the second transistor T2. In the first sub-phase t1, a turn-off reset control signal for the fourth transistor T4 is provided to the gate of the fourth transistor T4 via a corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, thereby turning off the fourth transistor T4. In the first sub-phase t1, a turn-off control signal is provided to the gate of the third reset transistor Tr3 via a corresponding third reset control signal line among the plurality of third reset control signal lines, thereby turning off the third reset transistor Tr3.

[0123] In the second sub-phase t2, a conduction reset control signal is provided to the gate of the third reset transistor Tr3 via a corresponding third reset control signal line rst3 among a plurality of third reset control signal lines, turning on the third reset transistor Tr3. This causes the initialization voltage signal from the corresponding third reset signal line Vint3 to pass through the third reset transistor Tr3 and, in turn, to the third node N3. The second electrode of the drive transistor Td is initialized. In the second sub-phase t2, a conduction control signal is provided to the gate of the second transistor T2 via a corresponding second gate line GL2 among a plurality of second gate lines, turning on the second transistor T2. This causes the initialization voltage signal from the third reset signal line Vint3 to pass through the third reset transistor Tr3 and the second transistor T2 and, in turn, to the first capacitor electrode Ce1 and the gate of the drive transistor Td. The gate of the drive transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the second sub-phase t2. During the second sub-phase t2, the corresponding first gate line GL1 is provided with an off signal, thereby turning off the first transistor T1. Each of the plurality of emission control signal lines em is provided with a high voltage signal, thereby turning off the third transistor T3. During the second sub-phase t2, a turn-off reset control signal is provided to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among the plurality of first reset control signal lines, thereby turning off the first reset transistor Tr1. A turn-on reset control signal for the fourth transistor T4 is provided to the gate of the fourth transistor T4 via a corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, thereby turning on the fourth transistor T4.

[0124] In the third sub-stage t3, a cut-off control signal is provided to the gate of the first transistor T1 through the corresponding first gate line GL1 among the multiple first gate lines, so as to cut off the first transistor T1; a cut-off control signal is provided to the gate of the second transistor T2 through the corresponding second gate line GL2 among the multiple second gate lines, so as to cut off the second transistor T2; a cut-off reset control signal is provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1 among the multiple first reset control signal lines, so as to cut off the first reset transistor Tr1; a cut-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 among the multiple second reset control signal lines, so as to cut off the second reset transistor Tr2; a cut-off control signal is provided to the gate of the third reset transistor Tr3 through the corresponding third reset control signal line among the multiple third reset control signal lines, so as to cut off the third reset transistor Tr3.

[0125] In the fourth sub-phase t4, a turn-on control signal is provided to the gate of the first transistor T1 via a corresponding first gate line GL1 among the plurality of first gate lines, thereby turning on the first transistor T1. A turn-on control signal is provided to the gate of the second transistor T2 via a corresponding second gate line GL2 among the plurality of second gate lines, thereby turning on the second transistor T2. A turn-off control signal is provided to the gate of the third reset transistor Tr3 via a corresponding third reset control signal line among the plurality of third reset control signal lines, thereby turning off the third reset transistor Tr3. The second electrode of the drive transistor Td is connected to the first electrode of the second transistor T2. The gate of the drive transistor Td is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on in the fourth sub-phase t4, the gate and the second electrode of the drive transistor Td are connected and short-circuited, leaving only the PN junction between the gate and the first electrode of the drive transistor Td active, thereby placing the drive transistor Td in a diode connection mode. The first transistor T1 is turned on in the fourth sub-phase t4. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate and the first electrode of the driving transistor Td is active, the voltage level of the first node N1 gradually rises to (Vdata + Vth) during the fourth sub-phase t4, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. During the fourth sub-phase t4, a high voltage signal is provided to the corresponding emission control signal line em, turning off the third transistor T3. During the fourth sub-phase t4, a turn-off reset control signal for the second reset transistor Tr2 is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, turning off the second reset transistor Tr2.

[0126] In the fifth sub-phase t5 , a turn-off control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among the plurality of first gate lines, so as to turn off the first transistor T1 .

[0127] The sixth sub-phase t6 is a conduction bias sub-phase serving as a stabilization period, during which no significant signal changes occur, thereby ensuring that the circuit maintains its state before emitting light. During the sixth sub-phase t6, a cutoff control signal is provided to the gate of the second transistor T2 via a corresponding second gate line GL2 among the plurality of second gate lines, thereby turning off the second transistor T2.

[0128] In the seventh sub-phase t7, the cutoff reset control signal is again provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, turning off the second reset transistor Tr2. The corresponding first gate line GL1 is provided with a cutoff signal, turning off the first transistor T1. In the seventh sub-phase t7, the cutoff control signal is provided to the gate of the second transistor T2 via the corresponding second gate line GL2 among the plurality of second gate lines, turning off the second transistor T2. A low voltage signal is provided to the corresponding light-emitting control signal line em among the plurality of light-emitting control signal lines, turning on the third transistor T3. The turn-on control signal for the fourth transistor T4 is provided to the gate of the fourth transistor T4 via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, turning on the fourth transistor T4. The voltage level of the first node N1 is maintained at (Vdata + Vth) in the seventh sub-phase t7. This voltage level turns on the drive transistor Td and operates in the saturation region. This forms a path to the light-emitting element LE via the third transistor T3, the drive transistor Td, and the fourth transistor T4. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. The voltage level at the third node N3 connected to the second electrode of the driving transistor Td is equal to the light emitting voltage of the light emitting element LE.

[0129] Reference Figures 3A to 3Q In some embodiments, the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit that are directly adjacent to each other and located at the current level (e.g., in the same row) are, for example, perpendicular to the main surface of the array substrate and substantially parallel to Figure 3A The planes of the data lines in the pixel driving circuit have substantial mirror symmetry with respect to each other. As used herein, the term "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, the term "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" does not include an anode layer or a pixel defining layer. In some examples, the term "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refers to a conductive layer of the first pixel driving circuit and a conductive layer of the second pixel driving circuit. In a specific example, the "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, or a second signal line layer. In another specific example, the "corresponding layer" also includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer.

[0130] In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate.

[0131] Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, and the like. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display device.

[0132] In another aspect, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a first reset signal network. In some embodiments, forming the first reset signal network includes forming a plurality of interconnected first reset signal lines and a plurality of first rings. Each of the plurality of first rings is connected to two adjacent first reset signal lines among the plurality of first reset signal lines. Each of the plurality of first reset signal lines is connected to two first rings. The two first rings are located in two adjacent rows of sub-pixels, respectively.

[0133] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and various modifications as are suited to a particular use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are to be used in their broadest reasonable sense unless otherwise indicated. Therefore, the terms "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to the specific examples, and reference to exemplary embodiments of the present invention is not intended to limit the invention, and no such limitation should be inferred. The present invention is limited solely by the spirit and scope of the appended claims. Furthermore, the claims may use the terms "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements to which they refer unless a specific number is provided. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, no element or component in this disclosure is intended to be dedicated to the public, regardless of whether the element or component is explicitly stated in the appended claims.

Claims

1. An array substrate comprising a first reset signal network; in, The first reset signal network includes a plurality of first reset signal lines and a plurality of first rings interconnected together; Each of the plurality of first rings is connected to two adjacent first reset signal lines among the plurality of first reset signal lines; Each of the plurality of first reset signal lines is connected to two first rings respectively; The two first rings are respectively located in two adjacent rows of sub-pixels.

2. The array substrate according to claim 1, wherein: Each of the first reset signal lines includes a first main body and a plurality of first branches connected to the first main body; The first body extends along a first direction; Each first branch of the plurality of first branches extends along the second direction; The first direction and the second direction are different from each other; as well as The first branches are respectively connected to the two first rings.

3. The array substrate according to claim 1, wherein: The plurality of first rings are located in a different layer from the plurality of first reset signal lines; and The respective first reset signal lines are connected to corresponding first rings through vias extending through at least one layer comprising insulating material.

4. The array substrate according to claim 1, wherein: The plurality of first rings are located in the third gate metal layer; The plurality of first reset signal lines are located in a first signal line layer; and Each of the first reset signal lines is connected to a corresponding first ring through a via extending through the passivation layer.

5. The array substrate according to any one of claims 1 to 4, comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a first reset transistor; The first electrodes of the two first reset transistors in the two adjacent pixel driving circuits in the same row are part of the integral structure; as well as The respective first reset signal lines are connected to the overall structure including the first electrodes of the two first reset transistors in the two adjacent pixel driving circuits in the same row through a first single via.

6. The array substrate according to claim 5, wherein: The overall structure further includes active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row; and The orthographic projections of the respective first reset signal lines on the base substrate at least partially overlap with the orthographic projections of the active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate.

7. The array substrate according to claim 2, comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a data writing transistor, a compensation transistor, a first light emission control transistor and a driving transistor; The orthographic projections of the first branches on the substrate separate the orthographic projections of two adjacent integral structures from two adjacent pixel driving circuits on the substrate; as well as Each of the two adjacent integral structures includes at least part of the second electrode of the data write transistor, the second electrode of the first light emission control transistor, and the first electrode of the drive transistor.

8. The array substrate according to claim 2, comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a compensation transistor, a driving transistor, a third reset transistor and a third node connection line; The third node connection line is connected to the first electrode of the compensation transistor through a first via, to the second electrode of the third reset transistor through a second via, and to the second electrode of the driving transistor through a third via.

9. The array substrate according to claim 8, wherein: The orthographic projections of the first branches on the base substrate separate the orthographic projections of two adjacent third node connection lines from two adjacent pixel driving circuits on the array substrate.

10. The array substrate according to claim 8, further comprising a plurality of first gate lines; in, The orthographic projection of the third node line on the substrate partially overlaps with the orthographic projection of the corresponding first gate line on the substrate.

11. The array substrate according to claim 10, further comprising a plurality of second gate lines; in, An orthographic projection of the third node line on the base substrate partially overlaps with an orthographic projection of a corresponding second gate line on the base substrate.

12. The array substrate according to claim 2, further comprising a plurality of data lines; in, The orthographic projections of the first branches on the base substrate separate the orthographic projections of two adjacent data lines among the plurality of data lines on the base substrate.

13. The array substrate according to any one of claims 1 to 12, further comprising a second reset signal network; in, The second reset signal network includes a plurality of second reset signal lines and a plurality of second rings interconnected together; Each second ring in the plurality of second rings is respectively connected to two adjacent second reset signal lines in the plurality of second reset signal lines; Each of the plurality of second reset signal lines is connected to two second rings, respectively; and The two second rings are respectively located in two adjacent rows of sub-pixels.

14. The array substrate according to claim 13, wherein: Each of the second reset signal lines includes a second body and a plurality of second branches connected to the second body; The second body extends along a first direction; Each second branch of the plurality of second branches extends along a second direction; the first direction and the second direction are different from each other; as well as The second branches are respectively connected to the two second rings.

15. The array substrate according to claim 13, wherein: the plurality of second rings being located in a different layer from the plurality of second reset signal lines; and The respective second reset signal lines are connected to corresponding second rings through vias extending through at least one layer comprising insulating material.

16. The array substrate according to claim 13, wherein: The plurality of second rings are located in the third gate metal layer; The plurality of second reset signal lines are located in the first signal line layer; and Each of the second reset signal lines is connected to a corresponding second ring through a via extending through the passivation layer.

17. The array substrate according to any one of claims 13 to 16, comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a second reset transistor; the first electrodes of the two second reset transistors in the two adjacent pixel driving circuits in the same row are part of the integral structure; and The respective second reset signal lines are connected to the overall structure including the first electrodes of the two second reset transistors in the two adjacent pixel driving circuits in the same row through a second single via.

18. The array substrate according to claim 17, wherein: The overall structure further includes active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row; and The orthographic projections of the respective second reset signal lines on the base substrate at least partially overlap with the orthographic projections of the active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate.

19. The array substrate according to any one of claims 1 to 17, wherein: Each of the first rings surrounds a window area in the array substrate, wherein accessories are mounted in the window area.

20. An array substrate comprising a second reset signal network; in, The second reset signal network includes a plurality of second reset signal lines and a plurality of second rings interconnected together; Each second ring in the plurality of second rings is respectively connected to two adjacent second reset signal lines in the plurality of second reset signal lines; Each of the plurality of second reset signal lines is connected to two second rings, respectively; and The two second rings are respectively located in two adjacent rows of sub-pixels. 21 . A display device comprising the array substrate according to claim 1 and one or more integrated circuits connected to the array substrate.

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