Harmonic analysis method based on double buffer window function optimization

Abstract

The invention discloses a harmonic analysis method based on double buffer window function optimization, and relates to the technical field of harmonic analysis and signal processing of a power system, and the method comprises the steps of hardware initialization, double buffer initialization, FFT module parameter configuration, data acquisition, buffer switching, data extraction and windowing and FFT processing. Parallel data acquisition and processing are realized through a double-buffer ping-pong mechanism, spectrum leakage is suppressed by applying a Hanning window function, and FFT calculation is performed after signal amplitude is recovered through a compensation factor; according to the method, the data acquisition continuity and real-time performance are improved, the harmonic amplitude error is controlled within + / -0.5%, the hardware resource utilization rate is optimized, and the method is suitable for power grid electric energy quality monitoring.

Description

Technical Field

[0001] The present invention relates to the technical field of power system harmonic analysis and signal processing, in particular to a harmonic analysis method based on double-buffer window function optimization. Background Art

[0002] With the widespread use of nonlinear loads in power systems, the problem of grid harmonic pollution has become increasingly prominent. Accurate harmonic analysis is crucial for power quality assessment and fault diagnosis. Existing technologies mainly face the following bottlenecks:

[0003] The traditional single-buffer mechanism adopts a serial mode of "collection-calculation-wait", which makes it impossible to synchronously collect new data during the FFT calculation. As a result, the preset sampling point data that matches the power frequency cycle may be overwritten or lost due to processing delays, causing sampling window periods and non-uniform sampling, and ultimately resulting in deviations in harmonic amplitude and phase estimation. In addition, the processor resource utilization rate in the single-buffer mode is low, making it difficult to meet the dynamic response capability requirements of real-time power grid monitoring.

[0004] The FFT algorithm is sensitive to non-integer period truncation. When the power grid signal period does not match the sampling window, the non-periodic extension of the time domain signal will lead to frequency domain energy diffusion (spectral leakage), which manifests as amplitude distortion of adjacent frequency points. Sidelobe interference may cause the energy of strong harmonic components to spread to adjacent frequency points.

[0005] The sidelobe attenuation rate of traditional rectangular windows is low (only -18dB / octave). In complex harmonic scenarios, the superposition of leakage effects can cause amplitude estimation errors exceeding ±15%, seriously affecting the measurement accuracy of harmonic parameters. Summary of the Invention

[0006] The object of the present invention is to provide a harmonic analysis method based on double-buffer window function optimization to solve the problems raised in the prior art.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A harmonic analysis method based on double-buffer window function optimization includes the following steps:

[0009] S1. After the system is powered on, hardware initialization is performed to configure parameters for the STM32F429 microcontroller, AD7606BADC sampling device, and timer.

[0010] S2. After the system hardware is initialized, a double buffer is initialized, creating two buffers A and B of the same size. Each buffer is preset to store the sampling point data that matches the FFT analysis and the power frequency period. Buffer A is set as the write buffer and Buffer B is set to the idle state. The buffer read and write status, pointer position, and data storage area are marked through a structure to build the hardware foundation for alternating storage.

[0011] S3. After the double buffer is initialized, the number of analysis points of the FFT module is configured to be consistent with the number of sampling points and matched with the power frequency period according to the sampling rule preset by the double buffer, and the frequency resolution is calculated according to the relationship between the sampling frequency and the number of analysis points, and the calculation rule of frequency domain conversion is established;

[0012] S4. After the FFT module parameters are configured, the timer periodically sends a conversion start signal to the AD7606B. After the AD7606B completes sampling, the falling edge of the BUSY pin triggers the STM32F429 interrupt, and the sampled data is written into the current write buffer in sequence, starting the data acquisition process.

[0013] S5. When the write buffer is full of sampling point data matching the power frequency cycle, the data ready status flag of the full buffer is set to 1 through the dual buffer management structure and the buffer is switched to the read buffer. At the same time, the other buffer is switched to the write buffer, so that new data collection and stored data processing are carried out synchronously;

[0014] S6. After the buffer is switched to the read state, the main task periodically detects the state of the read buffer data preparation state flag bit. When the flag is detected to be 1, all data in the buffer is read and the flag is cleared;

[0015] S7. After extracting the buffer data, apply the Hanning window function to perform windowing processing on the time domain data. By calculating the sum of the window function coefficients, the compensation factor is obtained and the signal amplitude is restored. Then, a fast Fourier transform is performed on the processed data to output the amplitude information of each frequency component to complete the harmonic analysis.

[0016] Said S1 further comprises the following contents:

[0017] S1.1: After the system is powered on, the hardware resources of the STM32F429 microcontroller are initialized, including configuring the timer's operating mode, counting period, and interrupt parameters. This enables the timer to periodically send a conversion start signal to the AD7606B ADC chip through the GPIO pin, providing a timing trigger mechanism for subsequent data acquisition.

[0018] S1.2: After initializing the STM32F429, initialize and configure the AD7606B ADC chip. This includes setting its sampling mode, conversion rate, data output format, and pin levels. This ensures that the AD7606B is ready to respond to sampling instructions triggered by the timer and complete analog-to-digital conversion.

[0019] Said S2 further comprises the following contents:

[0020] S2.1: The double buffer structure definition includes two parts: a single buffer structure and a double buffer management structure;

[0021] A single buffer structure is used to describe a single storage unit, including a status flag, a write position pointer, and a data storage array: the status flag uses an 8-bit unsigned integer to identify the buffer status, 0 indicates that it is not full and can be written, and 1 indicates that it is full and can be read; the write position pointer is a 16-bit unsigned integer, counting from 0 to locate the data storage location; the data storage array is an 8-bit unsigned integer array with the number of sampling points matching the power frequency cycle, which is used to store the sampling data of the sampling points matching the power frequency cycle within the power frequency cycle;

[0022] The dual buffer management structure is used to coordinate the control of two buffers. It contains the data ready flag, the current read and write buffer index, and the buffer array: the data ready flag is an 8-bit unsigned integer that indicates the data ready state, 0 for not ready and 1 for ready; the current write buffer index points to the buffer that is receiving data, and the current read buffer index points to the buffer from which data can be extracted; the buffer array contains two single buffer instances, which implement the physical carrier of write-read ping-pong switching;

[0023] S2.2: Initialize the double buffer according to the double buffer structure; specifically: first declare the double buffer management variable as an instance to carry the buffer status and data storage; then set the data storage area of ​​the two buffers to 0 through the memory clear operation; then initialize the status flag and pointer, set the data ready flag to 0, indicating that there is no ready data; the current write buffer index is 0, indicating the initial write to buffer 0; the current read buffer index is -1, indicating that there is no read buffer; finally, by looping through the two buffers, set the status flag of each buffer to 0, indicating that it can be written, and the write position pointer to 0, indicating that storage starts from the starting position of the array, establishing the initial state of buffer 0 writing and buffer 1 on standby, providing a basis for subsequent switching to the read buffer when it is full, and activating the parallel mechanism of writing to another buffer at the same time.

[0024] The S3 further includes the following:

[0025] S3.1: After the double buffer is initialized, the number of analysis points in the FFT module is configured to match the number of sampling points and the power frequency period. This ensures that the FFT calculation covers the complete power frequency period sampling data, ensures that the time domain signal is discretized into sampling points at equal intervals that match the power frequency period, and provides a complete time domain data foundation for frequency domain conversion.

[0026] S3.2: According to the sampling frequency f s The relationship between the number of analysis points N and the frequency resolution of the FFT module is calculated and configured as follows:

[0027]

[0028] Where Δf is the frequency resolution, f s is the sampling frequency, and N is the number of FFT analysis points, which is consistent with the number of sampling points.

[0029] Said S4 further comprises the following contents:

[0030] S4.1: After the FFT module parameters are configured, the STM32F429 microcontroller starts its internal timer and sends a periodic conversion start signal to the AD7606B ADC chip via a GPIO pin. The timer generates a pulse signal according to the preset sampling period, which is synchronized with the power frequency. This signal is transmitted to the trigger input of the AD7606B via a hardware connection, driving it to start the analog-to-digital conversion process. After each trigger signal is sent, the AD7606B samples the input power grid analog signal, discretizing the continuous signal into digital quantities, providing the original sampled values ​​for subsequent data processing.

[0031] S4.2: After AD7606B completes a single sampling, the BUSY pin status changes from high level to low level, sending a conversion completion interrupt signal to the STM32F429; the microcontroller captures the falling edge event through the external interrupt interface and immediately executes the interrupt handler: it reads the current sampling value from the data output pin of AD7606B, and writes the data to the data storage area of ​​the buffer according to the current write buffer index recorded in the double buffer management structure, initially buffer 0; the write position is located by the write position pointer of the buffer. Each time a data is written, the write position pointer automatically increases by 1 until the buffer capacity limit is reached, triggering the switching logic. The capacity limit is the number of sampling points that matches the power frequency cycle.

[0032] Said S5 further comprises the following contents:

[0033] S5.1: When the write position pointer of the current write buffer reaches the buffer capacity limit, the buffer is determined to be full. At this time, the status flag of the buffer is set to 1 through the dual buffer management structure, indicating that the data is ready for the main task to extract. At the same time, the status field of the buffer is updated from 0 to 1, completing the state transition from the write buffer to the read buffer.

[0034] S5.2: After the full mark is completed, the current write buffer index is first switched from 0 to 1, pointing to another free buffer, making it the new write buffer; at the same time, the current read buffer index is set to the original write buffer index, and a parallel process of writing data to the new buffer and extracting data from the original buffer is established; the write position pointer of the new write buffer is reset to 0, and it starts to receive the sampling data of the next cycle.

[0035] Said S6 further comprises the following contents:

[0036] S6.1: After the buffer is switched to the read state, the main task polls the data ready flag in the double buffer management structure at a fixed period. This flag is used to indicate whether the read buffer has completed data writing and can be extracted. When the data ready status flag is 1, it indicates that the corresponding buffer has been filled with sampling point data that matches the power frequency period and can be processed later. When the data ready status flag is 0, the main task continues to wait and does not perform data extraction operations.

[0037] S6.2: When the main task detects that the data preparation status flag of a buffer is 1, it extracts all sampling point data in sequence from the data storage area of ​​the buffer according to the current read buffer index in the double buffer management structure; after the data extraction is completed, the data preparation status flag is immediately set to 0 and the read buffer index is reset to -1, indicating that the buffer has completed data processing and can re-enter the write buffer queue.

[0038] The S7 further includes the following:

[0039] S7.1: After extracting the time domain data from the buffer, the Hanning window function is applied to the data to suppress spectrum leakage. The Hanning window function calculates the window coefficient of each sampling point through the formula, and then multiplies the original data by the corresponding window coefficient to make the signal edge transition smooth and reduce the frequency domain energy diffusion caused by non-integer period truncation. The window coefficient w i The calculation formula is as follows:

[0040]

[0041] Where i is the sampling point index and N is the number of sampling points;

[0042] Since the Hanning window will attenuate the signal amplitude, it is necessary to calculate the sum of the window function coefficients ∑w i Get the compensation factor The windowed data is then multiplied by the compensation factor to restore the true amplitude of the signal;

[0043] S7.2: Perform a fast Fourier transform on the windowed and compensated time-domain data to convert the signal from the time domain to the frequency domain. The FFT calculation is based on the number of analysis points configured during the initialization phase. The butterfly algorithm efficiently calculates the complex amplitude of each frequency component and then modulo-calculates the real amplitude at the corresponding frequency point. The number of analysis points matches the number of sampling points.

[0044] Then, according to the power frequency characteristics of the power grid signal, the fundamental frequency is the fundamental frequency of the target signal, and the amplitude information of the fundamental wave and its harmonics is extracted to form the spectrum distribution result.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] 1. Improved continuity and real-time data acquisition: Two buffers alternate between writing and reading. For example, when buffer A is full, it switches to reading, and buffer B is simultaneously activated for writing. This ensures seamless data acquisition at the preset number of sampling points that matches the power frequency cycle, eliminating the risk of data loss during FFT calculations. Furthermore, the parallel acquisition-processing mode enables the system to complete the entire sampling-switching-analysis process within a 20ms power frequency cycle, meeting hard real-time requirements and improving the ability to quickly respond to power grid faults.

[0047] 2. Improved harmonic analysis accuracy: The Hanning window function uses a formula to smooth and weight the time domain signal, effectively suppressing spectral leakage caused by non-integer cycle truncation, concentrating the frequency domain energy at the true frequency point, and reducing sidelobe interference by more than 90%. For example, experimental data shows that the amplitude error of the third harmonic is reduced from ±15% to ±0.5% after windowing. The compensation factor restores the true amplitude of the signal, ensuring the energy accuracy of the FFT result, and keeping the amplitude measurement error of the fundamental wave and each harmonic within ±0.5%.

[0048] 3. Optimized hardware resource utilization: The dual-buffer mechanism enables the processor to perform FFT calculations synchronously during the data acquisition phase, avoiding the idle period of calculation in single-buffer mode. This improves hardware resource utilization by more than 50%, reduces system power consumption, and enhances multitasking capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a flow chart of a harmonic analysis method based on double-buffered window function optimization according to the present invention;

[0050] Figure 2This is a comparison diagram of the frequency spectrum with and without windowing of a harmonic analysis method based on double-buffered window function optimization of the present invention. DETAILED DESCRIPTION

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0052] Example: Figure 1-Figure 2 As shown, the present invention provides a technical solution.

[0053] A harmonic analysis method based on double-buffer window function optimization includes the following steps:

[0054] S1. After the system is powered on, hardware initialization is performed to configure parameters for the STM32F429 microcontroller, AD7606BADC sampling device, and timer.

[0055] S2. After the system hardware is initialized, a double buffer is initialized, creating two buffers A and B of the same size. Each buffer is preset to store the sampling point data that matches the FFT analysis and the power frequency period. Buffer A is set as the write buffer and Buffer B is set to the idle state. The buffer read and write status, pointer position, and data storage area are marked through a structure to build the hardware foundation for alternating storage.

[0056] S3. After the double buffer is initialized, the number of analysis points of the FFT module is configured to be consistent with the number of sampling points and matched with the power frequency period according to the sampling rule preset by the double buffer, and the frequency resolution is calculated according to the relationship between the sampling frequency and the number of analysis points, and the calculation rule of frequency domain conversion is established;

[0057] S4. After the FFT module parameters are configured, the timer periodically sends a conversion start signal to the AD7606B. After the AD7606B completes sampling, the falling edge of the BUSY pin triggers the STM32F429 interrupt, and the sampled data is written into the current write buffer in sequence, starting the data acquisition process.

[0058] S5. When the write buffer is full of sampling point data matching the power frequency cycle, the data ready status flag of the full buffer is set to 1 through the dual buffer management structure and the buffer is switched to the read buffer. At the same time, the other buffer is switched to the write buffer, so that new data collection and stored data processing are carried out synchronously;

[0059] S6. After the buffer is switched to the read state, the main task periodically detects the state of the read buffer data preparation state flag bit. When the flag is detected to be 1, all data in the buffer is read and the flag is cleared;

[0060] S7. After extracting the buffer data, apply the Hanning window function to perform windowing processing on the time domain data. By calculating the sum of the window function coefficients, the compensation factor is obtained and the signal amplitude is restored. Then, a fast Fourier transform is performed on the processed data to output the amplitude information of each frequency component to complete the harmonic analysis.

[0061] Said S1 further comprises the following contents:

[0062] S1.1: After the system is powered on, the hardware resources of the STM32F429 microcontroller are initialized, including configuring the timer's operating mode, counting period, and interrupt parameters. This enables the timer to periodically send a conversion start signal to the AD7606B ADC chip through the GPIO pin, providing a timing trigger mechanism for subsequent data acquisition.

[0063] S1.2: After initializing the STM32F429, initialize and configure the AD7606B ADC chip. This includes setting its sampling mode, conversion rate, data output format, and pin levels. This ensures that the AD7606B is ready to respond to sampling instructions triggered by the timer and complete analog-to-digital conversion.

[0064] Said S2 further comprises the following contents:

[0065] S2.1: The double buffer structure definition includes two parts: a single buffer structure and a double buffer management structure;

[0066] A single buffer structure is used to describe a single storage unit, including a status flag, a write position pointer, and a data storage array: the status flag uses an 8-bit unsigned integer to identify the buffer status, 0 indicates that it is not full and can be written, and 1 indicates that it is full and can be read; the write position pointer is a 16-bit unsigned integer, counting from 0 to locate the data storage location; the data storage array is an 8-bit unsigned integer array with the number of sampling points matching the power frequency cycle, which is used to store the sampling data of the sampling points matching the power frequency cycle within the power frequency cycle;

[0067] The dual buffer management structure is used to coordinate the control of two buffers. It contains the data ready flag, the current read and write buffer index, and the buffer array: the data ready flag is an 8-bit unsigned integer that indicates the data ready state, 0 for not ready and 1 for ready; the current write buffer index points to the buffer that is receiving data, and the current read buffer index points to the buffer from which data can be extracted; the buffer array contains two single buffer instances, which implement the physical carrier of write-read ping-pong switching;

[0068] S2.2: Initialize the double buffer according to the double buffer structure; specifically: first declare the double buffer management variable as an instance to carry the buffer status and data storage; then set the data storage area of ​​the two buffers to 0 through the memory clear operation; then initialize the status flag and pointer, set the data ready flag to 0, indicating that there is no ready data; the current write buffer index is 0, indicating the initial write to buffer 0; the current read buffer index is -1, indicating that there is no read buffer; finally, by looping through the two buffers, set the status flag of each buffer to 0, indicating that it can be written, and the write position pointer to 0, indicating that storage starts from the starting position of the array, establishing the initial state of buffer 0 writing and buffer 1 on standby, providing a basis for subsequent switching to the read buffer when it is full, and activating the parallel mechanism of writing to another buffer at the same time.

[0069] The S3 further includes the following:

[0070] S3.1: After the double buffer is initialized, the number of analysis points in the FFT module is configured to match the number of sampling points and the power frequency period. This ensures that the FFT calculation covers the complete power frequency period sampling data, ensures that the time domain signal is discretized into sampling points at equal intervals that match the power frequency period, and provides a complete time domain data foundation for frequency domain conversion.

[0071] S3.2: According to the sampling frequency f s The relationship between the number of analysis points N and the frequency resolution of the FFT module is calculated and configured as follows:

[0072]

[0073] Where Δf is the frequency resolution, f s is the sampling frequency, N is the number of FFT analysis points, which is consistent with the number of sampling points;

[0074] The sampling frequency is 12.8kHz, which is determined by collecting 256 points within a 20ms power frequency period and is a fixed value. The frequency resolution is the sampling frequency divided by the number of analysis points, which is 50Hz. This value is consistent with the fundamental frequency of the power grid, so that the frequency scale of the FFT result accurately corresponds to the fundamental wave 50Hz and its harmonics, ensuring that the amplitude information of each frequency component can be accurately extracted during frequency domain analysis.

[0075] Said S4 further comprises the following contents:

[0076] S4.1: After the FFT module parameters are configured, the STM32F429 microcontroller starts its internal timer and sends a periodic conversion start signal to the AD7606B ADC chip via a GPIO pin. The timer generates a pulse signal according to the preset sampling period, which is synchronized with the power frequency. This signal is transmitted to the trigger input of the AD7606B via a hardware connection, driving it to start the analog-to-digital conversion process. After each trigger signal is sent, the AD7606B samples the input power grid analog signal, discretizing the continuous signal into digital quantities, providing the original sampled values ​​for subsequent data processing.

[0077] S4.2: After AD7606B completes a single sampling, the BUSY pin status changes from high level to low level, sending a conversion completion interrupt signal to the STM32F429; the microcontroller captures the falling edge event through the external interrupt interface and immediately executes the interrupt handler: it reads the current sampling value from the data output pin of AD7606B, and writes the data to the data storage area of ​​the buffer according to the current write buffer index recorded in the double buffer management structure, initially buffer 0; the write position is located by the write position pointer of the buffer. Each time a data is written, the write position pointer automatically increases by 1 until the buffer capacity limit is reached, triggering the switching logic. The capacity limit is the number of sampling points that matches the power frequency cycle.

[0078] Said S5 further comprises the following contents:

[0079] S5.1: When the write position pointer of the current write buffer reaches the buffer capacity limit, the buffer is determined to be full. At this time, the status flag of the buffer is set to 1 through the dual buffer management structure, indicating that the data is ready for the main task to extract. At the same time, the status field of the buffer is updated from 0 to 1, completing the state transition from the write buffer to the read buffer.

[0080] S5.2: After the full mark is completed, the current write buffer index is first switched from 0 to 1, pointing to another free buffer, making it the new write buffer; at the same time, the current read buffer index is set to the original write buffer index, and a parallel process of writing data to the new buffer and extracting data from the original buffer is established; the write position pointer of the new write buffer is reset to 0, and it starts to receive the sampling data of the next cycle.

[0081] Said S6 further comprises the following contents:

[0082] S6.1: After the buffer is switched to the read state, the main task polls the data ready flag in the double buffer management structure at a fixed period. This flag is used to indicate whether the read buffer has completed data writing and can be extracted. When the data ready status flag is 1, it indicates that the corresponding buffer has been filled with sampling point data that matches the power frequency period and can be processed later. When the data ready status flag is 0, the main task continues to wait and does not perform data extraction operations.

[0083] S6.2: When the main task detects that the data preparation status flag of a buffer is 1, it extracts all sampling point data in sequence from the data storage area of ​​the buffer according to the current read buffer index in the double buffer management structure; after the data extraction is completed, the data preparation status flag is immediately set to 0 and the read buffer index is reset to -1, indicating that the buffer has completed data processing and can re-enter the write buffer queue.

[0084] The S7 further includes the following:

[0085] S7.1: After extracting the time domain data from the buffer, the Hanning window function is applied to the data to suppress spectrum leakage. The Hanning window function calculates the window coefficient of each sampling point through the formula, and then multiplies the original data by the corresponding window coefficient to make the signal edge transition smooth and reduce the frequency domain energy diffusion caused by non-integer period truncation. The window coefficient w i The calculation formula is as follows:

[0086]

[0087] Where i is the sampling point index and N is the number of sampling points;

[0088] Since the Hanning window will attenuate the signal amplitude, it is necessary to calculate the sum of the window function coefficients ∑w i Get the compensation factor The windowed data is then multiplied by the compensation factor to restore the true amplitude of the signal;

[0089] S7.2: Perform a fast Fourier transform on the windowed and compensated time-domain data to convert the signal from the time domain to the frequency domain. The FFT calculation is based on the number of analysis points configured during the initialization phase. The butterfly algorithm efficiently calculates the complex amplitude of each frequency component and then modulo-calculates the real amplitude at the corresponding frequency point. The number of analysis points matches the number of sampling points.

[0090] Then, according to the power frequency characteristics of the power grid signal, the fundamental frequency is the fundamental frequency of the target signal, and the amplitude information of the fundamental wave and its harmonics is extracted to form the spectrum distribution result.

[0091] A power grid monitoring device needs to perform real-time analysis of harmonics generated by nonlinear loads to assess power quality.

[0092] 1. After the system is powered on, the core hardware is initialized first:

[0093] 1. STM32F429 MCU and timer configuration:

[0094] The microcontroller's internal timer is configured via registers to generate a trigger signal with a 20-ms period (synchronized with the power grid's power frequency). This signal is periodically transmitted to the AD7606B ADC chip via a GPIO pin, initiating the analog-to-digital conversion process. The timer interrupt is set to the highest priority to ensure the accuracy and real-time nature of the trigger signal.

[0095] 2. AD7606B ADC chip initialization:

[0096] Configure the AD7606B to operate in single-channel continuous sampling mode, with a sampling rate of 12.8 kHz (acquiring 256 points of data every 20 milliseconds) and a 16-bit two's complement data output format. Also, connect the AD7606B's BUSY pin to the microcontroller's external interrupt interface to send an interrupt signal after sampling is complete.

[0097] 3. Double buffer structure definition and initialization:

[0098] Define a management structure containing two buffers, each of which contains a status flag, a write position pointer, and a data storage area; specifically:

[0099] Status flag: 0 indicates that the buffer can be written to data, and 1 indicates that the buffer is full and can be read;

[0100] Write position pointer: starts counting from 0 and automatically increases by 1 each time a data is written until the buffer capacity limit of 256 points is reached;

[0101] Data storage area: used to sequentially store digital signals acquired by the AD7606B (each buffer can store 256 points of 16-bit integer data).

[0102] During initialization, the first buffer is set as the current write buffer, the second buffer is set to the idle state, the status flags of all buffers are set to 0, the write position pointer is set to 0, and the data storage area is cleared.

[0103] 2. Data acquisition process and double buffer switching mechanism to trigger sampling and interrupt response:

[0104] The timer sends a conversion start signal to the AD7606B every 20 milliseconds. Upon receiving the signal, the AD7606B samples the grid analog signal. Upon conversion completion, the falling edge of the BUSY pin triggers a microcontroller interrupt. The microcontroller, in its interrupt handler, reads the sampled data from the AD7606B and, based on the current write buffer index (initially the first buffer), writes the data to a specified location within that buffer (located by the write position pointer). Each time a piece of data is written, the write position pointer automatically increments by 1. The buffer full detection and switching logic is as follows:

[0105] When the write position pointer of the current write buffer reaches 256, the buffer is determined to be full. At this time: the status flag of the buffer is set to 1 (indicating that it can be read), and the global data ready flag is set; the current write buffer index is switched to another buffer (such as switching from 0 to 1), the write position pointer of the new write buffer is reset to 0, and the sampling data of the next cycle is received; the main task detects the global data ready flag through polling. When the flag is detected to be 1, all 256 points of data in the buffer that has been filled are read according to the current read buffer index, and the status flag of the buffer is reset to 0, and the data ready flag is cleared to prepare for writing in the next cycle.

[0106] 3. Hanning window processing and frequency domain analysis Time domain data windowing and amplitude compensation:

[0107] After extracting 256 points of time domain data from the buffer, the Hanning window function is applied for windowing to suppress spectral leakage. The window coefficient of each sampling point is calculated using this function, and the original data is multiplied by the corresponding window coefficient to smooth the transition of the signal edges and reduce the frequency domain energy diffusion caused by non-integer period truncation.

[0108] Since the Hanning window will attenuate the signal amplitude, it is necessary to calculate the sum of the window function coefficients ∑w i Get the compensation factor The windowed data is multiplied by the compensation factor to restore the true amplitude of the signal. Specifically, the compensation factor is equal to the number of sampling points divided by the sum of the window function coefficients, ensuring the energy accuracy of subsequent frequency domain analysis. Fast Fourier Transform (FFT) and Harmonic Analysis:

[0109] A 256-point fast Fourier transform (FFT) is performed on the windowed and compensated time domain data to convert the signal from the time domain to the frequency domain. The frequency resolution of the FFT calculation is 50 Hz (calculated from the sampling frequency of 12.8 kHz and the number of sampling points of 256), which is consistent with the fundamental frequency of the power grid. The amplitude information of the fundamental wave (50 Hz) and its various harmonics (such as 150 Hz, 250 Hz, etc.) is extracted from the FFT results to form a spectrum distribution result, thereby completing an accurate analysis of the harmonic content of the power grid. Through the above-mentioned double buffering mechanism and Hanning window optimization, the system realizes the parallel execution of data acquisition and processing. Experimental data shows that the amplitude error of the third harmonic after windowing is reduced from ±15% to ±0.5%, effectively improving the real-time and accuracy of harmonic analysis, and meeting the high requirements of the power system for power quality monitoring.

[0110] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A harmonic analysis method based on double-buffered window function optimization, characterized by: The following steps are involved: S1. After the system is powered on, hardware initialization is performed to configure parameters for the STM32F429 microcontroller, AD7606BADC sampling device, and timer. S2. After the system hardware is initialized, a double buffer is initialized, creating two buffers A and B of the same size. Each buffer is preset to store the sampling point data that matches the FFT analysis and the power frequency period. Buffer A is set as the write buffer and Buffer B is set to the idle state. The buffer read and write status, pointer position, and data storage area are marked through a structure to build the hardware foundation for alternating storage. S3. After the double buffer is initialized, the number of analysis points of the FFT module is configured to be consistent with the number of sampling points and matched with the power frequency period according to the sampling rule preset by the double buffer, and the frequency resolution is calculated according to the relationship between the sampling frequency and the number of analysis points, and the calculation rule of frequency domain conversion is established; S4. After the FFT module parameters are configured, the timer periodically sends a conversion start signal to the AD7606B. After the AD7606B completes sampling, the falling edge of the BUSY pin triggers the STM32F429 interrupt, and the sampled data is written into the current write buffer in sequence, starting the data acquisition process. S5. When the write buffer is full of sampling point data matching the power frequency cycle, the data ready status flag of the full buffer is set to 1 through the dual buffer management structure and the buffer is switched to the read buffer. At the same time, the other buffer is switched to the write buffer, so that new data collection and stored data processing are carried out synchronously; S6. After the buffer is switched to the read state, the main task periodically detects the state of the read buffer data preparation state flag bit. When the flag is detected to be 1, all data in the buffer is read and the flag is cleared; S7. After extracting the buffer data, apply the Hanning window function to perform windowing processing on the time domain data. By calculating the sum of the window function coefficients, the compensation factor is obtained and the signal amplitude is restored. Then, a fast Fourier transform is performed on the processed data to output the amplitude information of each frequency component to complete the harmonic analysis.

2. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: Said S1 further comprises the following contents: S1.1: After the system is powered on, the hardware resources of the STM32F429 microcontroller are initialized, including configuring the timer's operating mode, counting period, and interrupt parameters. This enables the timer to periodically send a conversion start signal to the AD7606B ADC chip through the GPIO pin, providing a timing trigger mechanism for subsequent data acquisition. S1.2: After initializing the STM32F429, initialize and configure the AD7606B ADC chip. This includes setting its sampling mode, conversion rate, data output format, and pin levels. This ensures that the AD7606B is ready to respond to sampling instructions triggered by the timer and complete analog-to-digital conversion.

3. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: Said S2 further comprises the following contents: S2.1: The double buffer structure definition includes two parts: a single buffer structure and a double buffer management structure; A single buffer structure is used to describe a single storage unit, including a status flag, a write position pointer, and a data storage array: the status flag uses an 8-bit unsigned integer to identify the buffer status, 0 indicates that it is not full and can be written, and 1 indicates that it is full and can be read; the write position pointer is a 16-bit unsigned integer, counting from 0 to locate the data storage location; the data storage array is an 8-bit unsigned integer array with the number of sampling points matching the power frequency cycle, which is used to store the sampling data of the sampling points matching the power frequency cycle within the power frequency cycle; The dual buffer management structure is used to coordinate the control of two buffers. It contains the data ready flag, the current read and write buffer index, and the buffer array: the data ready flag is an 8-bit unsigned integer that indicates the data ready state, 0 for not ready and 1 for ready; the current write buffer index points to the buffer that is receiving data, and the current read buffer index points to the buffer from which data can be extracted; the buffer array contains two single buffer instances, which implement the physical carrier of write-read ping-pong switching; S2.2: Initialize the double buffer according to the double buffer structure; specifically: first declare the double buffer management variable as an instance to carry the buffer status and data storage; then set the data storage area of ​​the two buffers to 0 through the memory clear operation; then initialize the status flag and pointer, set the data ready flag to 0, indicating that there is no ready data; the current write buffer index is 0, indicating the initial write to buffer 0; the current read buffer index is -1, indicating that there is no read buffer; finally, by looping through the two buffers, set the status flag of each buffer to 0, indicating that it can be written, and the write position pointer to 0, indicating that storage starts from the starting position of the array, establishing the initial state of buffer 0 writing and buffer 1 on standby, providing a basis for subsequent switching to the read buffer when it is full, and activating the parallel mechanism of writing to another buffer at the same time.

4. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: The S3 further includes the following: S3.1: After the double buffer is initialized, the number of analysis points in the FFT module is configured to match the number of sampling points and the power frequency period. This ensures that the FFT calculation covers the complete power frequency period sampling data, ensures that the time domain signal is discretized into sampling points at equal intervals that match the power frequency period, and provides a complete time domain data foundation for frequency domain conversion. S3.2: According to the sampling frequency f s The relationship between the number of analysis points N and the frequency resolution of the FFT module is calculated and configured as follows: Where Δf is the frequency resolution, f s is the sampling frequency, and N is the number of FFT analysis points, which is consistent with the number of sampling points.

5. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: Said S4 further comprises the following contents: S4.1: After the FFT module parameters are configured, the STM32F429 microcontroller starts its internal timer and sends a periodic conversion start signal to the AD7606B ADC chip via a GPIO pin. The timer generates a pulse signal according to the preset sampling period, which is synchronized with the power frequency. This signal is transmitted to the trigger input of the AD7606B via a hardware connection, driving it to start the analog-to-digital conversion process. After each trigger signal is sent, the AD7606B samples the input power grid analog signal, discretizing the continuous signal into digital quantities, providing the original sampled values ​​for subsequent data processing. S4.2: After AD7606B completes a single sampling, the BUSY pin status changes from high level to low level, sending a conversion completion interrupt signal to the STM32F429; the microcontroller captures the falling edge event through the external interrupt interface and immediately executes the interrupt handler: it reads the current sampling value from the data output pin of AD7606B, and writes the data to the data storage area of ​​the buffer according to the current write buffer index recorded in the double buffer management structure, initially buffer 0; the write position is located by the write position pointer of the buffer. Each time a data is written, the write position pointer automatically increases by 1 until the buffer capacity limit is reached, triggering the switching logic. The capacity limit is the number of sampling points that matches the power frequency cycle.

6. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: Said S5 further comprises the following contents: S5.1: When the write position pointer of the current write buffer reaches the buffer capacity limit, the buffer is determined to be full. At this time, the status flag of the buffer is set to 1 through the dual buffer management structure, indicating that the data is ready for the main task to extract. At the same time, the status field of the buffer is updated from 0 to 1, completing the state transition from the write buffer to the read buffer. S5.2: After the full mark is completed, the current write buffer index is first switched from 0 to 1, pointing to another free buffer, making it the new write buffer; at the same time, the current read buffer index is set to the original write buffer index, and a parallel process of writing data to the new buffer and extracting data from the original buffer is established; the write position pointer of the new write buffer is reset to 0, and it starts to receive the sampling data of the next cycle.

7. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: Said S6 further comprises the following contents: S6.1: After the buffer is switched to the read state, the main task polls the data ready flag in the double buffer management structure at a fixed period; This flag is used to identify whether the read buffer has completed data writing and can be extracted: when the data ready status flag is 1, it indicates that the corresponding buffer has been filled with sampling point data that matches the power frequency cycle and can be processed later; when the data ready status flag is 0, the main task continues to wait and does not perform data extraction operations; S6.2: When the main task detects that the data preparation status flag of a buffer is 1, it extracts all sampling point data in sequence from the data storage area of ​​the buffer according to the current read buffer index in the double buffer management structure; after the data extraction is completed, the data preparation status flag is immediately set to 0 and the read buffer index is reset to -1, indicating that the buffer has completed data processing and can re-enter the write buffer queue.

8. The harmonic analysis method based on double-buffered window function optimization according to claim 1, characterized in that: The S7 further includes the following: S7.1: After extracting the time domain data from the buffer, the Hanning window function is applied to the data to suppress spectrum leakage. The Hanning window function calculates the window coefficient of each sampling point through the formula, and then multiplies the original data by the corresponding window coefficient to make the signal edge transition smooth and reduce the frequency domain energy diffusion caused by non-integer period truncation. The window coefficient w i The calculation formula is as follows: Where i is the sampling point index and N is the number of sampling points; Since the Hanning window will attenuate the signal amplitude, it is necessary to calculate the sum of the window function coefficients ∑w i Get the compensation factor The windowed data is then multiplied by the compensation factor to restore the true amplitude of the signal; S7.2: Perform a fast Fourier transform on the windowed and compensated time-domain data to convert the signal from the time domain to the frequency domain. The FFT calculation is based on the number of analysis points configured during the initialization phase. The butterfly algorithm efficiently calculates the complex amplitude of each frequency component and then modulo-calculates the real amplitude at the corresponding frequency point. The number of analysis points matches the number of sampling points. Then, according to the power frequency characteristics of the power grid signal, the fundamental frequency is the fundamental frequency of the target signal, and the amplitude information of the fundamental wave and its harmonics is extracted to form the spectrum distribution result.

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