Signal monitoring via memory system

Abstract

Methods, systems, and apparatus for signal monitoring by a memory system are described. A memory system may receive signaling (e.g., from a host system), and may sample the signal and generate an eye pattern. During a normal mode of operation, the memory system monitors characteristics of the eye pattern to improve signaling. The memory system may determine a voltage level of the signaling based on one or more input parameters and a sampling time associated with the signaling. An indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system), and may be periodically transmitted to the host system.

Description

Technical Field

[0001] The following relates to one or more memory systems, including signal monitoring by the memory system. Background Art

[0002] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0003] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), selectable memory, chalcogenide memory technology, NOR and NAND memory devices, and the like. Memory cells can be described as either volatile or nonvolatile. A memory cell configured in a nonvolatile configuration can maintain a stored logic state for an extended period of time, even in the absence of an external power source. A memory cell configured in a volatile configuration may lose its stored state when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An example of a system supporting signal monitoring by a memory system according to examples as disclosed herein is shown.

[0005] Figure 2 Shown are examples of eye diagrams supporting signal monitoring through a memory system according to examples as disclosed herein.

[0006] Figure 3 An example of a process flow supporting signal monitoring by a memory system according to examples as disclosed herein is shown.

[0007] Figure 4 A block diagram of a memory system supporting signal monitoring through the memory system is shown according to examples as disclosed herein.

[0008] Figure 5 A flow chart showing one or more methods that enable signal monitoring by a memory system according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0009] Some memory systems (e.g., non-volatile memory systems, such as NAND memory systems) can receive signaling from a host system. For example, the memory system can receive the signaling via one or more channels. An oscilloscope or other component of the memory system can sample the signal and generate an eye diagram to provide an indication of the health of the signal integrity. The eye diagram can represent or show four symbols of the signal (e.g., "00," "01," "10," or "11"), and each symbol can be represented by a different voltage amplitude.

[0010] In some cases, it may be advantageous to monitor various aspects of the eye diagram by performing signal quality testing. Some memory systems may perform signal quality testing on signaling received from the host system during diagnostic mode. However, performing signal quality testing while operating in diagnostic mode may introduce additional signaling overhead or undesirable latency to the memory system. Therefore, it may be desirable to configure the memory system to perform signal quality testing during normal operating mode (e.g., non-diagnostic operating mode).

[0011] A memory system configured to perform a signal quality test during a normal operating mode is described herein. In some examples, the memory system may receive signaling (e.g., from a host system) and may sample the signal and generate an eye diagram. During normal operating mode, the memory system may receive signaling (e.g., a command) from the host system to initiate a signal quality test. To perform the signal quality test, the memory system may select one or more input parameters to determine a voltage level of a received signal. For example, the memory system may select a first input parameter (e.g., a timing parameter (Tstep)), a second timing parameter (e.g., a reference voltage parameter (Vstep)), or both. The memory system may then determine a voltage value of the received signal based on the selected input parameters and may store an indication of the voltage value in a register (e.g., a register of the memory system).

[0012] In some cases, the memory system may enter a sleep mode (e.g., a reduced power mode, a sleep mode) after determining the voltage value of the received signal based on selected input parameters. While in sleep mode, the memory system may increment one or more of the selected input parameters for subsequent instances of the signal quality test. For example, the memory system may increment Tstep, Vstep, or both. When the memory system enters (e.g., re-enters) normal operating mode, the memory system may determine (e.g., a second time) the voltage value of the received signal based on the incremented input parameters. The memory system may continue to increment the input parameters until the eye diagram has been sampled and the resulting data (e.g., the results of the signal quality test) can be transmitted to the host system. By performing the signal quality test as described herein, the signaling overhead and latency of the memory system may be reduced, and its overall performance may be improved.

[0013] Initially in reference Figure 1 Features of the present disclosure are described in the context of systems, devices, and circuits. Figure 2 and 3 The features of the present disclosure are described in the context of an eye diagram and process flow. Figure 4 and 5 These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flow diagrams related to signal monitoring through a memory system.

[0014] Figure 1 An example of a system 100 for supporting signal monitoring by a memory system according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and processing devices.

[0015] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0016] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or the devices therein. The processor chipset may include one or more cores, one or more cache memories (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0017] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled with the memory system controller 115).

[0018] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0019] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations that can generally be referred to as access operations at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0020] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0021] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0022] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that can store operating code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, such as in connection with the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 can serve as a cache memory for the memory system controller 115. For example, if the data is read from or written to the memory device 130, the data can be stored in the local memory 120 and the data can be made available within the local memory 120 to the host system 105 (e.g., with reduced latency relative to the memory device 130) for subsequent retrieval or manipulation (e.g., updating) according to the cache policy.

[0023] although Figure 1 The example of the memory system 110 in FIG. 1 has been described as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may each be internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may in some cases be alternatively performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0024] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0025] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown in , memory device 130 - a may include a local controller 135 - a , and memory device 130 - b may include a local controller 135 - b .

[0026] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a block of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0027] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) if each is configured to store two bits of information, triple-level cells (TLC) if each is configured to store three bits of information, quad-level cells (QLC) if each is configured to store four bits of information, or more generally, multi-level cells. Multi-level cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0028] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed on different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0029] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0030] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level, or portions thereof), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0031] In some cases, the memory system controller 115 or the local controller 135 may perform operations for the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background flushing, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that includes, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (eg, data subsequently received from the host system 105 ).

[0032] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0033] The system 100 may include any number of non-transitory computer-readable media that support signal monitoring by the memory system. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions as described herein.

[0034] In some examples, the memory system 110 may receive signaling (e.g., from the host system 105) and may sample the signal and generate an eye diagram. During normal operating mode, the memory system 110 may receive signaling (e.g., a command) from the host system 105 to initiate a signal quality test. To perform the signal quality test, the memory system controller 115 may select one or more input parameters to determine the voltage level of the received signal. For example, the memory system controller 115 may select a first input parameter (e.g., Tstep), a second timing parameter (e.g., Vstep), or both. The memory system controller 115 may then determine the voltage value of the received signal based on the selected input parameters and may store an indication of the voltage value in a register or local memory 120.

[0035] In some cases, the memory system 110 may enter a sleep mode (e.g., a reduced power mode, a sleep mode) after determining the voltage value of the received signal based on selected input parameters. While in sleep mode, the memory system controller 115 may increment one or more of the selected input parameters. For example, the memory system controller 115 may increment Tstep, Vstep, or both. When the memory system 110 enters (e.g., re-enters) a normal operating mode, the memory system controller 115 may determine (e.g., a second time) the voltage value of the received signal based on the incremented input parameters. The memory system controller 115 may continue to increment the input parameters until the eye diagram has been sampled and the resulting data (e.g., the results of the signal quality test) can be transmitted to the host system 105. By performing the signal quality test as described herein, the signaling overhead and latency of the memory system 110 may be reduced, and its overall performance may be improved.

[0036] Figure 2An example of an eye diagram 200 that supports signal monitoring by a memory system according to examples as disclosed herein is shown. Eye diagram 200 can be used to indicate the quality of a signal in high-speed transmission and can represent four symbols of a signal (e.g., "00," "01," "10," or "11"). In some examples, each of the four symbols can be represented by a different voltage amplitude (e.g., amplitudes 205-a, 205-b, 205-c, 205-d). In other examples, eye diagram 200 can represent a signal that can be used to communicate the quality of a memory system (e.g., as described in reference to FIG. 1 ). Figure 1 2. The eye diagram 200 may be used to provide a visual indication of the health of the signal integrity and may indicate the noise margin of the data signal. The noise margin may, for example, refer to the amount by which the signal exceeds the ideal limit of amplitude 205. In some examples, the memory system may perform signal quality testing during sampling period 210, which may reduce the signaling overhead and latency of the memory system while improving its overall performance.

[0037] To generate eye diagram 200, an oscilloscope or other computing device may sample a digital signal according to a sampling period 210 (e.g., a unit interval or bit period). Sampling period 210 may be defined by a clock associated with the transmission of the measured signal. In some examples, the oscilloscope or other computing device may measure the voltage level of the signal during sampling period 210 to form a trace 215. Noise and other factors may cause trace 215 measured from the signal to deviate from a set of ideal step functions. By overlaying multiple traces 215, various characteristics of the measured signal can be determined. For example, eye diagram 200 can be used to identify several characteristics of a communication signal, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. A closed eye may indicate a noisy and / or unpredictable signal or other problems.

[0038] In some examples, eye diagram 200 may indicate width 220. Width 220 of an eye in eye diagram 200 may be used to indicate timing synchronization of a measured signal or jitter effects on the measured signal. In some examples, comparing width 220 to sampling period 210 may provide a measure of the signal-to-noise ratio (SNR) of the measured signal. Each eye in the eye diagram may have a unique width based on characteristics of the measured signal. Width 220 of the measured signal may be modified using various encoding and decoding techniques.

[0039] In other examples, eye diagram 200 may indicate a sampling time 225 (e.g., an ideal sampling time) for determining the value of the logic state represented by the symbol of the measured signal. For example, determining the correct time for sampling the data of the measured signal (e.g., timing synchronization) may be important to minimize the error rate in the detection of the signal. For example, if a computing device samples the signal during a transition time (e.g., rise time 230 or fall time 235), errors may be introduced into the data represented by the symbol of the signal by the decoder. The ideal sampling time 225 of the measured signal may be modified using various encoding and decoding techniques.

[0040] Eye diagram 200 can be used to identify rise time 230 and / or fall time 235 for a transition from first amplitude 205 to second amplitude 205. In other aspects, the slope of trace 215 during rise time 230 or fall time 235 can indicate the sensitivity of the signal to timing errors. For example, the steeper the slope of trace 215 (e.g., the shorter rise time 230 and / or fall time 235), the more ideal the transition between amplitudes 205. Various encoding and decoding techniques can be used to modify the rise time 230 and / or fall time 235 of the measured signal.

[0041] In some examples, eye diagram 200 can be used to identify the amount of jitter 240 in the measured signal. Jitter 240 can refer to timing errors caused by misalignment of rise and fall times. Jitter 240 occurs when a rising or falling edge occurs at a time different from the ideal time defined by the data clock. Jitter 240 can be caused by signal reflections, intersymbol interference, crosstalk, process-voltage-temperature (PVT) variations, random jitter, additive noise, or a combination thereof. Various encoding and decoding techniques can be used to modify the jitter 240 of the measured signal. In some cases, jitter 240 can be different for each signal level or each eye.

[0042] In other examples, the eye diagram 200 may indicate an eye opening 245, which may represent the peak-to-peak voltage difference between the various amplitudes 205. The eye opening 245 may be related to the voltage tolerance used to distinguish between different amplitudes 205 of the measured signal. A smaller tolerance may make it more difficult to distinguish between adjacent amplitudes and may introduce more errors caused by noise. In some cases, a receiver of the signal may compare the signal to one or more threshold voltages positioned between the various amplitudes 205. In other cases, the larger the eye opening 245, the less likely it is that noise will falsely meet one or more voltage thresholds. The eye opening 245 can be used to indicate the amount of additive noise in the measured signal and can be used to determine the signal-to-noise ratio (SNR) of the measured signal. Various encoding and decoding techniques may be used to modify the eye opening 245 of the measured signal. In some cases, the eye opening 245 may be different for each eye. In such cases, the eyes of the multilevel signal may be different.

[0043] In other examples, eye diagram 200 may indicate distortion 250. Distortion 250 may represent overshoot and / or undershoot of the measured signal due to noise or interruptions in the signal path. As the signal settles from an old amplitude (e.g., amplitude 205-c) to a new amplitude (e.g., amplitude 205-b), the signal may overshoot and / or undershoot the new amplitude level. In some examples, distortion 250 may be caused by this overshoot and / or undershoot and may be caused by additive noise in the signal or interruptions in the signal path. Each eye in the eye diagram may have a unique opening based on the characteristics of the measured signal. Various encoding and decoding techniques may be used to modify the distortion 250 of the measured signal. In some cases, distortion 250 may be different for each signal level or each eye.

[0044] For illustrative purposes only Figure 2 Characteristics such as width 220, sampling time 225, rise time 230, fall time 235, jitter 240, eye opening 245, and / or distortion 250 may appear in locations not shown in FIG. Figure 2 In other parts of the eye diagram 200 specifically indicated in FIG.

[0045] As discussed herein, a memory system (e.g., as described in reference Figure 1 The memory system 110 described herein can be accessed from a host system (e.g., as described in reference Figure 1 2. The host system 105 described herein receives signaling. For example, when operating in normal operating mode, the memory system may receive a dedicated test data set and may use an oscilloscope or other components to generate the eye diagram 200. In other cases, the memory system may receive a write command and may generate the eye diagram 200 based on the write command.

[0046] As used herein, normal operating mode (e.g., active mode) may refer to a mode (or duration) when the memory system is receiving or processing commands, signaling, or both from a host system. Additionally or alternatively, sleep mode may refer to a mode (or duration) when the memory system is not receiving or processing commands or signaling from a host system. The memory system may enter sleep mode after receiving a command (e.g., a dedicated command) from the host system or after the absence of signaling for a predefined duration. For example, a sleep command may be defined by a specification such as the JEDEC Universal Flash Storage Host Controller Interface (UFSHCI) 3.0 standard and may be an example of an automatic sleep command. When idle time is detected, the host system (e.g., as described in reference Figure 1The host system 105 described herein may issue an automatic sleep command. That is, if the host system does not issue any commands within a duration, or if the memory system does not process any commands within a duration, the host system may issue an automatic sleep command. The memory system may remain in sleep mode for a duration (e.g., based on the value of a timer) or until one or more commands are received from the host system. For example, an idle timer may be started in response to various conditions being met (e.g., a command not being received or processed). The idle timer may be decremented until it reaches zero or until it is stopped due to the host system accessing the memory system in some manner. If the idle timer reaches zero, the memory system may enter a sleep state. After the memory system exits the sleep state, the idle timer may be reset and re-enabled. The memory system may exit the sleep state in response to a request to communicate information and / or process commands associated with the host system (e.g., via a UniPro link).

[0047] As an example, if the host system detects an idle duration of 2 ms or longer, it may issue an auto-sleep command and the memory system (e.g., as described in reference Figure 1 The memory system controller 115 described herein may perform various aspects of the signal quality test as described herein. An automatic sleep operation (e.g., a command) may allow the host system to autonomously place the UniPro link in a sleep state. In some cases, a first register associated with the memory system may store an indication of whether the memory system supports the automatic sleep operation. In some cases, a second register associated with the memory system may be used for the host system to enable or disable (or otherwise control) the automatic sleep operation.

[0048] In some cases, it may be necessary for the memory system to perform a signal quality test on the signaling received from the host system. For example, a signal quality test may be performed to determine characteristics of the signal, such as width 220, sampling time 225, rise time 230, fall time 235, jitter 240, eye opening 245, and / or distortion 250. To initiate a signal quality test, the memory system (e.g., as described in reference Figure 1 The memory system controller 115 described herein may receive a command from the host system. In some cases, the command may include an instruction to initiate a signal quality test. The command may be a vendor-specific command and may be defined by a standard or specification (e.g., the MPHY specification).

[0049] Upon receiving the command, the memory system controller may select one or more input parameters for performing the signal quality test. For example, the memory system controller may select initial values ​​for Tstep, Vstep, or both as input parameters for the signal quality test. The initial value of Tstep may correspond to the time within sampling period 210 at which the signal is sampled to determine the voltage level (e.g., an instance). In some cases, the initial value of Tstep may correspond to an ideal sampling time 225 (e.g., the midpoint or center of the eye). Over time, the ideal sampling time may change as eye characteristics change (e.g., due to device aging or changes in conditions such as temperature). As part of the signal quality test, different sampling times within sampling period 210 may be tried to determine the quality of the signal. Additionally or alternatively, the initial value of Vstep may correspond to an initial reference voltage 255 within the aperture 245. In some cases, the initial value of Vstep may correspond to the midpoint or center of the aperture 245. Over time, the ideal reference voltage used to distinguish between two states may change as eye characteristics change (e.g., due to device aging or changes in conditions such as temperature). As part of a signal quality test, different reference voltages may be tried to compare with the measured signal to determine the quality of the signal.In some examples, the terms Tstep and Vstep may refer to the incremental difference in value for the next test iteration relative to the current test iteration.

[0050] The memory system controller may also select a number of iterations (e.g., loops) for performing the signal quality test. For example, after determining the voltage value of the received signal based on Tstep and Vstep, the memory system controller may increment Tstep, Vstep, or both and determine (e.g., for a second instance) the voltage value of the received signal. Each instance in which the memory system controller determines the voltage value of the received signal (e.g., after incrementing Tstep, Vstep, or both) may correspond to an iteration (e.g., loop). The memory system controller may select the number of iterations so that sufficient data points are collected to accurately analyze the quality of the signal. For example, the memory system controller may select 100 or 1,000 iterations for performing the signal quality test.

[0051] In some examples, the memory system controller may determine a voltage value for the signal based on Tstep and Vstep (e.g., based on the ideal sampling time 225 and the initial reference voltage 255). As described herein, the initial values ​​of Tstep and Vstep may correspond to the midpoint of the width 220 and opening 245, respectively, of an ideal eye (e.g., an eye having characteristics corresponding to a known symbol). Thus, the memory system controller may determine a voltage value (e.g., a first voltage value) for the symbol at a first time (e.g., at Tstep, at the ideal sampling time 225) relative to the initial reference voltage 255 (e.g., relative to Vstep). The memory system controller may store (e.g., save) an indication of the voltage value to a component of the memory system. For example, the memory system controller may store the indication as a data point in a log or register of the memory system.

[0052] After determining the first voltage value of the signal, the memory system may enter a sleep mode. In some cases, the memory system may be prompted to enter the sleep mode based on a command received from the host system. In other cases, the memory system may enter the sleep mode based on the absence of signaling received from the host system (e.g., no dedicated command received). In either case, when operating in the sleep mode, the memory system controller may increment Tstep, Vstep, or both.

[0053] To increment Tstep, the memory system controller may select a second time within sampling period 210. The second time may be before or after the first time. That is, Tstep may be incremented (or decremented) in either direction relative to ideal sampling time 225. Additionally or alternatively, to increment Vstep, the memory system controller may select a second reference voltage within aperture 245. The second reference voltage may be greater than or less than the first reference voltage. That is, Vstep may be incremented (or decremented) in either direction relative to initial reference voltage 255. In some cases, during a signal quality test, Tstep may be incremented a different number of times than Vstep. For example, the memory system controller may increment Tstep a first number of times (e.g., 40 times) and may increment Vstep a second number of times (14 times) during a signal quality test. Thus, in some cases, both Tstep and Vstep may be incremented, while in other cases, only one of Tstep or Vstep may be incremented when operating in sleep mode.

[0054] After incrementing Tstep, Vstep, or both, the memory system may exit sleep mode. In some cases, the memory system may exit sleep mode (and enter normal or active operating mode) based on receiving a command received from the host system. In other cases, the memory system may exit sleep mode based on signaling received from the host system. For example, the memory system may receive a read command, a write command, or another type of command that may cause the memory system to exit sleep mode and enter (e.g., re-enter) active or normal operating mode.

[0055] When operating in a normal or active operating mode, the memory system controller may use the incremented Tstep or Vstep (or both) to determine a voltage value (e.g., a second voltage value) of a signal. The memory system controller may store (e.g., save) an indication of the second voltage value to a component of the memory system. For example, the memory system controller may store the indication as a data point in a log or register of the memory system. The memory system may continue to increment Tstep, Vstep, or both until a selected number of iterations (e.g., loops) is met.

[0056] Once the selected number of iterations is met, the memory system controller may write a value to the register indicating that the signal quality test is complete. For example, the memory system controller may update the value stored in the register (e.g., from 0 to 1), which may indicate that the signal quality test is complete. In some cases, the host system may periodically poll the register to determine whether the signal quality test is complete. That is, after initiating the signal quality test, the host system may poll the register at predefined intervals. When the host system determines (e.g., based on the value of the register) that the signal quality test is complete, the host system may transmit a command (e.g., a request) for the results of the signal quality test. The memory system may transmit the results of the signal quality test in response to the command and may delete the results after successfully transmitting them to the host system. By performing the signal quality test as described herein, the signaling overhead and latency of the memory system may be reduced, and its overall performance may be improved.

[0057] Figure 3 An example of a process flow 300 for supporting signal monitoring by a memory system according to examples as disclosed herein is shown. The process flow 300 may include one or more aspects of the system 100. For example, the process flow 300 may include a host system 305, a memory system 310, a memory system controller 315, registers 320, and a log 325, which may be any of the processes described herein (including with reference to FIG. 3 ). Figure 1) . The process flow 300 can support performing signal quality testing on data received from the host system 305, which can reduce signaling overhead and latency of the memory system 310 while improving its overall performance.

[0058] Process flow 300 may illustrate an example of memory system controller 315 performing signal quality testing on data received from host system 305. Alternative examples of the following may be implemented, with some of the processes performed in a different order than described or not performed at all. In some cases, the process may include additional features not mentioned below, or additional processes may be added.

[0059] Aspects of process flow 300 may be implemented by memory system controller 315 and other components. Additionally or alternatively, aspects of process flow 300 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to a host system or memory system). For example, when executed by a controller (e.g., memory system controller 315), the instructions may cause the controller to perform the operations of process flow 300.

[0060] At 327, the memory system 310 may operate in an active mode (eg, normal mode). As described herein, the memory system 310 may receive and process commands from the host system 305 while operating in active mode. Figure 3 Not shown, but memory system 310 may operate in an active mode until it transitions to a sleep mode (eg, at 341).

[0061] At 329, the memory system 310 may receive a command. In some cases, the command may be received by the memory system controller 315 from the host system 305 and may include an indication to initiate a signal quality test. The command may be a vendor-specific command and may be defined by a standard or specification (e.g., the MPHY specification).

[0062] At 331, the memory system 310 may receive data. In some examples, the data may be received by the memory system controller 315 from the host system 305. The data may be test data or a write command. For example, the host system 305 may transmit the test data to the memory system 310 for the purpose of performing a signal quality test. In other examples, the host system 305 may transmit a write command, and the memory system controller 315 may perform a signal quality test on the data associated with the write command.

[0063] At 333, the memory system may select initial input parameters. In some examples, the memory system controller 315 may select an initial first input parameter (e.g., Tstep) and an initial second input parameter (e.g., Vstep). In some cases, the memory system controller 315 may also select a number of iterations (e.g., loops) for performing the signal quality test.

[0064] At 335, a voltage value of the signal can be determined. The memory system controller 315 can determine the voltage value based on the signal associated with data received (e.g., at 331) from the host system 305. In some examples, the voltage value of the signal can be determined at a first time (e.g., according to an initial Tstep value) and can be determined based on the initial Vstep value.

[0065] Additionally or alternatively, at 335, the memory system controller 315 may determine a timing window for the signal based on the initial input parameters. The timing window may refer to a voltage value of the signal at a given time. For example, a voltage value within a threshold range of a target voltage value at a given time may indicate a signal (or portion of a signal) having relatively high signal quality. In other cases, a voltage value outside the threshold range of the target voltage value at a given time may indicate a signal (or portion of a signal) having relatively low signal quality.

[0066] At 337, the indication of the voltage value can be written to the memory system 310. In some examples, the memory system controller 315 can write the indication of the voltage value to the memory system log 325. The log 325 can store one or more indications of the corresponding voltage value, which can be transmitted to the host system 305 after the signal quality test is completed.

[0067] At 339, the memory system 310 may receive a command. In some cases, the command may be received by the memory system controller 315 from the host system 305 and may include an indication to transition from an active mode to a sleep mode.

[0068] The memory system 310 may transition from the active mode to the sleep mode at 341. As described herein, the sleep mode may refer to a low power mode, a reduced power mode, or any mode other than the active mode.

[0069] At 343, one or more of the input parameters may be incremented. In some examples, the memory system controller 315 may increment Tstep, Vstep, or both. For example, Tstep may be incremented and Vstep may remain constant, Tstep may remain constant and Vstep may be incremented, or both Tstep and Vstep may be incremented.

[0070] At 345, the memory system 310 may receive a command. In some cases, the command may be received by the memory system controller 315 from the host system 305 and may include an indication to transition from a sleep mode to an active mode.

[0071] At 347 , the memory system 310 may transition from the sleep mode to the active mode. As described herein, the active mode may refer to a mode in which the memory system 310 receives and processes commands received from the host system 305 .

[0072] At 349, the voltage value of the signal can be determined a second time. The memory system controller 315 can use the updated (e.g., incremented) input parameters to determine the voltage value at the second time. In some examples, the voltage value of the signal can be determined at the second time (e.g., according to the incremented Tstep value) and can be determined based on the incremented Vstep value.

[0073] Additionally or alternatively, at 349, the memory system controller 315 may determine a timing window for the signal based on the updated (e.g., incremented) input parameter. The timing window may refer to a voltage value of the signal at a given time. For example, a voltage value within a threshold range of a target voltage value at a given time may indicate a signal (or portion of a signal) having relatively high signal quality. In other cases, a voltage value outside the threshold range of the target voltage value at a given time may indicate a signal (or portion of a signal) having relatively low signal quality.

[0074] At 351, an indication of the second voltage value can be written to the memory system 310. In some examples, the memory system controller 315 can write the indication of the second voltage value to a log 325 of the memory system.

[0075] In some cases, although not Figure 4 , but the operations between 339 and 351 may be performed any number of times. For example, the operations performed between 339 and 351 may constitute one iteration (e.g., one loop). The number of loops performed as part of the signal quality test may be based on the number of iterations selected by the memory system controller (e.g., at 333).

[0076] At 353, a value may be written to register 320 of memory system 310. In some cases, memory system controller 315 may write (or update) a value indicating completion of the signal quality test to register 320. For example, memory system controller 315 may write a "1" (or update a "0" to a "1") to indicate completion of the signal quality test.

[0077] At 355, the memory system 310 may receive a command. In some cases, the command may be received by the memory system controller 315 from the host system 305 and may include a request to poll the register 320. Although not shown, the host system 305 may poll the register 320 at one or more intervals prior to 355.

[0078] At 357, the value of the register may be transmitted to the host system 305. In some cases, the value may be transmitted by the memory system controller 315 and may indicate that the signal quality test is complete.

[0079] At 359, the memory system 310 may receive a command. In some cases, the command may be received by the memory system controller 315 from the host system 305 and may include a request to store data to the log 325. The command may be transmitted by the host system 305 based on the value received (e.g., at 357).

[0080] At 361 , the data stored to the log 325 may be transferred to the host system 305 . In some cases, the data may be transferred by the memory system controller 315 .

[0081] At 363, the data stored to the log 325 may be deleted. In some cases, the data may be deleted by the memory system controller 315. By performing signal quality tests as described herein, the signaling overhead and latency of the memory system 310 may be reduced, and its overall performance may be improved.

[0082] Figure 4 A block diagram 400 is shown of a memory system 420 that supports signal monitoring by a memory system according to examples as disclosed herein. The memory system 420 may be a memory system as described in reference Figures 1 to 3 Memory system 420 or its various components may be examples of means for performing various aspects of signal monitoring by a memory system as described herein. For example, memory system 420 may include a receiving component 425, a determining component 430, a writing component 435, a transmitting component 440, a transforming component 445, a deleting component 450, an incrementing component 455, a selecting component 460, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0083] The receiving component 425 may be configured to or otherwise support means for receiving a command at the memory system, the command including an indication to initiate a signal quality test. The determining component 430 may be configured to or otherwise support means for determining, based at least in part on receiving the command, at a first time, a voltage level of a signal received by the memory system based on a first input parameter relative to a second input parameter. The writing component 435 may be configured to or otherwise support means for writing a value to a register of the memory system to indicate completion of the signal quality test based at least in part on determining the voltage level of the signal. The transmitting component 440 may be configured to or otherwise support means for transmitting data to the host system based at least in part on writing a value to a register of the memory system, the data including an indication of the voltage level of the signal based on the first input parameter and the second input parameter.

[0084] In some examples, transition component 445 can be configured as or otherwise support means for transitioning from an active mode to a dormant mode by the memory system based at least in part on a voltage level of the determination signal.

[0085] In some examples, the incrementing component 455 can be configured or otherwise support means for incrementing a first input parameter in response to operating in the sleep mode. In some examples, the transitioning component 445 can be configured or otherwise support means for transitioning from the sleep mode to the active mode based at least in part on incrementing the first input parameter. In some examples, the determining component 430 can be configured or otherwise support means for determining, at a second time, a voltage level of a signal received by the memory system relative to a second input parameter based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter.

[0086] In some examples, the incrementing component 455 can be configured or otherwise support means for incrementing the second input parameter when operating in the sleep mode. In some examples, the transitioning component 445 can be configured or otherwise support means for transitioning from the sleep mode to the active mode based at least in part on incrementing the second input parameter. In some examples, the determining component 430 can be configured or otherwise support means for determining, at a first time, a voltage level of a signal received by the memory system relative to the incremented second input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented second input parameter.

[0087] In some examples, the incrementing component 455 can be configured to or otherwise support means for incrementing the first input parameter and the second input parameter when operating in the sleep mode. In some examples, the transitioning component 445 can be configured to or otherwise support means for transitioning from the sleep mode to the active mode based at least in part on incrementing the first input parameter and the second input parameter. In some examples, the determining component 430 can be configured to or otherwise support means for determining, at a third time, a voltage level of a signal received by the memory system relative to the incremented second input parameter based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter and the second input parameter.

[0088] In some examples, the receiving component 425 can be configured to or otherwise support means for receiving a second command at the memory system that includes an indication to transition from the sleep mode to the active mode, wherein the transferring of data to the host system is based at least in part on receiving the second command.

[0089] In some examples, write component 435 can be configured as or otherwise support means for writing data to the memory system based at least in part on a voltage level of a determined signal, wherein transferring the data to the host system is based at least in part on writing the data to the memory system. In some examples, delete component 450 can be configured as or otherwise support means for deleting data from the memory system based at least in part on transferring the data to the host system.

[0090] In some examples, receiving component 425 can be configured to or otherwise support means for receiving a third command to poll a value of a register of the memory system based at least in part on writing the value to the register. In some examples, transmitting component 440 can be configured to or otherwise support means for transmitting an indication of the value of the register to the host system based at least in part on receiving the third command.

[0091] In some examples, receiving component 425 may be configured to or otherwise support means for receiving a fourth command requesting data associated with the signal quality test based at least in part on transmitting an indication of the value of the register to the host system, wherein the data is transmitted to the host system based at least in part on receiving the fourth command.

[0092] In some examples, the incrementing component 455 can be configured or otherwise support means for incrementing the first input parameter, the second input parameter, or both a plurality of times. In some examples, the determining component 430 can be configured or otherwise support means for determining a voltage level of the signal, a timing window of the signal, or both after each increment of the first input parameter, the second input parameter, or both.

[0093] In some examples, determining component 430 may be configured as or otherwise support means for determining that a voltage level of a signal has been determined a threshold number of times, wherein transmitting data to the host system is based at least in part on determining that the voltage level of the signal has been determined the threshold number of times.

[0094] In some examples, receiving component 425 can be configured or otherwise support means for receiving information for a signal quality test to be performed based at least in part on receiving a command, wherein the signal received by the memory system is associated with the information for the signal quality test to be performed.

[0095] In some examples, the receiving component 425 can be configured to or otherwise support means for receiving a write command based at least in part on a receive command, wherein a signal quality test is performed on a signal associated with the write command, wherein the signal received by the memory system is associated with the write command.

[0096] In some examples, selection component 460 can be configured as or otherwise support means for selecting, by the memory system, the first input parameter and the second input parameter based at least in part on receiving the command.

[0097] Figure 5 A flow chart illustrating a method 500 for supporting signal monitoring by a memory system according to an example disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 The memory system described herein performs. In some examples, the memory system may execute an instruction set to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform various aspects of the described functions.

[0098] At 505, the method may include receiving a command at a memory system, the command including an indication to initiate a signal quality test. The operations of 505 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 505 may be performed as described in reference to Figure 4 The receiving component 425 is described as executing.

[0099] At 510, the method may include determining, based at least in part on receiving the command, at a first time, a voltage level of a signal received by the memory system based on a first input parameter relative to a second input parameter. The operations of 510 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 510 may be as described in reference to Figure 4 The described determination component 430 performs.

[0100] At 515, the method may include writing a value to a register of the memory system to indicate completion of the signal quality test based at least in part on the voltage level of the determined signal. The operations of 515 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 515 may be described in detail with reference to Figure 4 The write component 435 is described as executing.

[0101] At 520, the method may include transmitting data to the host system based at least in part on writing a value to a register of the memory system, the data including an indication of a voltage level of a signal based on the first input parameter and the second input parameter. The operations of 520 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 520 may be implemented as described in reference to Figure 4 The described transmission component 440 is executed.

[0102] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0103] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: receiving a command at a memory system, the command comprising an indication to initiate a signal quality test; determining, based at least in part on receiving the command, at a first time, a voltage level of a signal received by the memory system based on a first input parameter relative to a second input parameter; based at least in part on determining the voltage level of the signal, writing a value to a register of the memory system to indicate completion of the signal quality test; and transmitting, based at least in part on writing the value to the register of the memory system, data to a host system, the data comprising an indication of the voltage level of the signal based on the first and second input parameters.

[0104] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for transitioning from an active mode to a sleep mode by the memory system based at least in part on determining the voltage level of the signal.

[0105] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of Aspect 2, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: incrementing the first input parameter in response to operating in the sleep mode; transitioning from the sleep mode to the active mode based at least in part on incrementing the first input parameter; and determining, at a second time, the voltage level of the signal received by the memory system relative to the second input parameter based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter.

[0106] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 2 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: while operating in the sleep mode, incrementing the second input parameter; transitioning from the sleep mode to the active mode based at least in part on incrementing the second input parameter; and determining, at the first time, the voltage level of the signal received by the memory system relative to the incremented second input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented second input parameter.

[0107] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 2 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: while operating in the sleep mode, incrementing the first input parameter and the second input parameter; transitioning from the sleep mode to the active mode based at least in part on incrementing the first input parameter and the second input parameter; and determining, at a third time, the voltage level of the signal received by the memory system relative to the incremented second input parameter based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter and the second input parameter.

[0108] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 2 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: receiving a second command at the memory system, the second command comprising an indication to transition from the sleep mode to the active mode, wherein transferring the data to the host system is based at least in part on receiving the second command.

[0109] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for performing the following operations: writing the data to the memory system based at least in part on determining the voltage level of the signal, wherein transferring the data to the host system is based at least in part on writing the data to the memory system, and deleting the data from the memory system is based at least in part on transferring the data to the host system.

[0110] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: receiving a third command to poll the value of the register based at least in part on writing the value to the register of the memory system; and transmitting an indication of the value of the register to the host system based at least in part on receiving the third command.

[0111] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for performing the following operations: based at least in part on transmitting the indication of the value of the register to the host system, receiving a fourth command requesting the data associated with the signal quality test, wherein based at least in part on receiving the fourth command, transmitting the data to the host system.

[0112] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: incrementing the first input parameter, the second input parameter, or both a plurality of times; and determining the voltage level of the signal, the timing window of the signal, or both after each increment of the first input parameter, the second input parameter, or both.

[0113] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of Aspect 10, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: determining that the voltage level of the signal has been determined a threshold number of times, wherein transmitting the data to the host system is based at least in part on determining that the voltage level of the signal has been determined the threshold number of times.

[0114] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 11, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for performing the following operations: based at least in part on receiving the command, receiving information on which the signal quality test is to be performed, wherein the signal received by the memory system is associated with the information on which the signal quality test is to be performed.

[0115] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 12, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing the following operations: receiving a write command based at least in part on receiving the command, wherein the signal quality test is performed on a signal associated with the write command, wherein the signal received by the memory system is associated with the write command.

[0116] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 13, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for selecting the first input parameter and the second input parameter by the memory system based at least in part on receiving the command.

[0117] It should be noted that the described techniques include possible implementations, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0118] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols, which may be referenced throughout the above description of signaling, may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0119] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component, such as a switch, transistor, or other component. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as a switch or transistor.

[0120] The term "coupled" (e.g., "electrically coupled") may refer to a condition that moves from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via conductive paths, to a closed-circuit relationship between the components in which signals can communicate between the components via conductive paths. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0121] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between them are isolated from one another when the switch is open. If a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0122] As used herein, the term "layer" or "level" refers to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or level can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or level can be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level can include different elements, components, and / or materials. In some instances, a layer or level can be composed of two or more sub-layers or sub-levels.

[0123] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if they are used to describe a conditional action, a conditional process, or a connection between parts of a process.

[0124] The term "in response to" may refer to a condition or action that occurs at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0125] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "at least partially based on," or "in response to" some other step, action, event, or condition may be performed in addition or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0126] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0127] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0128] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" and is not "preferred over" or "superior to other examples." The detailed description includes specific details that provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0129] In the drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0130] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0131] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0132] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0133] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0134] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a controller associated with the memory device, wherein the controller is configured to cause the apparatus to: receiving a command, the command including an instruction to initiate a signal quality test; determining, at a first time, a voltage level of a signal received by the controller based on a first input parameter relative to a second input parameter based at least in part on receiving the command; writing a value to a register of the memory device to indicate completion of the signal quality test based at least in part on determining the voltage level of the signal; as well as Based at least in part on writing the value to the register of the memory device, data is transmitted to a host system, the data including an indication of the voltage level of the signal based on the first input parameter and the second input parameter.

2. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Based at least in part on determining the voltage level of the signal, transitioning from an active mode to a sleep mode.

3. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: incrementing the first input parameter in response to operating in the sleep mode; transitioning from the dormant mode to the active mode based at least in part on incrementing the first input parameter; as well as The voltage level of the signal received by the controller relative to the second input parameter is determined at a second time based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter.

4. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: while operating in the sleep mode, incrementing the second input parameter; transitioning from the dormant mode to the active mode based at least in part on incrementing the second input parameter; as well as The voltage level of the signal received by the controller is determined at the first time relative to an incremented second input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented second input parameter.

5. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: while operating in the sleep mode, incrementing the first input parameter and the second input parameter; transitioning from the dormant mode to the active mode based at least in part on incrementing the first input parameter and the second input parameter; as well as The voltage level of the signal received by the controller relative to the incremented second input parameter is determined at a third time based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter and the second input parameter.

6. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: A second command is received, the second command including an indication to transition from the sleep mode to the active mode, wherein transferring the data to the host system is based at least in part on receiving the second command.

7. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: writing the data to the memory device based at least in part on determining the voltage level of the signal, wherein transmitting the data to the host system is based at least in part on writing the data to the memory device; and Based at least in part on transferring the data to the host system, the data is deleted from the memory device.

8. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Based at least in part on writing the value to the register of the memory device, receiving a third command to poll the value of the register; and Based at least in part on receiving the third command, an indication of the value of the register is transmitted to the host system.

9. The apparatus of claim 8, wherein the controller is further configured to cause the apparatus to: Based at least in part on transmitting the indication of the value of the register to the host system, receiving a fourth command requesting the data associated with the signal quality test, wherein the data is transmitted to the host system based at least in part on receiving the fourth command.

10. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: incrementing the first input parameter, the second input parameter, or both a plurality of times; and After each increment of the first input parameter, the second input parameter, or both, the voltage level of the signal, a timing window of the signal, or both are determined.

11. The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to: A determination is made that the voltage level of the signal has been determined a threshold number of times, wherein transmitting the data to the host system is based at least in part on determining that the voltage level of the signal has been determined the threshold number of times.

12. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Based at least in part on receiving the command, information that the signal quality test is to be performed is received, wherein the signal received by the controller is associated with the information that the signal quality test is to be performed.

13. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Based at least in part on receiving the command, a write command is received, wherein the signal quality test is performed on a signal associated with the write command, wherein the signal received by the controller is associated with the write command.

14. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Based at least in part on receiving the command, the first input parameter and the second input parameter are selected.

15. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command at a memory system, the command including an indication to initiate a signal quality test; determining, at a first time and based at least in part on receiving the command, a voltage level of a signal received by the memory system relative to a second input parameter based on a first input parameter; writing a value to a register of the memory system to indicate completion of the signal quality test based at least in part on determining the voltage level of the signal; as well as Based at least in part on writing the value to the register of the memory system, data is transmitted to a host system, the data including an indication of the voltage level of the signal based on the first input parameter and the second input parameter.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Based at least in part on determining the voltage level of the signal, transitioning, by the memory system, from an active mode to a sleep mode.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: incrementing the first input parameter in response to operating in the sleep mode; transitioning from the dormant mode to the active mode based at least in part on incrementing the first input parameter; as well as The voltage level of the signal received by the memory system relative to the second input parameter is determined at a second time based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter.

18. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: while operating in the sleep mode, incrementing the second input parameter; transitioning from the dormant mode to the active mode based at least in part on incrementing the second input parameter; as well as The voltage level of the signal received by the memory system is determined at the first time relative to an incremented second input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented second input parameter.

19. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: while operating in the sleep mode, incrementing the first input parameter and the second input parameter; transitioning from the dormant mode to the active mode based at least in part on incrementing the first input parameter and the second input parameter; as well as The voltage level of the signal received by the memory system relative to the incremented second input parameter is determined at a third time based on the incremented first input parameter, wherein the data transmitted to the host system includes an indication of the voltage level of the signal based on the incremented first input parameter and the second input parameter.

20. A method comprising: receiving a command at a memory system, the command including an indication to initiate a signal quality test; determining, at a first time and based at least in part on receiving the command, a voltage level of a signal received by the memory system relative to a second input parameter based on a first input parameter; writing a value to a register of the memory system to indicate completion of the signal quality test based at least in part on determining the voltage level of the signal; as well as Based at least in part on writing the value to the register of the memory system, data is transmitted to a host system, the data including an indication of the voltage level of the signal based on the first input parameter and the second input parameter.

Images