Pre-reading method of solid state disk and solid state disk

Abstract

The invention discloses a solid state disk pre-reading method and a solid state disk. The method is applied to a solid state disk controller, and comprises the following steps: receiving a first read instruction sent by a host; determining a pre-read data volume of the first read instruction according to the state information of the solid state disk; determining a first pre-read address interval based on a first read address interval in the first read instruction and a pre-read data volume, generating a pre-read instruction according to the first pre-read address interval, sending the pre-read instruction to a flash memory controller to read first pre-read data, and storing the first pre-read data in an internal cache; receiving a second read instruction sent by the host, wherein an address intersection exists between a second read address interval in the second read instruction and the first pre-read address interval; and responding to the second read instruction according to the first pre-read data and the address intersection. Through the scheme provided by the embodiment, the host read delay of the SSD can be reduced, and the influence of the pre-read operation on the effective bandwidth of the SSD is reduced.

Description

Technical Field

[0001] This article relates to the field of data storage technology, and in particular to a pre-reading method and electronic device for a solid-state hard disk. Background Art

[0002] With the rapid development of the big data service industry, especially in cutting-edge fields like 5G and AI, more and more data needs to be quickly stored on storage media such as SSDs (solid-state drives), and this data needs to be frequently accessed by hosts. This requires the SSD controller to have as low a read command latency as possible. The SSD controller needs to quickly return the data required by the host within a short period of time after receiving a read command from the host.

[0003] Host read latency is a key performance metric for an SSD controller. Currently, SSD pre-read technology is commonly used to reduce host read latency. SSD pre-read technology assumes that the host's next read behavior will still be sequential. Based on the address range of the host's read command, the SSD controller preemptively sends a flash memory read command to the flash memory controller (the address range corresponding to the flash memory read command corresponds to the address range that the SSD controller predicts the host will read next). The pre-read data is then read from the flash memory chip and cached in the SSD controller's internal data buffer. If the host's subsequent read behavior is indeed the sequential read predicted by the SSD controller, the SSD controller can return the cached data to the host, significantly reducing host read latency. After the pre-read data is transmitted to the host, the SSD controller invalidates all pre-read data previously cached in the internal cache. However, if the host's subsequent read behavior is not sequential, the pre-read data cached in the SSD controller's internal cache becomes invalid.

[0004] Current SSD pre-reading methods have complex management processes and lack data volume management for pre-read operations, which can easily lead to excessive data reading, writing, and transmission. Furthermore, when the SSD controller discovers that a previously issued pre-read instruction is invalid, there is no effective mechanism to promptly notify the SSD backend to terminate the pre-read operation, severely impacting the SSD's effective transmission bandwidth. Therefore, an SSD pre-reading strategy is needed to reduce the SSD controller's host read latency and minimize the impact of pre-reading operations on the SSD's effective bandwidth. Summary of the Invention

[0005] The embodiments of the present application provide a pre-reading method for a solid-state drive and a solid-state drive, which can reduce the host read latency of the SSD and reduce the impact of the pre-reading operation on the effective bandwidth of the SSD.

[0006] An embodiment of the present application provides a pre-reading method for a solid-state drive, which is applied to a solid-state drive controller and is characterized by comprising: Receive the first read command sent by the host; determining, according to the state information of the solid-state drive, an amount of pre-read data for the first read instruction; determining a first pre-read address interval based on the first read address interval and the amount of pre-read data in the first read instruction, generating a pre-read instruction based on the first pre-read address interval, and sending the pre-read instruction to the flash memory controller to read the first pre-read data and store it in an internal cache; receiving a second read instruction sent by a host, wherein a second read address interval in the second read instruction and the first pre-read address interval have an address intersection; The second read instruction is responded to according to the intersection of the first pre-read data and the address.

[0007] In an exemplary embodiment, responding to the second read instruction according to the intersection of the first pre-read data and the address includes: If the first pre-read address interval completely covers the second read address interval, the data corresponding to the second read address interval included in the first pre-read data is directly read from the internal cache and returned to the host.

[0008] In an exemplary embodiment, responding to the second read instruction according to the intersection of the first pre-read data and the address includes: If the first pre-read address interval partially covers the second read address interval, determining a second pre-read address interval based on the read address interval of the second read instruction and the address intersection; wherein the second pre-read address interval is the address outside the address intersection in the second read interval; generating a pre-read instruction according to the second pre-read address interval, and sending the instruction to the flash memory controller to read the second pre-read data and store the data in the internal cache; The data corresponding to the address intersection included in the first pre-read data and the second pre-read data are read from the internal cache and returned to the host.

[0009] In an exemplary embodiment, determining the pre-read data amount of the first read instruction according to the status information of the solid-state drive includes: According to the status information of the solid state drive, a preset weight arbitration strategy is used to determine a first weight; if the first weight is greater than a preset weight threshold, the pre-read data amount of the first read instruction is determined according to the first weight.

[0010] In an exemplary embodiment, after returning the data to the host, the method further includes: A second weight is determined using a preset weight arbitration strategy according to the state information of the solid-state drive; if the second weight is greater than a preset weight threshold, a pre-read is initiated for the second read instruction.

[0011] In an exemplary embodiment, the preset weight arbitration strategy includes: Calculating corresponding weight values ​​according to each piece of status information in the status information of the solid state drive; Add up all the calculated weight values ​​to get the weight calculation result; The state information of the solid state drive includes one or more of the following: available space in the internal cache, the number of read instructions sent by the host, and bandwidth utilization of the flash memory controller.

[0012] In an exemplary embodiment, if no read instruction with a read address interval having an address intersection with the first pre-read address interval sent by the host is received within a preset time period, the execution status of the pre-read instruction is marked as invalid, and the first pre-read data is released from the internal cache.

[0013] In an exemplary embodiment, after generating a pre-read instruction according to the first pre-read address range and sending the instruction to the flash memory controller to read the first pre-read data, and before storing the data in the internal cache, the method further includes: monitoring the execution status of the pre-read instruction; If the execution status of the pre-read instruction is marked as invalid before the first pre-read data is read, the execution of the pre-read instruction is terminated immediately.

[0014] In an exemplary embodiment, when the execution status of the pre-read instruction is marked as invalid, the method further includes: The first read instruction corresponding to the pre-read instruction is promoted to the highest priority to immediately terminate the execution of the pre-read instruction.

[0015] In another embodiment of the present application, a solid state drive is provided, including a solid state drive controller. The solid state drive controller is used to execute the solid state drive pre-reading method described above.

[0016] The technical solution provided by the embodiments of the present application can reduce the host read latency of the SSD and reduce the impact of the pre-read operation on the effective bandwidth of the SSD.

[0017] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0019] Figure 1 A schematic diagram of a flow chart of a pre-reading method for a solid-state hard disk provided in an embodiment of the present application; Figure 2 A functional module block diagram of a solid-state drive pre-reading method provided in an embodiment of the present application; DETAILED DESCRIPTION

[0020] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the range encompassed by the embodiments described in this application. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0021] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of the appended claims.

[0022] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and range of the embodiments of the present application.

[0023] Figure 1 A schematic flow chart of a solid state drive pre-reading method provided by an embodiment of the present application is shown, which is applied to a solid state drive controller. Figure 2 The functional module block diagram of the solid state drive pre-reading method in this embodiment is shown as follows: Figure 1 As shown, the method includes: Step 100: Receive a first read instruction sent by a host; In this embodiment, a host read command monitor monitors read commands from the host in real time. When a valid read command is detected, the host read command information is promptly transmitted to other modules. The first read command includes the first read command received by the solid-state drive controller after power-on, as well as read commands whose read address range does not overlap with the first pre-read address range of a previously initiated pre-read operation.

[0024] Step 101: determining the pre-read data amount of the first read instruction according to the status information of the solid state drive; In this embodiment, the pre-read data amount of the first read instruction can be dynamically determined according to the real-time status information of the solid state hard disk.

[0025] Step 102: determining a first pre-read address interval based on the first read address interval and the amount of pre-read data in the first read instruction, generating a pre-read instruction based on the first pre-read address interval, and sending the instruction to the flash memory controller to read the first pre-read data and store it in an internal cache; In this embodiment, the solid-state drive controller may record the pre-read operation related information of the first read instruction in a pre-read mapping table to facilitate tracking of the processing status of each pre-read operation, and timely and accurately update the information of each element in the pre-read mapping table through a pre-read mapping table manager.

[0026] In an exemplary embodiment, the pre-read mapping table is shown in Table 1, where each row in the table represents information related to a pre-read command issued by the SSD controller for a pre-read operation: Table 1 Pre-reading mapping table The meaning of each column in the pre-read mapping table is as follows: prd_stas (pre read command status) is the pre-read command status, used to track the execution stage of the pre-read command. The SSD controller can subdivide the entire pre-read process into several stages and record the stage status in the prd_stas column of the pre-read mapping table in real time.

[0027] In an exemplary embodiment, the entire pre-reading process can be divided into five stages, and 0, 1, 2, 3, and 4 are used as status marks to mark the execution status of the pre-reading instruction in real time. The meaning of each status is shown in Table 2: Table 2 prd_stas meaning prd_ctag (pre read command tag) is the pre-read command tag. In this example, the SSD controller maps the read command information corresponding to each read command issued by the host with a command tag, and records the command tag corresponding to the issued pre-read command in the prd_ctag column of the pre-read mapping table in real time.

[0028] The SSD controller can sequentially and cyclically tag the command tags of read commands sent by the host, for example, with tags of 0, 1, 2, ..., 511. The specific number can be adjusted based on actual needs. Initially, the SSD controller assigns command tags to received read commands in the following order: 0, 1, ..., 511. When the data corresponding to a host read command is returned to the host, the command tag corresponding to the host read command is withdrawn and inserted at the end of the command tag queue in a FIFO format. Each time the SSD receives a host read command, it associates it with a command tag received from the peer.

[0029] prd_fofst (pre read command first offset) and prd_lofst (pre read command last offset) are the pre-read command start offset and pre-read command end offset, respectively, indicating the starting and ending offsets of the first pre-read address range. Based on the amount of pre-read data in the first read command, the SSD controller can record the logical block address range corresponding to the issued pre-read command in the prd_fofst and prd_lofst columns of the pre-read mapping table in real time.

[0030] In an exemplary embodiment, after receiving a read instruction, the SSD master controller can use the end offset of the first read address interval of the read instruction + 1 as the starting offset of the first pre-read address interval, and add the pre-read data volume of the first read instruction to the starting offset to obtain the end offset of the first pre-read address interval, wherein the pre-read data volume can be divided into multiple levels, and the specific value of the pre-read data volume of each level can be pre-specified. For example, the pre-read data volume of levels 1 to 4 is 8 / 12 / 16 / 24 respectively, and the specific level can be dynamically selected based on the real-time status information of the SSD.

[0031] The pre-read process controller queries the FTL handle according to the first pre-read address interval to obtain the physical block address of the first pre-read address interval, generates a pre-read command, and sends it to the NAND flash memory controller to read the first pre-read data and store it in the internal cache.

[0032] The FTL handle implements the mapping between logical block addresses and physical block addresses, as well as functions such as garbage collection, wear leveling, read disturb, write disturb, and data retention. The NAND flash controller / NAND physical layer generates a command sequence that complies with the NAND flash data sheet standard based on the host read command information issued by the pre-read process controller.

[0033] Data written to and read from the SSD controller share an internal data buffer. Because NAND flash memory uses a common bus for both reading and writing data, the host writes data to the NAND flash memory and reads data from it simultaneously, impacting bandwidth on both ends. The SSD controller caches data to be written from the host and data read from the NAND flash memory in corresponding locations according to pointers specified by the buffer management.

[0034] The internal cache space is managed by the cache management module. Whenever data needs to be cached in the internal cache, the cache management module finds a pointer for it, and the area corresponding to the pointer becomes the used space. The cache management module breaks read commands into fixed-size data units. For example, if a single unit contains 4KB of data, both host write and read data are cached in 4KB units in the internal cache. If the maximum data transfer size (MDTS) of the SSD controller is 1MB (1MB is composed of 256 4KB units), the logical block address offset of a read command ranges from 0 to 255. For example, if the data size of a pre-read command is 32KB (requiring 8 4KB units in the internal cache to cache the read data), assuming prd_fofst = 6, then prd_lofst = 13.

[0035] Step 103: Receive a second read instruction sent by the host, where a second read address interval in the second read instruction and the first pre-read address interval have an address intersection; In this embodiment, the second read instruction specifically refers to a read instruction having an address intersection between the read address interval and the first pre-read address interval of the pre-read operation started previously.

[0036] In the pre-read mapping table of Table 1, the actual read command starting offset (rrd_fofst) and the actual read command ending offset (rrd_lofst) are determined according to the second read address interval and the first pre-read address interval in the second read instruction, respectively.

[0037] When the SSD controller receives the second read command from the host, it determines the number of logical blocks carried in the command, indicating the amount of data the host requires from the SSD. If the SSD controller's pre-read mapping table already contains the corresponding pre-read information, it needs to enter the rrd_fofst and rrd_lofst values ​​representing the amount of data the host will read. For example, if the amount of data corresponding to a pre-read command is 24KB (requiring six 4KB cache cells in the internal cache to cache the read data), and rrd_fofst = 6, then rrd_lofst = 11.

[0038] Step 104: Respond to the second read instruction according to the intersection of the first pre-read data and the address.

[0039] A pre-read process controller responds to the second read instruction according to the intersection of the first pre-read data and the address, and returns the data requested by the host.

[0040] In the technical solution provided by the embodiment of the present application, after receiving the first read instruction sent by the host, the solid-state drive controller dynamically determines the amount of data to be pre-read by the first read instruction based on the real-time status information of the SSD master, thereby avoiding excessive bandwidth consumption and reducing the host read latency of the SSD. The solution provided by this embodiment can effectively balance the host's read latency and the real-time performance status indicators of the SSD master, thereby reducing the host read latency of the SSD while also reducing the impact of the pre-read operation on the effective bandwidth of the SSD. This avoids the problem in related technologies of pre-reading a large amount of invalid data at the expense of read and write bandwidth in exchange for a smaller host read latency.

[0041] In an exemplary embodiment, responding to the second read instruction according to the intersection of the first pre-read data and the address includes: If the first pre-read address interval completely covers the second read address interval, the data corresponding to the second read address interval included in the first pre-read data is directly read from the internal cache and returned to the host.

[0042] In this embodiment, when the SSD master controller parses that the second read address interval of the second read instruction can be completely covered by the first pre-read address interval, it indicates that the offset area (prd_fofst~prd_lofst) of the first pre-read address interval has covered the second read address interval offset area (rrd_fofst~rrd_lofst) of the second read instruction.

[0043] Taking the pre-read mapping table scenario 1 shown in Table 3 as an example, the first pre-read address interval (prd_fofst to prd_lofst) has an address range of 14 to 22, which completely covers the second read address interval (rrd_fofst to rrd_lofst) of 14 to 20. In this case, the pre-read process controller only needs to wait until the prd_stas status is updated to indicate that the first pre-read data has been read and stored in the internal cache (i.e., state 3 in Table 2). It then notifies the cache management module to directly select the corresponding data cached in the internal cache based on the address range of rrd_fofst to rrd_lofst and return it to the host. After the host completes the read operation of the second read instruction, the pre-read mapping table manager notifies the cache management module to release the data corresponding to rrd_fofst to rrd_lofst.

[0044] Table 3 Pre-read mapping table case 1 In this embodiment, the cache management module is responsible for generating corresponding read command information based on read commands sent by the host. During a host read transaction, the host read command, host read command information, and command tag are in a one-to-one correspondence. The mapping between command tags and read command information is recorded in a command tag mapping table (ctag table) within the pre-read process controller. The host read command information includes important information carried by the read command, such as the queue identifier, command identifier, metadata pointer, data pointer, starting logical block address (LBA), and number of logical blocks. This information can be determined based on the transmission information specified in the standard protocol used for communication between the SSD controller and the host (e.g., PCIE specification, NVME specification, and ONFI specification).

[0045] For example, a host sends a read command to an SSD controller, requesting 1MByte of data. This event is referred to as a host read operation in this article. Assuming the PCIE and NVME specifications limit the amount of data that can be returned to the host at one time to 128 bytes, the SSD controller interprets the read command. Since the total amount of data required for this host read operation is 1MByte, the controller must return 1MByte of data to the host in 8 batches (1MByte / 128Byte = 8). In other words, the SSD controller splits the read command, reads the corresponding data from the NAND flash memory in 8 batches, and returns them to the host.

[0046] Typically, during data transmission between the SSD controller and the host, read commands support out-of-order transmission to improve transmission efficiency. Therefore, sideband signals are required to ensure data consistency between the read command sent by the host and the read data returned by the SSD controller. When the SSD controller sends a data read request to the NAND controller / NAND physical layer based on the host's read command, it also sends the instruction tag corresponding to the read command as a sideband signal. Subsequently, when the NAND controller / NAND physical layer returns the read data to the SSD controller, the instruction tag is returned from the NAND controller / NAND physical layer to the SSD controller as a sideband signal along with the read data. When the data required by the host's read command is cached in the controller's internal cache, the SSD controller first queries the instruction tag mapping table to obtain the host read command information corresponding to the read command. Then, based on the read command information, the read data is accurately placed at the read address (read addr) corresponding to the read command, successfully completing the operation of returning the read data to the host. After the last read data of this host read operation is returned to the host, the instruction tag can be disassociated from the host read instruction information.

[0047] In an exemplary embodiment, assuming the instruction tag assigned to a first read instruction is 100, the first pre-read address interval is determined based on the first read address interval and the amount of pre-read data in the first read instruction. After generating a pre-read instruction based on the first pre-read address interval, the SSD controller, along with the instruction tag 100, is sent to the flash memory controller to read the first pre-read data. After receiving the first pre-read data with the instruction tag 100 from the flash memory controller, the SSD controller stores the data in the internal cache. Subsequently, the SSD controller receives a second read instruction from the host, in which the first pre-read address interval completely overlaps the second read address interval, indicating that the second read instruction hits data in the first pre-read address interval. In this case, the SSD controller does not remove a new instruction tag from the instruction tag queue and associate it with the second read instruction. Instead, the SSD controller reuses the instruction tag 100 from the first read instruction and assigns it to the second read instruction. The SSD controller then queries the instruction tag mapping table to obtain host read instruction information corresponding to the second read instruction. Subsequently, based on the read instruction information, the SSD controller retrieves the data corresponding to the second read address interval included in the first pre-read data and places it at the read address corresponding to the second read instruction, thereby returning the data requested by the second read instruction to the host. This allows the hit pre-read data to be returned to the host as quickly as possible, significantly reducing read latency.

[0048] In an exemplary embodiment, responding to the second read instruction according to the intersection of the first pre-read data and the address includes: If the first pre-read address interval partially covers the second read address interval, determining a second pre-read address interval based on the read address interval of the second read instruction and the address intersection; wherein the second pre-read address interval is the address outside the address intersection in the second read interval; In this embodiment, when the SSD master controller parses the second read instruction, the offset region (prd_fofst to prd_lofst) of the first pre-read address interval partially overlaps the offset region (rrd_fofst to rrd_lofst) of the second read address interval of the second read instruction. For example, as shown in Table 4, during the first pre-read operation, prd_fofst = 14 and prd_lofst = 24 in the first pre-read address interval. When the second read instruction is subsequently received from the host, the second read address interval of the second read instruction is 14-27. At this point, the second pre-read address interval needs to be immediately determined, and the pre-read process controller is notified to initiate a second pre-read operation. The offset region of the second pre-read address interval can be prd_lofst to rrd_lofst, and the instruction information of the second pre-read operation is recorded in the pre-read mapping table.

[0049] In an exemplary embodiment, as shown in Table 5, the amount of pre-read data for the second read instruction can be determined based on the current status information of the solid-state drive. If the current resources of the solid-state drive are relatively abundant, the amount of data in the second pre-read address interval can be appropriately amplified for pre-reading. For example, the second read address interval is 14-27. After determining the amount of pre-read data for the second read instruction based on the current status information of the solid-state drive, the second pre-read address interval is calculated to be 25-30, thereby pre-reading the data in the address interval 14-30 twice. In this way, when the second read address interval hits the first pre-read address interval, it is predicted that the host will still perform a sequential read operation next. The amount of pre-read data can be appropriately increased, and the number of times the pre-read operation is initiated can be reduced, thereby reducing the host read latency of the SSD and reducing the impact of frequently initiating pre-read operations on SSD system resources.

[0050] Table 4 First pre-read instruction information Table 5 Second pre-read instruction information generating a pre-read instruction according to the second pre-read address interval, and sending the instruction to the flash memory controller to read the second pre-read data and store the data in the internal cache; The data corresponding to the address intersection included in the first pre-read data and the second pre-read data are read from the internal cache and returned to the host.

[0051] In this embodiment, the pre-read process controller only needs to wait until the first and second pre-read instruction information prd_stas becomes 3 before returning the data corresponding to the address intersection of the first pre-read data and the second pre-read data cached in the internal cache to the host. After the read operation is completed, the pre-read mapping table manager can notify the cache management module to release the data corresponding to rrd_fofst to rrd_lofst in the first and second pre-read instruction information.

[0052] In an exemplary embodiment, determining the pre-read data amount of the first read instruction according to the status information of the solid-state drive includes: According to the status information of the solid state drive, a preset weight arbitration strategy is used to determine a first weight; if the first weight is greater than a preset weight threshold, the pre-read data amount of the first read instruction is determined according to the first weight.

[0053] In an exemplary embodiment, the preset weight arbitration strategy includes: Calculating corresponding weight values ​​according to each piece of status information in the status information of the solid state drive; Add up all the calculated weight values ​​to get the weight calculation result; The state information of the solid state drive includes one or more of the following: available space in the internal cache, the number of read instructions sent by the host, and bandwidth utilization of the flash memory controller.

[0054] In this embodiment, the available space of the internal cache can be monitored in real time by an internal cache status monitor (data buffer status monitor), and the execution status of read / write instructions and bandwidth utilization of the NAND flash memory controller module can be monitored in real time by a bandwidth status monitor (bandwidth status monitor).

[0055] The weight arbiter determines a first weight based on information such as the SSD's real-time internal cache available space, the number of read commands issued by the host, and the bandwidth utilization of the NAND flash controller. It then determines whether to initiate a pre-read operation based on whether the first weight exceeds a preset weight threshold. For example, if the internal cache available space is greater than one-third (weight 0.4), the host has issued three consecutive read commands (weight 0.4), and the bandwidth utilization of the NAND flash controller reaches 90% (weight 0.2), then a pre-read operation can be initiated if the sum of these three factors is at least 0.6. Otherwise, initiating a pre-read operation is likely to result in an invalid read operation, which is not worth the effort.

[0056] After the pre-read operation is initiated, the amount of data pre-read each time can be dynamically adjusted based on the first weight. For example, if the weighted arbitrator output is 0.9, the pre-read data amount is set to 16; if the weighted arbitrator output is 0.8, the pre-read data amount is set to 12; if the weighted arbitrator output is 0.7, the pre-read data amount is set to 8; if the weighted arbitrator output is 0.6, the pre-read data amount is set to 4, and so on.

[0057] In an exemplary embodiment, after returning the data to the host, the method further includes: A second weight is determined using a preset weight arbitration strategy according to the state information of the solid-state drive; if the second weight is greater than a preset weight threshold, a pre-read is initiated for the second read instruction.

[0058] In this embodiment, after the data corresponding to the second read address interval is returned to the host, if it can be determined that the conditions for starting the pre-read operation are met based on the real-time status information of the solid-state drive, the pre-read operation can be started again for the second read instruction, and the pre-read instruction information can be recorded accordingly in the pre-read mapping table.

[0059] In an exemplary embodiment, if no read instruction with a read address interval having an address intersection with the first pre-read address interval sent by the host is received within a preset time period, the execution status of the pre-read instruction is marked as invalid, and the first pre-read data is released from the internal cache.

[0060] In an exemplary embodiment, after generating a pre-read instruction according to the first pre-read address range and sending the instruction to the flash memory controller to read the first pre-read data, and before storing the data in the internal cache, the method further includes: monitoring the execution status of the pre-read instruction; If the execution status of the pre-read instruction is marked as invalid before the first pre-read data is read, the execution of the pre-read instruction is terminated immediately.

[0061] In this embodiment, if the read address interval of a read instruction received by the SSD master controller does not match the data range of the first pre-read address interval within a preset time period, it indicates that the corresponding first pre-read data in the internal cache is invalid, and the space occupied by it can be released. At this time, the SSD master controller detects that the host's read instruction is no longer a sequential read. The pre-read mapping table manager needs to notify the cache management module to release the data corresponding to the address range prd_fofst to prd_lofst in the first pre-read address interval. At the same time, it sets the prd_stas status in the pre-read instruction record to the invalid state 4, thereby immediately notifying the NAND flash memory controller / NAND physical layer, FTL handle, and other modules to stop the pre-read operation. For example, as shown in Table 6, before receiving the second read instruction, the address range prd_fofst~prd_lofst of the pre-read instruction in the pre-read mapping table is 14~24. Within the preset time length, the SSD master control does not receive a read instruction from the host whose read address interval has an address intersection with the first pre-read address interval. At this time, the pre-read instruction information is modified to the pre-read instruction information marked as invalid in Table 7. At the same time, the instruction label can also be withdrawn, and other modules need to be notified immediately to terminate the execution of the pre-read instruction.

[0062] Table 6 Pre-read instruction information before receiving the second read instruction Table 7 Pre-read instruction information marked as invalid In an exemplary embodiment, when the execution status of the pre-read instruction is marked as invalid, the method further includes: The first read instruction corresponding to the pre-read instruction is promoted to the highest priority to immediately terminate the execution of the pre-read instruction.

[0063] In this embodiment, when the pre-read mapping table manager module finds that the data of the pre-read instruction in the pre-read mapping table is not the data that the host wants to read, it needs to upgrade the first read instruction to the highest priority as soon as possible and transmit it to the pre-read process controller and other modules to immediately terminate the execution of the pre-read instruction. This can minimize the delay of the host read instruction to the greatest extent and avoid the invalid pre-read operation affecting the effective bandwidth of the SSD master.

[0064] Yet another embodiment of the present application provides a solid-state hard disk, including a solid-state hard disk controller, wherein the solid-state hard disk controller is configured to execute the pre-reading method of the solid-state hard disk provided in the above embodiment.

[0065] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the methods, systems, and devices disclosed above may be implemented as software, firmware, hardware, or any combination thereof. In hardware implementations, the division between functional modules / units described above does not necessarily correspond to the division between physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is well known to those skilled in the art, the term "computer storage media" encompasses volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A pre-reading method for a solid state drive, applied to a solid state drive controller, characterized in that: include: Receive the first read command sent by the host; determining, according to the state information of the solid-state drive, an amount of pre-read data for the first read instruction; determining a first pre-read address interval based on the first read address interval and the amount of pre-read data in the first read instruction, generating a pre-read instruction based on the first pre-read address interval, and sending the pre-read instruction to the flash memory controller to read the first pre-read data and store it in an internal cache; receiving a second read instruction sent by a host, wherein a second read address interval in the second read instruction and the first pre-read address interval have an address intersection; The second read instruction is responded to according to the intersection of the first pre-read data and the address.

2. The pre-reading method of a solid state drive according to claim 1, wherein: The responding to the second read instruction according to the intersection of the first pre-read data and the address includes: If the first pre-read address interval completely covers the second read address interval, the data corresponding to the second read address interval included in the first pre-read data is directly read from the internal cache and returned to the host.

3. The pre-reading method of a solid state drive according to claim 1, wherein: The responding to the second read instruction according to the intersection of the first pre-read data and the address includes: If the first pre-read address interval partially covers the second read address interval, determining a second pre-read address interval based on the read address interval of the second read instruction and the address intersection; wherein the second pre-read address interval is the address outside the address intersection in the second read interval; generating a pre-read instruction according to the second pre-read address interval, and sending the instruction to the flash memory controller to read the second pre-read data and store the data in the internal cache; The data corresponding to the address intersection included in the first pre-read data and the second pre-read data are read from the internal cache and returned to the host.

4. The pre-reading method of a solid state drive according to claim 1, wherein: The determining, according to the status information of the solid-state drive, the amount of pre-read data of the first read instruction includes: According to the status information of the solid state drive, a preset weight arbitration strategy is used to determine a first weight; if the first weight is greater than a preset weight threshold, the pre-read data amount of the first read instruction is determined according to the first weight.

5. The pre-reading method of a solid state drive according to claim 2, wherein: After returning the information to the host, the method further includes: A second weight is determined using a preset weight arbitration strategy according to the state information of the solid-state drive; if the second weight is greater than a preset weight threshold, a pre-read is initiated for the second read instruction.

6. The pre-reading method for a solid state drive according to claim 4 or 5, characterized in that: The preset weight arbitration strategy includes: Calculating corresponding weight values ​​according to each piece of status information in the status information of the solid state drive; Add up all the calculated weight values ​​to get the weight calculation result; The state information of the solid state drive includes one or more of the following: available space in the internal cache, the number of read instructions sent by the host, and bandwidth utilization of the flash memory controller.

7. The pre-reading method for a solid state drive according to any one of claims 1 to 5, wherein: If no read instruction having an address intersection between a read address interval and the first pre-read address interval sent by the host is received within a preset time period, the execution status of the pre-read instruction is marked as invalid, and the first pre-read data is released from the internal cache.

8. The pre-reading method of a solid state drive according to claim 7, wherein: After generating a pre-read instruction according to the first pre-read address interval and sending the instruction to the flash memory controller to read the first pre-read data, and before storing the data in the internal cache, the method further includes: monitoring the execution status of the pre-read instruction; If the execution status of the pre-read instruction is marked as invalid before the first pre-read data is read, the execution of the pre-read instruction is terminated immediately.

9. The pre-reading method of a solid state drive according to claim 8, wherein: When the execution status of the pre-read instruction is marked as invalid, the method further includes: The first read instruction corresponding to the pre-read instruction is promoted to the highest priority to immediately terminate the execution of the pre-read instruction.

10. A solid state drive, comprising a solid state drive controller, characterized in that: The solid-state hard disk controller is used to execute the solid-state hard disk pre-reading method according to any one of claims 1 to 9.

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