Verification device based on standard PIPE interface

Abstract

The embodiment of the invention discloses a verification device based on a standard PIPE interface, and the device comprises a PIPE switching circuit device which is used for being connected with a PCIe PIPE interface in actual work and a PIPE interface to be tested and designed; the to-be-tested design comprises a PCIe (Peripheral Component Interconnect Express) controller; the controller provides a sideband control signal to the PIPE switching circuit device; the global configuration module is used for configuring the current working mode of the PIPE switching circuit device; based on the current working mode and the sideband control signal, the PIPE switching circuit device can be connected with any physical layer unit. According to the method, the problems of long iteration period, tedious project file version management and the like caused by low PCIe related software verification environment reusability and low PCIe interface verification flexibility in the existing workflow can be solved. Moreover, the universality of the to-be-tested design in different verification environments is effectively improved, the project period is shortened, and the project verification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a verification device based on a standard PIPE interface. Background Art

[0002] The relevant terms are explained as follows:

[0003] PCIe, peripheral component interconnect express, high-speed serial computer expansion bus

[0004] PHY, Physical, physical layer

[0005] PIPE, Physical Interface for PCI Express, PCIe physical layer interface

[0006] PLD, Palladium, Paladin simulation platform

[0007] VIP, Verification IP, Verification of Intellectual Property

[0008] RTL, Register-transfer level, register transfer level

[0009] FPGA, Field Programmable Gate Array

[0010] For designs under test (DUTs) with PCIe PHYs, the traditional verification process involves multiple verification scenarios, such as software simulation, hardware simulation, and programmable gate array (FPGA) simulation, to meet different verification requirements. Software simulation typically uses verification models provided by the PCIe PHY vendor. The other two methods require partial implementation modifications to the DUT to ensure compatibility with PCIe physical connections and their verification requirements.

[0011] The following is a brief description of the work of these verifications in the project process:

[0012] After the front-end designers complete the initial version of the code for the design to be tested, they will verify the PCIe-related basic functions of the design to be tested in a software simulation environment with PCIeVIP.

[0013] After verifying that the basic functionalities of the design under test meet expectations in the software simulation environment, hardware accelerated simulation verification can begin. Because the maximum frequency of projects executed in such hardware accelerated simulation devices is only a few MHz, there is still a significant difference between the hardware speed and the physical PCIe device they are connected to. To address this issue, hardware emulator vendors (such as Cadence) provide a corresponding adapter, the SpeedbridgeAdapter, based on their Palladium platform. Front-end designers need to use the Speedbridge adapter model provided by the emulator vendor as a basis, using the PCIe PIPE interface as a partition, and modify the PCIe-related RTL in the design under test to make it compatible with the hardware emulator's engineering runtime environment. Based on this engineering implementation, software developers will be involved in performing hardware emulator verification, requiring the development of drivers and firmware.

[0014] After verifying that the basic functionalities of the design under test meet expectations on the software verification platform, programmable gate array (PGE) simulation verification can also be performed. This verification method has the advantage of being closer to actual circuit behavior and wider applicability than hardware simulation. However, due to hardware limitations, large-scale chips require tailoring, and compilation is time-consuming, making debugging and troubleshooting difficult. Because the PCIe PHY module or controller module actually used in the PGE platform differs from the module design in the ASIC version, designers need to modify some PCIe-related RTL designs in the design under test.

[0015] Although the current working method can solve engineering problems, it has the following disadvantages:

[0016] 1. Designers’ work is repeated

[0017] Current solutions require designers to create different RTL adaptation designs for each project's different verification environments and DUTs. However, the PCIe PHY connection relationships are specified by the PIPE protocol, and reference designs can be created based on standard interfaces and existing verification environments or platforms for multiple reuse.

[0018] 2. Insufficient flexibility leads to poor debugging and iteration timeliness

[0019] It is difficult to reuse the existing verification environment. FPGA or PLD verification is usually carried out after the software simulation verification reaches a certain stage. If the FPGA or PLD compatibility project and the software simulation environment are independent, it will result in the compatibility project based on the design to be tested being unable to directly reuse the existing verification environment for simple debugging work after the designer completes it. All verification must be carried out on the FPGA or PLD platform, resulting in a waste of project resources and time.

[0020] 3. Inconvenient for project file version management

[0021] Although the DUT and verification projects are independent, each verification environment actually calls a different RTL project containing the same DUT. This can easily introduce uncertainties due to differences in project RTL. This process can also cause inconvenience in project file version management. Summary of the Invention

[0022] The purpose of the embodiment of the present invention is to provide a verification device based on the standard PIPE interface to solve the problems of low reuse of PCIe-related software verification environment in the existing workflow, low flexibility in PCIe interface verification resulting in long iteration cycle, and complicated project file version management.

[0023] To achieve the above objectives, in a first aspect, an embodiment of the present invention provides a verification device based on a standard PIPE interface, comprising:

[0024] A PIPE switching circuit device is configured to connect to an actual working PCIe PIPE interface and a PIPE interface of a design to be tested; the design to be tested includes a PCIe controller, which is connected to the PIPE switching circuit device via the PIPE interface and provides sideband control signals to the PIPE switching circuit device;

[0025] A global configuration module, configured to configure the current working mode of the PIPE switching circuit device;

[0026] Based on the current working mode and the sideband control signal, the PIPE switching circuit device can be connected to any physical layer unit.

[0027] The physical layer unit includes but is not limited to a speed bridge encapsulation unit, a CXL speed bridge encapsulation unit, a field-programmable gate array encapsulation unit, a dedicated integrated circuit physical layer encapsulation unit, and an inter-chip interconnection encapsulation unit.

[0028] Furthermore, the speed bridge encapsulation unit or CXL speed bridge encapsulation unit is used to verify the EP function or RC function in a hardware accelerated simulation environment; the inter-chip interconnection encapsulation unit is used to verify the RC docking EP function in hardware accelerated simulation; and the field editable gate array encapsulation unit is used for FPGA simulation.

[0029] Furthermore, different physical layer units are connected to different external devices to construct multiple pathways for PLD simulation, FPGA simulation, and software simulation, specifically including:

[0030] A first path is formed by connecting the speed bridge encapsulation unit to the PIPE switching circuit device and the X86 service host respectively; the first path is used for PLD simulation;

[0031] A second path is formed by connecting the CXL speed bridge encapsulation unit to the PIPE switching circuit device and the PCIe endpoint device respectively; the second path is used for PLD simulation;

[0032] A third path is formed by connecting the field editable gate array package unit to the PIPE switching circuit device, the X86 service host, and the PCIe endpoint device respectively; the third path is used for FPGA simulation;

[0033] a fourth path formed by the field-editable gate array package unit connecting the PIPE switching circuit device and the PCIe VIP RC and PCIe VIP EP respectively; the fourth path is used for software simulation;

[0034] A fifth path is formed by connecting the inter-chip interconnect encapsulation unit to the PIPE switching circuit device, the PCIe RC device, and the PCIe EP device respectively; the fifth path is used for PLD simulation.

[0035] In a second aspect, an embodiment of the present invention further provides another verification device based on a standard PIPE interface, comprising:

[0036] At least one basic module, the basic module including a PIPE switching circuit device and a basic PIPE_WRAPPER; the basic PIPE_WRAPPER is used to provide multiple interface units;

[0037] The global configuration module is used to configure the current working mode of the PIPE switching circuit device and realize the coordination between multiple basic modules, thereby building multiple verification environments.

[0038] As a specific implementation of the present application, the interface unit provided by the basic PIPE_WRAPPER includes:

[0039] Used to connect the PIPE interface of the design to be tested;

[0040] Speed ​​bridge package unit or CXL speed bridge package unit used to verify EP function or RC function in hardware accelerated simulation environment;

[0041] Inter-chip interconnect packaging unit used to verify the RC docking EP function in hardware accelerated simulation;

[0042] FPGA_PHY unit for FPGA simulation;

[0043] ASIC_PHY unit for software emulation.

[0044] Furthermore, the operating modes of the PIPE switching circuit device include:

[0045] The first one is used for the SPEEDBRIDGE path used in the PLD simulation environment to connect to the X86 HOST;

[0046] The second type is the CXL_SPEEDBRIDGE path used to connect to the EP DEVICE in the PLD simulation environment;

[0047] The third type is used to connect to the X86 HOST path and the EP DEVICE path in the FPGA simulation environment;

[0048] The fourth type is used to connect to the PCIe VIP RC path and PCIe VIP EP path in the software simulation environment;

[0049] The fifth type is used to connect to the peer PCIe RC device and the peer PCIe EP device in the PLD simulation environment.

[0050] The implementation of this invention provides a verification device based on a standard PIPE interface. This device addresses existing workflow issues such as low reuse of PCIe-related software verification environments, limited flexibility in PCIe interface verification leading to long iteration cycles, and complex project file version management. Furthermore, this invention effectively leverages the characteristics of various verification environments to improve the versatility of the design under test across different verification environments, shortening project cycles and increasing project verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the specific implementation of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the specific implementation or the description of the prior art.

[0052] Figure 1 This is a structural diagram of a verification device based on a standard PIPE interface provided by an embodiment of the present invention;

[0053] Figure 2 In the PLD hardware simulation environment, the PCIe controller in the design under test is connected to the peer X86_HOST as a PCIE EP DEVICE through the configured PIPE_WRAPPER;

[0054] Figure 3 In the PLD hardware simulation environment, the PCIe controller in the design under test is connected to the peer PCIe EP DEVICE as a PCIe RC DEVICE through the configured PIPE_WRAPPER;

[0055] Figure 4 In the PLD hardware simulation environment, the PCIe controller in the design under test 0 is connected as a PCIE RC DEVICE to the PCIe controller in the design under test 1 as a PCIE EP DEVICE via the configured PIPE_WRAPPER;

[0056] Figure 5 is Figures 2 to 4 Based on the connection mode, a CHIP 2CHIP verification environment based on PCIe connection is built;

[0057] Figure 6 and Figure 7 This is a structural diagram of the original verification device after transformation. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0059] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0060] Please refer to Figure 1 , is a verification device based on a standard PIPE interface provided by the first embodiment of the present invention, comprising:

[0061] The PIPE switching circuit device is used to connect with the actual working PCIe PIPE interface and the PIPE interface of the design to be tested, and needs to adapt different sideband signal processing logics for the physical layer (PHY) unit currently selected for integration. Figure 1As shown, the physical layer unit includes but is not limited to the speed bridge packaging unit, CXL speed bridge packaging unit, field-editable gate array packaging unit, dedicated integrated circuit physical layer packaging unit and inter-chip interconnect packaging unit. The dedicated integrated circuit physical layer packaging unit is mainly used for software simulation and actual chip tape-out. Its physical layer IP supplier needs to ensure that the corresponding physical layer IP module behaves equivalently in both scenarios. In actual usage scenarios, this unit is connected to the PCIeVIP during the software verification phase, and the external interface of this module in the actual product, i.e. the finished chip, is the PCIe edge connector. It should be noted that the PIPE switching circuit device contains clock generation and frequency division logic, which is used and only used in the inter-chip interconnect packaging unit usage scenario. For other scenarios, the usage environment can provide the clock.

[0062] The global configuration module is used to configure the current working mode of the PIPE switching circuit device.

[0063] Figure 1 In the diagram, DUT_0 (design under test) contains a PCIe Controller (PCIe dual-role controller) connected to the PIPE_WRAPPER module via the PIPE interface. The PCIe Controller can be connected to any PHY unit by configuring the operating mode of the switch circuit device (PIPE_SWITCH) through the global configuration (GLOBAL_CFG) module. The diagram shows several available options:

[0064] 1. Speed ​​bridge (SPEEDBRIDGE) path used for connecting to X86 HOST in PLD simulation environment

[0065] 2. CXL speed bridge (CXL_SPEEDBRIDGE) path used for connecting PCIe endpoint devices in PLD simulation environment

[0066] 3. Used to connect to the X86 service host (X86 HOST) channel in the FPGA simulation environment

[0067] 4. Used to connect PCIe endpoint device channels in FPGA simulation environment

[0068] 5. Used to connect PCIe VIP RC channel in software simulation environment

[0069] 6. Used to connect PCIe VIP EP channel in software simulation environment

[0070] 7. Used to connect to the peer PCIe RC device in PLD simulation environment

[0071] 8. Used to connect to the peer PCIe EP device in PLD simulation environment

[0072] When in use, the configuration of the GLOBAL_CFG module can be used to switch the current module working state, thereby switching the internal PHY module connection relationship and its corresponding adaptation logic of the current design under test.

[0073] It should be noted that Figure 1 The design under test shown may include the following types of PCIe controllers: a PCIe dual-role controller, a PCIe endpoint device controller, and a PCIe root complex controller. The difference between these three types of controllers lies in their different working roles. The PCIe dual-role controller can switch between two working states through static configuration to meet the requirements of the application scenario.

[0074] In addition, the above-mentioned design under test not only includes the above-mentioned type of PCIe controller, but also includes at least one control unit, usually a central processing unit, which can be used to configure the global configuration and control the basic work of the PCIe controller.

[0075] Furthermore, the main usage process of the design under test has the following steps:

[0076] (1) Project compilation: It is recommended to use macro definitions to distinguish the current scenario in advance during compilation. In fact, it is recommended to use macro definitions to distinguish the current scenario. The global configuration unit contains registers whose values ​​can be affected by macro definitions. The software can directly judge the current working scenario based on the current register values ​​to facilitate related configuration.

[0077] In fact, if sufficient resources are available, the entire PIPE encapsulation layer can be compiled directly without using macro definitions to distinguish between scenarios. In this case, scenarios involving logic synthesis (such as PLD and FPGA verification) can automatically optimize unused logic during the tool synthesis phase. In scenarios not involving logic synthesis, redundant logic does not affect the selected path. However, this approach adds an additional step for confirming scenarios in the software and verification driver, preventing automated configuration and is not optimal for current designs.

[0078] In other words, the actual working scenario of the current project has been determined when the project is compiled.

[0079] (2) Release the reset after the system is powered on normally: This process is a major stage in the on-chip system verification. After the design under test is released from reset, it will start to enter the working state. At this time, the PCIe link is not connected.

[0080] (3) Execute the configuration process of the global configuration module: At this time, if the design to be tested uses macro definitions to distinguish the current scenario in advance during the engineering compilation stage, the global configuration module will automatically execute the relevant configuration process according to the current scenario. After the configuration is completed at this stage, a software-readable register identifier will be provided for software polling or interruption for use; if the design to be tested does not use macro definitions to distinguish during the engineering compilation stage, the verification personnel will need to actively configure the internal registers of the global configuration module through register configuration to tell the internal circuit how to start working, and manually configure to start the configuration process. Similarly, after the configuration is completed, a software-readable register identifier will be provided for software polling or reporting interruption for use.

[0081] (4) When the corresponding interrupt report is queried or the register identifier is polled, the controller-related configuration can be started. If the design to be tested includes a master device similar to a central processing unit, it is necessary to control it to execute the configuration process of the PCIe controller; if there is no similar master device (such as a software verification environment in which VIP participates), the verification personnel need to add the corresponding register configuration process in the test.

[0082] After this configuration is executed, the PCIe link training state machine will be enabled and the PCIe link establishment will begin.

[0083] If the currently used PCIe controller contains some signals closely related to the currently working PIPE in addition to some standard PIPE interface signals, they will be regarded as sideband control signals and connected to the PIPE switching circuit device for processing. This path does not need to be actively configured.

[0084] The link training state machine of the PCIe controller is stable in the L0 state. At this time, verification services can be performed normally. It should be noted that the global configuration module related configuration cannot be performed at this stage. The module configuration requires a quasi-static configuration.

[0085] The verification device based on the standard PIPE interface provided by the embodiment of the present invention is suitable for deploying a PCIe-connected verification environment in a large-scale PCIe connection system. The connection mode of a single controller is first described below.

[0086] Figure 2 In the PLD hardware simulation environment, the PCIe controller in the design under test is connected to the peer X86_HOST as a PCIE EP DEVICE through the configured PIPE_WRAPPER.

[0087] It should be noted that the PIPE_WRAPPER includes the following interface units:

[0088] Used to connect the PIPE interface of the design to be tested, the SPEEDBRIDGE unit or CXL_SPEDBRIDGE unit used to verify the EP function or RC function in the hardware acceleration simulation environment, the C2C_PIPE_WRAPPER unit used to verify the RC docking EP function in hardware acceleration simulation, the FPGA_PHY unit for FPGA simulation and the ASIC_PHY unit for software simulation.

[0089] Figure 3 In the PLD hardware simulation environment, the PCIe controller in the design under test is connected to the peer PCIe EP DEVICE as a PCIe RC DEVICE through a configured PIPE_WRAPPER.

[0090] Figure 4 In the PLD hardware simulation environment, the PCIe controller in the design under test 0 is connected as a PCIE RC DEVICE to the PCIe controller in the design under test 1 as a PCIE EP DEVICE via the configured PIPE_WRAPPER.

[0091] exist Figures 2 to 4 Based on the three connection modes, a large-scale CHIP 2CHIP verification environment based on PCIe connection can be easily built, such as Figure 5 As shown in the figure, each design under test contains five PCIe controllers, configured in EP and RC modes. The scenario set up in the PLD verification environment includes a total of eight DUTs. Each DUT includes an EP device that needs to be connected to the X86 host, and the remaining PCIe devices are connected in a C2C manner. Based on this implementation, the repetitive work of traditional re-engineering is eliminated. The code in the software verification environment can be directly transferred to the PLD platform after configuration, effectively utilizing the flexibility and compatibility of the present invention.

[0092] Based on the same inventive concept, an embodiment of the present invention further provides another verification device based on a standard PIPE interface, comprising:

[0093] At least one basic module, the basic module including a PIPE switching circuit device and a basic PIPE_WRAPPER; the basic PIPE_WRAPPER is used to provide multiple interface units;

[0094] The global configuration module is used to configure the current working mode of the PIPE switching circuit device and realize the coordination between multiple basic modules, thereby building multiple verification environments.

[0095] Among them, the interface units provided by the basic PIPE_WRAPPER include:

[0096] Used to connect the PIPE interface of the design to be tested;

[0097] Speed ​​bridge package unit or CXL speed bridge package unit used to verify EP function or RC function in hardware accelerated simulation environment;

[0098] Inter-chip interconnect packaging unit used to verify the RC docking EP function in hardware accelerated simulation;

[0099] FPGA_PHY unit for FPGA simulation;

[0100] ASIC_PHY unit for software emulation.

[0101] In specific implementation, in addition to the number of PIPE interfaces used to connect to the design under test, the number of other units can also be freely customized to adapt to the design of the current project. The above embodiment provides the usage method when the number of PIPE_DUT is 1. The following are several different implementation methods:

[0102] Based on the original device, an additional DUT port is added at the PIPE_WRAPPER level to connect to another PCIe controller. An additional PHY_OUT_1 port is added to this DUT port to perform software simulation and ASIC version RTL implementation. The original PHY_OUT port is changed to PHY_OUT_0.

[0103] In this form, the advantage of the device is that it can verify the three basic verification requirements of the PCIe controller in the same project, namely the functional characteristics of the PCIe controller when it is used as an EP, the functional characteristics of the PCIe controller when it is used as an RC, and the functional characteristics of the PCIe interconnection. Figure 6 As shown, this scenario can be directly implemented using one PIPE_WRAPPER per DUT.

[0104] Furthermore, the compatibility with the FPGA environment can be enhanced specifically based on the original device. Figure 7 As shown, this implementation supports access from X86_HOST to DUT and EP_DEVICE when FPGA resources are sufficient, and adds CTL_SWITCH to the FPGA environment to switch the specified PCIe controller module in the FPGA environment, thereby improving the flexibility of the corresponding DUT in the FPGA verification environment.

[0105] From the above description, it can be seen that the verification device based on the standard PIPE interface provided by the embodiment of the present invention implements a circuit switching device based on the standard PIPE interface. When used, it integrates multiple PCIe PHYs that may participate in the chip verification process. Replacement units and support flexible configuration selection units and their corresponding sideband signal processing logic can be flexibly combined with large-scale designs to be tested that have been verified to be connected with PCIe, and can support static switching configuration to support software verification environment reuse.

[0106] Compared with the existing technology, the verification device of the present invention can significantly improve the verification efficiency of the design to be tested that includes dual-mode PCIe. Regardless of whether the design to be tested includes a single PCIe controller or multiple controllers, the device of the present invention can enhance its compatibility under software simulation verification, FPGA verification and PLD verification platforms through simple configuration adaptation to achieve the effects of improving efficiency, reusing resources, accelerating project progress and reducing duplication of work.

[0107] In addition, it should be noted that the main role of the present invention is played in the research and development stage and design iteration stage of chip design. At the beginning of the design, the working scenario involving PCIe is determined, and the basic PIPE_WRAPPER is implemented based on PIPE_SWITCH and other required interface units (ASIC_PHY, FPGA PHY, SEPEEDBRIDGE and other PHY units), which are then connected to the PCIe Controller PIPE interface in the design to be tested via a standard PIPE interface.

[0108] In actual verification and debugging, you only need to statically configure the CGLOBAL_CFG module according to the current scenario to modify the working mode of PIPE_SWITCH. PIPE_SWITCH will automatically bind the PIPE interface and other related sideband control signals to the corresponding wrapper resources for related verification processes.

[0109] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A verification device based on a standard PIPE interface, characterized in that: include: A PIPE switching circuit device is used to connect with the actual working PCIe PIPE interface and the PIPE interface of the design to be tested; The design under test includes a PCIe controller, which is connected to the PIPE switching circuit device through a PIPE interface and provides a sideband control signal to the PIPE switching circuit device; A global configuration module, configured to configure the current working mode of the PIPE switching circuit device; Based on the current working mode and the sideband control signal, the PIPE switching circuit device can be connected to any physical layer unit.

2. The verification device according to claim 1, wherein: The physical layer unit includes a speed bridge encapsulation unit, a CXL speed bridge encapsulation unit, a field editable gate array encapsulation unit, a dedicated integrated circuit physical layer encapsulation unit and an inter-chip interconnection encapsulation unit.

3. The verification device according to claim 1, wherein: The speed bridge encapsulation unit or CXL speed bridge encapsulation unit is used to verify the EP function or RC function in a hardware accelerated simulation environment; the inter-chip interconnection encapsulation unit is used to verify the RC docking EP function in hardware accelerated simulation; the field editable gate array encapsulation unit is used for FPGA simulation.

4. The verification device according to claim 2, wherein: Different physical layer units are connected to different external devices to construct multiple paths for PLD simulation, FPGA simulation and software simulation.

5. The verification device according to claim 4, wherein: The various pathways include: A first path is formed by connecting the speed bridge encapsulation unit to the PIPE switching circuit device and the X86 service host respectively; the first path is used for PLD simulation; A second path is formed by connecting the CXL speed bridge encapsulation unit to the PIPE switching circuit device and the PCIe endpoint device respectively; the second path is used for PLD simulation; A third path is formed by connecting the field editable gate array package unit to the PIPE switching circuit device, the X86 service host, and the PCIe endpoint device respectively; the third path is used for FPGA simulation; A fourth path is formed by the field-editable gate array package unit connecting the PIPE switching circuit device and the PCIeVIP RC and PCIe VIP EP respectively; the fourth path is used for software simulation; A fifth path is formed by connecting the inter-chip interconnect encapsulation unit to the PIPE switching circuit device, the PCIe RC device, and the PCIe EP device respectively; the fifth path is used for PLD simulation.

6. A verification device based on a standard PIPE interface, characterized in that: include: At least one basic module, the basic module including a PIPE switching circuit device and a basic PIPE_WRAPPER; the basic PIPE_WRAPPER is used to provide multiple interface units; The global configuration module is used to configure the current working mode of the PIPE switching circuit device and realize the coordination between multiple basic modules, thereby building a variety of verification environments.

7. The verification device according to claim 1, wherein: The interface units provided by the basic PIPE_WRAPPER include: Used to connect the PIPE interface of the design to be tested; Speed ​​bridge package unit or CXL speed bridge package unit used to verify EP function or RC function in hardware accelerated simulation environment; Inter-chip interconnect packaging unit used to verify the RC docking EP function in hardware accelerated simulation; FPGA_PHY unit for FPGA simulation; ASIC_PHY unit for software emulation.

8. The verification device according to claim 7, wherein: The design to be tested includes a PCIe controller, which is connected to the PIPE switching circuit device through a PIPE interface and provides a sideband control signal to the PIPE switching circuit device.

9. The verification device according to claim 1, wherein: The working modes of the PIPE switching circuit device include: The first one is used for the SPEEDBRIDGE path used in the PLD simulation environment to connect to the X86 HOST. The second type is the CXL_SPEEDBRIDGE path used to connect to the EP DEVICE in the PLD simulation environment; The third type is used to connect to the X86 HOST path and the EP DEVICE path in the FPGA simulation environment; The fourth type is used to connect to the PCIe VIP RC path and PCIe VIP EP path in the software simulation environment; The fifth type is used to connect to the peer PCIe RC device and the peer PCIe EP device in the PLD simulation environment.

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