Conflict processing method and device

Abstract

The invention relates to the technical field of servers, and discloses a conflict processing method and device. The method comprises the following steps: acquiring a state value of a first register from a bus state management chip under the condition that a first computing node determines that an access request needs to be sent to a bus arbitration chip; when the access request is a super control right access request and the state value of the first register is a second state value, a control request is sent to a bus state management chip, and the control request is used for requesting to use a bus super control right; and after the state value of the first register is updated to the first state value from the second state value and the state value of a second register corresponding to the first computing node is updated to the first state value, sending the access request to a bus arbitration chip. Therefore, effective management of the bus control authority is realized, and access conflicts are avoided.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a conflict handling method and device. Background Art

[0002] A multi-node server is an important server in the server field. It includes multiple computing nodes. Each computing node has a baseboard management controller (BMC). The BMC management module on each computing node has the need to access components in the server, such as reading and writing register information of components such as the power supply unit (PSU), network card, hard disk, and fan, or upgrading the firmware of these components.

[0003] Since each computing node has equal access requirements to components, the bus arbitration chip can be used to perform bus arbitration on the access requirements of multiple nodes to determine the access priority. Figure 1 As shown, the multi-node server includes multiple compute nodes, a bus arbitration chip, and multiple components. Each compute node is equipped with a BMC management module. Because the bus arbitration chip cannot handle the compute node's need for long-term exclusive bus use, if compute node 1 needs to upgrade the firmware in a component, and other compute nodes also need to upgrade their firmware during the upgrade, the bus arbitration chip will lose access control to the other nodes, resulting in component upgrade anomalies. At the very least, this can cause component malfunction or, in severe cases, lead to a system crash.

[0004] Therefore, a conflict handling method is urgently needed to solve the access conflict problem that occurs when multiple computing nodes try to access components in a server at the same time. Summary of the Invention

[0005] The embodiments of the present application provide a conflict handling method and apparatus to resolve the access conflict problem that occurs when multiple computing nodes request bus super control rights.

[0006] In a first aspect, an embodiment of the present application provides a conflict handling method, which is applied to a first computing node among multiple computing nodes included in a server, wherein the server also includes a bus status management chip, and the bus status management chip also includes a first register and multiple second registers, and the multiple second registers correspond one-to-one to the multiple computing nodes. The method includes: determining that an access request needs to be sent to the bus arbitration chip of the server; when the access request is an access request for bus super control rights, sending a control request to the bus status management chip, wherein the control request is used to request the use of bus super control rights; after determining that the status value of the first register is a first status value, and the status value of the second register corresponding to the first computing node is the first status value, sending the access request to the bus arbitration chip; wherein the first status value of the first register and the first status value of the second register corresponding to the first computing node are used to indicate that the first computing node is allowed to use the bus super control rights.

[0007] Using the above method, when the first computing node determines that the access request is an access request for bus super control rights, it sends a control request to the bus state management chip to request the use of bus super control rights. Only when the first computing node determines that the state value of the first register is the first state value and the state value of the second register corresponding to the first computing node is the first state value, will it send the access request for bus super control rights to the bus arbitration chip. In this way, it can be ensured that only one computing node can use the bus super control rights, avoiding conflicts caused by access by other computing nodes when a computing node is using the bus super control rights.

[0008] In an optional implementation, the bus super control right includes at least one of the following: permission to read and write registers in components of the server for a long time, and permission to upgrade firmware of components of the server.

[0009] In an optional embodiment, the method further includes: when the access request is an access request for normal bus control rights and the state value of the first register is a second state value, sending the access request to the bus arbitration chip.

[0010] Using the above method, when the access request is an access request for normal control of the bus, there is no need to send a control request to the bus status management chip. The first computing node only needs to send an access request for normal control of the bus to the bus arbitration chip when it determines that the status value of the first register is the second status value.

[0011] In an optional implementation, the general bus control right includes at least one of the following: short-term read and write permission for registers in components of the server, and character-type operation permission for registers in components of the server.

[0012] In a second aspect, an embodiment of the present application provides a conflict handling method, which is applied to a bus status management chip in a server, wherein the bus status management chip includes a first register and multiple second registers, and the multiple second registers correspond one-to-one to multiple computing nodes in the server. The method includes: receiving a control request from a first computing node among the multiple computing nodes, wherein the control request is used to request the use of bus super control rights, and the first computing node is one of the multiple computing nodes; when the status value of the first register is a first status value, rejecting the control request; or, when the status value of the first register is a second status value, accepting the control request, and updating the status value of the first register from the second status value to the first status value, and updating the status value of the second register corresponding to the first computing node to the first status value.

[0013] Using the above method, after receiving a control request, the bus state management chip determines whether a computing node is currently using bus super control rights based on the status value of the first register. Only when no computing node is currently using bus super control rights will the chip accept the control request from the first computing node and allow the first computing node to use bus super control rights by modifying the status values ​​of the first register and the second register corresponding to the first computing node. This ensures that there will be no conflict in bus super control rights.

[0014] In an optional implementation, when the control request is accepted, the method further includes:

[0015] Receive a release request from the first computing node, the release request being used to request the release of super control rights; according to the release request, update the state value of the first register from the first state value to the second state value, and update the state value of the second register corresponding to the first computing node to the second state value.

[0016] By adopting the above method, the state values ​​of the first register and the second register corresponding to the first computing node are modified through the release request, thereby informing other computing nodes that the current bus super control right is in an applicable state.

[0017] In a third aspect, an embodiment of the present application provides a conflict handling device, which is a first computing node among multiple computing nodes in a server, wherein the server further includes a bus state management chip, the bus state management chip further includes a first register and multiple second registers, the multiple second registers corresponding one-to-one to the multiple computing nodes, including:

[0018] a determination module, configured to determine whether an access request needs to be sent to a bus arbitration chip of the server;

[0019] A sending module is configured to send a control request to the bus state management chip when the access request is an access request for bus super control rights, the control request being used to request the use of bus super control rights; and after determining that the state value of the first register is a first state value and the state value of the second register corresponding to the first computing node is the first state value, send the access request to the bus arbitration chip; wherein the first state value of the first register and the first state value of the second register corresponding to the first computing node are used to indicate that the first computing node is allowed to use the bus super control rights.

[0020] In an optional implementation, the bus super control right includes at least one of the following: permission to read and write registers in components of the server for a long time, and permission to upgrade firmware of components of the server.

[0021] In an optional implementation, the sending module is further configured to send the access request to the bus arbitration chip when the access request is an access request for normal bus control rights and the state value of the first register is a second state value.

[0022] In an optional implementation, the general bus control right includes at least one of the following: short-term read and write permission for registers in components of the server, and character-type operation permission for registers in components of the server.

[0023] In a fourth aspect, an embodiment of the present application provides a conflict handling device, comprising a first register and a plurality of second registers, wherein the plurality of second registers correspond one-to-one to a plurality of computing nodes in a server, including:

[0024] a receiving module, configured to receive a control request from a first computing node among the plurality of computing nodes, the control request being used to request the use of super control rights, the first computing node being one of the plurality of computing nodes;

[0025] A processing module is used to reject the control request when the state value of the first register is a first state value; or accept the control request when the state value of the first register is a second state value, and update the state value of the first register from the second state value to the first state value, and update the state value of the second register corresponding to the first computing node to the first state value.

[0026] In an optional embodiment, when accepting the control request, the receiving module is used to receive a release request from the first computing node, and the release request is used to request the release of super control rights; the processing module is also used to update the status value of the first register from the first status value to the second status value according to the release request, and update the status value of the second register corresponding to the first computing node to the second status value.

[0027] In a fifth aspect, an embodiment of the present application provides a server, comprising the conflict handling device described in the third aspect and the conflict handling device described in the fourth aspect, on which the method described in the first aspect or the second aspect is executed.

[0028] In a sixth aspect, an embodiment of the present invention provides a conflict handling device, comprising: a memory for storing a computer program; and a processor for executing the method described in the first or second aspect according to the obtained program when executing the computer program stored in the memory.

[0029] In a seventh aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a computer program is stored. When a computer reads and executes the computer program, the method described in the first or second aspect above is executed.

[0030] In an eighth aspect, an embodiment of the present invention provides a computer program product. When a computer reads and executes the computer program product, the method described in the first or second aspect above is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic diagram of a conflict handling structure provided in an embodiment of the present application;

[0033] Figure 2A schematic diagram of a conflict handling structure provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a conflict handling structure provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of a system architecture provided in an embodiment of the present application;

[0036] Figure 5 A flowchart corresponding to a conflict handling method provided in an embodiment of the present application;

[0037] Figure 6 A flowchart corresponding to a conflict handling method provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of the structure of a conflict handling device provided in an embodiment of the present application;

[0039] Figure 8 A schematic diagram of the structure of a conflict handling device provided in an embodiment of the present application;

[0040] Figure 9 A schematic diagram of the structure of a conflict handling device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the embodiments of the present invention, multiple refers to two or more. Words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0042] Before introducing the conflict handling method provided by the embodiment of the present application, in order to facilitate understanding, the professional terms and background of the embodiment of the present invention are first introduced.

[0043] PSU: refers to the power supply unit, which is responsible for converting AC power into DC power required by the device.

[0044] BMC: A core component of server hardware management, responsible for core functions such as hardware status management, operating system management, health status management, and power consumption management. BMC is a small operating system independent of the server system.

[0045] Firmware: is software embedded in a hardware device that controls the basic functions of the device.

[0046] Multi-node servers are an important type of server in the server field. They include multiple computing nodes. Each computing node has equal access requirements to components. When multiple computing nodes send access requests to the bus arbitration chip at the same time, there is a risk of access conflict.

[0047] Currently, there are multiple implementation methods to resolve access conflicts of computing nodes, including: Implementation Method 1 and Implementation Method 2.

[0048] Implementation method 1: Figure 2 As shown, a dedicated management module provides unified management for multiple compute nodes across the entire server. The BMC in each compute node is solely responsible for management within that compute node, and only the dedicated management module can send access requests to the bus arbitration chip. This approach requires the addition of a dedicated management module, increasing server complexity and overall cost. Furthermore, a failure in the dedicated management module directly impacts the availability and maintainability of the entire server, reducing server reliability.

[0049] Implementation method 2: Figure 3 As shown, a mutual communication mechanism is established between each of the multiple computing nodes in the server, and synchronization signals are used to inform other computing nodes whether the current node requires bus super control. For example, when computing node 1 receives an instruction to upgrade the firmware in a component in the server, computing node 1 notifies other computing nodes in advance through a synchronization signal that it needs to obtain bus super control. After receiving the synchronization signal, the other computing nodes suspend sending access requests to the bus arbitration chip. After computing node 1 completes the firmware upgrade in the component, it notifies the other computing nodes through a synchronization signal that the bus super control has been released. After receiving the bus status update information, the other computing nodes resume normal bus access requests. However, this implementation method can basically achieve the preset functions when there are only two computing nodes in the server. When the number of computing nodes in the server increases, the complexity of the hardware links and software design for information synchronization between multiple computing nodes will increase exponentially, making it difficult to ensure the reliability of information exchange in the entire server.

[0050] Based on this, an embodiment of the present application provides a conflict handling method, in which, when a first computing node determines that it needs to send an access request to a bus arbitration chip, it obtains the state value of the first register from the bus state management chip; when the access request is a request for super control rights and the state value of the first register is the second state value, it sends a control request to the bus state management chip, the control request being used to request the use of bus super control rights; after the state value of the first register is updated from the second state value to the first state value, and the state value of the second register corresponding to the first computing node is updated to the first state value, it sends an access request to the bus arbitration chip. In this way, it can avoid the problem of multiple computing nodes simultaneously sending access requests for super control rights to the bus arbitration chip, causing access conflicts.

[0051] Figure 4 A schematic diagram of a system architecture provided in an embodiment of the present application is shown as follows: Figure 4 As shown, the system architecture includes multiple computing nodes, a bus state management chip, a bus arbitration chip, and multiple components. The bus state management chip includes a first register and multiple second registers. The multiple second registers correspond one-to-one with the multiple computing nodes in the system. The multiple computing nodes are connected to the bus arbitration chip. Each computing node can include a BMC management module to manage the computing node.

[0052] The method provided in this application is described in detail below with reference to specific embodiments.

[0053] Figure 5 This is a flowchart corresponding to a conflict handling method provided in an embodiment of the present application, such as Figure 5 As shown, the method includes:

[0054] Step 101: A first computing node determines that an access request needs to be sent to a bus arbitration chip of a server.

[0055] Exemplarily, the first computing node is any one of the multiple computing nodes included in the server. The above-mentioned access request can be an access request for bus super control rights, or it can also be an access request for bus general control rights. The bus super control rights include at least one of the following: long-term read and write permissions for registers in the server's components, and permissions for firmware upgrades for the server's components. For example, when the first computing node needs to read and write registers in the server's components for a long time, the access request is an access request for bus super control rights; or, when the first computing node needs to upgrade the firmware of the server's components, the access request is an access request for bus super control rights. The general bus control rights include at least one of the following: short-term read and write permissions for registers in the server's components, and permissions for character-type operations on registers in the server's components. For example, when the first computing node needs to read and write registers in the server's components for a short time, the access request is an access request for bus general control rights; or, when the first computing node performs character-type operations on registers in the server's components, the access request is an access request for bus general control rights.

[0056] Step 102: If the access request is for bus super control, the first computing node sends a control request to the bus state management chip, and the corresponding bus state management chip receives the control request from the first computing node. The control request is for requesting the use of bus super control.

[0057] In an optional implementation, when the access request is an access request for normal bus control rights and the state value of the first register is the second state value, the access request is sent to the bus arbitration chip.

[0058] For example, when the first computing node needs to send an access request to the bus arbitration chip of the server for bus super control rights, the first computing node needs to send a control request to the bus status management chip, allowing the bus status management chip to determine whether the first computing node is allowed to use the general super control rights. When the first computing node needs to send an access request to the bus arbitration chip of the server for bus normal control rights, it is not necessary to send a control request to the bus status management chip. Instead, it only needs to obtain the status value of a first register in the bus status management chip. When the status value of the first register is a second status value, an access request is sent to the bus arbitration chip. When the status value of the first register is a first status value, no access request is sent. The bus status management chip includes a first register, and the status value of the first register is used to indicate whether a computing node is currently using the bus super control rights. The status value of the first register includes a first status value and a second status value. When the status value of the first register is the first status value, it indicates that no computing node is currently using the bus super control rights; when the status value of the first register is the second status value, it indicates that a computing node is currently using the bus super control rights. For example, the first state value can be set to 1, and the second state value can be set to 0. That is, when the state value of the first register obtained by the first computing node is 1, it indicates that there is currently a computing node using the bus super control right. At this time, the first computing node cannot send an access request for the bus normal control right to the bus arbitration chip. When the state value of the first register obtained by the first computing node is 0, it indicates that there is currently no computing node using the bus super control right. At this time, the first computing node is allowed to send an access request for the bus normal control right to the bus arbitration chip. The bus state management chip also includes multiple second registers, and the multiple second registers correspond one-to-one to multiple computing nodes. For example, the state value of the second register corresponding to the first computing node among the multiple computing nodes is used to indicate whether the first computing node is allowed to use the bus super control right.

[0059] Step 103: When the status value of the first register is the first status value, the bus status management chip rejects the control request; or, when the status value of the first register is the second status value, the bus status management chip accepts the control request and updates the status value of the first register from the second status value to the first status value, and updates the status value of the second register corresponding to the first computing node to the first status value.

[0060] Exemplarily, after receiving a control request from a first computing node among multiple computing nodes of a server, the bus state management chip processes the control request according to the state value of the first register. Specifically, when the state value of the first register is the first state value, the control request of the first computing node is rejected, that is, when the state value of the first register is the first state value, it indicates that there is currently a computing node using the bus super control right, and the first computing node is not allowed to request to use the bus super control right. When the state value of the first register is the second state value, the control request of the first computing node is accepted. That is, when the state value of the first register is the second state value, it indicates that no computing node is currently using the bus super control right, and the first computing node is allowed to request to use the bus super control right. At the same time, the bus state management chip updates the state value of the first register from the second state value to the first state value, and updates the state value of the second register corresponding to the first computing node to the first state value.

[0061] Step 104: The first computing node obtains a state value of the first register and a state value of a second register corresponding to the first computing node.

[0062] Step 105: After the first computing node determines that the state value of the first register is the first state value and the state value of the second register corresponding to the first computing node is the first state value, it sends the access request to the bus arbitration chip.

[0063] Exemplarily, before the first computing node sends an access request to the bus arbitration chip of the server, it needs to obtain the status value of the first register and the status value of the second register corresponding to the first computing node from the bus status management chip. After the first computing node determines that the status value of the first register is the first status value and the status value of the second register corresponding to the first computing node is the first status value, the first computing node sends an access request for bus super control rights to the bus arbitration chip. When the status value of the first register is not the first status value and the status value of the second register corresponding to the first computing node is not the first status value, the first computing node cannot send an access request for bus super control rights to the bus arbitration chip. The first status value of the first register and the first status value of the second register corresponding to the first computing node are used to indicate that the first computing node is allowed to use bus super control rights.

[0064] The status values ​​of the first and second registers are divided into the following three cases:

[0065] Case 1, as shown in Table 1, when the state value of the first register is 1, and the state value of the second register (i.e., second register 1) corresponding to the first computing node (i.e., computing node 1) is 1, it means that the first computing node is allowed to use super control rights. The first computing node can send an access request for bus super control rights to the bus arbitration chip, use the bus super control rights to upgrade the firmware of the components in the server, or perform long-term read and write operations on the registers in the components of the server.

[0066] Table 1: An example of the status values ​​of the first register and the second register

[0067]

[0068] Case 2, as shown in Table 2, when the state value of the first register is 1, the state value of the second register (i.e., second register 1) corresponding to the first computing node (i.e., computing node 1) is 0, indicating that the first computing node does not have the authority to use the bus super control right. However, since the state value of the first register is 1, there is a computing node other than the first computing node among the multiple computing nodes that has the bus super control right. As shown in Table 2, at this time, the state value corresponding to the second register 2 is 1, indicating that computing node 2 has obtained the bus super control right.

[0069] Table 2: An example of the status values ​​of the first register and the second register

[0070]

[0071] Case 3, as shown in Table 3, when the state value of the first register is 0 and the state values ​​of multiple second registers are all 0, it means that no computing node is using the bus super control right and the bus super control right is in an applicable state.

[0072] Table 3: An example of the status values ​​of the first register and the second register

[0073]

[0074] Step 106: The bus state management chip receives a release request from the first computing node.

[0075] For example, a first computing node obtains bus super control rights and uses the bus super control rights to upgrade the firmware of a server component or perform long-term read and write operations on registers in the server component. After the first computing node completes the server upgrade, i.e., the first computing node has exhausted its use of the bus super control rights, the first computing node sends a release request to the bus state management chip, which in turn receives the release request from the first computing node. The release request is used to request the release of the super control rights.

[0076] Step 107 : The bus state management chip updates the state value of the first register from the first state value to the second state value according to the release request, and updates the state value of the second register corresponding to the first computing node to the second state value.

[0077] Illustratively, the bus state management chip updates the state value of the first register from 1 to 0 according to the release request, and sets the state value of the second register corresponding to the first computing node to 0, indicating that the current bus super control right is available for application.

[0078] By adopting the above method, the present application classifies the access requests sent to the bus arbitration chip, defines the requests for short-term reading and writing of registers in the server's components and the requests for character-type operations on registers in the server's components as access requests for normal bus control rights, and defines the requests for long-term reading and writing of registers in the server's components and the requests for firmware upgrades on the server's components as access requests for bus super control rights, and binds the bus control rights to the operating characteristics (short time / long time) to form a dedicated resource scheduling strategy. In addition, for access requests for normal bus control rights, there is no need to send a control request to the bus state management chip. It is only necessary to send an access request for normal bus control rights to the bus arbitration chip by the first computing node when it is determined that the state value of the first register is the second state value. For access requests for bus super control rights, the first computing node sends a control request to the bus state management chip to request the use of bus super control rights. As Figure 6 As shown, when the bus state management chip receives a control request from the first computing node, it queries the state value of the first register. If the state value of the first register is the first state value, the control request is rejected; if the state value of the first register is the second state value, the control request is accepted, and the state value of the first register is set to the first state value, and the state value of the second register corresponding to the first computing node is set to the first state value. In this way, the first computing node sends an access request for the bus super control right to the bus arbitration chip through the state value of the first register and the state value of the second register corresponding to the first computing node. The first computing node uses the general super control right to access the components in the server. In this way, high flexibility and high controllability management of bus access rights are achieved, ensuring the reliability of different access and control requirements of different computing nodes to components in a multi-node server, and avoiding upgrade anomalies caused by multiple computing nodes using the bus super control right at the same time.

[0079] Based on the same technical concept, an embodiment of the present invention further provides a conflict handling device 7000. Figure 7 A schematic diagram of the structure of a conflict handling device provided by an embodiment of the present invention is shown in FIG. Figure 7As shown, the conflict handling device may be a first computing node among multiple computing nodes in a server, the server further comprising a bus state management chip, the bus state management chip further comprising a first register and multiple second registers, the multiple second registers corresponding one-to-one to the multiple computing nodes, including:

[0080] A determination module 701 is configured to determine whether an access request needs to be sent to a bus arbitration chip of the server;

[0081] A sending module 702 is configured to send a control request to the bus status management chip when the access request is an access request for bus super control rights, wherein the control request is used to request the use of bus super control rights; after determining that the status value of the first register is a first status value and the status value of the second register corresponding to the first computing node is the first status value, send the access request to the bus arbitration chip; wherein the first status value of the first register and the first status value of the second register corresponding to the first computing node are used to indicate that the first computing node is allowed to use the bus super control rights.

[0082] In an optional implementation, the bus super control right includes at least one of the following: permission to read and write registers in components of the server for a long time, and permission to upgrade firmware of components of the server.

[0083] In an optional implementation, the sending module 702 is further configured to send the access request to the bus arbitration chip when the access request is an access request for normal bus control rights and the state value of the first register is a second state value.

[0084] In an optional implementation, the general bus control right includes at least one of the following: short-term read and write permission for registers in components of the server, and character-type operation permission for registers in components of the server.

[0085] Based on the same technical concept, an embodiment of the present invention further provides a conflict handling device 8000. Figure 8 A schematic diagram of the structure of a conflict handling device provided by an embodiment of the present invention is shown in FIG. Figure 8 As shown, the conflict handling device may be a bus state management chip, and the conflict handling device includes a first register and a plurality of second registers, wherein the plurality of second registers correspond one-to-one to a plurality of computing nodes in the server, including:

[0086] A receiving module 801 is configured to receive a control request from a first computing node among the multiple computing nodes, the control request being for requesting to use super control rights, the first computing node being one of the multiple computing nodes;

[0087] Processing module 802 is used to reject the control request when the state value of the first register is a first state value; or, when the state value of the first register is a second state value, accept the control request and update the state value of the first register from the second state value to the first state value, and update the state value of the second register corresponding to the first computing node to the first state value.

[0088] In an optional embodiment, when accepting the control request, the receiving module 801 is used to receive a release request from the first computing node, and the release request is used to request the release of super control rights; the processing module 802 is also used to update the status value of the first register from the first status value to the second status value according to the release request, and update the status value of the second register corresponding to the first computing node to the second status value.

[0089] Based on the same concept, the embodiment of the present application also provides a structural diagram of a conflict handling device, such as Figure 9 As shown, the device 9000 includes at least one processor 901 and a memory 902 connected to the at least one processor 901. The specific connection medium between the processor 901 and the memory 902 is not limited in the embodiment of the present application. Figure 9 For example, processor 901 and memory 902 are connected via a bus. Buses can be divided into address buses, data buses, control buses, etc. In this embodiment of the present application, memory 902 stores instructions executable by at least one processor 901. By executing the instructions stored in memory 902, at least one processor 901 can implement the steps of the above-mentioned conflict handling method.

[0090] The processor 901 is the control center of the computer device. It can connect various parts of the computer device using various interfaces and lines, and perform resource settings by running or executing instructions stored in the memory 902 and calling data stored in the memory 902. Optionally, the processor 901 may include one or more processing units. The processor 901 may integrate an application processor and a modem processor. The application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 901. In some embodiments, the processor 901 and the memory 902 may be implemented on the same chip. In some embodiments, they may also be implemented on separate chips.

[0091] The processor 901 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0092] The memory 902 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 902 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (RAM), a static random access memory (SRAM), a programmable read-only memory (PROM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic memory, a disk, an optical disk, and the like. The memory 902 is any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 902 in the embodiment of the present application can also be a circuit or any other device that can implement a storage function for storing program instructions and / or data.

[0093] Based on the same inventive concept, embodiments of the present application provide a computer-readable storage medium, a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to execute any of the conflict resolution methods discussed above. Because the principles for resolving issues using the computer-readable storage medium are similar to those of the conflict resolution methods, the implementation of the computer-readable storage medium can be referenced to the implementation of the methods, and any repetitions will not be repeated.

[0094] Based on the same inventive concept, embodiments of the present application further provide a computer program product comprising computer program code that, when executed on a computer, causes the computer to execute any of the conflict resolution methods discussed above. Because the principles underlying the aforementioned computer program products and conflict resolution methods are similar, the implementation of the aforementioned computer program products can be referenced to the implementation of the methods, and any repetitions will not be repeated.

[0095] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0096] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0097] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0099] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A conflict handling method, characterized in that: The method is applied to a first computing node among a plurality of computing nodes included in a server, the server further comprising a bus state management chip, the bus state management chip further comprising a first register and a plurality of second registers, the plurality of second registers corresponding one-to-one to the plurality of computing nodes, the method comprising: Determining that an access request needs to be sent to a bus arbitration chip of the server; In a case where the access request is an access request for bus super control right, sending a control request to the bus state management chip, wherein the control request is used to request to use the bus super control right; After determining that the state value of the first register is the first state value and the state value of the second register corresponding to the first computing node is the first state value, the access request is sent to the bus arbitration chip; wherein the first state value of the first register and the first state value of the second register corresponding to the first computing node are used to indicate that the first computing node is allowed to use the bus super control right.

2. The method according to claim 1, characterized in that The bus super control right includes at least one of the following: a long-term read and write permission for registers in components of the server, and a firmware upgrade permission for components of the server.

3. The method according to claim 1, characterized in that The method further comprises: When the access request is an access request for normal bus control right and the state value of the first register is the second state value, the access request is sent to the bus arbitration chip.

4. The method according to claim 3, characterized in that The general bus control right includes at least one of the following: a short-term read and write permission for registers in components of the server, and a character-type operation permission for registers in components of the server.

5. A conflict handling method, characterized in that: The method is applied to a bus state management chip in a server, the bus state management chip including a first register and multiple second registers, the multiple second registers corresponding one-to-one to multiple computing nodes in the server, and the method includes: receiving a control request from a first computing node among the plurality of computing nodes, the control request being used to request a bus super control right, the first computing node being one of the plurality of computing nodes; When the state value of the first register is a first state value, reject the control request; or, when the state value of the first register is a second state value, accept the control request, and update the state value of the first register from the second state value to the first state value, and update the state value of the second register corresponding to the first computing node to the first state value.

6. The method according to claim 5, characterized in that In case of accepting the control request, the method further includes: receiving a release request from the first computing node, the release request being used to request release of the super control right; According to the release request, the state value of the first register is updated from the first state value to the second state value, and the state value of the second register corresponding to the first computing node is updated to the second state value.

7. A conflict handling device, characterized in that: The conflict handling device is a first computing node among multiple computing nodes in a server. The server further includes a bus state management chip. The bus state management chip further includes a first register and multiple second registers. The multiple second registers correspond one-to-one to the multiple computing nodes, including: a determination module, configured to determine whether an access request needs to be sent to a bus arbitration chip of the server; A sending module is configured to send a control request to the bus state management chip when the access request is an access request for bus super control rights, the control request being used to request the use of bus super control rights; and after determining that the state value of the first register is a first state value and the state value of the second register corresponding to the first computing node is the first state value, send the access request to the bus arbitration chip; wherein the first state value of the first register and the first state value of the second register corresponding to the first computing node are used to indicate that the first computing node is allowed to use the bus super control rights.

8. A conflict handling device, characterized in that: The conflict handling device includes a first register and a plurality of second registers, wherein the plurality of second registers correspond one-to-one to a plurality of computing nodes in the server, including: a receiving module, configured to receive a control request from a first computing node among the plurality of computing nodes, the control request being used to request the use of super control rights, the first computing node being one of the plurality of computing nodes; A processing module is used to reject the control request when the state value of the first register is a first state value; or accept the control request when the state value of the first register is a second state value, and update the state value of the first register from the second state value to the first state value, and update the state value of the second register corresponding to the first computing node to the first state value.

9. A server, characterized in that: The server includes the conflict handling device as claimed in claim 7 and the conflict handling device as claimed in claim 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is executed.

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