A control circuit of a switching converter and a switching converter

Abstract

The application discloses a control circuit of a switching converter and the switching converter. An output feedback signal and a reference signal are subjected to error amplification to obtain a compensation signal. The compensation signal is clamped according to a peak value of a ramp signal, so that the compensation signal is clamped at an upper limit voltage when the compensation signal is greater than or equal to a clamping voltage. A comparison signal is generated according to the compensation signal, the ramp signal and a ripple signal to control a switching state of a main switch tube of the switching converter. The application has high current limiting precision for inductance peak current, can perform overcurrent protection on inductance current, and does not cause sub-harmonic oscillation during overcurrent protection.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically, to a control circuit and a switching converter. Background Technology

[0002] In power electronic circuits, switching converters are typically required for signal conversion. Figure 1 This diagram illustrates a switching converter, taking a buck converter as an example. Figure 2 This illustrates a conventional control circuit. Figure 3 It indicated Figure 2 Waveforms of various signals corresponding to the control circuit. The buck converter includes the connected upper transistor Q1 (main switch) and lower transistor Q2, inductor L1, and output capacitor C. OUT One end of the inductor is connected to the switching node SW between the upper and lower transistors, and the other end of the inductor is connected to the output capacitor. The control circuit generates a switching control signal Q. 1D Q 2D They are used to control the switching states of the upper and lower transistors respectively, and the switching states of the upper and lower transistors are complementary.

[0003] The control circuit uses a conventional fixed-frequency control method. To ensure the converter's stability at a 50% duty cycle, slope compensation is required for the compensation signal. See [link to relevant documentation]. Figure 2 The operational amplifier 00 will output the feedback signal V. FB and reference signal V REF Error amplification is performed to obtain the compensation signal V C0 The ramp signal generation circuit 01 generates a ramp signal V based on the clock pulse signal CLK. RAMP1 The arithmetic unit 02 will compensate the signal V C0 The difference signal V is obtained by subtracting the slope signal from the slope signal. C1 Comparator 03 will convert the difference signal V C1 With inductor current sampling signal V ISNS1 The comparison generates a comparison signal PWM, and the drive unit 03 generates a switching control signal Q based on the comparison signal PWM and the clock pulse signal CLK. 1D and Q 2D See also Figure 3 When the clock pulse signal CLK has a rising edge, the switch control signal Q... 1D To switch from low to high to control the upper transistor to turn on, the ramp signal V... RAMP1 Starting from the trough, the difference signal V rises. C1 The inductor current sampling signal V starts to decline from its peak. ISNS1 Rise to the difference signal V C1 At that time, the ramp signal V RAMP Reset, compare signal PWM generates a high-level pulse to indicate the switch control signal Q1D flip from high level to low level to control the upper tube to turn off.

[0004] In the prior art, in order to protect the switching converter, the inductor peak current is overcurrent protected, and the existing two overcurrent protection schemes are as follows: the first scheme is to clamp the compensation signal at the set threshold value when the compensation signal reaches the set threshold value, and the peak current limiting value of this scheme is not accurate and is greatly affected by the duty cycle and the slope signal slope; the second scheme is to directly turn off the main switch tube when the inductor peak current is detected to be too large, and this scheme may appear sub-harmonic oscillation during overcurrent protection. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a switching converter control circuit and a switching converter to solve the problems of low inductor peak current limiting accuracy and easy sub-harmonic oscillation in the prior art.

[0006] According to the switching converter control circuit of the present application, the control circuit comprises:

[0007] a first error amplifier for error amplifying an output feedback signal and a reference signal to obtain a compensation signal;

[0008] a slope signal generating circuit for generating a slope signal according to a clock pulse signal;

[0009] a clamping circuit connected to the output end of the first error amplifier, for generating an upper limit voltage according to the peak value of the slope signal, and for clamping the compensation signal at the upper limit voltage when the compensation signal is greater than or equal to the upper limit voltage;

[0010] a comparison circuit for generating a comparison signal according to the compensation signal, the slope signal and a ripple signal, the comparison signal being used to control the switching state of a main switch tube in the switching converter, and the ripple signal being in phase with the inductor current of the switching converter.

[0011] Optionally, the comparison circuit compares the difference between the compensation signal and the slope signal with the ripple signal, and generates an effective comparison signal to control the main switch tube to turn off when the ripple signal reaches the difference.

[0012] Optionally, the average value of the switching node voltage of the switching converter is obtained to obtain the ripple signal, and the switching node voltage is the voltage between the switch tube and the inductor connection end of the switching converter.

[0013] Optionally, the sampling signal of the inductor current is obtained to obtain the ripple signal.

[0014] Optionally, the clamping circuit adds the first threshold voltage and a peak value of the ramp signal to obtain the upper limit voltage.

[0015] Optionally, the first threshold voltage is a constant voltage signal set according to an overcurrent protection threshold.

[0016] Optionally, the clamping circuit comprises a threshold generating circuit, configured to perform error amplification on a sampling signal of the inductor current and a second threshold voltage to obtain an error signal, and obtain the first threshold voltage according to the error signal.

[0017] Optionally, the threshold generating circuit superimposes the error signal and a third threshold voltage to obtain the first threshold voltage.

[0018] Optionally, the clamping circuit comprises a second error amplifier and a diode, a non-inverting input terminal of the second error amplifier receives the clamping voltage, a cathode of the diode is connected to an inverting input terminal of the second error amplifier, an anode of the diode is connected to an output terminal of the second error amplifier, and the cathode of the diode is connected to the output terminal of the first error amplifier.

[0019] Optionally, the ramp signal generating circuit comprises a first current source, a first capacitor and a first switch, the first capacitor and the first switch are connected in parallel,

[0020] When the rising edge of the clock pulse signal triggers the first switch to be turned off, the first current generated by the first current source charges the first capacitor, and the voltage of the first capacitor starts to rise from zero;

[0021] When the ripple signal reaches the difference between the compensation signal and the ramp signal, the first switch is turned on, and the voltage of the first capacitor is reset;

[0022] The voltage of the first capacitor is the ramp signal.

[0023] Optionally, the control circuit further comprises a driving unit configured to receive the comparison signal and the clock pulse signal, and generate a switch control signal to control the switching state of a main switch tube in the switch converter.

[0024] When the ripple signal reaches the difference between the compensation signal and the ramp signal, the comparison signal is valid, the switch control signal controls the main switch tube to be turned off, and when the rising edge of the clock pulse signal appears, the switch control signal controls the main switch tube to be turned on.

[0025] The application further provides a switch converter, comprising a main switch tube and any one of the control circuits described above, and the control circuit is configured to control the switching state of the main switch tube.

[0026] Compared with the prior art, the application has the following advantages: the output feedback signal and the reference signal are error-amplified to obtain a compensation signal, the compensation signal is clamped according to the peak value of the ramp signal, so that the compensation signal is clamped at an upper limit voltage when the compensation signal is greater than or equal to the clamping voltage, and the switching state of the main switch tube of the switching converter is controlled according to the comparison result of the compensation signal and the ramp signal. The application can perform overcurrent protection on the inductor current, has high current-limiting precision for the inductor peak current, and does not cause sub-harmonic oscillation during current-limiting / overcurrent protection. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a schematic diagram of a switching converter;

[0028] Figure 2 It is a schematic diagram of a conventional control circuit;

[0029] Figure 3 It is Figure 2 It is a signal waveform diagram of the control circuit;

[0030] Figure 4 It is a schematic diagram of the control circuit of the step-down converter of the application;

[0031] Figure 5 It is Figure 4 It is an embodiment schematic diagram of the middle clamping circuit;

[0032] Figure 6 It is Figure 4 It is an embodiment schematic diagram of the threshold voltage generating unit;

[0033] Figure 7 It is a signal waveform diagram of the control circuit of the application. DETAILED DESCRIPTION

[0034] The preferred embodiments of the application are described in detail below with reference to the accompanying drawings, but the application is not limited to only these embodiments. The application covers any alternative, modification, equivalent method and scheme made within the spirit and scope of the application.

[0035] In order for the public to have a thorough understanding of the application, specific details are described in the following preferred embodiments of the application, and the application can also be fully understood without the description of these details by those skilled in the art.

[0036] The application is described in more detail below with reference to the accompanying drawings in the following paragraphs. It should be noted that the drawings are in a simplified form and use non-precise proportions, only to facilitate and clearly assist the purpose of describing the embodiments of the application.

[0037] Reference is made to Figure 4The application designs a control circuit for controlling the switching state of each switch tube in a switching converter to limit the peak value of inductor current and perform current limiting / overcurrent protection. The switching converter includes a main switch tube, and when the main switch tube is turned on, the inductor of the switching converter charges and stores energy. The switching converter also includes a rectifier tube, which is complementary to the switching state of the main switch tube, and when the rectifier tube is turned on, the inductor continues to flow. The switching converter can be a buck converter, a boost converter, or a buck-boost converter, and the application is not limited to the structure of the switching converter.

[0038] Referring to Figure 4 , the control circuit controls Figure 1 a buck converter as shown in the schematic to perform output voltage V OUT division sampling to obtain an output feedback signal V FB , a first error amplifier 00 performs error amplification on the output feedback signal V FB and a reference signal V REF to obtain a compensation signal V C0 , a slope signal generating circuit 01 generates a slope signal V RAMP according to a clock pulse signal. A clamping circuit 05 (see Figure 5 ) samples the peak value of the slope signal and generates an upper limit voltage according to the peak value of the slope signal for clamping the maximum value of the compensation signal, and when the compensation signal reaches the upper limit voltage, the compensation signal is clamped at the upper limit voltage. An operation unit 02 subtracts the compensation signal and the slope signal to obtain a difference signal V C1 , and a comparator 03 compares a ripple signal V ISNS representing the inductor current and the difference signal V C1 to generate a PWM signal, wherein when the ripple signal reaches the difference signal, the PWM signal changes from invalid to valid, and the ripple signal is in phase with the inductor current (the same / synchronous timing changes), the ripple signal is a sampling signal of the inductor current, or a signal equivalent to the inductor current obtained by filtering the voltage of the switching node SW. A driving unit 04 generates switching control signals Q 1D , Q 2D according to the PWM signal and the clock pulse signal CLK to control the switching state of the upper tube Q1 and the lower tube Q2 in the buck converter, respectively. When the pulse of the clock pulse signal occurs, the switching control signal Q 1D is valid, and the switching control signal Q 2D is invalid to control the upper tube to turn on and the lower tube to turn off, respectively. When the PWM signal changes from invalid to valid, the switching control signal Q 1D is invalid, and the switching control signal Q 2D is valid to control the upper tube Q1 to turn off and the lower tube Q2 to turn on, respectively. The slope signal generating circuit 01 includes a current source I1, a capacitor C1, and a switch K1, and the capacitor C1 and the switch K1 are connected in parallel. When the pulse of the clock pulse signal CLK occurs, the switching control signal Q2D Invalid, control switch K1 off, current source I1 charging capacitor C1, capacitor voltage, that is, the ramp signal begins to rise, that is, the ramp start value of the ramp signal is synchronized with the pulse occurrence edge of the clock pulse signal; when the PWM signal changes from invalid to valid, the control signal Q 2D of the switch K2 is turned on, and the capacitor voltage, that is, the ramp signal is reset to zero.

[0039] Referring to Figure 5 , a schematic diagram of the clamping circuit in Figure 4 is shown, which includes a sampling unit 501, a threshold voltage generating unit 502, an operation unit 503, and a clamping unit 504. The sampling unit 501 includes a sampling switch K2 and a holding capacitor C2. When the ripple signal V ISNS reaches the difference signal V C1 , the instantaneous control signal PWM_SMP controls the sampling switch K2 to be briefly turned on to sample the peak value of the ramp signal, and the peak value signal V R_SM is obtained through the holding capacitor. The operation unit 503 adds the peak value signal V R_SM and the first threshold voltage V ILIM generated by the threshold voltage generating unit 502 to obtain the upper limit voltage V CLAMP . The clamping unit 504 receives the upper limit voltage V CLAMP and is connected to the output end of the first error amplifier 00, for clamping the compensation signal V C0 at the upper limit voltage V CLAMP when the compensation signal reaches the upper limit voltage, thereby clamping the inductor current peak value at the current limit value. The clamping unit 504 includes a second error amplifier 505 and a diode D1. The non-inverting input end of the second error amplifier 505 receives the upper limit voltage, the inverting input end thereof is connected to the output end of the first error amplifier, that is, the output end of the clamping circuit 05, and the output end thereof is connected to the cathode of the diode D1. The anode of the diode D1 is connected to the inverting input end of the second error amplifier. When the compensation signal V C0 is greater than the clamping voltage, the second error amplifier outputs a negative voltage, the diode D1 is turned on, the size of the diode D1 turn-on voltage drop is ignored, and the compensation signal V C0 at the anode of the diode D1 is equal to the upper limit voltage V CLAMP (the second error amplifier 505 is equivalent to a voltage follower, and the compensation signal is clamped at the upper limit voltage), when the compensation signal V C0 is less than the upper limit voltage V CLAMP , the diode D1 is cut off, and the clamping circuit does not clamp the compensation signal.

[0040] Optionally, the threshold voltage generating unit generates a first threshold voltage V ILIMThe constant voltage signal is set according to the overcurrent protection threshold value. When the ripple signal is the inductor current sampling signal, since the ripple signal can accurately represent the inductor current, by directly giving the first threshold voltage, the peak current limitation can be more accurate, and the current limiting accuracy is high. When the ripple signal is not the signal obtained by sampling the inductor current, but the signal obtained by averaging the voltage of the switching node, or the signal obtained by calculating and constructing the inductor current, the ripple signal cannot accurately represent / equivalent to the inductor current. If the first threshold voltage is directly given, the limitation of the inductor peak current will not be very accurate, and the current limiting accuracy will not be high. Therefore, optionally, the threshold voltage generating unit obtains the first threshold voltage according to the inductor current sampling signal, so as to accurately limit the inductor peak current and realize accurate current limiting protection. See Figure 6 .

[0041] Figure 6 An embodiment schematic diagram of the threshold voltage generating unit 502 is shown, including a sampling switch K3, a holding capacitor C3, a third error amplifier 5021, a diode D2 and an adder 5022. When the upper tube Q1 is turned on, the effective switch control signal Q 1D is turned on, and the holding capacitor C3 holds the inductor current sampling signal V ISNS1 . The third error amplifier 5021 amplifies the error between the second threshold voltage V ILIM2 and the inductor current sampling signal V ISNS1 to obtain an error signal. The cathode of the diode D2 is connected to the output end of the third error amplifier, and the adder 5022 adds the output signal of the anode of the diode D2 and the third threshold voltage V ILIM3 to obtain the first threshold voltage V ILIM . The third threshold voltage V ILIM3 is a voltage signal set according to the overcurrent protection threshold value (the current limiting value of the inductor peak current). When the sampling signal V ISNS1 is less than the second threshold voltage V ILIM2 , the third error amplifier outputs a positive voltage, the diode D2 is cut off, and the third threshold voltage is the first threshold voltage. When the inductor current sampling signal V ISNS1 is greater than the second threshold voltage V ILIM2 , the third error amplifier outputs a negative voltage, the diode D2 is turned on (ignoring the diode turn-on voltage drop), and the sum of the output voltage of the third error amplifier and the third threshold voltage is the first threshold voltage. The first threshold voltage obtained in this way can be flexibly adjusted according to the inductor current. When the sampling signal of the inductor current is less than the second threshold voltage, the difference between the second threshold voltage and the sampling signal is added to the slope peak value, which can more accurately limit the inductor peak current, the current limiting value of the inductor peak current is more stable and accurate, and the current control accuracy can be further improved.

[0042] SeeFigure 7 The diagram illustrates the signal waveform of the control circuit of this invention. When the clock pulse signal CLK is generated, the switch control signal Q... 1D Effective, used to control the turn-on of the upper transistor Q1 (main switch transistor), and simultaneously the ramp signal V RAMP Starting from zero, the difference signal V obtained by subtracting the ramp signal from the compensation signal is... C1 The ripple signal V, representing the inductor current, begins to decrease. ISNS It begins to rise when the ripple signal V ISNS Reaching signal V C1 At that time, the PWM signal generates pulses, and the ramp signal V... RAMP Reset, switch control signal Q 1D Ineffective, upper transistor Q1 is turned off. When the average current signal is too large (ripple signal V), ISNS If the trough value is too large, the signal V will be reached in a relatively short period of time. C1 This leads to a decrease in the duty cycle, resulting in a decrease in the peak value V of the ramp signal. R_SM and the upper limit voltage (signal V) C1 The peak current decreases accordingly, but the peak current of the inductor can still remain basically constant.

[0043] This invention samples the peak value of the ramp signal during the turn-on period of the main switch on a cycle-by-cycle basis and superimposes a preset current limiting threshold voltage as the clamping value of the compensation signal. This results in high current limiting accuracy for the inductor current, with minimal impact of the duty cycle and ramp signal on the current limiting value of the inductor peak current. No subharmonic oscillations will occur during the cycle-by-cycle protection process.

[0044] It should be noted that the specific implementations and corresponding illustrations provided are merely one way of describing the implementation method of the present invention, and are not intended to limit the specific structure of the implementation scheme of the present invention. Various changes or modifications can be made to these implementation schemes without departing from the principles and essence of the present invention, but all such changes and modifications fall within the protection scope of the present invention.

[0045] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.

[0046] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A control circuit of a switching converter, the control circuit comprising: a first error amplifier configured to error amplify an output feedback signal and a reference signal to obtain a compensation signal; a ramp signal generating circuit configured to generate a ramp signal according to a clock signal; a clamping circuit connected to an output terminal of the first error amplifier, configured to generate an upper limit voltage according to a peak value of the ramp signal, and configured to clamp the compensation signal at the upper limit voltage when the compensation signal is greater than or equal to the upper limit voltage; a comparison circuit configured to generate a comparison signal according to the compensation signal, the ramp signal and a ripple signal, the comparison signal being used to control a switching state of a main switch in the switching converter, the ripple signal being in phase with an inductor current of the switching converter; the clamping circuit is configured to add a first threshold voltage and the peak value of the ramp signal to obtain the upper limit voltage; the clamping circuit comprises a threshold generating circuit configured to error amplify a sampling signal of the inductor current and a second threshold voltage to obtain an error signal, and configured to obtain the first threshold voltage according to the error signal.

2. The control circuit of claim 1, wherein: the comparison circuit is configured to compare a difference between the compensation signal and the ramp signal with the ripple signal, and configured to generate a valid comparison signal to control the main switch to be turned off when the ripple signal reaches the difference.

3. The control circuit of claim 1, wherein: an average of a switching node voltage of the switching converter is obtained to obtain the ripple signal, the switching node voltage being a voltage between a switch and an inductor of the switching converter.

4. The control circuit of claim 1, wherein: a sampling signal of the inductor current is obtained to obtain the ripple signal.

5. The control circuit of claim 1, wherein: the threshold generating circuit is configured to add the error signal and a third threshold voltage to obtain the first threshold voltage.

6. The control circuit of claim 1, wherein: the clamping circuit comprises a second error amplifier and a diode, a non-inverting input terminal of the second error amplifier receives the clamping voltage, an inverting input terminal of the second error amplifier is connected to a cathode of the diode, an output terminal of the second error amplifier is connected to an anode of the diode, and the cathode of the diode is connected to the output terminal of the first error amplifier.

7. The control circuit of claim 1, wherein: the ramp signal generating circuit comprises a first current source, a first capacitor and a first switch, the first capacitor and the first switch are connected in parallel, when a rising edge of the clock signal triggers the first switch to be turned off, the first current source charges the first capacitor, and a voltage of the first capacitor starts to rise from zero; when the ripple signal reaches the difference between the compensation signal and the ramp signal, the first switch is turned on, and the voltage of the first capacitor is reset; the voltage of the first capacitor is the ramp signal.

8. The control circuit of claim 6, wherein: a driving unit is further included, configured to receive the comparison signal and the clock signal, and generate a switching control signal to control the switching state of the main switch in the switching converter; when the ripple signal reaches the difference between the compensation signal and the ramp signal, the comparison signal is valid, the switching control signal controls the main switch to be turned off, and when the rising edge of the clock signal occurs, the switching control signal controls the main switch to be turned on.

9. A switching converter characterized by: The main switch tube and the control circuit according to any one of claims 1-8 are included, and the control circuit is used for controlling the switching state of the main switch tube.

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