Hardware description language generation method and system based on large language model

Abstract

The invention relates to a hardware description language generation method and system based on a large language model, and the method comprises the following steps: S1, generating an initial digital circuit design code by adopting the large language model; s2, performing grammar verification on the initial digital circuit design code to obtain grammar verification information; s3, correcting the initial digital circuit design code according to the grammar verification information to obtain a corrected digital circuit design code; s4, performing simulation verification on the corrected digital circuit design code to obtain simulation verification information; s5, judging whether the large language model needs to be optimized or not according to the simulation verification information, if yes, optimizing the large language model, and returning to execute the step S1 after the large language model is optimized; if not, outputting a corrected digital circuit design code, and storing the corrected digital circuit design code to a sample database; according to the method, a'generation-verification-optimization 'closed-loop architecture is constructed, and the code error rate is reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation and artificial intelligence technology, and in particular to a method and system for generating a hardware description language based on a large language model. Background Art

[0002] Currently, LLMs (Language Models) are widely used to generate code for programming languages ​​like C, C++, Python, and Java, significantly improving programmer productivity. However, LLMs' ability to generate hardware description languages ​​like Verilog and VHDL needs improvement (using Verilog as an example below). This is primarily due to the following challenges: 1. Verilog code generation requires large, high-quality Verilog datasets for training, but such datasets are currently scarce. This results in the model failing to fully understand the complexity and diversity of hardware designs when generating code, impacting the accuracy and reliability of the generated code. 2. Verilog code generated by large language models may contain logical errors. Even if the syntax is correct, it may not achieve the intended functionality. For example, the model may not correctly handle boundary conditions or special cases, causing the generated code to fail to run in a real-world hardware environment. 3. Verilog code generated by large language models may contain syntax errors, which can lead to compilation failures. These issues may include incorrect variable type declarations, mismatched brackets, and incorrect keyword usage. 4. Large language models can be inefficient when generating complex Verilog code, especially when tackling system-level or advanced hardware design tasks. Furthermore, the code generated by the model may be suboptimal, resulting in low hardware resource utilization or slow execution. 5. Currently, there is a lack of effective evaluation methods to comprehensively verify the quality of the generated Verilog code. Traditional string matching-based evaluation methods (such as BLEU) are insufficient for this complex code generation task, and functional correctness evaluation requires a complex test environment and a large number of test cases.

[0003] In summary, the code error rate obtained by generating the hardware description language using the existing technology is relatively high. Summary of the Invention

[0004] In order to solve the technical problems in the prior art such as high error rate of codes obtained by using language models to generate hardware description languages, the present invention provides a method and system for generating hardware description languages ​​based on a large language model.

[0005] The technical solution of the present invention to solve the above technical problems is as follows:

[0006] A method for generating a hardware description language based on a large language model comprises the following steps:

[0007] S1, using a large language model to generate initial digital circuit design code;

[0008] S2. Performing syntax verification on the initial digital circuit design code to obtain syntax verification information;

[0009] S3. Modify the initial digital circuit design code according to the syntax verification information to obtain a modified digital circuit design code;

[0010] S4, performing simulation verification on the modified digital circuit design code to obtain simulation verification information;

[0011] S5. Determine whether the large language model needs to be optimized based on the simulation verification information. If so, optimize the large language model and return to step S1 after optimizing the large language model. If not, output the revised digital circuit design code and store the revised digital circuit design code in a sample database.

[0012] The beneficial effects of the present invention are: after the initial digital circuit design code is generated by a large language model, the initial digital circuit design code is then subjected to syntax verification and simulation verification, and the large language model is continuously optimized based on the verification results, thereby constructing a "generation-verification-optimization" closed-loop architecture and reducing the code error rate; compared with the traditional large language model obtained by training with a large amount of data, the present invention can train with a small amount of data and continuously optimize the large language model during the code generation process, so as to achieve more accurate code generated by the continuously optimized and iterated large language model through training with a small amount of data.

[0013] On the basis of the above technical solution, the present invention can also be improved as follows.

[0014] Furthermore, the large language model is used to generate the initial digital circuit design code, which specifically includes the following steps:

[0015] S101, collecting digital circuit design information;

[0016] S102, constructing the large language model based on a reinforcement learning method;

[0017] S103 : Input the digital circuit design information into the large language model, so that the large language model outputs the initial digital circuit design code.

[0018] Furthermore, the syntax verification information includes syntax error type information, syntax error location information, and error description information, and the syntax error location information includes code line number and code column number;

[0019] Correcting the initial digital circuit design code according to the syntax verification information to obtain a corrected digital circuit design code specifically includes the following steps:

[0020] S301, calling a preset repair strategy according to the error type information and the error description information in the syntax verification information;

[0021] S302, querying the code segment to be corrected in the initial digital circuit design code according to the code line number and the code column number;

[0022] S303: Use the preset repair strategy to correct the queried code segment.

[0023] Furthermore, simulation verification is performed on the modified digital circuit design code to obtain simulation verification information, which specifically includes the following steps:

[0024] S401, constructing multiple simulation verification reference models according to digital circuit design information;

[0025] S402, determining whether the output results of the plurality of simulation verification reference models are consistent, if so, selecting any one of the simulation verification reference models as the simulation verification model, if not, returning to step S401;

[0026] S403, inputting the modified digital circuit design code into the simulation verification model, so that the simulation verification model outputs a first simulation result;

[0027] S404: Input the modified digital circuit design code into digital circuit synthesis software for simulation verification to obtain a second simulation result; wherein the simulation verification information includes the first simulation result and the second simulation result.

[0028] Further, judging whether the large language model needs to be optimized based on the simulation verification information, the specific steps are as follows:

[0029] Determine whether the first simulation result is consistent with the second simulation result. If the first simulation result is inconsistent with the second simulation result, determine that the large language model needs to be optimized; if the first simulation result is consistent with the second simulation result, calculate the quantitative evaluation value of the corrected digital circuit design code according to the chip PPA index, and when the quantitative evaluation value is less than or equal to a preset PPA index threshold, determine that the large language model needs to be optimized.

[0030] Furthermore, the quantitative evaluation value of the modified digital circuit design code is calculated according to the chip PPA index, which specifically includes the following steps:

[0031] Performing comprehensive simulation on the modified digital circuit design code using the digital circuit synthesis and power consumption simulation software under preset chip parameter conditions to obtain chip power consumption and chip area values; wherein the preset chip parameters include a chip operating frequency value;

[0032] The chip PPA index is calculated according to the chip area value, the chip operating frequency value, and the chip power consumption value.

[0033] Furthermore, the chip PPA index is calculated according to the chip area value, the chip operating frequency value, and the chip power consumption value, and the specific steps are as follows:

[0034] Normalizing the chip area value, the chip operating frequency value, and the chip power consumption value respectively to obtain a normalized area value, a normalized frequency value, and a normalized power consumption value;

[0035] The chip PPA index is calculated according to the normalized area value, the normalized frequency value, and the normalized power consumption value.

[0036] Furthermore, a calculation formula for calculating the chip PPA index according to the normalized area value, the normalized frequency value, and the normalized power consumption value is as follows:

[0037] PPA_score=α*NormArea+β*NormPower+γ*NormFreq;

[0038] Among them, α+β+γ=1, PPA_score represents the chip PPA indicator, NormArea represents the normalized area value, NormPower represents the normalized power consumption value, NormFreq represents the normalized frequency value, α represents the area cost value, β represents the power consumption sensitivity value, and γ represents the timing path weight.

[0039] Furthermore, the specific steps for optimizing the large language model are as follows:

[0040] Constructing a reinforcement learning reward function based on the grammar verification information, the simulation verification information, and the chip PPA indicator; wherein the grammar verification information also includes a grammar verification score value, and the simulation verification information also includes a simulation verification score value;

[0041] Optimizing the large language model using the reinforcement learning reward function;

[0042] The specific formula of the reinforcement learning reward function is as follows:

[0043] Total_reward=-λ1*Syntax_Error_Percent+λ2*(ω2-Function_Mism atch_Percent)+λ3*(PPA_score-ω3);

[0044] Among them, Total_reward represents the value of the reinforcement learning reward function, λ1 represents the syntax verification weight coefficient, Syntax_Error_Percent represents the syntax verification score value, λ2 represents the simulation verification weight coefficient, ω2 represents the preset simulation verification score threshold, Function_Mismatch_Percent represents the simulation verification score value, λ3 represents the chip PPA indicator weight coefficient, and ω3 represents the preset PPA indicator threshold.

[0045] In order to solve the above technical problems, the present invention also provides a hardware description language generation system based on a large language model, the specific technical contents of which are as follows:

[0046] A hardware description language generation system obtained by using the hardware description language generation method based on a large language model as described above comprises:

[0047] An intelligent generation module for generating initial digital circuit design code using a large language model;

[0048] a verification feedback module, configured to perform syntax verification on the initial digital circuit design code to obtain syntax verification information; modify the initial digital circuit design code according to the syntax verification information to obtain a modified digital circuit design code; and perform simulation verification on the modified digital circuit design code to obtain simulation verification information;

[0049] An optimization iteration module determines whether the large language model needs to be optimized based on the simulation verification information. If so, the large language model is optimized and the initial digital circuit design code is regenerated using the optimized large language model; if not, the revised digital circuit design code is output and stored in a sample database. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 Flowchart of a method for generating a hardware description language based on a large language model in an embodiment of the present invention;

[0051] Figure 2 This is a flowchart of grammar verification in an embodiment of the present invention;

[0052] Figure 3 This is a simulation verification flow chart in an embodiment of the present invention;

[0053] Figure 4 The figure is a structural diagram of a hardware description language generation system based on a large language model in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0055] like Figure 1 As shown, this embodiment provides a method for generating a hardware description language based on a large language model, comprising the following steps:

[0056] S1, using a large language model to generate initial digital circuit design code;

[0057] Using a large language model to generate initial digital circuit design code includes the following steps:

[0058] S101. Collect digital circuit design information; wherein the digital circuit design information is natural language requirement information or a digital circuit state transition diagram or a code segment.

[0059] S102. Build a large language model based on reinforcement learning method;

[0060] Data Collection: Collect a large amount of hardware description language (such as Verilog HDL) code data from sources such as open source IP cores (such as OpenCores, RISC-V Rocket Core, etc.) and industrial-grade IP cores (desensitized commercial IP, such as PCIe controllers and DDR PHY).

[0061] Data cleaning: Remove low-quality, duplicate, or incomplete code snippets, and handle errors and anomalies in the code to ensure data quality and availability.

[0062] Data preprocessing: As shown in Table 1, the code is processed through word segmentation, stemming, and part-of-speech tagging to convert it into a format that can be understood by the large language model. At the same time, the comments and docstrings in the code are processed so that the model can better understand the semantics of the code.

[0063] Table 1 Preprocessing examples

[0064]

[0065] Model architecture selection for large language models: Choose a model architecture with strong language understanding and generation capabilities, such as the Transformer. The Transformer architecture can effectively process sequential data and capture long-range dependencies in code.

[0066] Training target selection: The code generation task is regarded as a sequence-to-sequence (seq2seq) problem. The goal of the model is to generate corresponding code based on the input natural language description or code context.

[0067] Model training: Pre-training is performed on large-scale code data to allow the model to learn the syntax, semantics, and structural patterns of the code. During the pre-training process, the model uses self-supervised learning methods, such as the Masked Language Model, to predict missing parts in the code or the next code snippet.

[0068] Fine-tuning the large language model: During the fine-tuning phase, supervised learning is used, with the input natural language description or code context and the corresponding code as training samples. The backpropagation algorithm is used to calculate the loss function (such as cross-entropy loss) between the model output and the actual code, and then the above parameters are adjusted based on the gradient of the loss function. The goal is to minimize the value of the loss function so that the model can more accurately generate the corresponding code based on the input. For example, if there is a large difference between the code generated by the model and the actual code, the value of the loss function will be large. At this time, the parameters are updated through the gradient descent algorithm, so that the model is closer to the actual code in subsequent predictions.

[0069] Reward mechanism for large language models: The generation strategy is adjusted in real time based on the reward functions of the verification feedback layer and the optimization iteration layer to ensure that the generated code gradually converges to a high-quality state.

[0070] S103 : Inputting digital circuit design information into the large language model so that the large language model outputs an initial digital circuit design code.

[0071] S2. Perform syntax verification on the initial digital circuit design code to obtain syntax verification information;

[0072] Syntax verification information includes syntax error type information, syntax error location information and error description information. Syntax error location information includes code line number and code column number.

[0073] Syntax Checker Integration: Integrate with syntax checkers such as Verilog or Synopsys VCS to perform real-time syntax checking on generated Verilog code. Configure the tool to output a detailed syntax check report, including error type, error location (line and column), and error description.

[0074] Syntax errors are grouped into the following categories:

[0075] Variable declaration errors: such as incorrect variable type declaration, undeclared variables, incorrect variable bit width, etc.

[0076] Grammatical structure errors: such as mismatched brackets, incorrect keywords, etc.

[0077] Module interface error: such as mismatch in port number or type.

[0078] S3. Modify the initial digital circuit design code according to the syntax verification information to obtain a modified digital circuit design code;

[0079] Correcting the initial digital circuit design code according to the syntax verification information to obtain a corrected digital circuit design code specifically includes the following steps:

[0080] S301, calling a preset repair strategy according to error type information and error description information in the syntax verification information;

[0081] S302, searching for a code segment to be corrected in the initial digital circuit design code according to the code line number and the code column number;

[0082] S303: Use a preset repair strategy to correct the queried code segment.

[0083] S304, and use the corrected digital circuit design code to return to step S301 to step S303 until there is no error information in the syntax verification information.

[0084] like Figure 2 As shown, the specific process of syntax verification is as follows:

[0085] The generated RTL code, i.e., the digital circuit design code, is subjected to syntax checking. If the syntax check passes (i.e., there is no syntax error information in the syntax verification information), the RTL code is directly output; if the syntax check passes (i.e., there is error type information and error description information in the syntax verification information), the RTL code is corrected according to the error description information by calling a repair strategy that matches the error description information in the rule library to achieve automatic repair of the RTL code. If the RTL code that has been automatically repaired multiple times still contains error type information and error description information in the syntax verification information obtained after syntax verification, manual intervention is initiated, i.e., the error type information and error description information are output to a manual repair platform, the RTL code is repaired manually, and the manual repair process information is recorded, and the manual repair process information is transferred to a sample database as a repair strategy; and the manual repair process information is associated with the error type information and error description information in the sample database, so that when the same error type information and error description information appear subsequently, the manual repair process information can be called from the sample database to automatically repair the RTL code.

[0086] S4. Perform simulation verification on the modified digital circuit design code to obtain simulation verification information;

[0087] Perform simulation verification on the modified digital circuit design code to obtain simulation verification information, which specifically includes the following steps:

[0088] S401, constructing multiple simulation verification reference models according to digital circuit design information;

[0089] S402: Determine whether the output results of multiple simulation verification reference models are consistent. If so, select any simulation verification reference model as the simulation verification model. If not, return to step S401.

[0090] S403, inputting the corrected digital circuit design code into the simulation verification model, so that the simulation verification model outputs a first simulation result;

[0091] S404 , inputting the modified digital circuit design code into digital circuit synthesis software for simulation verification to obtain a second simulation result; wherein the simulation verification information includes the first simulation result and the second simulation result.

[0092] like Figure 3 As shown, according to natural language requirements or state transition diagrams, an LLM (the above-mentioned large language model (English: Large Language Model, abbreviated as LLM) refers to a deep learning model trained with a large amount of text data, so that the model can generate natural language text or understand the meaning of language text) is used to generate a C reference model (the above-mentioned simulation verification reference model). The C reference model should contain functional logic equivalent to the hardware design, but does not involve hardware implementation details. To ensure the correctness of the C reference model, a multi-model generation mechanism can be used: if the output results of the C reference models generated by multiple models are consistent, the results are considered correct, that is, any C reference model is selected as the simulation verification model; the corrected digital circuit design code is input into the simulation verification model, so that the simulation verification model outputs the first simulation result.

[0093] RTL verification model construction: Based on natural language requirements or state transition diagrams, LLM is used to generate an RTL verification model, and a certain number of verification scenarios are generated by generating the RTL verification model. Among them, RTL code (Register Transfer Level code) is a digital circuit design code at the register transfer level abstraction level implemented in a hardware description language (HDL), which is used to describe data transfer between registers and clock-driven logical operations.

[0094] Functional verification: An integrated simulation tool (such as a VCS logic simulation tool or a Simvision simulation tool) simulates the RTL code and outputs the final result in a binary file to obtain a second simulation functional result; wherein the second simulation result includes a second simulation functional result and a second simulation physical result.

[0095] Physical verification: Generate a bitstream from the RTL code on the Xilinx Vivado, Intel Quartus, or Synopsys HAPS platform and run it on the corresponding platform. The final result is transmitted to the verification feedback layer through an interface (such as PCIe) and output as a binary file to obtain the second simulation physical result.

[0096] Data comparison: The output results of the C reference model are compared with the simulation results of the RTL code one by one. This means that the first simulation result is compared with the second simulation functional result. If the comparison results are consistent, the functional check passes and the physical verification process is executed; otherwise, the functional check fails. The physical verification process compares the first simulation result in the output results of the C reference model with the second simulation physical result in the physical verification results one by one. If the comparison results are consistent, the physical verification passes; otherwise, the physical verification fails.

[0097] If the functional check fails, the comparison results are fed back to the intelligent generation layer, that is, the large language model for model optimization, triggering a new round of code generation. The failed verification scenario is recorded in the sample database for subsequent supervised learning of the large language model.

[0098] By performing functional and physical verification on the code generated by the large language, the code can meet the functional and physical requirements of actual needs, and feedback supervised learning is performed on the large language model to improve the accuracy of the code generated by the large language model, while reducing the computing power consumption caused by relying solely on large amounts of data to train the model.

[0099] S5. Determine whether the large language model needs to be optimized based on the simulation verification information. If so, optimize the large language model and return to step S1 after optimizing the large language model. If not, output the corrected digital circuit design code and store the corrected digital circuit design code in the sample database.

[0100] Determine whether the large language model needs to be optimized based on the simulation verification information. The specific steps are as follows:

[0101] Determine whether the first simulation result is consistent with the second simulation result. If the first simulation result is inconsistent with the second simulation result, determine that the large language model needs to be optimized; if the first simulation result is consistent with the second simulation result, calculate the quantitative evaluation value of the corrected digital circuit design code according to the chip PPA index, and when the quantitative evaluation value is less than or equal to the preset PPA index threshold, determine that the large language model needs to be optimized.

[0102] Specifically, the quantitative evaluation value of the modified digital circuit design code is calculated based on the chip PPA index, which specifically includes the following steps:

[0103] S501. Use the digital circuit synthesis and power consumption simulation software to perform comprehensive simulation on the modified digital circuit design code under preset chip parameter conditions to obtain chip power consumption value and chip area value; wherein the preset chip parameters include chip operating frequency value.

[0104] The RTL code is simulated in a synthesis tool (such as Synopsys DC) with different processes, i.e. preset chip parameters (such as 7nm chip parameters, 14nm chip parameters, 28nm chip parameters), and different frequency points (such as 100MHz, 200MHz, 300MHz, etc.) to obtain area reports and timing reports (timing reports in electronic design automation (EDA)) for each process and frequency point.

[0105] In the verification feedback layer, namely the verification feedback module, power consumption data is collected during physical verification through a power collection device and transmitted to the optimization iteration layer.

[0106] S502: Calculate the chip PPA index according to the chip area value, the chip operating frequency value, and the chip power consumption value.

[0107] The chip PPA index is calculated based on the chip area value, chip operating frequency value, and chip power consumption value. The specific steps are as follows:

[0108] Normalizing the chip area value, chip operating frequency value, and chip power consumption value respectively to obtain a normalized area value, a normalized frequency value, and a normalized power consumption value;

[0109] Preprocessing: Under the same process, filter out the frequency points without timing violations in the timing report and determine the maximum operating frequency (MaxFreq) of each module with the same function.

[0110] Extract key information such as the CellArea and frequency from the area report and store it in an area data file. Subtract the power consumption of the physical verification platform when running idle from the collected power consumption data to obtain the actual power consumption data of the module.

[0111] The calculation methods for normalizing the chip area value, chip operating frequency value, and chip power consumption value are as follows:

[0112] For area data, calculate the maximum area maxArea and the minimum area minArea values ​​among all frequency points of the module that implements the same function, and define the normalized area NormArea as follows:

[0113]

[0114] Among them, CellArea represents the comprehensive area value of the chip, maxArea represents the maximum area value of the chip, and minArea represents the minimum area value of the chip.

[0115] For power consumption data, the minimum power consumption minPower value is calculated at all frequency points of the module that implements the same function. The normalized power consumption NormPower is defined as follows:

[0116]

[0117] Here, minPower indicates the minimum power consumption value, and Power indicates the rated power consumption.

[0118] For frequency data, among all the frequency points of the module that implements the same function, calculate the highest frequency point MaxFreq value and the highest frequency point CurMaxFreq of the current module, and define the NormFreq calculation as follows:

[0119]

[0120] Among them, CurMaxFreq represents the maximum frequency point of the current chip, and MaxFreq represents the maximum frequency point of the corrected digital circuit design code.

[0121] The chip PPA index is calculated based on the normalized area value, normalized frequency value, and normalized power consumption value.

[0122] The calculation formula for the chip PPA index is calculated based on the normalized area value, normalized frequency value, and normalized power consumption value as follows:

[0123] PPA_score=α*NormArea+β*NormPower+γ*NormFreq;

[0124] Among them, α+β+γ=1, PPA_score represents the chip PPA index, NormArea represents the normalized area value, NormPower represents the normalized power consumption value, NormFreq represents the normalized frequency value, α represents the area cost value, β represents the power consumption sensitivity value, and γ represents the timing path weight. Further, the specific steps for optimizing the large language model are as follows:

[0125] Constructing a reinforcement learning reward function based on the syntax verification information, the simulation verification information, and the chip PPA indicator; wherein the syntax verification information also includes a syntax verification score value, and the simulation verification information also includes a simulation verification score value;

[0126] Optimizing large language models using reinforcement learning reward functions;

[0127] The specific formula of the reinforcement learning reward function is as follows:

[0128] Total_reward=-λ1*Syntax_Error_Percent+λ2*(ω2-Function_Mism atch_Percent)+λ3*(PPA_score-ω3);

[0129] Where Total_reward represents the value of the reinforcement learning reward function, λ1 represents the syntax verification weight coefficient, Syntax_Error_Percent represents the syntax verification score, λ2 represents the simulation verification weight coefficient, ω2 represents the preset simulation verification score threshold, Function_Mismatch_Percent represents the simulation verification score, λ3 represents the chip PPA weight coefficient, and ω3 represents the preset PPA threshold. λ1, λ2, and λ3 are weight coefficients representing the impact of syntax errors, function errors, and PPA, respectively. When Function_Mismatch_Percent > ω2, a penalty is deducted; when Function_Mismatch_Percent < ω2, a bonus is awarded. When PPA_score < ω3, a penalty is deducted; when Function_Mismatch_Percent > ω3, a bonus is awarded.

[0130] Use reinforcement learning algorithms (such as Q-learning or PPO) to optimize large language models:

[0131] The verification results are used as reward signals to gradually adjust the model parameters. In each iteration, the parameters of the generative model are updated according to the value of the reward function, ensuring that the generated code gradually converges to a high-quality state.

[0132] Golden Sample Library Update

[0133] Sample database updates: Code that meets the PPA comprehensive scoring requirements will be regularly added to the sample database. Outdated or poor-quality code samples will be cleaned up to maintain the diversity and representativeness of the sample database.

[0134] After generating initial digital circuit design code using a large language model, the present invention performs syntax verification and simulation validation on the initial digital circuit design code. Based on the verification results, the large language model is continuously optimized, creating a closed-loop "generate-verify-optimize" architecture that reduces code error rates. Unlike traditional large language models trained with large amounts of data, the present invention uses a small amount of data for training and continuously optimizes the large language model during code generation. This allows for more accurate code generated by the continuously optimized and iterative large language model, resulting in a revolutionary improvement in digital circuit development efficiency: The syntax accuracy of the first-time generated code is improved, reducing debugging time and shortening the development cycle of complex IP cores. This breakthrough in functional reliability improves the pass rate of system-level functional verification and the rate of achieving timing margins for cross-clock domain designs. The PPA optimization capability is significantly enhanced: the highest frequency of the IP can be used as an input condition during code generation, reducing PPA optimization time. The technical threshold is lowered: mixed natural language and waveform input are supported, enabling the completion of relatively complex RTL designs. A dynamic sample library enables the accumulation of design knowledge, resulting in a high reuse rate for new module development. Furthermore, flexibility is enhanced: adaptive optimization is supported for multiple process nodes, including 7nm, 14nm, and 28nm.

[0135] like Figure 4 As shown, in some other embodiments, a hardware description language generation system obtained by using the hardware description language generation method based on the large language model is also provided, including:

[0136] An intelligent generation module for generating initial digital circuit design code using a large language model;

[0137] The verification feedback module is used to perform syntax verification on the initial digital circuit design code to obtain syntax verification information; correct the initial digital circuit design code according to the syntax verification information to obtain a corrected digital circuit design code; and perform simulation verification on the corrected digital circuit design code to obtain simulation verification information;

[0138] The optimization iteration module determines whether the large language model needs to be optimized based on the simulation verification information. If so, the large language model is optimized and the initial digital circuit design code is regenerated using the optimized large language model; if not, the corrected digital circuit design code is output and stored in the sample database.

[0139] In this embodiment, the intelligent generation module, the verification feedback module, and the optimization iteration module may be computer programs or computer instruction modules or computers or computing devices with corresponding functions.

[0140] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the concept and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for generating a hardware description language based on a large language model, characterized in that: The steps include: S1, using a large language model to generate initial digital circuit design code; S2. Performing syntax verification on the initial digital circuit design code to obtain syntax verification information; S3. Modify the initial digital circuit design code according to the syntax verification information to obtain a modified digital circuit design code; S4, performing simulation verification on the modified digital circuit design code to obtain simulation verification information; S5. Determine whether the large language model needs to be optimized based on the simulation verification information. If so, optimize the large language model and return to step S1 after optimizing the large language model. If not, output the revised digital circuit design code and store the revised digital circuit design code in a sample database.

2. The method for generating a hardware description language based on a large language model according to claim 1, wherein: Using a large language model to generate initial digital circuit design code includes the following steps: S101, collecting digital circuit design information; S102, constructing the large language model based on a reinforcement learning method; S103 : Input the digital circuit design information into the large language model, so that the large language model outputs the initial digital circuit design code.

3. The method for generating a hardware description language based on a large language model according to claim 2, wherein: The syntax verification information includes syntax error type information, syntax error location information and error description information, and the syntax error location information includes code line number and code column number; Correcting the initial digital circuit design code according to the syntax verification information to obtain a corrected digital circuit design code specifically includes the following steps: S301, calling a preset repair strategy according to the error type information and the error description information in the syntax verification information; S302, querying the code segment to be corrected in the initial digital circuit design code according to the code line number and the code column number; S303: Use the preset repair strategy to correct the queried code segment.

4. The method for generating a hardware description language based on a large language model according to claim 3, wherein: Performing simulation verification on the modified digital circuit design code to obtain simulation verification information specifically includes the following steps: S401, constructing multiple simulation verification reference models according to digital circuit design information; S402, determining whether the output results of the plurality of simulation verification reference models are consistent, if so, selecting any one of the simulation verification reference models as the simulation verification model, if not, returning to step S401; S403, inputting the modified digital circuit design code into the simulation verification model, so that the simulation verification model outputs a first simulation result; S404: Input the modified digital circuit design code into digital circuit synthesis software for simulation verification to obtain a second simulation result; wherein the simulation verification information includes the first simulation result and the second simulation result.

5. The method for generating a hardware description language based on a large language model according to claim 4, characterized in that: Determining whether the large language model needs to be optimized based on the simulation verification information is as follows: determining whether the first simulation result is consistent with the second simulation result, and if the first simulation result is inconsistent with the second simulation result, determining that the large language model needs to be optimized; If the first simulation result is consistent with the second simulation result, a quantitative evaluation value of the modified digital circuit design code is calculated based on the chip PPA index, and when the quantitative evaluation value is less than or equal to a preset PPA index threshold, it is determined that the large language model needs to be optimized.

6. The method for generating a hardware description language based on a large language model according to claim 5, characterized in that: Calculating the quantitative evaluation value of the modified digital circuit design code according to the chip PPA index specifically includes the following steps: Performing comprehensive simulation on the modified digital circuit design code using the digital circuit synthesis and power consumption simulation software under preset chip parameter conditions to obtain chip power consumption and chip area values; wherein the preset chip parameters include a chip operating frequency value; The chip PPA index is calculated according to the chip area value, the chip operating frequency value, and the chip power consumption value.

7. The method for generating a hardware description language based on a large language model according to claim 6, characterized in that: The chip PPA index is calculated according to the chip area value, the chip operating frequency value, and the chip power consumption value, and the specific steps are as follows: Normalizing the chip area value, the chip operating frequency value, and the chip power consumption value respectively to obtain a normalized area value, a normalized frequency value, and a normalized power consumption value; The chip PPA index is calculated according to the normalized area value, the normalized frequency value, and the normalized power consumption value.

8. The method for generating a hardware description language based on a large language model according to claim 7, wherein: The calculation formula for calculating the chip PPA index according to the normalized area value, the normalized frequency value, and the normalized power consumption value is as follows: PPA_score=α*NormArea+β*NormPower+γ*NormFreq; Among them, α+β+γ=1, PPA_score represents the chip PPA indicator, NormArea represents the normalized area value, NormPower represents the normalized power consumption value, NormFreq represents the normalized frequency value, α represents the area cost value, β represents the power consumption sensitivity value, and γ represents the timing path weight.

9. The method for generating a hardware description language based on a large language model according to claim 8, wherein: The specific steps for optimizing the large language model are as follows: Constructing a reinforcement learning reward function based on the grammar verification information, the simulation verification information, and the chip PPA indicator; wherein the grammar verification information also includes a grammar verification score value, and the simulation verification information also includes a simulation verification score value; Optimizing the large language model using the reinforcement learning reward function; The specific formula of the reinforcement learning reward function is as follows: Total_reward=-λ1*Syntax_Error_Percent+λ2*(ω2-Function_Mism atch_Percent)+λ3*(PPA_score-ω3); Among them, Total_reward represents the value of the reinforcement learning reward function, λ1 represents the syntax verification weight coefficient, Syntax_Error_Percent represents the syntax verification score value, λ2 represents the simulation verification weight coefficient, ω2 represents the preset simulation verification score threshold, Function_Mismatch_Percent represents the simulation verification score value, λ3 represents the chip PPA indicator weight coefficient, and ω3 represents the preset PPA indicator threshold.

10. A hardware description language generation system obtained by using the hardware description language generation method based on a large language model according to any one of claims 1 to 9, characterized in that: include: An intelligent generation module for generating initial digital circuit design code using a large language model; A verification feedback module, configured to perform syntax verification on the initial digital circuit design code to obtain syntax verification information; Correcting the initial digital circuit design code according to the syntax verification information to obtain a corrected digital circuit design code; Performing simulation verification on the modified digital circuit design code to obtain simulation verification information; An optimization iteration module determines whether the large language model needs to be optimized based on the simulation verification information. If so, the large language model is optimized and the initial digital circuit design code is regenerated using the optimized large language model; if not, the revised digital circuit design code is output and stored in a sample database.

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