Mixer layout structure, IQ double-balanced mixer layout structure and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a mixer layout structure, an IQ double-balanced mixer layout structure and electronic equipment. In the invention, four symmetrically arranged MOS transistors (M1, M2, M3 and M4) are symmetrically arranged through a longitudinal symmetry axis and a transverse symmetry axis, grid electrodes of the M1 and the M4 are connected to a first port of a local oscillator, and grid electrodes of the M2 and the M3 are connected to a second port of the local oscillator; the source electrodes of the M1 and the M2 are connected with a first radio frequency input port through symmetrical leads, and the source electrodes of the M3 and the M4 are connected with a second radio frequency input port; drain electrodes of the M1 and the M3 are connected to serve as a first intermediate frequency output port, and drain electrodes of the M2 and the M4 are connected to serve as a second intermediate frequency output port. All grid, source and drain leads adopt the same type of metal; the intervals of the MOS tubes are equal, and the arrangement of radio frequency and intermediate frequency leads can eliminate phase errors. The signal processing capability of the mixer is effectively improved, and the stability and reliability of the system are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a mixer layout structure, an IQ double-balanced mixer layout structure, and electronic equipment. Background Art

[0002] A mixer is a key RF circuit used to combine two signals of different frequencies to generate an output signal containing the original frequency as well as its sum and difference frequencies. This frequency conversion capability makes it widely used in communication systems (such as wireless transceivers and satellite communications), radar systems (such as millimeter-wave radar and target detection), spectrum monitoring equipment, and other fields requiring frequency conversion signal processing.

[0003] In traditional mixer design, circuit performance is often limited by non-ideal symmetry, manifesting itself in local oscillator (LO) leakage, phase asymmetry, DC offset, poor temperature stability, and limited dynamic range. LO leakage refers to the leakage of the LO signal into the RF or IF port due to parasitic capacitance or trace length mismatch between the gate and RF leads, resulting in receiver sensitivity degradation or transmit spectrum contamination. Phase asymmetry refers to the phase error and gain mismatch caused by an asymmetric layout, which affects the mixer's quadrature modulation (e.g., in-phase / quadrature double-balanced mixers, or IQ double-balanced mixers). DC offset refers to the DC voltage offset generated by resistance mismatch between the source or drain leads, requiring additional calibration circuitry to compensate and increasing system complexity. Poor temperature stability is due to uneven local heat distribution. Limited dynamic range is due to the nonlinear distortion introduced by inconsistencies in parasitic resistance or capacitance, which reduces signal processing capabilities.

[0004] Traditional technologies attempt to improve performance through circuit design or process optimization, but fail to fundamentally solve the parasitic parameter mismatch problem caused by layout asymmetry, such as Figure 1 As shown, Figure 1The MOS tubes (i.e. M1-M4) are placed in two rows. The full Chinese name of the MOS tube is "Metal-Oxide Semiconductor Field-Effect Transistor", and the full English name is Metal-Oxide-SemiconductorField-Effect Transistor. The MOS tube belongs to the insulated gate type in the field effect transistor. It forms an electric field effect through the metal-oxide-semiconductor structure to control the on and off of the current. Its core structure includes three terminals: gate (G), source (S), and drain (D). The switching or amplification function is achieved through voltage control. The layout design of this type of switching circuit is that the MOS tubes are placed in two rows. Although there is a partially symmetrical structure indicated by the first symmetry axis and the second symmetry axis, the height is too high, and the connection method of the four MOS tube gate leads and the RF leads increases the overall width and height of the layout, which will have problems such as limited application scenarios; and the first intermediate frequency line ( Figure 1 Middle IFIP) and Second IF Line ( Figure 1 The parasitic capacitance of IFIN is naturally unequal, which will lead to phase asymmetry, thus causing phase error and gain adaptation. Figure 2 The layout design of the mixer circuit shown is not completely symmetrical, and still has problems such as poor temperature stability and phase asymmetry. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a mixer layout structure, an IQ double-balanced mixer layout structure, and an electronic device, which can simplify design and debugging, reasonably arrange the complete symmetry between the signal lines of the layout, effectively improve the signal processing capability of the mixer, and enhance the stability and reliability of the system.

[0006] To solve the above technical problems, an embodiment of the present invention provides a mixer layout structure, comprising: a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein the first MOS transistor and the fourth MOS transistor are arranged sequentially in a first row, and the second MOS transistor and the third MOS transistor are arranged sequentially in a second row; the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all metal oxide semiconductors and are connected to each other via leads, wherein all leads have the same lead width, through-hole layer, and through-hole number, and are made of the same type of metal; the left-right distance between the first MOS transistor and the fourth MOS transistor is equal to the left-right distance between the second MOS transistor and the third MOS transistor, and are symmetrical about the BB symmetry axis; the first MOS transistor and the fourth MOS transistor are symmetrical about the BB symmetry axis; The distance between the upper and lower parts of the two MOS transistors is equal to the distance between the upper and lower parts of the fourth MOS transistor and the third MOS transistor, and the two MOS transistors are symmetrical about the AA symmetry axis, and the AA symmetry axis is perpendicular to the BB symmetry axis. The gate of the first MOS transistor and the gate of the fourth MOS transistor are connected to serve as a first local oscillator port, and the gate of the second MOS transistor and the gate of the third MOS transistor are connected to serve as a second local oscillator port. The source of the first MOS transistor and the source of the second MOS transistor are connected to serve as a first RF input port, and the source of the third MOS transistor and the source of the fourth MOS transistor are connected to serve as a second RF input port. The drain of the first MOS transistor and the drain of the third MOS transistor are connected to serve as a first intermediate frequency output port, and the drain of the second MOS transistor and the drain of the fourth MOS transistor are connected to serve as a second intermediate frequency output port.

[0007] An embodiment of the present invention also provides an IQ double-balanced mixer layout structure, including: the mixer layout structure as described above is used as an I-channel mixer layout structure, the I-channel mixer layout structure and the Q-channel mixer layout structure are mirror-symmetrical about the DD symmetry axis; the lead of the RF input first port of the I-channel mixer layout structure is connected together with the lead of the RF input second port of the Q-channel mixer layout structure as the lead outlet of the RF input first port of the IQ double-balanced mixer layout structure; the lead of the RF input second port of the I-channel mixer layout structure is connected together with the lead of the RF input first port of the Q-channel mixer layout structure as the lead outlet of the RF input second port of the IQ double-balanced mixer layout structure; the outlets of all leads are symmetrical about the DD symmetry axis, the lead line width is consistent, and the same type of metal is used, and the through-hole level and number of through-holes are also consistent.

[0008] An embodiment of the present invention further provides an electronic device, comprising: a circuit having the mixer layout structure as described above; and / or a circuit having the IQ double-balanced mixer layout structure as described above.

[0009] To enhance the overall performance and reliability of the mixer, a rational layout and high symmetry between signal lines are crucial. In this embodiment of the present invention, four symmetrically arranged MOS transistors (M1, M2, M3, and M4) are symmetrically arranged along the AA and BB axes of symmetry. The gates of M1 and M4 are connected to form the first local oscillator port, while the gates of M2 and M3 are connected to the second local oscillator port. The sources of M1 and M2 are connected to the first RF input port via symmetrical leads, while the sources of M3 and M4 are connected to the second RF input port. The drains of M1 and M3 are connected to form the first intermediate frequency (IF) output port, while the drains of M2 and M4 are connected to form the second IF output port. All gate, source, and drain leads utilize the same high-layer, thick metal. The spacing between the MOS transistors is even, and the RF and IF lead layout eliminates phase errors. This effectively improves the mixer's signal processing capability and enhances system stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0011] Figure 1 It is a switch circuit layout structure in a traditional mixer; Figure 2 This is another conventional switch circuit layout structure in a mixer; Figure 3 A schematic diagram of metal layers and through holes provided in one embodiment of the present application; Figure 4 A layout structure of a mixer circuit provided in one embodiment of the present application; Figure 5 A circuit schematic diagram of a mixer with parasitic capacitance annotations provided in one embodiment of the present application; Figure 6 A layout structure of a mixer circuit with resistors provided in one embodiment of the present application; Figure 7 A circuit schematic diagram of a mixer with resistors and parasitic capacitances marked, provided in accordance with an embodiment of the present application; Figure 8 A layout structure of an IQ double-balanced mixer circuit provided in an embodiment of the present application; Figure 9 A circuit schematic diagram of an IQ double-balanced mixer provided in one embodiment of the present application; Figure 10 Two sets of schematic diagrams and layout structures of an IQ double-balanced mixer circuit provided in one embodiment of the present application; Figure 11 A layout structure of an IQ double-balanced mixer circuit with resistors provided in one embodiment of the present application; Figure 12 This is a circuit schematic diagram of an IQ double-balanced mixer with resistors provided in one embodiment of the present application. DETAILED DESCRIPTION

[0012] In the description of the embodiments of the present invention, technical terms such as "first" and "second" are used solely to distinguish between different objects and should not be understood to indicate or imply relative importance or to implicitly specify the quantity, specific order, or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present invention, "plurality" means more than two, unless otherwise specifically defined.

[0013] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0014] In the description of the embodiments of the present invention, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0015] In the description of the embodiments of the present invention, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0016] In the description of the embodiments of the present invention, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the embodiments of the present invention.

[0017] In the description of the embodiments of the present invention, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and can refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the embodiments of the present invention based on specific circumstances.

[0018] In the accompanying drawings corresponding to the embodiments of the present invention, the thickness and area of ​​layers are exaggerated for better understanding and ease of description. When a component (such as a layer, film, region, or substrate) is described as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. Conversely, when a component is described as being on the surface of another component, or as being formed or disposed on the surface of one component, it indicates that there is no third component between the two components. Furthermore, when a component is described as being "substantially" formed on another component, this means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0019] In the description of the embodiments of the present invention, when a component is referred to as "including" another component, unless otherwise specified, this does not exclude other components, and other components may further be included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them) or another component may be present between them. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, this means that no other components are present between them.

[0020] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and referenced to each other under the premise that there is no contradiction.

[0022] One embodiment of the present invention relates to a mixer layout structure comprising four symmetrically arranged MOS transistors (M1-M4), with a symmetrical layout achieved along the AA and BB axes of symmetry. The gates of M1 and M4 are connected to form the first local oscillator port, while the gates of M2 and M3 are connected to the second local oscillator port. The sources of M1 and M2 are connected to the first RF input port via symmetrical leads, while the sources of M3 and M4 are connected to the second RF input port. The drains of M1 and M3 are connected to form the first intermediate frequency (IF) output port, while the drains of M2 and M4 are connected to form the second IF output port. All gate, source, and drain leads utilize the same type of high-layer thick metal. The MOS transistors are evenly spaced, and the RF and IF lead layout eliminates phase errors. This effectively improves the mixer's signal processing capability and enhances system stability and reliability. The following details the implementation of the mixer layout structure of this embodiment. The following details are provided for ease of understanding and are not required for implementation.

[0023] The mixer layout structure of this embodiment includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. The first MOS transistor and the fourth MOS transistor are arranged in sequence in the first row, and the second MOS transistor and the third MOS transistor are arranged in sequence in the second row.

[0024] The first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all metal oxide semiconductors and are connected to each other through leads. The lead width, through hole layer and through hole number of all leads are equal and the same type of high-layer thick metal is used. In one example, the metal layer and through hole are as follows: Figure 3As shown, metal layer 1, metal layer 2, and metal layer 3 are all high-layer thick metals of the same type. The same type of high-layer thick metal refers to the same metal block resistance and the same metal overcurrent capability. This ensures that the parasitic impedance and parasitic capacitance of each trace and the overcurrent capability to each tube are completely consistent. In addition, the high-layer thick metal has extremely small parasitic resistance and large overcurrent capability. The use of high-layer thick metal greatly reduces the trace resistance of each line, which will increase the gain. This can greatly improve the differential of the mixer and obtain better local oscillator leakage suppression effect. Via 12 is a through hole between metal layer 1 and metal layer 2, used to connect metal layer 1 and metal layer 2. Via 23 is a through hole between metal layer 2 and metal layer 3, used to connect metal layer 2 and metal layer 3.

[0025] The left-right distance between the first MOS transistor and the fourth MOS transistor is equal to the left-right distance between the second MOS transistor and the third MOS transistor, and they are symmetrical about the BB symmetry axis; the top-bottom distance between the first MOS transistor and the second MOS transistor is equal to the top-bottom distance between the fourth MOS transistor and the third MOS transistor, and they are symmetrical about the AA symmetry axis, and the AA symmetry axis and the BB symmetry axis are perpendicular to each other; the gate of the first MOS transistor and the gate of the fourth MOS transistor are connected to serve as a first local oscillator port, and the gate of the second MOS transistor and the gate of the third MOS transistor are connected to serve as a second local oscillator port; the source of the first MOS transistor and the source of the second MOS transistor are connected to serve as a first RF input port, and the source of the third MOS transistor and the source of the fourth MOS transistor are connected to serve as a second RF input port; the drain of the first MOS transistor and the drain of the third MOS transistor are connected to serve as a first intermediate frequency output port, and the drain of the second MOS transistor and the drain of the fourth MOS transistor are connected to serve as a second intermediate frequency output port.

[0026] In an example, the mixer layout is as follows Figure 4 As shown, Figure 4 The circuit diagram of the mixer is as follows: Figure 5 As shown, Figure 4The implementation details of the mixer layout structure shown are provided for ease of understanding only and are not required for implementing this solution. In the figure, AA is the symmetry axis of the mixer circuit layout structure in the X direction (i.e., AA: symmetry axis x), and BB is the symmetry axis of the mixer circuit layout structure in the Y direction (i.e., BB: symmetry axis y). The mixer layout includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor (i.e., M1, M2, M3, and M4). The first row sequentially arranges the first and fourth MOS transistors, and the second row sequentially arranges the second and third MOS transistors. The four MOS transistors are arranged symmetrically. The left-right distance between the first and fourth MOS transistors is equal to the left-right distance between the second and third MOS transistors, and they are symmetrical about the symmetry axis BB. The top-bottom distance between the first and second MOS transistors is equal to the top-bottom distance between the fourth and third MOS transistors, and they are symmetrical about the symmetry axis AA. The two symmetry axes are perpendicular to each other. The first, second, third, and fourth MOS transistors can be composed of a single transistor or multiple transistors.

[0027] The gate of the first MOS transistor and the gate of the fourth MOS transistor are connected as the first local oscillator port, namely inp_lo; the gate of the second MOS transistor and the gate of the third MOS transistor are connected as the second local oscillator port, namely inn_lo; the source of the first MOS transistor and the source of the second MOS transistor are connected as the first RF input port, namely inn_rf; the source of the third MOS transistor and the source of the fourth MOS transistor are connected as the second RF input port, namely inp_rf; the drain of the first MOS transistor and the drain of the third MOS transistor are connected as the first intermediate frequency output port, namely outn_if; the drain of the second MOS transistor and the drain of the fourth MOS transistor are connected as the second intermediate frequency output port, namely outp_if.

[0028] In one example, the length of the lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor is equal to the length of the lead between the gate of the second MOS transistor and the gate of the third MOS transistor; the length of the lead between the source of the first MOS transistor and the source of the second MOS transistor is equal to the length of the lead between the source of the third MOS transistor and the source of the fourth MOS transistor; the length of the lead between the drain of the first MOS transistor and the drain of the third MOS transistor is equal to the length of the lead between the drain of the second MOS transistor and the drain of the fourth MOS transistor. The gate routing, source routing, and drain routing of each MOS transistor are strictly symmetrical. like Figure 4As shown, the gate of the first MOS tube and the gate of the fourth MOS tube are connected by metal layer 1, first connected to the center of the symmetry axis BB, and then led to both sides from the symmetry axis BB. The metal layer 1 is replaced with metal layer 2 using a through hole 12 for connection, and the wiring is routed left and right. The left wiring is routed to the top of the first MOS tube, then turns 45 degrees downward to the top of the symmetry axis AA, and is replaced with metal layer 1 using a through hole 12. The right wiring is routed to the top of the fourth MOS tube, then turns 45 degrees downward to the top of the symmetry axis AA, and is replaced with metal layer 1 using a through hole 12. At this point, the gate lead of the first MOS tube and the gate lead of the fourth MOS tube are completely symmetrical about the symmetry axis BB. The metal layer 1 is then used for horizontal routing, and finally the metal layer 2 is replaced for vertical downward connection as the lead of inp_lo. Similarly, the gate connection wires of the second MOS tube and the third MOS tube are first connected to the center of the BB symmetry axis, and then the wires are led outward from the BB symmetry axis. The metal layer 1 is replaced with the metal layer 2 using the through hole 12 for connection, and the wires are routed left and right. The left wire is routed to the bottom of the second MOS tube, then turns 45 degrees upward to below the symmetry axis AA, and is replaced with the metal layer 1 using the through hole 12. The right wire is routed to the bottom of the third MOS tube, then turns 45 degrees upward to below the symmetry axis AA, and is replaced with the metal layer 1 using the through hole 12. At this point, the gate leads of the second MOS tube and the gate leads of the third MOS tube are completely symmetrical about the BB symmetry axis. The wires are then routed horizontally using the metal layer 1, and finally the metal layer 2 is replaced to connect vertically downward as the lead opening of inn_lo. The two leads inp_lo and inn_lo have the same overall length, consistent line width, and consistent spacing from their respective MOS tubes to the end of the leads. In addition, the two leads are completely symmetrical about the AA symmetry axis, both use high-layer thick metal, and the through-hole level and number are consistent. The overall environment is completely consistent, which ensures the same parasitic resistance and parasitic capacitance, and improves the performance and stability of the circuit.

[0029] The source of the first MOS tube and the source of the second MOS tube are first connected to the center of the AA symmetry axis using the metal layer 3. Then, from the AA symmetry axis, the metal layer 1 and the through hole 12 and the through hole 23 are superimposed and wired vertically to the upper and lower sides respectively. The lower lead is connected to the lower boundary of the second MOS tube horizontal metal layer 2, and the upper lead is connected to the upper boundary of the first MOS tube horizontal metal layer 2. Then, the lead is continued upward and the metal layer 2 and the through hole 12 are changed to be wired horizontally. Then, the metal layer 2 is used for wiring horizontally, and then the line is turned 45 degrees upward to a certain distance and then wired horizontally. This serves as the inn_rf lead outlet. Similarly, the source of the third MOS tube and the first The sources of the four MOS transistors are similarly connected to the center of the AA symmetry axis using metal layer 3. From the AA symmetry axis, metal layer 1, through-hole 12, and through-hole 23 are stacked and wired vertically to the upper and lower sides. The wires are then routed upwards, followed by switching to metal layer 2 and through-hole 12 for horizontal routing. The lower wire is routed to the lower boundary of the third MOS transistor's horizontal metal layer 2, and the upper wire is routed to the upper boundary of the fourth MOS transistor's horizontal metal layer 2. The wires are then routed horizontally using metal layer 2. The wires then turn 45 degrees upward, switching to metal layer 1 and through-hole 12 for a distance, and then switching to metal layer 2 and through-hole 12 again for routing. This serves as the inp_rf wire outlet. Moreover, from the MOS tube to the end of the lead, all metal layers have the same width and spacing, which ensures the same parasitic resistance and parasitic capacitance, thereby suppressing local oscillator (LO) leakage, improving phase asymmetry, reducing offset voltage, improving signal integrity, optimizing frequency response, improving noise performance, enhancing linearity and overall stability, and improving circuit performance and stability.

[0030] The drain of the first MOS tube is connected to the drain of the third MOS tube. First, it is connected horizontally from the first MOS tube to the right side of the tube, then the 45-degree bend is connected vertically downward, and then the 45-degree bend is made to the left side of the third MOS tube. After the line is routed downward again, the 45-degree bend is made to enter the drain of the third MOS tube. Then, a 45-degree bend is made with the metal layer 1 at the center of the symmetry axis AA and the symmetry axis BB. After the line is turned to the lower left, the line is led vertically downward to the bottom. The metal layer 1 is connected to the metal layer 3 through the through hole 12 and the through hole 23, thus forming outn_if. Similarly, the drain of the second MOS tube is connected horizontally from the second MOS tube to the drain of the fourth MOS tube. On the right side of the tube, a 45-degree bend is made to connect vertically upwards, and metal layer 1 is replaced with metal layer 2 through through-hole 12. Then, a 45-degree bend is made to the left side of the fourth MOS tube. After routing upwards again, metal layer 2 is replaced with metal layer 1 through through-hole 12. The 45-degree bend enters the drain of the fourth MOS tube. Then, a 45-degree bend is made with metal layer 2 at the center of the symmetry axis AA and the symmetry axis BB. After turning to the lower right, the wire is led vertically downwards to the bottom. Metal layer 2 is connected to metal layer 3 through through-hole 12 and through-hole 23. In order to have the same parasitic resistance and parasitic capacitance values ​​as the lead outn_if, a through-hole 12 is also placed here, thus forming outp_if. outn_if and outp_if are completely symmetrical about the symmetry axis BB, and the overlapping area of ​​the two leads is symmetrical about the symmetry axis BB. The drain traces use the same type of high-layer thick metal, and the metal layer width and spacing are consistent from the exit of each MOS tube to the end of the lead. This ensures the same parasitic resistance and parasitic capacitance, thereby suppressing LO leakage, improving phase asymmetry, reducing offset voltage, improving signal integrity, optimizing frequency response, improving noise performance, enhancing linearity, and enhancing overall stability, thereby improving circuit performance and stability.

[0031] In an example, the lead from the gate of the first MOS transistor to the first port of the local oscillator, the lead from the gate of the second MOS transistor to the second port of the local oscillator, the lead from the gate of the third MOS transistor to the second port of the local oscillator, and the lead from the gate of the fourth MOS transistor to the first port of the local oscillator have equal lengths, equal widths, and consistent routing levels.

[0032] Because the lead from the gate of the first MOS tube to inp_lo, the lead from the gate of the second MOS tube to inn_lo, the lead from the gate of the third MOS tube to inn_lo, and the lead from the gate of the fourth MOS tube to inp_lo, these four leads are exactly the same in length, width, and routing level. Figure 4Therefore, for the parasitic capacitance C1 generated between the gate of the first MOS tube and the lead inn_rf, the parasitic capacitance C2 generated between the gate of the second MOS tube and the lead inn_rf, the parasitic capacitance C3 generated between the gate of the third MOS tube and the lead inp_rf, and the parasitic capacitance C4 generated between the gate of the fourth MOS tube and the lead inp_rf, as shown in FIG. Figure 5 As shown in FIG, the values ​​of the four parasitic capacitors C1, C2, C3, and C4 are completely consistent, thereby suppressing LO leakage, improving phase asymmetry, reducing offset voltage, improving signal integrity, optimizing frequency response, improving noise performance, enhancing linearity, and improving overall stability.

[0033] In one example, the first, second, third, and fourth MOS transistors are each placed in their own deep N-well (DNW), with the same distance between them. Specifically, the first, second, third, and fourth MOS transistors are each placed in their own deep N-well (DNW), with the same distance between them. This not only ensures a consistent surrounding environment, but also provides good isolation and significantly improves heat dissipation.

[0034] In one example, all leads are located outside the MOS transistor, with no metal laminated on the metal electronic device. This significantly reduces the parasitic capacitance of the metal layer to the MOS transistor, making the simulation model more accurate. The first, second, third, and fourth MOS transistors all have identical circuit structures.

[0035] In one example, the mixer layout structure further includes: a resistor array R1 and a resistor array R2; the sources of the first MOS transistor and the second MOS transistor first pass through the resistor array R1 and then are connected to the first RF input port, and the sources of the third MOS transistor and the fourth MOS transistor first pass through the resistor array R2 and then are connected to the second RF input port. Figure 6 As shown, a layout structure of a mixer circuit with resistors provided in an embodiment of the present application is shown. Figure 6 The circuit schematic diagram of the mixer with parasitic capacitance annotation is as follows Figure 7 As shown ( Figure 7 The meaning of the symbols in Figure 6 to be consistent), Figure 6 The source electrodes of the first and second MOS tubes first pass through the resistor array R1 and then lead to inn_rf. The source electrodes of the third and fourth MOS tubes first pass through the resistor array R2 and then lead to inp_rf. The rest of the leads and other parts are connected to Figure 4The embodiments are completely consistent and will not be described in detail.

[0036] In this embodiment, four symmetrically arranged MOS transistors (M1-M4) are symmetrically arranged along the symmetry axis AA (symmetry axis x) and the symmetry axis BB (symmetry axis y). The gates of M1 and M4 are connected to the first local oscillator port, while the gates of M2 and M3 are connected to the second local oscillator port. The sources of M1 and M2 are connected to the first RF input port via symmetrical traces, while the sources of M3 and M4 are connected to the second RF input port. The drains are cross-connected to form differential IF output ports 1 and 2. All gate, source, and drain traces utilize the same high-layer thick metal layer, with trace lengths, widths, and parasitic parameters strictly matched. The MOS transistors are evenly spaced, and the RF and IF traces are arranged to eliminate phase errors. This effectively improves the mixer's signal processing capability and enhances system stability and reliability.

[0037] Another embodiment of the present invention relates to an IQ double-balanced mixer layout structure, comprising: the mixer layout structure of the above embodiment serving as an I-channel mixer layout structure, the I-channel mixer layout structure and the Q-channel mixer layout structure being mirror-symmetrical about a DD axis of symmetry; a lead of a first RF input port of the I-channel mixer layout structure and a lead of a second RF input port of the Q-channel mixer layout structure being connected together to serve as a lead outlet of the first RF input port of the IQ double-balanced mixer layout structure; a lead of a second RF input port of the I-channel mixer layout structure and a lead of a first RF input port of the Q-channel mixer layout structure being connected together to serve as a lead outlet of the second RF input port of the IQ double-balanced mixer layout structure; all lead outlets being symmetrical about the DD axis of symmetry, having a uniform lead width, using the same type of high-layer thick metal, and having a uniform through-hole hierarchy and number.

[0038] The following is a detailed description of the implementation details of the IQ double-balanced mixer layout structure of this embodiment. Figure 8 The content shown is only implementation details provided to facilitate understanding and is not required to implement this solution. Figure 8 A layout structure of an IQ double-balanced mixer circuit provided according to an embodiment of the present application is provided. Figure 9 for Figure 8 A circuit schematic diagram of an IQ double-balanced mixer corresponding to the layout structure shown. Figure 8 and Figure 9 The symbols have the same meaning. Figure 8 CC is the symmetry axis in the X direction of the layout structure of the IQ double balanced mixer circuit (i.e. CC: symmetry axis x), and DD is the symmetry axis in the Y direction of the layout structure of the IQ double balanced mixer circuit (i.e. DD: symmetry axis x). Figure 8 As shown in the figure, there are 8 MOS tubes (M1, M2, M3, M4, M5, M6, M7, M8). The left side of the symmetry axis DD is the I-channel mixer layout structure, and the right side is the Q-channel mixer layout structure. The I-channel and Q-channel are symmetrical about the symmetry axis DD. M1, M2, M3, and M4 belong to the I-channel mixer layout structure, and M5, M6, M7, and M8 belong to the Q-channel mixer layout structure. The gate of M1 is connected to the lead of inp_lo_I, and M The gate of M2 connects to the inn_lo_I lead, the gate of M3 connects to the inn_lo_I lead, the gate of M4 connects to the inp_lo_I lead; the gate of M5 connects to the inp_lo_Q lead, the gate of M6 connects to the inn_lo_Q lead, the gate of M7 connects to the inn_lo_Q lead, and the gate of M8 connects to the inp_lo_Q lead. These eight leads are of equal length, width, and routing hierarchy. The internal inn_rf lead of the left I channel is connected together with the internal inp_rf lead of the right Q channel to form the inn_rf lead outlet of the IQ double-balanced mixer. The internal inp_rf lead of the left I channel is connected together with the internal inn_rf lead of the right Q channel to form the inp_rf lead outlet of the IQ double-balanced mixer. The lead outlets are symmetrical about the DD axis of symmetry, have consistent width, use the same type of high-layer thick metal, and have the same via hierarchy and number. The spacing between the leads inn_rf and inp_rf in the IQ double-balanced mixer circuit layout and the internal leads of the I and Q paths is also consistent, and the surrounding environment is completely consistent, thus ensuring the same parasitic resistance and parasitic capacitance.

[0039] In one example, the center portions of the two leads of the RF input first port of the IQ double-balanced mixer layout structure and the RF input second port of the IQ double-balanced mixer layout structure are cross-placed and symmetrically located on the DD symmetry axis. Figure 8 As shown, the center parts of the two leads inn_rf and inp_rf are placed crosswise and symmetrically about the DD symmetry axis, ensuring that the parasitic capacitances of the two leads to the substrate are consistent.

[0040] In one example, the two schematic layout structures of the IQ double-balanced mixer circuit are as follows: Figure 10 As shown, it includes two groups, a first group and a second group. The first group includes the first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube. The second group includes the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, and the eighth MOS tube. The first row of the first group includes the first MOS tube and the fourth MOS tube from left to right, and the second row includes the second MOS tube and the third MOS tube. The first row of the second group includes the eighth MOS tube and the fifth MOS tube from left to right, and the second row includes the seventh MOS tube and the sixth MOS tube. The two groups of layout structures are symmetrical with each other about the symmetry axis in the middle.

[0041] In one example, the mixer layout structure further includes: a resistor array R1, a resistor array R2, a resistor array R3, and a resistor array R4; a lead of a first RF input port of the IQ double-balanced mixer layout structure first passes through the resistor array R1, and then is connected together with a lead of a second RF input port of the IQ double-balanced mixer layout structure that first passes through the resistor array R4, serving as a lead outlet of the first RF input port of the IQ double-balanced mixer layout structure; a lead of a second RF input port of the IQ double-balanced mixer layout structure first passes through the resistor array R2, and then is connected together with a lead of a first RF input port of the IQ double-balanced mixer layout structure that first passes through the resistor array R3, serving as a lead outlet of the second RF input port of the IQ double-balanced mixer layout structure.

[0042] like Figure 11 A layout structure of an IQ double-balanced mixer circuit with resistors provided in an embodiment of the present application, Figure 12 for Figure 11 The circuit schematic diagram of the IQ double-balanced mixer with a layout structure and resistors. Figure 11 and Figure 12 The symbols have exactly the same meaning. Figure 11 The port and parasitic capacitance are Figure 8 The leads are completely consistent, that is, M1, M2, M3, and M4 belong to the I-channel mixer layout structure, and M5, M6, M7, and M8 belong to the Q-channel mixer layout structure; the gate of M1 is to the lead of inp_lo_I, the gate of M2 is to the lead of inn_lo_I, the gate of M3 is to the lead of inn_lo_I, and the gate of M4 is to the lead of inp_lo_I; the gate of M5 is to the lead of inp_lo_Q, the gate of M6 is to the lead of inn_lo_Q, the gate of M7 is to the lead of inn_lo_Q, and the gate of M8 is to the lead of inp_lo_Q; ​​these eight leads are completely equal in length, consistent in width, and consistent in routing levels. The internal inn_rf lead of the left I circuit and the internal inp_rf lead of the right Q circuit are connected together to form the inn_rf lead outlet of the IQ double-balanced mixer. The internal inp_rf lead of the left I circuit and the internal inn_rf lead of the right Q circuit are connected together to form the inp_rf lead outlet of the IQ double-balanced mixer. The lead outlets are symmetrical about the DD axis of symmetry. The entire lead width is consistent, and the same type of high-layer thick metal is used. The via level and number are also consistent. The inn_rf and inp_rf leads in the IQ double-balanced mixer circuit layout are also spaced the same as the internal leads of the I and Q circuits, and the surrounding environment is completely consistent. Resistor arrays R1, R2, R3, and R4 are also positioned accordingly as shown in the figure and will not be further described here.

[0043] In this embodiment, four symmetrically arranged MOS transistors are symmetrically arranged along the AA and BB axes of symmetry. The gates of M1 and M4 are connected to the first local oscillator port, while the gates of M2 and M3 are connected to the second local oscillator port. The sources of M1 and M2 are connected to the first RF input port via symmetrical leads, while the sources of M3 and M4 are connected to the second RF input port. The drains are cross-connected to form the first and second differential IF output ports. All gate, source, and drain leads utilize the same high-layer thick metal layer, with trace lengths, widths, and parasitic parameters strictly matched. The MOS transistors are evenly spaced, and the RF and IF lead layout eliminates phase errors. This effectively improves the mixer's signal processing capability and enhances system stability and reliability.

[0044] The above structural division is only for the purpose of clear description. During implementation, they can be merged into one structure or some structures can be split and decomposed into multiple structures. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0045] The present invention is not limited to being applied to the layout structure of a mixer, but can also be applied to other circuits.

[0046] The layout structure provided by the present invention exhibits superior linearity performance and is not limited to mixer layouts; it can also be applied to other circuits. In the present invention, equality is not limited to complete equality; rather, a certain degree of deviation is permitted. One objective of the present invention is to ensure that the lengths of the gate traces of each MOS transistor are as equal as possible, without requiring that the lengths of the gate traces of each MOS transistor be completely identical.

[0047] It is worth noting that all modules involved in this embodiment are logical modules. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovations of the present invention, this embodiment does not include units that are not closely related to solving the technical problems proposed by the present invention. However, this does not mean that other units do not exist in this embodiment.

[0048] Another embodiment of the present invention relates to an electronic device, including a circuit having the mixer layout structure described in the above embodiment; and / or a circuit having the IQ double-balanced mixer layout structure described in the above embodiment.

[0049] The electronic device can be applied to wireless communication systems and radar systems, and can be a spectrum monitoring device or a satellite communication terminal.

[0050] For example, when applied to wireless communication systems, mixers can be used to implement carrier modulation and demodulation in Orthogonal Frequency Division Multiplexing (OFDM) systems. In millimeter-wave radars (such as vehicle-mounted radars and drone obstacle avoidance radars), mixers are used to convert echo signals into intermediate frequencies, combined with fast Fourier transform (FFT) processing to detect target distance and speed. When scanning and analyzing wide-band signals, mixers are used for frequency shifting to facilitate sampling and digital processing by the back-end analog-to-digital converter (ADC). In low-noise block downconverters, satellite band signals are down-converted, etc.

[0051] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above and will not be repeated here.

[0052] While the basic concepts have been described above, it will be apparent to those skilled in the art that the detailed disclosure herein is merely illustrative and does not constitute a limitation of the present disclosure. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and revisions to the present disclosure. Such modifications, improvements, and revisions are suggested in the present disclosure and remain within the spirit and scope of the exemplary embodiments of the present disclosure.

[0053] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A mixer layout structure, characterized in that: include: a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein the first MOS transistor and the fourth MOS transistor are sequentially arranged in a first row, and the second MOS transistor and the third MOS transistor are sequentially arranged in a second row; The first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all metal oxide semiconductors and are connected to each other through leads. The lead width, through-hole layer, and through-hole number of all leads are equal and made of the same type of metal; The left-right distance between the first MOS transistor and the fourth MOS transistor is equal to the left-right distance between the second MOS transistor and the third MOS transistor, and the two transistors are symmetrical about the BB symmetry axis; The distance between the first MOS transistor and the second MOS transistor is equal to the distance between the fourth MOS transistor and the third MOS transistor, and the transistors are symmetrical about the AA symmetry axis, and the AA symmetry axis is perpendicular to the BB symmetry axis. The gate of the first MOS transistor and the gate of the fourth MOS transistor are connected as a first local oscillator port, and the gate of the second MOS transistor and the gate of the third MOS transistor are connected as a second local oscillator port; The source of the first MOS transistor and the source of the second MOS transistor are connected as a first RF input port, and the source of the third MOS transistor and the source of the fourth MOS transistor are connected as a second RF input port; The drain of the first MOS transistor and the drain of the third MOS transistor are connected as a first intermediate frequency output port, and the drain of the second MOS transistor and the drain of the fourth MOS transistor are connected as a second intermediate frequency output port.

2. The mixer layout structure according to claim 1, wherein: The length of the lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor is equal to the length of the lead between the gate of the second MOS transistor and the gate of the third MOS transistor; The length of the lead between the source of the first MOS transistor and the source of the second MOS transistor is equal to the length of the lead between the source of the third MOS transistor and the source of the fourth MOS transistor; The length of the lead between the drain of the first MOS transistor and the drain of the third MOS transistor is equal to the length of the lead between the drain of the second MOS transistor and the drain of the fourth MOS transistor.

3. The mixer layout structure according to claim 1, wherein: The lead from the gate of the first MOS transistor to the first port of the local oscillator, the lead from the gate of the second MOS transistor to the second port of the local oscillator, the lead from the gate of the third MOS transistor to the second port of the local oscillator, and the lead from the gate of the fourth MOS transistor to the first port of the local oscillator have the same length, the same width, and the same routing levels.

4. The mixer layout structure according to claim 1, wherein: The first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are respectively placed in their own deep N wells, and are at the same distance from each other.

5. The mixer layout structure according to claim 1, wherein: All leads are located outside the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor, and no metal is laminated on the metal electronic components.

6. The mixer layout structure according to claim 1, wherein: The mixer layout structure further includes: a resistor array R1 and a resistor array R2; The sources of the first MOS transistor and the second MOS transistor first pass through the resistor array R1 and then are connected to the first RF input port, and the sources of the third MOS transistor and the fourth MOS transistor first pass through the resistor array R2 and then are connected to the second RF input port.

7. An IQ double-balanced mixer layout structure, characterized in that: include: The mixer layout structure according to any one of claims 1 to 5 is used as an I-channel mixer layout structure, wherein the I-channel mixer layout structure and the Q-channel mixer layout structure are mirror-symmetrical about the DD symmetry axis; The lead of the RF input first port of the I-channel mixer layout structure and the lead of the RF input second port of the Q-channel mixer layout structure are connected together as the lead outlet of the RF input first port of the IQ double-balanced mixer layout structure; The lead of the second RF input port of the I-channel mixer layout structure and the lead of the first RF input port of the Q-channel mixer layout structure are connected together as the lead outlet of the second RF input port of the IQ double-balanced mixer layout structure; The outlets of all leads are symmetrical about the DD symmetry axis, the lead width is consistent, and the same type of metal is used, and the through-hole level and number of through-holes are also consistent.

8. The IQ double-balanced mixer layout structure according to claim 7, wherein: The center parts of two leads of the RF input first port of the IQ double-balanced mixer layout structure and the RF input second port of the IQ double-balanced mixer layout structure are cross-placed and symmetrical about the DD symmetry axis.

9. The IQ double-balanced mixer layout structure according to claim 7, wherein: The IQ double-balanced mixer layout structure further includes: a resistor array R1, a resistor array R2, a resistor array R3, and a resistor array R4; The lead of the RF input first port of the IQ double-balanced mixer layout structure first passes through the resistor array R1, and then is connected together with the lead of the RF input second port of the IQ double-balanced mixer layout structure that first passes through the resistor array R4, serving as the lead outlet of the RF input first port of the IQ double-balanced mixer layout structure; The lead of the second RF input port of the IQ double-balanced mixer layout structure first passes through the resistor array R2, and then is connected together with the lead of the first RF input port of the IQ double-balanced mixer layout structure that first passes through the resistor array R3, serving as the lead outlet of the second RF input port of the IQ double-balanced mixer layout structure.

10. An electronic device, characterized in that: include: A circuit having a mixer layout structure according to any one of claims 1 to 6; and / or, A circuit having an IQ double-balanced mixer layout structure according to any one of claims 7 to 9.

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