Clock-buffer bidirectional linkage adjusting method and device for voice gateway

Abstract

The invention relates to the technical field of voice communication, and discloses a clock-buffer bidirectional linkage adjustment method and device for a voice gateway, and the method comprises the steps: obtaining a clock frequency error, and carrying out the compensation of a jitter buffer initial depth according to the clock frequency error, and obtaining a jitter buffer target depth; the jitter cache initial depth is a dynamic initial depth at the current moment determined based on a prediction model; based on the original depth of the jitter cache and the target depth of the jitter cache, determining a depth change rate corresponding to the jitter cache; and determining a dynamic gain of a clock phase-locked loop based on the depth change rate, and updating a clock signal according to the dynamic gain, thereby effectively improving the accuracy and reliability of voice playing by the voice gateway through clock-buffer bidirectional linkage adjustment.

Description

Technical Field

[0001] The present disclosure generally relates to the field of voice communication technology, and in particular to a clock-buffer bidirectional linkage adjustment method and device for a voice gateway. Background Art

[0002] A voice gateway is a VoIP (Voice over IP) / FoIP (Fax over IP) media access gateway used in Next Generation Network (NGN) or IP Multimedia Subsystem (IMS) networks. In NGN and IMS network architectures, voice and data services are transmitted over IP networks. A voice gateway converts analog voice data into IP data, enabling traditional analog telephone equipment to connect to modern IP networks, thus achieving IP-based voice communications.

[0003] In IP networks, real-time voice data is transmitted via RTP (Realtime Transport Protocol) encapsulated within UDP (User Datagram Protocol) packets. Using UDP to transmit data can lead to packet out-of-order and duplicate packets. To ensure efficient voice transmission over data networks and maintain call quality, factors such as network latency, jitter, packet loss, out-of-order packets, and duplicate packets must be considered.

[0004] Network jitter refers to latency variation. In VoIP applications, the DSP (digital signal processing) of the sending gateway sends compressed and encoded voice packets at uniform intervals. After traversing the IP network, these packets experience jitter. By the time they reach the receiving gateway, the intervals between adjacent voice packets have changed and are no longer the same as when they were sent. If the receiving gateway plays these jittered packets directly, the receiving user will hear something different from what the sender said, affecting the quality of voice communication.

[0005] Currently, the solution to this type of network jitter is to add a jitter buffer (JB) to the receiving gateway. This mechanism caches received voice packets for a certain period of time, allowing the receiving gateway to play them back at the same intervals as when they were sent. This adds a certain delay at the receiving end, thus eliminating the jitter problem caused by the IP network.

[0006] The JB depth is the difference between the time the first packet arrives at the JB queue and the time the packet is played (i.e., leaves the JB queue). Once the play time of the first packet is determined, the play time of subsequent packets is also determined. Therefore, the JB depth is used to describe the initial delay generated by the JB queue.

[0007] Traditional solutions for jitter problems rely primarily on static JB mechanisms. Static JB mechanisms maintain a constant JB depth throughout the entire voice playback process. However, because voice packet latency in IP networks varies with network conditions, static JB solutions with fixed JB depths do not effectively mitigate jitter.

[0008] Based on this, related technologies propose to accurately reflect the current network status by calculating the average network delay and jitter in real time, and adjust the JB depth in real time based on the changing average delay and jitter conditions in the network. However, dynamic adjustment of the JB depth can cause clock frequency fluctuations, resulting in abnormal voice playback. Summary of the Invention

[0009] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a clock-buffer bidirectional linkage adjustment method and device for a voice gateway, which can effectively improve the accuracy and reliability of voice playback of the voice gateway through clock-buffer bidirectional linkage adjustment.

[0010] In a first aspect, an embodiment of the present application provides a clock-buffer bidirectional linkage adjustment method for a voice gateway, comprising: Acquiring a clock frequency error and compensating an initial depth of the jitter buffer according to the clock frequency error to obtain a target jitter buffer depth; the initial depth of the jitter buffer is a dynamic initial depth at a current moment determined based on a prediction model; Determining a depth change rate corresponding to the jitter buffer based on the jitter buffer original depth and the jitter buffer target depth; A dynamic gain of a clock phase-locked loop is determined based on the depth change rate, and a clock signal is updated according to the dynamic gain.

[0011] In some embodiments, obtaining a clock frequency error and compensating an initial jitter buffer depth according to the clock frequency error includes: Obtaining the clock frequency error and the nominal sampling rate, and determining a frequency compensation coefficient; The initial jitter buffer depth is compensated based on the frequency compensation coefficient to obtain the jitter buffer target depth.

[0012] In some embodiments, when the voice gateway adopts satellite communication, the method further includes: Predict the Doppler frequency shift and Doppler dynamic compensation factor caused by satellite switching; Obtaining a Doppler dynamic compensation coefficient according to the Doppler frequency shift amount and the Doppler dynamic compensation factor; The initial jitter buffer depth is compensated according to the Doppler dynamic compensation coefficient to obtain a jitter buffer target depth.

[0013] In some embodiments, before determining the dynamic initial depth at the current moment based on the prediction model, the method further includes: Predicting a switching warning time and a current time of satellite switching according to the satellite ephemeris, and determining a switching growth factor according to the switching warning time and the current time; The initial depth of the jitter buffer is determined according to the switching growth factor and the original depth of the jitter buffer.

[0014] In some embodiments, before determining the depth change rate corresponding to the jitter buffer based on the jitter buffer original depth and the jitter buffer target depth, the method further includes: Obtaining a compensated jitter buffer target depth requirement value and resource data corresponding to the voice gateway terminal, the resource data including at least available memory, utilization factor, encoding bit rate, and frame duration; Determining a jitter buffer target depth constraint value based on the resource data; The jitter buffer target depth for calculating the depth change rate is determined according to the jitter buffer target depth requirement value and the jitter buffer target depth constraint value.

[0015] In some embodiments, determining a dynamic gain of a clock phase-locked loop based on the depth change rate includes: A dynamic proportional gain and a dynamic integral gain corresponding to the clock phase-locked loop are determined according to the depth change rate.

[0016] In a second aspect, an embodiment of the present application provides a clock-buffer bidirectional linkage adjustment device for a voice gateway, comprising: a depth compensation module, configured to obtain a clock frequency error and compensate an initial depth of the jitter buffer according to the clock frequency error to obtain a target jitter buffer depth; the initial depth of the jitter buffer being a dynamic initial depth at a current moment determined based on a prediction model; A determination module, configured to determine a depth change rate corresponding to the jitter buffer based on an original depth of the jitter buffer and a target depth of the jitter buffer; A clock update module is used to determine a dynamic gain of a clock phase-locked loop based on the depth change rate, and update a clock signal according to the dynamic gain.

[0017] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method described in the embodiment of the present application when executing the program.

[0018] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, which, when executed by a processor, implements the method described in the embodiment of the present application.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, it implements the method described in the embodiment of the present application.

[0020] The clock-buffer bidirectional linkage adjustment method and device for a voice gateway, proposed in the embodiments of this application, utilizes clock frequency error-buffer compensation and buffer compensation-clock dynamic gain compensation to accurately and reliably adjust the jitter buffer depth of the voice gateway, adapting to dynamic delay changes and improving voice playback accuracy. Furthermore, by dynamically adjusting the dynamic gain of the clock phase-locked loop (PLL) based on the depth change rate, the reliability of clock operation is guaranteed. When the jitter buffer depth fluctuates frequently or dramatically, the clock signal converges as quickly as possible, further ensuring the accuracy and reliability of voice playback.

[0021] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 The following is an architecture diagram of an implementation environment for a clock-buffer bidirectional linkage adjustment method for a voice gateway provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a receiving gateway provided in an embodiment of the present application is shown; Figure 3 A flow chart of a clock-buffer bidirectional linkage adjustment method for a voice gateway provided by an embodiment of the present application is shown; Figure 4 A schematic diagram of the structure of a clock-buffer bidirectional linkage adjustment device for a voice gateway provided in one embodiment of the present application is shown; Figure 5 A schematic diagram of the structure of a computer system of an electronic device or server suitable for implementing an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0024] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] With the rapid development of communications technology, Integrated Access Devices (IADs), key equipment for integrating voice communications with the internet, have been widely used in enterprise communications, IP telephony, call centers, and other fields. In today's highly valued information security environment, various industries are increasingly demanding the domestication of communications equipment, requiring independent control of core components, operating systems, and software to ensure communication security.

[0026] Existing voice gateway technical solutions lack functional integration, compatibility, and scalability. Regarding functional integration, some devices' voice processing and network adaptation modules are relatively independent and lack efficient collaboration, resulting in low signal transmission efficiency and large processing delays. Furthermore, when connecting to communication terminals and network equipment of different brands, protocol incompatibility and data exchange anomalies are prone to occur. Regarding scalability, when an enterprise's business scale expands and requires the addition of new features or the integration of more devices, existing technical solutions struggle to rapidly implement functional expansion, often requiring large-scale equipment modification or even replacement, increasing the enterprise's operating costs and technical risks.

[0027] Some voice gateways have numerous issues with voice playback quality. Voice quality is unstable, and in complex network environments or with high call concurrency, voice loss, distortion, and disconnection are common. Voice storage management capabilities are weak, lacking efficient storage strategies and retrieval mechanisms. When voice data volumes are large, finding and retrieving specific voice files is time-consuming and labor-intensive, making it difficult to meet actual business needs.

[0028] The specific implementation environment of the clock-buffer bidirectional linkage adjustment method for voice gateway proposed in this application can be found in Figure 1 . Figure 1 The following is a diagram showing the implementation environment architecture of the clock-buffer bidirectional linkage adjustment method for a voice gateway provided in an embodiment of the present application.

[0029] like Figure 1 As shown, the implementation environment architecture includes: a voice sending device 101, a sending gateway 102, a satellite network 103, a receiving gateway 104 and a voice receiving device 105.

[0030] Voice sending device 101 is used to receive voice signals from the voice sending user and convert the voice signals into analog voice signals. Sending gateway 102 is used to encode and compress the analog voice signals and transmit the encoded and compressed voice packets to receiving gateway 104 via satellite network 103. Receiving gateway 104 is used to store and play the received voice packets, and when playing the received voice packets, it is also used to reduce the abnormality of the voice listener's voice perception.

[0031] In the embodiments of this application, Figure 2 As shown, the receiving gateway 104 includes a chip module, an FPGA module, an external interface module, a serial port module, a storage module, an analog signal processing module and a network interface module.

[0032] The chip module utilizes a domestically produced multi-core processor (such as the GigaDevice GD32F470 series or the HiSilicon Hi3516DV300) featuring an integrated ARM Cortex-M7 core with a clock speed of ≥400MHz, 2MB of Flash memory, and 512KB of SRAM. The chip is soldered to the center of the motherboard in a 40-pin LGA package. Eight 10μF tantalum capacitors are located around the module for power filtering and stable power supply. Two PCIe 2.0 interfaces (500MB / s per channel) connect the FPGA and network control module, respectively. A 4-channel SPI interface (up to 50MHz) controls the ADC conversion of the domestically produced analog module. An integrated SDIO 3.0 controller supports high-speed TF card read / write (up to 50MB / s). This interface also features a dedicated voice data transmission channel, allowing it to operate independently from other data transmissions to avoid interference.

[0033] The FPGA module uses the domestically produced Unisplendour Tongchuang PGT280H FPGA chip, manufactured using a 28nm process. It features ≥280K logic cells and 16 built-in hard-core DSP modules. The chip is soldered to the upper left corner of the motherboard via a BGA package, ≤2cm from the main control chip. 200-pin high-speed differential traces (controlled impedance of 50Ω) are used to minimize signal latency. A 125MHz differential crystal oscillator (accuracy ±50ppm) provides the reference clock for timing control. The crystal is shielded by a metal cover to isolate it from electromagnetic interference.

[0034] The analog signal processing module utilizes a three-stage signal processing architecture, consisting of a front-end amplifier, a filter, and an ADC conversion stage. The front-end amplifier uses a domestic Shengbang Microelectronics SGM8552 operational amplifier, with a gain of 20dB and an input impedance ≥1MΩ, matching the 600Ω characteristic impedance of a telephone line. The filter stage utilizes a fourth-order Butterworth low-pass filter (cutoff frequency 3.4kHz) and uses domestic Fenghua High-Tech 0603 packaged inductors and capacitors with ripple suppression ≥40dB. The ADC conversion stage features a domestic Xinhai Technology CS5368 16-bit ADC with an 8kHz sampling rate and a signal-to-noise ratio (SNR) ≥90dB. Digital signals are transmitted to the FPGA via an SPI interface (clock frequency 2MHz).

[0035] The voice conversion process involves an analog telephone signal (-10dBm to +2.0dBm) input via an RJ11 connector, first clamped by an ESD protection diode (SMBJ6.0CA), and then DC-blocked by an RC coupling circuit (R = 470Ω, C = 10μF). The amplified and filtered signal is then fed into the ADC, where it is sampled and quantized under the FPGA's voice timing control. The resulting PCM-encoded output (A-law format) is transmitted to the FPGA via an 8-bit parallel bus (data rate 128kbps). In voice mode, the ADC sampling frequency and quantization accuracy are dynamically adjusted based on instructions from the main control chip to meet varying voice quality requirements.

[0036] The memory module uses a sunken TF card holder, soldered to the lower right corner of the motherboard. It connects to the main control chip's SDIO interface via a five-wire connection (CLK, CMD, D0-D2). The trace length is ≤3cm, and a 10Ω matching resistor is connected in series to eliminate signal reflections. A 100nF ceramic capacitor (0603 package) is placed next to the card holder for power supply decoupling. The operating voltage is 3.3V ±5%.

[0037] The network interface module uses the domestically produced Yutai Microelectronics YT8521 Gigabit Ethernet controller, supporting 10 / 100 / 1000Mbps auto-sensing, integrating the MAC and PHY layers, and connecting to the main control chip via the RMII interface (25MHz clock). The network interface uses an RJ45 socket (with an H1102NL transformer) with a built-in LED indicator (LINK / ACT). The transformer's primary and secondary isolation voltage is ≥1500Vrms, meeting carrier-grade protection requirements.

[0038] The clock-buffer bidirectional linkage adjustment method for a voice gateway proposed in this application can be implemented by a receiving gateway.

[0039] In order to further illustrate the technical solutions provided by the embodiments of the present application, this is described in detail below with reference to the accompanying drawings and specific embodiments. Although the embodiments of the present application provide the method operation instruction steps shown in the following embodiments or drawings, more or fewer operation instruction steps may be included in the method based on conventional or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiments of the present application. The method may be executed in the order of the methods shown in the embodiments or drawings or in parallel during the actual processing process or when the device is executed.

[0040] It should be noted that the acquisition or use of data in the embodiments of this application requires the user's consent. The relevant data can only be obtained after the user's authorization and permission, and the acquisition or use of the data complies with the provisions of relevant laws and regulations.

[0041] Please refer to Figure 3 , Figure 3 FIG1 shows a flow chart of a clock-buffer bidirectional linkage adjustment method for a voice gateway provided by an embodiment of the present application. Figure 3 As shown, the method includes: Step 301 : Acquire a clock frequency error, and compensate the jitter buffer initial depth according to the clock frequency error to obtain a jitter buffer target depth; the jitter buffer initial depth is a dynamic initial depth at the current moment determined based on a prediction model.

[0042] Step 302 : Determine a depth change rate corresponding to the jitter buffer based on the original jitter buffer depth and the target jitter buffer depth.

[0043] Step 303: Determine a dynamic gain of a clock phase-locked loop based on the depth change rate, and update the clock signal according to the dynamic gain.

[0044] It should be noted that clock frequency error is the frequency deviation between the receiving gateway's clock frequency and the sending gateway's clock frequency. A fast receiving clock causes the playback rate to exceed the arrival rate, leading to jitter buffer underload. A slow receiving clock causes the playback rate to fall below the arrival rate, leading to jitter buffer overflow. For example, a 100ppm drift in the 8kHz clock frequency results in a cumulative error of 0.8 frames per second, or a 10-minute offset of 480 frames. Therefore, clock frequency error can severely impact the accuracy and reliability of voice playback at the receiving gateway.

[0045] On the other hand, during the buffer compensation process, sudden changes in buffer depth can cause the traditional fixed-gain phase-locked loop (PLL) to lose lock. Moreover, when the buffer depth changes frequently or drastically, the clock reconvergence speed is slow, which in turn will affect the accuracy and reliability of the voice playback on the final receiving gateway.

[0046] Based on this, the clock-buffer bidirectional linkage adjustment method for voice gateways proposed in the embodiments of this application, through the interaction of clock frequency error-buffer compensation and buffer compensation-clock dynamic gain compensation, can accurately and reliably adjust the voice gateway jitter buffer depth, adapt to dynamic delay changes, and improve voice playback accuracy. At the same time, by dynamically adjusting the dynamic gain of the clock phase-locked loop based on the depth change rate, the reliability of clock operation is guaranteed. When the jitter buffer depth fluctuates frequently or drastically, the clock signal can converge as quickly as possible, further ensuring the accuracy and reliability of voice playback.

[0047] It should be noted that in the embodiment of the present application, the initial jitter buffer depth is a dynamic initial depth at the current moment determined based on a prediction model. Specifically, the initial jitter buffer depth may be determined by predicting the time of satellite switching in a communication satellite constellation.

[0048] In a specific embodiment, the switching warning time and current time of satellite switching are predicted based on the satellite ephemeris, and the switching growth factor is determined based on the switching warning time and current time. The initial depth of the jitter buffer is determined based on the switching growth factor and the original depth of the jitter buffer.

[0049] It should be understood that compared to IP network jitter, the jitter time of satellite intersatellite handovers is longer, for example, greater than 500ms. Therefore, this application uses a prediction model to predict the handover time based on the satellite ephemeris and the location of the receiving gateway, obtaining a handover warning time, i.e., the handover start time. Then, based on the handover warning time and the current time, a handover growth factor is determined, i.e., the factor that affects the increase in the jitter buffer depth during the satellite handover. Finally, the initial jitter buffer depth is determined based on the handover growth factor and the original jitter buffer depth.

[0050] For example, the following formula may be used to determine the initial depth of the jitter buffer:

[0051] in, Initial depth of the jitter buffer. Cache original depth for dithering, is the satellite coefficient, that is, the scene sensitivity corresponding to the satellite constellation, is the growth factor, To switch the warning time, The current time is the current system time of the receiving gateway.

[0052] It should also be noted that in the embodiments of this application, the compensation requirements caused by clock frequency changes include two aspects: first, the compensation requirements caused by the natural clock frequency drift under normal conditions, that is, the compensation requirements caused by the frequency error caused by multiple clock alignments; second, when the voice gateway uses satellite communication, the compensation requirements caused by the Doppler frequency shift caused by satellite handover.

[0053] In a feasible embodiment, obtaining a clock frequency error and compensating an initial jitter buffer depth based on the clock frequency error includes: obtaining the clock frequency error and a nominal sampling rate, determining a frequency compensation coefficient, and compensating the initial jitter buffer depth based on the time compensation coefficient to obtain a target jitter buffer depth.

[0054] For example, the compensation caused by the natural frequency drift of the clock under normal conditions can be calculated using the following formula:

[0055] in, is the target depth requirement of the jitter buffer obtained by compensation based on the clock frequency, Initial depth of the jitter buffer. is the frequency sensitivity coefficient, is the clock frequency error, that is, the frequency error between the local time of the receiving gateway and the sending time of the sending gateway, is the nominal sampling frequency, is the frequency compensation coefficient.

[0056] Therefore, the present application can increase the depth deviation caused by the time frequency error to the jitter buffer buffer through the frequency compensation coefficient based on the initial jitter buffer depth, thereby improving the reliability of the dynamic setting of the jitter buffer depth.

[0057] In another embodiment, the Doppler frequency shift and the Doppler dynamic compensation factor caused by satellite switching are predicted, and Doppler dynamic compensation is obtained based on the Doppler frequency shift and the Doppler dynamic compensation factor. The initial depth of the jitter buffer is compensated based on the Doppler dynamic compensation coefficient to obtain the target depth of the jitter buffer.

[0058] For example, the compensation caused by the Doppler frequency shift generated by satellite switching can be calculated using the following formula:

[0059] in, is the jitter buffer target depth requirement value obtained by compensation based on satellite switching, Initial depth of the jitter buffer. is the Doppler frequency shift, that is, the frequency deviation caused by relative motion, is the Doppler dynamic compensation factor, is the Doppler dynamic compensation coefficient.

[0060] It should be understood that the two types of jitter buffer initial depth compensation can be performed independently or in combination. For example, when there is no satellite handover requirement, only the compensation algorithm based on the natural clock frequency drift under normal conditions can be used. When there is a satellite handover requirement, the two compensation algorithms can be used in combination. Optionally, when the two compensation algorithms are used in combination, the frequency compensation coefficient and the Doppler compensation coefficient can be used simultaneously to compensate the initial jitter buffer depth to obtain the target jitter buffer depth.

[0061] For example, it can be expressed as:

[0062] in, Target depth requirement for the dither buffer.

[0063] Therefore, the present application provides a solution for depth compensation under different working conditions for the receiving gateway, realizes dynamic depth adjustment of the jitter buffer, and provides a reliable time interval basis for subsequent voice playback.

[0064] In some embodiments, in order to further make the dynamic adjustment of the jitter buffer depth more reliable, for example, to meet the hardware resource or capability constraints of the receiving gateway, the present application also proposes: obtaining the compensated jitter buffer target depth requirement value and the resource data corresponding to the voice gateway terminal, determining the jitter buffer target depth constraint value based on the resource data, and determining the jitter buffer target depth for calculating the depth change rate according to the jitter buffer target depth requirement value and the jitter buffer target depth constraint value.

[0065] The resource data includes at least available memory, utilization factor, encoding bit rate and frame duration.

[0066] Specifically, the jitter buffer target depth constraint value is the maximum jitter buffer depth that can be provided by the receiving gateway in its current state. Therefore, this application takes the smaller value between the jitter buffer target depth requirement value and the jitter buffer target depth constraint value to ensure that the buffer area of ​​the receiving gateway can provide the jitter buffer target depth. That is, if the jitter buffer target depth requirement value is less than the jitter buffer target depth constraint value, it means that the receiving gateway can provide sufficient jitter buffer target depth, and the jitter buffer target depth requirement value can be used as the jitter buffer target depth to adjust the jitter buffer depth. If the jitter buffer target depth constraint value is less than the jitter buffer target depth requirement value, it means that the receiving gateway cannot provide sufficient jitter buffer target depth. In order to avoid operational failures of the receiving gateway, the jitter buffer target depth constraint value is used as the jitter buffer target depth to adjust the jitter buffer depth, so as to provide the largest possible depth while ensuring stable operation of the receiving gateway and meet more buffering requirements.

[0067] For example, the following formula may be used to determine the target depth of the jitter buffer:

[0068] in, The target depth for the jitter buffer. The target depth requirement value for the jitter buffer, is the memory utilization factor, is the available memory, is the encoding bit rate of the voice data, is the frame duration.

[0069] In another feasible embodiment of the present application, determining the dynamic gain of the clock phase-locked loop based on the depth change rate includes: determining the dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop according to the depth change rate respectively.

[0070] For example, the dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop can be determined using the following formula:

[0071]

[0072] in, is the dynamic proportional gain, is the dynamic integral gain, is the depth change rate, is the sensitivity coefficient corresponding to the phase-locked loop, is the basic proportional gain, is the basic integral gain.

[0073] It should be understood that the receiving gateway provided in the embodiment of the present application uses a digital phase-locked loop DPLL to provide a stable clock signal. After the present application determines the dynamic proportional gain and dynamic integral gain corresponding to the clock phase-locked loop, the digital phase-locked loop can update the clock signal in real time according to the dynamic proportional gain and dynamic integral gain.

[0074] In summary, the clock-buffer bidirectional linkage adjustment method for voice gateways proposed in the embodiments of this application, through the coordinated implementation of clock frequency error-buffer compensation and buffer compensation-clock dynamic gain compensation, enables accurate and reliable adjustment of the voice gateway jitter buffer depth, adapting to dynamic delay changes and improving voice playback accuracy. Furthermore, by dynamically adjusting the dynamic gain of the clock phase-locked loop based on the depth change rate, the reliability of clock operation is guaranteed. When the jitter buffer depth fluctuates frequently or dramatically, the clock signal converges as quickly as possible, further ensuring the accuracy and reliability of voice playback.

[0075] It should be noted that although the operations of the present method are described in a particular order in the drawings, this does not require or imply that the operations must be performed in this particular order, or that all illustrated operations must be performed to achieve desirable results.

[0076] Figure 4 A schematic structural diagram of a clock-buffer bidirectional linkage adjustment device for a voice gateway provided in one embodiment of the present application is shown.

[0077] like Figure 4 As shown, the clock-buffer bidirectional linkage adjustment device 10 for a voice gateway includes: A depth compensation module 11 is configured to obtain a clock frequency error and compensate an initial jitter buffer depth according to the clock frequency error to obtain a target jitter buffer depth; the initial jitter buffer depth is a dynamic initial depth at a current moment determined based on a prediction model; A determination module 12 is configured to determine a depth change rate corresponding to the jitter buffer based on an original depth of the jitter buffer and a target depth of the jitter buffer; The clock updating module 13 is configured to determine a dynamic gain of a clock phase-locked loop based on the depth change rate, and update a clock signal according to the dynamic gain.

[0078] In some embodiments, the depth compensation module 11 is specifically configured to: Obtaining the clock frequency error and the nominal sampling rate, and determining a frequency compensation coefficient; The initial jitter buffer depth is compensated based on the frequency compensation coefficient to obtain the jitter buffer target depth.

[0079] In some embodiments, the depth compensation module 11 is specifically configured to: Predict the Doppler frequency shift and Doppler dynamic compensation factor caused by satellite switching; Obtaining a Doppler dynamic compensation coefficient according to the Doppler frequency shift amount and the Doppler dynamic compensation factor; The initial jitter buffer depth is compensated according to the Doppler dynamic compensation coefficient to obtain a jitter buffer target depth.

[0080] In some embodiments, the depth compensation module 11 is specifically configured to: Predicting a switching warning time and a current time of satellite switching according to the satellite ephemeris, and determining a switching growth factor according to the switching warning time and the current time; The initial depth of the jitter buffer is determined according to the switching growth factor and the original depth of the jitter buffer.

[0081] In some embodiments, the determination module 12 is specifically configured to: Obtaining a compensated jitter buffer target depth requirement value and resource data corresponding to the voice gateway terminal, the resource data including at least available memory, utilization factor, encoding bit rate, and frame duration; Determining a jitter buffer target depth constraint value based on the resource data; The jitter buffer target depth for calculating the depth change rate is determined according to the jitter buffer target depth requirement value and the jitter buffer target depth constraint value.

[0082] In some embodiments, the clock update module 13 is specifically configured to: A dynamic proportional gain and a dynamic integral gain corresponding to the clock phase-locked loop are determined according to the depth change rate.

[0083] It should be understood that the modules or modules described in the clock-buffer bidirectional linkage adjustment device 10 for voice gateway are similar to those described in the reference Figure 3 The various steps in the described method correspond to each other. Therefore, the operations and features described above for the method are also applicable to the clock-buffer bidirectional linkage adjustment device 10 for voice gateway and the modules contained therein, and will not be repeated here. The clock-buffer bidirectional linkage adjustment device 10 for voice gateway can be pre-implemented in the browser or other security applications of the electronic device, and can also be loaded into the browser or its security application of the electronic device by downloading or the like. The corresponding modules in the clock-buffer bidirectional linkage adjustment device 10 for voice gateway can cooperate with the modules in the electronic device to implement the solution of the embodiment of the present application.

[0084] The several modules or units mentioned in the detailed description above are not necessarily divided into one module or unit. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0085] Reference below Figure 5 , Figure 5 A schematic diagram of the structure of a computer system of an electronic device or server suitable for implementing the embodiments of the present application is shown. like Figure 5 As shown, computer system 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes according to programs stored in read-only memory (ROM) 502 or programs loaded from storage unit 508 into random access memory (RAM) 503. RAM 503 also stores various programs and data required for the system's operating instructions. CPU 501, ROM 502, and RAM 503 are connected to each other via bus 504. An input / output (I / O) interface 505 is also connected to bus 504.

[0086] The following components are connected to the I / O interface 505: an input section 506 including a keyboard, mouse, and the like; an output section 507 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 508 including devices such as a hard disk; and a communication section 509 including a network interface card such as a LAN card or a modem. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the I / O interface 505 as needed. Removable media 511, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 510 as needed, so that computer programs read therefrom can be installed in the storage section 508 as needed.

[0087] In particular, according to the embodiment of the present application, the above reference flow chart Figure 2 The described processes can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for executing the method illustrated in the flowchart. In such an embodiment, the computer program contains program code for executing the method illustrated in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 509 and / or installed from removable media 511. When the computer program is executed by the central processing unit (CPU) 501, the aforementioned functions defined in the system of the present application are performed.

[0088] It should be noted that the computer-readable medium described herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical cable, RF, or any suitable combination thereof.

[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operating instructions of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the aforementioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than the order marked in the accompanying drawings. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operating instruction, or can be implemented using a combination of dedicated hardware and computer instructions.

[0090] The units or modules involved in the embodiments described in the present application can be implemented by software or by hardware. The described units or modules can also be set in a processor. For example, they can be described as: a processor includes a depth compensation module, a determination module and a clock update module. Among them, the names of these units or modules do not constitute a limitation on the units or modules themselves under certain circumstances. For example, the depth compensation module can also be described as "obtaining a clock frequency error, and compensating the initial depth of the jitter buffer according to the clock frequency error to obtain a jitter buffer target depth; the initial depth of the jitter buffer is a dynamic initial depth at the current moment determined based on a prediction model."

[0091] As another aspect, the present application further provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not be incorporated into the electronic device. The computer-readable storage medium stores one or more programs, which, when used by one or more processors, execute the clock-buffer bidirectional linkage adjustment method for a voice gateway described in the present application.

[0092] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by a specific combination of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned disclosed concepts. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A clock-buffer bidirectional linkage adjustment method for a voice gateway, characterized in that: include: Acquire a clock frequency error, and compensate an initial jitter buffer depth according to the clock frequency error to obtain a target jitter buffer depth; The jitter buffer initial depth is a dynamic initial depth at the current moment determined based on a prediction model; Determining a depth change rate corresponding to the jitter buffer based on the jitter buffer original depth and the jitter buffer target depth; A dynamic gain of a clock phase-locked loop is determined based on the depth change rate, and a clock signal is updated according to the dynamic gain.

2. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that: The obtaining of the clock frequency error and compensating the initial depth of the jitter buffer according to the clock frequency error includes: Obtaining the clock frequency error and the nominal sampling rate, and determining a frequency compensation coefficient; The initial jitter buffer depth is compensated based on the frequency compensation coefficient to obtain the jitter buffer target depth.

3. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that: When the voice gateway adopts satellite communication, the method further includes: Predict the Doppler frequency shift and Doppler dynamic compensation factor caused by satellite switching; Obtaining a Doppler dynamic compensation coefficient according to the Doppler frequency shift amount and the Doppler dynamic compensation factor; The initial jitter buffer depth is compensated according to the Doppler dynamic compensation coefficient to obtain a jitter buffer target depth.

4. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 3, characterized in that: Before the dynamic initial depth at the current moment is determined based on the prediction model, the method further includes: Predicting a switching warning time and a current time of satellite switching according to the satellite ephemeris, and determining a switching growth factor according to the switching warning time and the current time; The initial depth of the jitter buffer is determined according to the switching growth factor and the original depth of the jitter buffer.

5. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that: Before determining the depth change rate corresponding to the jitter buffer based on the jitter buffer original depth and the jitter buffer target depth, the method further includes: Obtaining a compensated jitter buffer target depth requirement value and resource data corresponding to the voice gateway terminal, the resource data including at least available memory, utilization factor, encoding bit rate, and frame duration; Determining a jitter buffer target depth constraint value based on the resource data; The jitter buffer target depth for calculating the depth change rate is determined according to the jitter buffer target depth requirement value and the jitter buffer target depth constraint value.

6. The clock-buffer bidirectional linkage adjustment method for a voice gateway according to claim 1, characterized in that: Determining a dynamic gain of a clock phase-locked loop based on the depth change rate includes: A dynamic proportional gain and a dynamic integral gain corresponding to the clock phase-locked loop are determined according to the depth change rate.

7. A clock-buffer bidirectional linkage adjustment device for a voice gateway, characterized in that: include: a depth compensation module, configured to obtain a clock frequency error and compensate an initial jitter buffer depth according to the clock frequency error to obtain a target jitter buffer depth; The jitter buffer initial depth is a dynamic initial depth at the current moment determined based on a prediction model; A determination module, configured to determine a depth change rate corresponding to the jitter buffer based on an original depth of the jitter buffer and a target depth of the jitter buffer; A clock update module is used to determine a dynamic gain of a clock phase-locked loop based on the depth change rate, and update a clock signal according to the dynamic gain.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, it implements the clock-buffer bidirectional linkage adjustment method for a voice gateway as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the clock-buffer bidirectional linkage adjustment method for a voice gateway as described in any one of claims 1 to 6 is implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the clock-buffer bidirectional linkage adjustment method for a voice gateway according to any one of claims 1 to 6 is implemented.

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