Optical computing chip of vertical micromirror structure and wafer-level intelligent manufacturing method thereof

Abstract

The invention discloses an optical computing chip with a vertical micromirror structure and a wafer-level intelligent manufacturing method thereof, the optical computing chip comprises a plurality of optical modulators and a plurality of quantum logic gates, and interference optical paths in the optical modulators are set based on a vertical micromirror, so that optical modulation is realized; the quantum logic gate constructs a stable light path through a reflecting mirror arranged vertical to the micro-mirror, interference is realized by using a beam splitter, and Hadamard transform is executed by a wave plate at an inlet or an outlet of a target light path, so that light calculation is realized; a deep groove beam splitter or a deep wall beam splitter is adopted as a beam splitter, a silicon wall in the deep wall beam splitter is arranged to be perpendicular to two side walls of a substrate to form a preset included angle, and the deep groove beam splitter is manufactured by the following steps: photoetching a pattern of a deep groove on the surface of a monocrystalline silicon wafer; etching a deep groove with a preset angle by using a deep etching method, and smoothing the side wall; depositing an optical thin film in the deep groove; photoetching and deeply etching the shape of the deep groove beam splitter, wherein the side wall of the deep groove beam splitter is smooth; and growing an optical antireflection film on the vertical side wall.

Description

Technical Field

[0001] The present invention relates to the fields of integrated circuits, optoelectronic technology, advanced packaging and digital manufacturing, and in particular to an optical computing chip with a vertical micromirror structure and a wafer-level intelligent manufacturing method thereof. Background Art

[0002] As semiconductor processing advances into the sub-10nm scale, integrated circuits face two fundamental challenges: First, signal latency and crosstalk caused by metal interconnects have outpaced transistor performance improvements, becoming the primary bottleneck restricting computing power growth; second, while three-dimensional stacked packaging can increase integration density, it also leads to a surge in heat flux per unit area. Against this backdrop, optical computing has emerged as a transformative technology. Silicon-based photonics technology leverages a mature microelectronics manufacturing system to build a fully functional link for optical signal generation, transmission, and control by integrating components such as lasers, modulators, waveguides, and detectors on a silicon substrate. Its core principle is to replace electrons with photons for data transmission and processing. Compared to electrons, photons have no rest mass, and different wavelengths of light can be used for multiple simultaneous communications, resulting in greater bandwidth, higher speeds, and enhanced resistance to electromagnetic interference, thus overcoming the physical limitations of electrical interconnects. However, silicon-based photonics technology still faces pain points in industrialization: the mainstream solution relies on SOI (silicon on insulator) substrates to construct waveguide structures, but SOI materials are expensive and have compatibility barriers with bulk silicon integrated circuit processes, resulting in a sharp increase in the difficulty of heterogeneous integration; in addition, the edge roughness during the silicon waveguide etching process will cause significant light scattering losses, seriously restricting device performance, yield and integration scale. Summary of the Invention

[0003] In response to the problems of complex process of traditional silicon-based photonic technology and the disadvantages of MEMS (Micro-Electro-Mechanical System) horizontal micromirrors that are not conducive to horizontal optical path transmission and control, the purpose of the embodiments of the present application is to provide an optical computing chip with a vertical micromirror structure and a wafer-level intelligent manufacturing method thereof.

[0004] According to a first aspect of an embodiment of the present application, the present application proposes an optical computing chip with a vertical micromirror structure, comprising a plurality of optical modulators and a plurality of quantum logic gates. Interference optical paths in the optical modulators are arranged based on the vertical micromirrors to achieve optical modulation. The quantum logic gates construct a stable optical path using reflectors arranged in the vertical micromirrors, achieve interference using a beam splitter, and perform Hadamard transforms using wave plates at the entrance or exit of the target optical path, thereby achieving optical computing. The quantum logic gate uses a deep trench beam splitter or a deep wall beam splitter as the beam splitter. In the deep wall beam splitter, the silicon wall is perpendicular to the two side walls of the substrate and is arranged at a predetermined angle. The deep trench beam splitter is manufactured by the following method: photolithography is performed on the surface of a single crystal silicon wafer to form a deep trench pattern; deep etching is performed to form a deep trench with a predetermined angle and the side walls are smoothed; an optical thin film is deposited in the deep trench; photolithography and deep etching are performed to form the shape of the deep trench beam splitter and the side walls are smoothed; and an optical anti-reflection film is grown on the vertical side walls.

[0005] Furthermore, the adjustable interferometer arms in the optical modulator adopt thermo-optical modulation and voltage modulation and are manufactured in the following manner: an insulating layer is deposited on the surface of a single-crystal silicon wafer; a heavily doped substrate region is formed by ion implantation and annealing; a metal layer is deposited and annealed to form a substrate region electrode with ohmic contact properties; a gate electrode is formed on the surface-deposited insulating layer; a vertical structure is deeply etched on the single-crystal silicon wafer and the sidewalls are smoothed to form a vertical micromirror; and an optical anti-reflection film is deposited on the surface of the vertical micromirror.

[0006] Furthermore, the adjustable interferometer arm in the optical modulator adopts PN junction modulation and is manufactured by the following method: A deep etching method is used to carve vertical sidewalls on the surface of a single-crystal silicon wafer and the sidewalls are smoothed to form a number of vertical micromirrors; the surface of the vertical micromirrors is patterned using a spray glue or two-photon lithography method; the vertical sidewalls are doped and annealed to form P regions, N regions, P+ regions, and N+ regions; electrodes are grown and an optical anti-reflection film is grown on the surface of the vertical micromirrors to form adjustable interferometer arms based on a comb-tooth PN junction modulation structure.

[0007] Furthermore, the quantum logic gate also includes a metal grating polarizer, which is manufactured by: photolithography and vertical deep etching of nano-gratings or nano-pillars on a single-crystal silicon wafer, and depositing metal to form a metal gate; or using two-photon printing to form grating gaps on the vertical sidewalls after vertical deep etching and sidewall smoothing, patterning the sidewalls by spraying and photolithography and depositing metal, and stripping off the glue to obtain a metal gate; or patterning by spraying and photolithography, depositing metal and stripping off the glue, and etching away the metal in the gaps using the grayscale milling function of focused ion beam etching to obtain a metal gate.

[0008] Furthermore, the quantum logic gate also includes a grating wave plate, which is manufactured by: using the grayscale milling function of deep reactive ion etching or focused ion beam etching to etch a grating periodic structure on the vertical sidewall after deep vertical etching and sidewall smoothing, and depositing metal to form a wave plate with a reflective metal grating structure; or using a two-photon printing method to manufacture a grating periodic structure on the vertical sidewall after deep vertical etching and sidewall smoothing, and depositing metal to form a wave plate with a reflective metal grating structure.

[0009] Furthermore, the quantum logic gate further includes a collimating lens, which is manufactured by: additively manufacturing the vertical sidewalls after the sidewalls are smoothed by two-photon printing, or by reducing the sidewalls by focused ion beam etching.

[0010] Furthermore, the optical modulator and the quantum logic gate both include a reflector, which is manufactured by deep etching a vertical sidewall and smoothing it to form a vertical micromirror, and depositing an optical anti-reflection film on the surface of the vertical micromirror.

[0011] Furthermore, the optical computing chip also includes a spectrometer. In the spectrometer, light emitted by a laser manufactured by epitaxial growth on a single crystal silicon wafer or through heterogeneous integration passes through a vertical aperture to reach a vertical concave mirror, and then is reflected to a spectrometer to separate light of different wavelengths into different angles, and then reflected to a vertical concave mirror to focus light of different wavelengths at different positions for detection by a detector.

[0012] Furthermore, a blazed grating is used as the light splitting element, and the blazed grating is manufactured by the following method: After deep vertical etching and smooth sidewalls, a serrated groove is made on the vertical micromirror using additive or subtractive manufacturing methods, and a metal layer is deposited to form a blazed grating.

[0013] According to a second aspect of the embodiments of the present application, the present application further proposes a wafer-level intelligent manufacturing method for an on-wafer system, wherein the on-wafer system includes the optical computing chip with a vertical micromirror structure according to the first aspect, and the method includes: At the system level, the wafer is divided into optical computing units, electrical computing units, storage units, control units, and power supply units, and a wafer-level system architecture is formed through system-level modeling; Based on the wafer-level system architecture, the optoelectronic collaborative functional structure of the optical computing unit and the electrical computing unit is designed; Design an optoelectronic on-chip interconnection network within the optoelectronic collaborative functional architecture. This network uses an adaptive routing algorithm to reduce blocking delays, redundant interconnects to automatically switch to backup paths in the event of a failure, and dynamic voltage regulation to reduce idle power consumption. In the optoelectronic on-wafer interconnect network, an artificial intelligence mapping model between manufacturing parameters and device performance is established, automatic wiring is performed according to functional requirements, and the on-wafer system wiring layout under multi-physics field coupling conditions is simulated. If the simulation results do not meet the requirements, the on-wafer interconnect network is optimized according to the simulation results and then simulated again until the requirements are met; Build a global perception layer, establish data on integrated circuit manufacturing equipment, clean room environments, and microelectronic materials, and construct a multi-dimensional mapping digital manufacturing model. Combine the wiring layout design of the on-chip system and drive the microelectronic process line with the digital manufacturing model to complete the manufacturing of optoelectronic integrated systems. Among them, the chip's process parameters are tested in real time during the manufacturing process, and the drift of equipment parameters is extracted in real time. Dynamic closed-loop control is implemented in combination with the test results and equipment parameters, and device performance is predicted, compensated and dynamically feedback adjusted in advance, and the on-chip system wiring layout design is optimized.

[0014] The technical solutions provided by the embodiments of the present application may have the following beneficial effects: The present invention smoothes the sidewalls of deeply etched through-silicon vias (TSVs) through high-temperature, dry, or wet methods to form a vertical micromirror structure with a roughness of less than 1 nm, thereby manufacturing a deep trench beam splitter with higher reliability than single-crystal silicon thin-film beam splitters. Based on the deep trench beam splitter, various optical modulators and quantum logic gates are further constructed, realizing an optical computing chip structure for spatial light beyond macroscopic space optics and silicon-based optoelectronics. Compared with silicon-based optoelectronics, this not only simplifies the process, but also reduces the transmission loss of light in air compared to silicon waveguides, making it suitable for large-scale integration.

[0015] The present invention also proposes a wafer-level intelligent manufacturing method for an on-wafer system including the above-mentioned optical computing chip, forming a top-down full-process manufacturing method from architecture to design to manufacturing to test feedback, thereby comprehensively improving the design and manufacturing efficiency of wafer-level optoelectronic on-wafer integrated systems.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 Figure 1 shows the manufacturing process flow for a DC voltage-modulated MZI adjustable interferometer arm with a MOS structure, where (a-1)-(f-1) are top views of the wafer for each process, (a-2)-(f-2) are front views of the wafer for each process, and (a-3)-(f-3) are cross-sectional views of the wafer for each process. Figure 2 Schematic diagram of a DC voltage-modulated MZI tunable interferometer arm in a MOS structure, where (a)-(d) are schematic diagrams of substrate electrodes and gate electrodes set at different positions; Figure 3 Figure 1 shows the manufacturing process of the adjustable interferometer arm of the comb-tooth PN junction modulation structure, where (a) is a schematic diagram of the wafer after sidewall doping, and (b) is a schematic diagram of the wafer after the electrodes and anti-reflection film are grown; Figure 4The figure shows the manufacturing process flow chart of the deep trench beam splitter, where (a-1)-(e-1) are top views of the wafer for each process, and (a-2)-(e-2) are cross-sectional views of the wafer for each process. Figure 5 Figure 1 shows the schematic structure of a metal grating polarizer based on vertical micromirrors, where (a) is a nano-grating or nano-pillar vertical grating, (b) is a nano-grating or nano-pillar vertical grating with an added substrate structure, (c) is a reflective vertical metal grating wave plate, and (d) is a reflective horizontal metal grating wave plate. Figure 6 Figure 2 shows the schematic diagram of the structure of a blazed grating spectrometer based on a vertical micromirror, where (a) is a blazed grating, (b) is a spectrometer, (c) and (d) are two structural settings for deflecting the blazed grating using a MEMS electrostatic actuator structure, (e) and (f) are two structural settings for deflecting the blazed grating using a comb-tooth electrostatic drive structure, (g) is a slit-type vertical aperture, and (h) is a circular hole-type vertical aperture. Figure 7 Figure 2 shows the schematic diagram of the structure of an optical computing chip based on vertical micromirrors, where (a) is the MZI schematic diagram, (b) is the Michelson interferometer schematic diagram, (c) is the two-bit quantum logic gate schematic diagram, and (d) is a schematic diagram of the on-wafer system. Figure 8 Figure 2 shows a schematic diagram of the structure of a deep-wall beam splitter, where (a) is a three-dimensional structural diagram of a prism-shaped deep-wall beam splitter, (b) is a top view of the prism-shaped deep-wall beam splitter, (c) is a top view of a single-side wall coating of the prism-shaped deep-wall beam splitter, (d) is a top view of a single-side wall coating of a rectangular deep-wall beam splitter, (e) is a top view of a double-side wall coating of the prism-shaped deep-wall beam splitter, and (f) is a top view of a double-side wall coating of the rectangular deep-wall beam splitter. Figure 9 Shown is a flow chart of a wafer-level intelligent manufacturing method for optical computing chips with vertical micromirror structures.

[0019] Figure 1: Single crystal silicon wafer 1, insulating layer 2, substrate region 3, substrate region electrode 4, gate electrode 5, vertical structure 6, antireflection film 7, deep trench 8, optical film 9, vertical sidewall 10, optical antireflection film 11, metal gate 12, substrate structure 13, reflective metal grating wave plate 14, grating periodic structure 15, blazed grating 16, laser 17, vertical aperture 18, first vertical concave mirror 19, second vertical concave mirror 20, detector 21, vertical cantilever beam 22, rear vertical fixed electrode plate 23, front vertical fixed electrode plate 24, moving electrode plate 25, first fixed electrode plate 26, second fixed electrode plate 27, third fixed electrode plate 28, fourth fixed electrode plate 29, slit 30, circular hole structure 31, first beam splitter 32, first reflecting mirror 33, first interferometer arm 34, second beam splitter 35, second interferometer arm 36, second reflecting mirror 3 7. Third beam splitter 38, third reflector 39, first detector 40, third interferometer arm 41, fourth reflector 42, first half beam splitter 43, second half beam splitter 44, third half beam splitter 45, fourth half beam splitter 46, first one-third beam splitter 47, second one-third beam splitter 48, third one-third beam splitter 49, first reflective metal grating half-wave plate 50, second reflective metal grating half-wave plate 51, first collimating lens 52, second collimating lens 53, third collimating lens 54, fourth collimating lens 55, laser 56, on-chip optical computing chip 57, second detector 58, electrical signal processing chip 59, adapter board 60, circuit board 61, power supply module 62, deep wall beam splitter 63, transmissive sidewall optical anti-reflection film 64, reflective sidewall optical film 65. DETAILED DESCRIPTION

[0020] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0021] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0022] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0023] The present application provides an optical computing chip with a vertical micromirror structure, comprising a plurality of optical modulators and a plurality of quantum logic gates. An interference optical path in the optical modulator is arranged based on the vertical micromirrors to achieve optical modulation. The quantum logic gate constructs a stable optical path through vertically arranged reflectors, utilizes a beam splitter to achieve classical and non-classical interference, and performs a Hadamard transform on wave plates at the entrance / exit of the target optical path, thereby achieving optical computing. The quantum logic gate uses a deep trench beam splitter or a deep wall beam splitter as the beam splitter. In the deep wall beam splitter, the silicon walls are arranged at a predetermined angle perpendicular to the two sidewalls of the substrate. The deep trench beam splitter is manufactured by: photolithography of a deep trench pattern on the surface of a single crystal silicon wafer; deep etching to carve a deep trench with a predetermined angle and smoothing the sidewalls; depositing an optical thin film in the deep trench; photolithography and deep etching to form the shape of the deep trench beam splitter and smoothing the sidewalls; and growing an optical anti-reflection film on the vertical sidewalls.

[0024] An optical computing chip with a vertical micromirror structure is an on-chip optical system composed of optical modulators, quantum logic gates, and other devices. In specific implementations, the optical modulators can be intensity modulators, phase modulators, polarization modulators, and other devices, all of which can achieve optical phase modulation through vertical micromirrors. Subsequent embodiments describe the Mach-Zehnder modulator in detail, taking the example of a Mach-Zehnder interferometer (MZI) with adjustable interferometer arms, a deep trench beam splitter, and a reflector. The deep trench beam splitter, reflector, and other components organize the optical path, and the MZI's adjustable interferometer arms achieve optical phase modulation. Quantum logic gates are used to implement basic logical operations in quantum computing. For example, a two-bit controlled NOT (CNOT) quantum logic gate includes a deep trench beam splitter, a reflector, a beam splitter, and a wave plate. A stable optical path is constructed using vertically arranged mirrors. The deep trench beam splitter achieves classical and nonclassical interference, and the wave plates at the entrance and exit of the target optical path perform Hadamard transforms, ultimately completing the controlled NOT quantum logic operation.

[0025] Vertical micromirrors innovatively create three-dimensional optical structures and key optical components perpendicular to the wafer plane directly on single-crystal silicon wafers through a high-precision deep etching process. The sidewalls are smoothed to a surface roughness of less than 1 nanometer, meeting the stringent requirements of optical interfaces. Compared to conventional horizontal micromirrors in Micro-Opto-Electro-Mechanical Systems (MOEMS) systems, this technology eliminates the need for subsequent alignment and microassembly processes, enabling the direct fabrication of vertical optical components on a silicon substrate and achieving a complete horizontal integrated optical circuit.

[0026] Examples 1-4 and 6 illustrate the structure and manufacturing steps of key optical components based on vertical micromirrors, respectively. Example 5 describes an optical computing chip and optoelectronic integrated system composed of these key optical components. Example 7 illustrates the design and collaborative intelligent manufacturing methods for wafer-level optoelectronic integrated systems, forming a top-down, full-process manufacturing approach from architecture to design, manufacturing, and testing feedback.

[0027] Example 1

[0028] MZI is the most basic structural unit in optical computing. MZI uses the interference effect of light to implement linear matrix operations by adjusting the phase difference between the two interferometer arms. This application is based on the MOS (Metal-Oxide Semiconductor, MOS) structure, and modulates the refractive index of the vertical micromirrors of the adjustable interferometer arms in the MZI by electricity or heat, thereby changing the interference phase of the two beams of light. This embodiment takes the structure and manufacturing process of the vertical micromirrors of the adjustable interferometer arms in the MZI as an example to provide a method for manufacturing an optical computing chip. However, the application scenarios of the present invention are not limited to the examples given, and can also be applied to scenarios of manufacturing MZIs using vertical micromirrors with other structures and principles.

[0029] like Figure 1 As shown in FIG, the manufacturing steps of the DC voltage modulated MZI adjustable interferometer arm of the MOS structure are as follows: S11: First, on the single crystal silicon wafer 1 ( Figure 1 An insulating layer 2 is deposited on the surface of (a-1), (a-2), and (a-3) in the figure. The material of the insulating layer includes but is not limited to one or more high-dielectric-constant materials such as silicon dioxide, silicon nitride, and hafnium oxide. Then, a portion of the insulating layer is removed by photolithography and etching to expose the silicon substrate ( Figure 1 (b-1), (b-2), (b-3)).

[0030] S12: Form a heavily doped substrate region 3 by ion implantation and annealing ( Figure 1 (c-1), (c-2), (c-3)).

[0031] S13: Deposit a metal layer and anneal it, forming a substrate region electrode 4 with ohmic contact properties on the substrate region 3, and forming a gate electrode 5 on the surface deposited insulating layer 2 ( Figure 1 (d-1), (d-2), (d-3)).

[0032] S14: Deeply etch the vertical structure 6 on the single crystal silicon wafer 1 and smooth the sidewalls to produce a good optical plane and electrical vertical plane, i.e., a vertical micromirror ( Figure 1 (e-1), (e-2), (e-3)).

[0033] A deep etching process is used to etch vertical structures with a depth greater than 100 microns, a verticality better than 90°±0.3°, and an initial sidewall roughness better than 50 nanometers on the top surface of a single-crystal silicon wafer6.

[0034] The sidewalls of the vertical structures 6 are smoothed using methods including, but not limited to, low-flow dry etching, low-concentration wet chemical etching, reduced alternating etching and protection process cycles, gas cluster ion beam etching, focused ion beam milling, ion beam etching, and chemical mechanical polishing of the sidewalls with hard mask metal protection on the front side. In one embodiment of the present invention, the deep-etched through-silicon vias are preferably etched using a solution comprising less than 5 wt.% of potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), 10 wt.% to 30 wt.% of isopropyl alcohol, and deionized water. This can produce vertical structures 2 with sidewall roughness less than 5 nm, providing excellent optical and electrical vertical surfaces. In another embodiment of the present invention, the vertical structures are preferably post-etched using one or more low-flow steps of one or more of sulfur hexafluoride (SF6), argon plasma, oxygen plasma, and xenon difluoride (XeF2). The gas flow rate should generally be less than 30 sccm, resulting in vertical structures 6 with sidewall roughness less than 1 nm.

[0035] S15: Deposit an optical antireflection film on the surface of the vertical micromirror and pattern it, leaving only the antireflection film 7 on the sidewall of the vertical micromirror and removing the optical antireflection film on the upper surface ( Figure 1 (f-1), (f-2), (f-3)).

[0036] It should be noted that the substrate region electrode 4 and the gate electrode 5 of the adjustable interferometer arm of the DC voltage modulated MZI of the MOS structure can be arranged in a variety of ways according to the actual depletion layer electric field distribution requirements. The substrate region electrode 4 can be arranged on the upper surface ( Figure 2 (a) and (b) in the figure), double-polished silicon wafers and double-sided processes can also be used to make the bottom surface ( Figure 2 (c) and (d) in the figure); the gate electrode 5 can be on the top of the vertical micromirror ( Figure 2(a) and (c) in the figure), or a ring structure ( Figure 2 (b) and (d) in the figure).

[0037] It should be noted that the structure of a thermo-optically modulated MZI is similar to that of a voltage-modulated MZI, but the electrode material is preferably titanium nitride. The essence of the thermo-optic effect is that the dielectric constant of a material changes with temperature, resulting in a change in the refractive index. Therefore, heating the titanium nitride can change the refractive index of the vertical micromirrors in the adjustable interferometer arms, thereby changing the interference phase of the two beams. The ring electrode structure is also suitable for thermo-optically modulated MZIs.

[0038] It should be noted that the aforementioned MZIs, whether voltage-modulated or thermo-optically modulated, are all MOS structures. However, compared to the MZI with MOS structure, PN junction modulation allows the bias voltage to directly regulate the carrier concentration in the depletion region or the injection region. However, unlike silicon optical waveguides, the depth of the vertical micromirror usually reaches tens of microns or even hundreds of microns. It is very difficult to directly perform ion implantation of tens of microns into the silicon vertical micromirror vertically downward. If only the sidewalls (XZ plane) of the vertical micromirror are implanted with ions, the doping depth is limited and may not be enough to completely cover the entire modulation phase. Therefore, the present invention proposes an adjustable interferometer arm of a comb-tooth PN junction modulation structure to meet the needs of different application scenarios. First, the surface of the vertical micromirror after deep vertical etching and smoothing of the sidewalls is patterned by spraying or two-photon lithography; then, the vertical sidewalls are doped and annealed to form P regions, N regions, P+ regions, and N+ regions. The doping methods of the sidewalls include but are not limited to tilted angle ion implantation, plasma doping (PLAD), etc. ( Figure 3 (a) in FIG); Finally, an electrode is grown and an antireflection film 7 is preferably grown on the surface of the vertical micromirror by atomic layer deposition (ALD) ( Figure 3 (b) in the figure).

[0039] Example 2

[0040] Another application of optical computing is quantum computing. This embodiment provides a method for manufacturing a deep trench beam splitter to achieve a more reliable quantum logic gate. However, the application scenarios of the present invention are not limited to the example given and can also be applied to the manufacturing of beam splitters for other devices.

[0041] S21: First, on the single crystal silicon wafer 1 ( Figure 4The surface of (a-1) and (a-2) is photoetched to form a deep groove pattern; then, a deep groove 8 with a certain angle is etched by a deep etching method; finally, the sidewall of the deep groove is smoothed, and the smoothing method includes but is not limited to high temperature annealing, low flow dry etching, low concentration wet chemical etching, reducing the alternating cycle of etching and protection process, gas cluster ion beam etching, focused ion beam etching milling, ion beam etching, chemical mechanical polishing of the sidewall based on hard mask metal protection front, etc. ( Figure 4 (b-1), (b-2)).

[0042] S22: Depositing an optical thin film 9 in the deep trench 8. Methods for depositing the optical thin film include but are not limited to physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. In order to achieve a deep trench filling with a higher aspect ratio, the atomic layer deposition method is preferred. The deposited optical thin film includes but is not limited to one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium dioxide, etc. ( Figure 4 (c-1), (c-2)).

[0043] S23: First, the outer shape of the deep trench beam splitter is formed by photolithography and deep etching; then, the outer shape of the deep trench beam splitter is smoothed to obtain the vertical sidewall 10 ( Figure 4 (d-1), (d-2)).

[0044] S24: ALD is preferably used to grow an optical antireflection film 11 on the vertical sidewall 10 of the deep trench beam splitter ( Figure 4 (e-1), (e-2)).

[0045] Since the optical film filled in the deep trench plays the role of splitting in the deep trench, and the outer side of the deep trench is single crystal silicon that can play a mechanical support function, its length, thickness and depth are usually greater than or equal to 100 microns. In order to avoid serious Fabry-Perot interference, the thickness of the deeply etched single crystal silicon film directly used as the beam splitter is usually less than or equal to 5 microns. Therefore, the deep trench beam splitter has higher reliability than the single crystal silicon film beam splitter.

[0046] Example 3

[0047] Polarizers and half-wave plates are important optical components. Polarizers based on vertical micromirrors can be implemented not only with the deep groove structure described in Example 2, but also with a grating structure. Gratings can be classified into transmission gratings and reflection gratings.

[0048] Figure 5(a) in the figure shows a schematic structural diagram of a transmissive grating polarizer based on vertical micromirrors. First, nano-gratings or nano-pillars are photolithographically and vertically etched on a single-crystal silicon wafer, and then metal is deposited by physical vapor deposition, preferably using a method such as physical vapor deposition, to form a metal grating 12. When unpolarized light is incident on the metal grating, its electric field components can be decomposed into two orthogonal directions: transverse electric polarization (TE polarization) and transverse magnetic polarization (TM polarization). TE polarized light is strongly suppressed and almost impossible to transmit; while TM polarized light can be efficiently transmitted, forming highly linearly polarized output light. Compared with traditional horizontal metal grating polarizers, the metal grating polarizer based on vertical micromirrors proposed in the present invention not only has a spatial dimensional structure that is suitable for the requirements of optical systems on vertical micromirrors, but also because the vertical grating is supported by the bottom, there is no need to set a substrate support structure in the direction of the light path, thereby reducing losses and simplifying the model without considering equivalent media.

[0049] Figure 5 Although the nano-grating or nano-pillar vertical grating shown in (a) has many advantages, it also has the problem of low structural strength of the nano-grating or nano-pillar, which is suitable for non-high vibration environments. For high vibration environments, the substrate structure 13 can be added, but in this case, the equivalent medium theory needs to be considered, such as Figure 5 As shown in (b) in the figure. There are many methods for its manufacturing process. The present invention provides two feasible methods as embodiments, but the use of other methods to manufacture this structure should not be considered a new method. Method 1: First, use two-photon printing to print grating gaps on the vertical sidewall after vertical deep etching and sidewall smoothing; then, use spraying and photolithography to protect the back side of the vertical sidewall and only expose and develop the side with the grating gaps; finally, preferably use physical vapor deposition to deposit metal and strip off the resist, remove the photoresist and metal on the back side of the vertical sidewall, and the grating gaps and metal printed by two-photon printing, to obtain the vertical metal grating polarizer. Method 2: First, use spraying and photolithography to protect the back side of the vertical sidewall and only expose and develop the front side; then, preferably use physical vapor deposition to deposit metal and strip off the resist, remove the photoresist and metal on the back side of the vertical sidewall, and only retain the metal on the front side of the vertical sidewall; finally, use the grayscale milling function of focused ion beam etching to etch away the metal in the grating gaps, to obtain the vertical metal grating polarizer.

[0050] Half-wave plates and quarter-wave plates can be manufactured using a reflective metal grating structure. The working principle is to introduce a specific phase difference for the TE / TM polarization component during reflection through the grating groove depth and material combination. Figure 5(c) in the figure shows a reflective metal grating wave plate based on a vertical micromirror. There are multiple methods for its manufacturing process. The present invention provides two feasible methods as embodiments, but the use of other methods to manufacture this structure should not be considered a new method. Method 1: First, a grating periodic structure is etched on the vertical sidewall after deep vertical etching and sidewall smoothing using the grayscale milling function of deep reactive ion etching or focused ion beam etching; then, metal is deposited to form a reflective metal grating wave plate 14. Method 2: First, a grating periodic structure is manufactured on the vertical sidewall after deep vertical etching and sidewall smoothing using a two-photon printing method; then, metal is deposited to form a reflective metal grating wave plate 14.

[0051] It should be noted that the two manufacturing methods of wave plates have their own characteristics and meet the needs of different application scenarios. Method 1 is to use the subtractive manufacturing method to manufacture the wave plate of the all-silicon structure, which has better structural stability. Method 2 is to use the additive manufacturing method to manufacture the wave plate, which has higher flexibility in spatial structure design. Its grating periodic structure can be rotated at any angle on the vertical side wall parallel to the XZ plane to achieve different angles with the Z axis. For example, Figure 5 If the structure in (c) is manufactured using method 2, the angle between the grating periodic structure 14 and the Z axis is 0°; Figure 5 The structure in (d) is that the angle between the grating periodic structure 15 and the Z axis is 90°.

[0052] Example 4

[0053] Example 3 illustrates the structure and fabrication method of vertical micromirror-based grating polarizers and wave plates, key components of optical computing chips. Gratings can also serve as spectrometers. This example uses a blazed grating based on vertical micromirrors as an example to illustrate the structure of an on-chip spectrometer. A blazed grating is a reflective grating composed of a set of sawtooth-shaped grooves. By designing the sawtooth groove structure and blaze angle, the blazed grating shifts the main diffraction maximum of a single slit from the zeroth order to the target diffraction order, solving the energy dispersion problem of traditional gratings.

[0054] Figure 6 (a) is a schematic structural diagram of a blazed grating based on a vertical micromirror structure. The blazed grating 16 can be formed by using a subtractive manufacturing method such as deep etching or focused ion beam etching on the vertical sidewall after vertical deep etching and sidewall smoothing to make a serrated groove, and then depositing a metal layer; or it can be formed by using an additive manufacturing method such as two-photon printing on the vertical sidewall after vertical deep etching and sidewall smoothing to make a serrated groove, and then depositing a metal layer.

[0055] Figure 6Figure (b) shows a schematic diagram of an on-chip spectrometer based on a blazed grating with a vertical micromirror structure. Its operating principle is as follows: Light emitted by a laser 17, either epitaxially grown on a single-crystal silicon wafer or through heterogeneous integration, passes through a vertical aperture 18 and reaches a first vertical concave mirror 19. This light is then reflected by a blazed grating 16, which separates the light of different wavelengths into different angles. This light is then reflected by a second vertical concave mirror 20, which focuses the light of different wavelengths at different locations for detection by a detector 21.

[0056] It should be noted that wavelength selection can usually be achieved by deflecting the blazed grating 16. The angular deflection of the blazed grating 16 based on a vertical micromirror structure can be achieved by loading it on a typical MEMS electrostatic actuator structure. Figure 6 The structure shown in (c) is that the blazed grating 16 is made on the vertical cantilever beam 22 to form a moving electrode plate, and the angular deflection of the blazed grating 16 is achieved by applying an electrostatic voltage between the rear vertical fixed electrode plate 23 and the vertical cantilever beam 22. Figure 6 The structure shown in (d) is that a rear vertical fixed electrode plate 23 and a front vertical fixed electrode plate 24 are respectively set before and after the blazed grating 16 is made on the vertical cantilever beam 22 to form a moving electrode plate. The angular deflection of the blazed grating can be achieved by changing the voltage polarity. Figure 6 (e) and Figure 6 Figure (f) shows schematic diagrams of the blazed grating 16 and vertical concave mirror 20 fabricated on a comb-tooth electrostatic drive structure. The comb-tooth electrostatic drive structure consists of a moving electrode plate 25 and independent first, second, third, and fourth fixed electrodes 26, 27, 28, and 29. When the moving electrode plate 25 is connected to the negative power supply voltage and the fixed electrodes 26 and 27 are connected to the positive power supply voltage, the moving electrode plate 25 causes the blazed grating 16 and vertical concave mirror 20 to deflect to the left. When the moving electrode plate 25 is connected to the negative power supply voltage and the fixed electrodes 28 and 29 are connected to the positive power supply voltage, the moving electrode plate 25 causes the blazed grating 16 and vertical concave mirror 20 to deflect to the right.

[0057] It should be noted that the vertical aperture 18 can be a slit type or a circular hole type. Figure 6 The slit-type vertical aperture shown in (g) can be realized by first manufacturing the slit 30 by a vertical deep etching method and then depositing a metal layer on the surface of the slit. Figure 6 The circular hole type vertical aperture shown in (h) can be realized by printing a circular hole structure 31 on the vertical side wall or the bottom of a single crystal silicon wafer using a two-photon printing method, and then depositing a metal layer on the slit surface. In addition, Figure 6The on-chip spectrometer in (b) uses a blazed grating to diffract and disperse complex light, spatially separating and focusing light of different wavelengths to measure spectral intensity. However, this doesn't necessarily mean the core dispersion element must be a blazed grating. It can also be a vertical prism fabricated using deep vertical etching and sidewall smoothing, or using additive manufacturing methods such as two-photon printing.

[0058] Example 5

[0059] In Example 1, the structure and manufacturing process of the vertical micromirrors of the MZI tunable interferometer arms in optical computing, as provided by the present invention, were described. In Examples 2 and 3, the deep-trench beam splitter and the reflective metal grating half-wave plate based on the vertical micromirrors, key optical components in the CNOT gate for quantum computing in optical computing, as provided by the present invention, were respectively described. This example will illustrate how these key optical components are assembled into an optical computing chip on a single-crystal silicon wafer.

[0060] Figure 7 (a) in the figure shows a schematic diagram of an MZI. A beam of light ① is irradiated onto the first beam splitter 32. A beam of reflected light ② passes through the first reflector 33 and the light ③ passes through the first interferometer arm 34 to reach the second beam splitter 35, with a path of ①-②-③. A beam of transmitted light ④ passes through the second interferometer arm 36 and the second reflector 37 and the light ⑤ reaches the third beam splitter 35, with a path of ①-④-⑤. The two beams of light ③ and ⑤ interfere with each other in the third beam splitter 35 to form interference light ⑥. The first interferometer arm 34 and the second interferometer arm 36 can be one of the electrically or thermally adjustable interferometer arms of the MOS structure or PN junction structure described in Example 1.

[0061] Figure 7 (b) in the figure shows a schematic diagram of an embodiment in which the adjustable interferometer arm of Example 1 and the deep trench beam splitter of Example 2 are applied to a Michelson interferometer. One beam of light ① is irradiated onto the third beam splitter 38, one beam is reflected onto the third reflector 39, and then transmitted through the third beam splitter 38 to the detector 40, following the path ①-②-③-④. The other beam of light is transmitted through the third interferometer arm 41, irradiated onto the fourth reflector 42, and then reflected back through the third beam splitter 38 to the first detector 40, following the path ①-⑤-⑥-⑦-⑧-⑨. The third interferometer arm 41 can be one of the electrically or thermally adjustable interferometer arms with a MOS structure or a PN junction structure described in Example 1.

[0062] It should be noted that Figure 7 (a) and Figure 7(b) in the figure only illustrates the MZI and Michelson interferometer commonly used in optical computing as examples. The method of forming an on-chip optical system by combining vertical interferometer arms and deep trench beam splitters on a single crystal silicon wafer in this embodiment is also applicable to other types of interferometers such as Fabry-Perot interferometer and Sagnac interferometer.

[0063] Figure 7 (c) shows a schematic diagram of a two-bit controlled-not-(CNOT) quantum logic gate based on the deep trench beam splitter described in Example 2 and the reflective metal grating half-wave plate described in Example 3. In the CNOT gate, the first half beam splitter 43 and the second half beam splitter 44 form an MZI, into which the control bit enters after input. The third half beam splitter 45 and the fourth half beam splitter 46 form another MZI, into which the target bit enters after input. After the control bit uses the first one-third beam splitter 47, the second one-third beam splitter 48, and the third one-third beam splitter 49 to conditionally control the target bit's phase, the control bit is phase-adjusted by the first reflective metal grating half-wave plate 50 and then output. The target bit is phase-adjusted by the second reflective metal grating half-wave plate 51 and then output. The CNOT gate is also provided with a first collimating lens 52, a second collimating lens 53, a third collimating lens 54, and a fourth collimating lens 55, all of which are formed by two-photon printing additive manufacturing or grayscale milling of focused ion beam etching on the vertical sidewalls after sidewall polishing to ensure the collimation and pattern matching of the light beam. Figure 7 Figure (d) shows a schematic diagram of an on-wafer system integrating an optical computing chip and an electrical chip at the wafer level using vertical micromirrors. Light emitted by a laser 56, either epitaxially grown on a single-crystal silicon wafer or through heterogeneous integration, passes through an on-chip optical computing chip 57 based on vertical micromirrors. The light is then converted to an electrical signal by a second detector 58, which is then integrated with an electrical signal processing chip 59 on an adapter board 60. Multiple adapter boards and computing chips can be integrated on a circuit board 61, with vertical short-distance power supply provided by a bottom power supply module 62.

[0064] Example 6

[0065] As a simplified form of a deep trench beam splitter, the deep wall beam splitter of this embodiment can be used to simplify the process flow in certain situations where high-precision control of the splitting ratio is not required. Generally, it is difficult to etch a vertical silicon wall structure with a thickness less than or equal to the wavelength on a silicon wafer through deep vertical etching. For example, if the vertical silicon wall is 300 microns long (in the X direction), 200 microns deep (in the Z direction), and less than or equal to 1 micron thick (in the Y direction), while designing the appropriate incident light angle according to the Fresnel equation can achieve a specific ratio of reflected and transmitted light, reliability is poor. Thin silicon walls can easily crack, leading to device failure. If the thickness is increased to several times the wavelength, such as 5 to 20 microns, the two sidewalls of the silicon wall (parallel to the X and Z planes) form parallel plates, resulting in multi-beam Fabry-Perot interference. This results in the beam splitting effect being a superposition of the Fresnel equation and Fabry-Perot interference. In order to eliminate Fabry-Perot interference, the two side walls of the silicon wall perpendicular to the substrate can be set at a certain angle (the angle can be obtained by comprehensively considering the Fresnel equation, Fabry-Perot interference and total reflection, preferably 1.5°), forming a prism-shaped deep wall beam splitter 63 (such as Figure 8 As shown in (a) in the figure), its top view is trapezoidal (as shown in Figure 8 As shown in (b) in the figure), the Fabry-Perot interference between the first and second reflections can be eliminated.

[0066] Although the above method eliminates the Fabry-Perot interference between the primary and secondary reflections, the secondary reflection does not enter the primary reflection light path, so the loss of this part of the light intensity should be considered as a system loss. In order to eliminate the Fabry-Perot interference without generating significant system loss, the transmissive sidewall optical antireflection film 64 (such as ) can be deposited on the transmissive sidewall of the deep wall beam splitter 63 by the ALD method. Figure 8 This method is applicable not only to pyramidal deep wall beam splitters, but also to rectangular deep wall beam splitters (such as Figure 8 As shown in (d) in the figure). According to actual needs, the reflecting surface of the prism-shaped beam splitter (such as Figure 8 (e) in the figure) and the reflecting surface of the rectangular deep wall beam splitter (as shown in Figure 8 As shown in (f) in FIG. 5 ), the reflective sidewall optical film 65 is preferably deposited using an ALD method. The transmissive sidewall optical antireflection film 64 and the reflective sidewall optical film 65 can be the same or different, depending on actual needs.

[0067] It should be noted that Figure 8 The angles and size ratios in the figure are just schematic diagrams. When designing angles in actual use, in addition to comprehensively considering the Fresnel equation and Fabry-Perot interference to achieve interference-free spectroscopy, it is also necessary to consider avoiding total reflection.

[0068] Example 7

[0069] Large-scale optoelectronic integrated chip systems have complex structures and processes, so collaborative optimization of design and manufacturing is required during the design and manufacturing process, such as Figure 9 As shown, this embodiment proposes a design-technology co-optimization (DTCO) intelligent manufacturing method for optical computing chips and optoelectronic integrated systems with vertical micromirror structures, which mainly includes: wafer-level system modeling, optoelectronic collaborative architecture design, optoelectronic on-wafer interconnection network simulation design, automatic wiring and multi-physics field coupling simulation optimization, and digital twin manufacturing steps.

[0070] S61: Wafer-level system modeling. At the system level, the wafer is divided into optical computing units, electrical computing units, storage units, control units, and power units. Through system-level modeling, a fully functional wafer-level system architecture is formed.

[0071] S62: Optoelectronic collaborative architecture design. Design the collaborative structure of the core optical computing unit and electrical computing unit within the wafer-level system architecture established in S61, taking into account the top-level optoelectronic collaborative functional architecture, including standardized interfaces, software-defined networks, hierarchical topology, and joint scheduling mechanisms. S63: Simulation Design of Photonics on-Chip Interconnect Network. Design of the Photonics on-Chip Interconnect Network, based on the Photonics Collaborative Functional Architecture established in S62, includes using an adaptive routing algorithm to reduce blocking delays, implementing redundant interconnect design to automatically switch to backup paths in the event of a failure, and reducing idle power consumption through dynamic voltage regulation, thereby realizing a Photonics on-Chip Interconnect Network. S64: Automatic routing and multi-physics coupling simulation optimization. Based on the optoelectronic on-wafer interconnect network completed in S63, an artificial intelligence mapping model is established between manufacturing parameters and device performance. Automatic routing is performed based on functional requirements, and the on-wafer system routing layout is further simulated under multi-physics coupling conditions such as optical, electrical, and thermal. If the simulation results do not fully meet the requirements, the optoelectronic on-wafer interconnect network is optimized based on the results. Repeated iterative optimization is performed until the design achieves the optimal overall performance. S65: Digital Twin Manufacturing. First, a global perception layer is constructed to establish data on integrated circuit manufacturing equipment, cleanroom environments, and microelectronic materials. Next, a multi-dimensional mapping digital manufacturing model is constructed. Furthermore, the on-wafer system wiring layout design completed in S64 is combined with the digital manufacturing model to drive the microelectronics process line, completing the manufacturing of the optoelectronic integrated system. Among them, the chip's process parameters are tested in real time during the manufacturing process, and the drift of equipment parameters is also extracted in real time. Dynamic closed-loop control is implemented based on the test results and equipment parameters, and device performance is predicted, compensated and dynamically adjusted through feedback. The system wiring layout design on the S64 chip is optimized to further optimize and improve system performance.

[0072] It should be noted that, unlike the real-time testing of chip process parameters during the manufacturing process of traditional silicon photonics and CMOS integrated circuits, the real-time testing of online process parameters of optoelectronic integrated on-wafer systems with vertical micromirror structures not only includes measurements of film thickness, sheet resistance, and etching depth of planar structures, but also includes the use of confocal optical profilers to measure the morphology of on-chip spatial optical systems to ensure the normal function of the on-chip optical systems.

[0073] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art that are not disclosed in this application.

[0074] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An optical computing chip with a vertical micromirror structure, characterized in that: The system comprises a plurality of optical modulators and a plurality of quantum logic gates. Interference optical paths in the optical modulators are arranged based on vertical micromirrors to achieve optical modulation. The quantum logic gates construct a stable optical path through reflectors arranged in the vertical micromirrors, use a beam splitter to achieve interference, and perform Hadamard transforms on wave plates at the entrance or exit of the target optical path to achieve optical computing. The quantum logic gate uses a deep trench beam splitter or a deep wall beam splitter as the beam splitter. In the deep wall beam splitter, the silicon wall is perpendicular to the two side walls of the substrate and is arranged at a predetermined angle. The deep trench beam splitter is manufactured by the following method: photolithography is performed on the surface of a single crystal silicon wafer to form a deep trench pattern; deep etching is performed to form a deep trench with a predetermined angle and the side walls are smoothed; an optical thin film is deposited in the deep trench; photolithography and deep etching are performed to form the shape of the deep trench beam splitter and the side walls are smoothed; and an optical anti-reflection film is grown on the vertical side walls.

2. The optical computing chip according to claim 1, characterized in that: The adjustable interferometer arms in the optical modulator are manufactured by thermo-optical modulation and voltage modulation in the following manner: an insulating layer is deposited on the surface of a single-crystal silicon wafer; a heavily doped substrate region is formed by ion implantation and annealing; a metal layer is deposited and annealed to form an ohmic contact substrate region electrode; a gate electrode is formed on the surface-deposited insulating layer; and a vertical micromirror is formed by deep etching a vertical structure on the single-crystal silicon wafer and smoothing the sidewalls. Deposit an optical antireflection film on the surface of the vertical micromirror.

3. The optical computing chip according to claim 1, wherein: The adjustable interferometer arm in the optical modulator adopts PN junction modulation and is manufactured by the following method: A deep etching method is used to carve vertical sidewalls on the surface of a single-crystal silicon wafer and the sidewalls are smoothed to form a number of vertical micromirrors; the surface of the vertical micromirrors is patterned using a spray glue or two-photon lithography method; the vertical sidewalls are doped and annealed to form P regions, N regions, P+ regions, and N+ regions; electrodes are grown and an optical anti-reflection film is grown on the surface of the vertical micromirrors to form adjustable interferometer arms based on a comb-tooth PN junction modulation structure.

4. The optical computing chip according to claim 1, wherein: The quantum logic gate also includes a metal grating polarizer, which is manufactured by: photolithography and vertical deep etching of nano-gratings or nano-pillars on a single-crystal silicon wafer, and depositing metal to form a metal gate; or using two-photon printing to form grating gaps on the vertical sidewalls after vertical deep etching and sidewall smoothing, patterning the sidewalls by spraying and photolithography, depositing metal, and stripping off the glue to obtain a metal gate; or patterning by spraying and photolithography, depositing metal and stripping off the glue, and etching away the metal in the gaps using the grayscale milling function of focused ion beam etching to obtain a metal gate.

5. The optical computing chip according to claim 1, wherein: The quantum logic gate also includes a grating wave plate, which is manufactured by: using the grayscale milling function of deep reactive ion etching or focused ion beam etching on the vertical sidewall after deep vertical etching and sidewall smoothing to etch a grating periodic structure, and depositing metal to form a wave plate with a reflective metal grating structure; or using a two-photon printing method to manufacture a grating periodic structure on the vertical sidewall after deep vertical etching and sidewall smoothing, and depositing metal to form a wave plate with a reflective metal grating structure.

6. The optical computing chip according to claim 1, characterized in that: The quantum logic gate further includes a collimating lens, which is manufactured by: additively manufacturing the vertical sidewalls after the sidewalls are smoothed by two-photon printing, or by reducing the vertical sidewalls by focused ion beam etching and milling.

7. The optical computing chip according to claim 1, characterized in that: The optical modulator and the quantum logic gate both further include a reflector, which is manufactured by: using a deep etching method to carve out vertical sidewalls and smoothing them to form vertical micromirrors, and depositing an optical anti-reflection film on the surface of the vertical micromirrors.

8. The optical computing chip according to claim 1, wherein: The optical computing chip also includes a spectrometer. In the spectrometer, light emitted by a laser manufactured by epitaxial growth on a single-crystal silicon wafer or through heterogeneous integration passes through a vertical aperture and reaches a vertical concave mirror. It is then reflected to a spectrometer element to separate light of different wavelengths into different angles. It is then reflected to a vertical concave mirror and focused to different wavelengths at different positions for detection by a detector.

9. The optical computing chip according to claim 8, characterized in that: A blazed grating is used as the light splitting element, and the blazed grating is manufactured by the following method: After deep vertical etching and smooth sidewalls, a serrated groove is made on the vertical micromirror using additive or subtractive manufacturing methods, and a metal layer is deposited to form a blazed grating.

10. A wafer-level intelligent manufacturing method for an on-wafer system, characterized in that: The on-wafer system includes an optical computing chip with a vertical micromirror structure according to any one of claims 1 to 9, and the method includes: At the system level, the wafer is divided into optical computing units, electrical computing units, storage units, control units, and power supply units, and a wafer-level system architecture is formed through system-level modeling; Based on the wafer-level system architecture, the optoelectronic collaborative functional structure of the optical computing unit and the electrical computing unit is designed; Design an optoelectronic on-chip interconnection network within the optoelectronic collaborative functional architecture. This network uses an adaptive routing algorithm to reduce blocking delays, redundant interconnects to automatically switch to backup paths in the event of a failure, and dynamic voltage regulation to reduce idle power consumption. In the optoelectronic on-wafer interconnect network, an artificial intelligence mapping model between manufacturing parameters and device performance is established, automatic wiring is performed according to functional requirements, and the on-wafer system wiring layout under multi-physics field coupling conditions is simulated. If the simulation results do not meet the requirements, the on-wafer interconnect network is optimized according to the simulation results and then simulated again until the requirements are met; Build a global perception layer, establish data on integrated circuit manufacturing equipment, clean room environments, and microelectronic materials, and construct a multi-dimensional mapping digital manufacturing model. Combine the wiring layout design of the on-chip system and drive the microelectronic process line with the digital manufacturing model to complete the manufacturing of optoelectronic integrated systems. Among them, the chip's process parameters are tested in real time during the manufacturing process, and the drift of equipment parameters is extracted in real time. Dynamic closed-loop control is implemented in combination with the test results and equipment parameters, and device performance is predicted, compensated and dynamically feedback adjusted in advance, and the on-chip system wiring layout design is optimized.

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