Clock monitoring system and method based on multi-parameter comprehensive monitoring and self-adaptive calibration

Abstract

The invention provides a clock monitoring system and method based on multi-parameter comprehensive monitoring and self-adaptive calibration, which are applied to the technical field of digital signal processing, and the method comprises a signal sampling module used for calling an analog-to-digital converter to collect clock signals in real time to obtain input clock data; the digital signal processing module is used for filtering the input clock data to obtain a plurality of target measurement data; the adaptive calibration module is used for comparing the multiple pieces of target measurement data with preset reference data to obtain a deviation value; dynamically generating a control instruction based on the deviation value, and driving a signal generator built in the error code test equipment to perform automatic correction through the control instruction to obtain an internal reference signal output by the signal generator; and the hardware locking module is used for performing high-speed comparison and locking on the input clock data and the internal reference signal through the phase-locked loop and the delay phase-locked loop. According to the invention, the state of the clock signal can be comprehensively and accurately mastered.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a clock monitoring system and method based on multi-parameter comprehensive monitoring and adaptive calibration. Background Art

[0002] In today's high-speed data transmission, error detection (BERT), pattern generators, and other high-precision test equipment, the stability of the input clock signal is crucial for ensuring the accuracy and reliability of test results. Existing technologies primarily rely on traditional phase-locked loop (PLL) or delay-locked loop (DLLL) locking techniques, along with simple digital signal processing methods, to monitor and calibrate clock frequency.

[0003] Most existing technical solutions only monitor the clock frequency, ignoring the comprehensive analysis of multiple key parameters such as jitter, phase noise, and duty cycle, resulting in the inability to fully and accurately reflect the overall status of the clock signal. Summary of the Invention

[0004] The present invention provides a clock monitoring system and method based on multi-parameter comprehensive monitoring and adaptive calibration, which is used to solve the defect that the clock signal processing method in the existing technology cannot fully and accurately reflect the overall state of the clock signal, and realizes comprehensive and accurate grasp of the state of the clock signal through real-time acquisition and comprehensive analysis of multiple parameters.

[0005] The present invention provides a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration, comprising: a signal sampling module, used to call an analog-to-digital converter to perform real-time acquisition of a clock signal to obtain input clock data; a digital signal processing module, communicatively connected to the signal sampling module, used to filter the input clock data to obtain a plurality of target measurement data; an adaptive calibration module, communicatively connected to the digital signal processing module, used to compare the plurality of target measurement data with preset reference data to obtain a deviation value; the adaptive calibration module is further used to dynamically generate a control instruction based on the deviation value, and drive a built-in signal generator of the error test equipment to perform automatic correction through the control instruction to obtain an internal reference signal output by the signal generator; a hardware locking module, communicatively connected to the signal sampling module and the adaptive calibration module respectively, used to perform high-speed comparison and locking of the input clock data with the internal reference signal through a phase-locked loop and a delay phase-locked loop.

[0006] According to the application, a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration is provided, and the digital signal processing module is specifically used for frequency extraction on the input clock data to obtain frequency, jitter analysis on the input clock data to obtain jitter, phase noise analysis on the input clock data to obtain phase noise, and duty cycle test on the input clock data to obtain duty cycle.

[0007] According to the application, a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration is provided, and the distributed detection module is in communication connection with the digital signal processing module and is used for collecting and preprocessing local signal data through multiple preset collection nodes to obtain multiple distributed signals, wherein the local signal data is a clock signal in a target physical coverage range.

[0008] According to the application, a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration is provided, and the system further comprises a data fusion and feedback control platform in communication connection with the distributed detection module and the adaptive calibration module, used for fusing the multiple distributed signals, the multiple target measurement data and the hardware layer signal to obtain a feedback control signal, and driving the adaptive calibration module to perform real-time correction through the feedback control signal.

[0009] According to the application, a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration is provided, and the distributed detection module is further used for monitoring hardware states in the target physical coverage range through multiple preset collection nodes.

[0010] According to the application, a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration is provided, and the hardware locking module is further used for high-speed comparison and locking of the input clock data and the internal reference signal through a digital phase-locked loop.

[0011] The application further provides a clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration, comprising the following steps: calling an analog-to-digital converter to perform real-time collection on a clock signal to obtain input clock data; performing filtering processing on the input clock data to obtain multiple target measurement data; comparing the multiple target measurement data with preset reference data to obtain a deviation value; dynamically generating a control instruction based on the deviation value, and driving a signal generator built in a bit error test device to perform automatic correction through the control instruction to obtain an internal reference signal output by the signal generator; and performing high-speed comparison and locking of the input clock data and the internal reference signal through a phase-locked loop and a delay phase-locked loop.

[0012] The application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration according to any one of the above when executing the program.

[0013] The application further provides a non-transitory computer-readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration according to any one of the above.

[0014] The application further provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration according to any one of the above.

[0015] The application provides a clock monitoring system and method based on multi-parameter comprehensive monitoring and adaptive calibration, which realizes real-time monitoring of clock signals, accurate multi-parameter analysis, closed-loop adaptive calibration and high-speed hardware synchronization, and effectively improves the clock synchronization precision and stability of error code test equipment. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description one by one. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0017] Figure 1 is a structural schematic diagram of the clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration provided by the application.

[0018] Figure 2 is a flowchart of the filtering process provided by the application.

[0019] Figure 3 is a flowchart of the filtering process provided by the application.

[0020] Figure 4 is a flowchart of the filtering process provided by the application.

[0021] Figure 5 It is a flow chart of distributed data collection and fusion provided by the present invention.

[0022] Figure 6 It is a flow chart of feedback control and dynamic adjustment provided by the present invention.

[0023] Figure 7 It is a flow chart of a clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present invention.

[0024] Figure 8 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] In today's high-precision test equipment, such as high-speed data transmission, bit error testers (BERTs), and pattern generators, the stability of the input clock signal is crucial for ensuring the accuracy and reliability of test results. Existing technical approaches primarily rely on traditional locking technologies, such as phase-locked loops (PLLs) or delay-locked loops (DLLs), as well as simple digital signal processing methods, to monitor and calibrate clock frequencies. However, these solutions often have limitations. Some patents or technical solutions focus solely on a single parameter, such as frequency, or local parameters, such as phase noise and jitter, and employ fixed thresholds for anomaly detection and correction. This fails to fully reflect the true state of the clock signal.

[0027] Most existing technical solutions only monitor the clock frequency, ignoring the comprehensive analysis of multiple key parameters such as jitter, phase noise, and duty cycle, resulting in the inability to fully and accurately reflect the overall status of the clock signal.

[0028] Traditional adaptive calibration schemes usually use fixed parameter settings, which are difficult to adapt to dynamic changes caused by environmental factors such as temperature changes, voltage fluctuations, and device aging, affecting the timeliness and accuracy of calibration.

[0029] Existing technologies mainly rely on static thresholds to judge abnormal situations, lack intelligent early warning capabilities based on comprehensive analysis of multi-parameter data, and cannot provide timely intervention and prevention before abnormalities occur.

[0030] The design of a single monitoring node is easily affected by single point failures and lacks the design concept of distributed data collection and fusion, resulting in low stability and reliability of the entire system, making it difficult to meet the needs of high-precision testing.

[0031] This application proposes an input clock monitoring system that integrates multiple classic digital signal processing techniques and adaptive calibration strategies to overcome the shortcomings of existing technologies. Specifically, it includes: The built-in adaptive calibration module is designed to sample the input clock data in real time through a high-speed analog-to-digital converter, extract key data such as frequency, jitter, phase noise and duty cycle, compare it with the preset reference value, calculate the deviation value and automatically adjust the output of the signal generator to achieve closed-loop correction, ensuring the stability and accuracy of the clock signal.

[0032] Advanced digital signal processing algorithms are used to filter, decompose and analyze the collected data, accurately detect various key parameters, provide high-precision data support for subsequent correction processes, and improve the overall performance of the system.

[0033] The collected multi-parameter data are comprehensively evaluated, and abnormal situations are judged through preset thresholds and statistical analysis methods. A feedback closed-loop mechanism is constructed, so that the adaptive calibration module can adjust the calibration strategy according to the dynamic changes of multi-parameter data, thereby improving the system's response speed and correction accuracy.

[0034] Multiple monitoring nodes are arranged in a large-scale test system, and the input clock signal is redundantly monitored using a distributed sampling method. The data of each node is integrated through a high-speed data bus to achieve a unified assessment of the global status, reduce the risk of single point failure, and significantly improve the overall stability and reliability of the system.

[0035] At the hardware level, high-performance PLL or DLL technology is used to compare the input clock signal with the internal high-precision reference signal to achieve high-speed locking and automatic adjustment, providing solid hardware support for the overall calibration process.

[0036] Based on the multi-parameter data and feedback information collected in real time, the system can automatically adjust the calibration parameters to adapt to the dynamic changes of environmental factors such as temperature and voltage, thereby achieving dynamic correction and maintaining long-term stable operation of the system.

[0037] Figure 1 The present invention provides a clock monitoring system based on multi-parameter integrated monitoring and adaptive calibration, which is applied to error detection equipment, such as Figure 1As shown, it specifically includes the following modules.

[0038] The signal sampling module 101 is used to call the analog-to-digital converter to collect the clock signal in real time to obtain input clock data; The digital signal processing module 102 is in communication with the signal sampling module 101 and is used to filter the input clock data to obtain a plurality of target measurement data; The adaptive calibration module 103 is in communication with the digital signal processing module 102 and is used to compare the multiple target measurement data with the preset reference data to obtain a deviation value; The adaptive calibration module 103 is further configured to dynamically generate a control instruction based on the deviation value, and drive the signal generator built into the bit error test device to perform automatic correction through the control instruction, thereby obtaining an internal reference signal output by the signal generator; The hardware locking module 104 is in communication with the signal sampling module 101 and the adaptive calibration module 103 respectively, and is used to perform high-speed comparison and locking of input clock data and an internal reference signal through a phase-locked loop and a delay-locked loop.

[0039] refer to Figure 2 , Figure 2 This is a schematic diagram of the clock monitoring process based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present invention, which includes: starting, collecting input clock signals, extracting multiple parameters through digital signal processing, comparing with preset reference values, calculating deviations, generating control instructions, driving the signal generator to adjust the output, and confirming PLL / DLL lock.

[0040] In an embodiment of the present invention, the signal sampling module uses a high-speed analog to digital converter (ADC) to sample the input clock signal in real time to obtain multiple data including frequency, jitter, phase noise and duty cycle.

[0041] For example, the ADC sampling rate must be at least twice the measured clock frequency (to meet the Nyquist criterion), and an anti-aliasing filter must be configured to eliminate high-frequency noise. The ADC trigger timing is controlled by a field-programmable gate array (FPGA) or a dedicated clock synchronization circuit to accurately capture clock edges and output a discrete input clock data stream containing amplitude, phase, and timestamp information.

[0042] The digital signal processing module performs efficient filtering, decomposition and multi-parameter analysis on the collected signal data, outputs high-precision measurement data, and provides a reliable basis for subsequent processing.

[0043] For example, the input clock data is subjected to noise reduction processing based on a digital filter to filter out high-frequency interference and random jitter; the clock signal's fundamental frequency, phase jitter, duty cycle and other parameters are extracted as target measurement data through fast Fourier transform analysis.

[0044] The adaptive calibration module compares the output of the digital signal processing module with preset reference data, calculates the deviation value, and drives the BERT's built-in signal generator for automatic correction. The calibration strategy can be dynamically adjusted based on real-time feedback data to ensure calibration flexibility and accuracy.

[0045] The preset reference data is stored in non-volatile memory and includes the standard frequency, phase tolerance range, and duty cycle threshold. By comparing the target measurement data with the reference value item by item, deviation values ​​such as frequency deviation and phase offset are calculated.

[0046] Here, in addition to using preset thresholds for static judgment, traditional methods such as statistical analysis and filtering algorithms can also be used to make abnormal judgments on the collected data to achieve similar early warning effects and further enhance the intelligence and early warning capabilities of the system.

[0047] Based on the PID control algorithm (Proportion Integral Differential), digital control instructions (such as voltage tuning signals or frequency compensation coefficients) are dynamically generated and sent to the signal generator (such as a direct digital synthesizer or PLL chip) of the bit error test equipment via the SPI / I2C bus. The output frequency and phase are adjusted to generate a calibrated internal reference signal.

[0048] The hardware locking module adopts high-performance PLL or DLL technology to achieve high-speed comparison and locking of the input clock signal and the internal reference signal, providing precise control at the hardware level to ensure stable operation of the system.

[0049] Here, we can explore the use of digital phase-locked loop (DPLL) or other advanced clock synchronization technologies to further improve the locking speed and interference suppression capabilities, thereby enhancing the system's hardware performance.

[0050] For example, a phase-locked loop (PLL) receives input clock data and an internal reference signal, detects the phase difference through a phase detector, and drives a voltage-controlled oscillator (VCO) to adjust the output frequency to achieve coarse locking of the input signal.

[0051] The delay-locked loop (DLL) fine-tunes the propagation delay of the clock path based on the PLL locking result through a programmable delay line to eliminate metastable errors.

[0052] The integrated high-speed comparator circuit (such as a differential amplifier) monitors the locking state in real time, triggers a dynamic reset mechanism to prevent lock loss, and finally realizes sub-nanosecond synchronization of the input signal and the reference signal.

[0053] Through the embodiments of the present application, the input clock data is collected in real time by the signal sampling module, and the multi-dimensional measurement parameters are extracted after filtering by the digital signal processing module; the adaptive calibration module compares the measurement data with the preset reference value to calculate the deviation, dynamically generates a calibration instruction to drive the built-in signal source of the error code instrument to automatically correct the output reference signal; finally, the hardware locking module compares and locks the input clock and the reference signal at high speed through the phase-locked loop technology, realizes real-time monitoring of the clock signal, accurate analysis of multiple parameters, closed-loop adaptive calibration and high-speed hardware synchronization, and effectively improves the clock synchronization accuracy and stability of the error code test equipment.

[0054] According to the clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present application, the digital signal processing module is specifically used for: extracting the frequency of the input clock data to obtain the frequency; analyzing the jitter of the input clock data to obtain the jitter; analyzing the phase noise of the input clock data to obtain the phase noise; testing the duty cycle of the input clock data to obtain the duty cycle.

[0055] Reference Figure 3 , Figure 3 is a flowchart of the filtering process provided by the present application, which includes: input signal data, filtering, frequency extraction, jitter analysis, phase noise analysis, duty cycle measurement and output of high-precision parameters.

[0056] In some embodiments, the frequency extraction includes: using a built-in high-precision counter to capture the time interval (period number / time base frequency) of adjacent rising edges of the input clock, calculating the instantaneous frequency, which is suitable for low-frequency signals. 1024-point FFT is performed on the time domain data sampled by the ADC, the fundamental frequency is calculated through the position of the main lobe peak of the spectrum, and the resolution is improved to 0.01Hz by using the parabolic interpolation algorithm, which is suitable for high-frequency and complex harmonic environments.

[0057] In some embodiments, the jitter analysis includes: using a time-to-digital converter to measure the deviation of the clock edge from the ideal position, and calculating the peak-to-peak value and the root mean square value. The phase deviation data within 1000 cycles are accumulated to generate a histogram, the random jitter and the deterministic jitter are distinguished by fitting the Gaussian / double Dirac distribution, and the separation index is output.

[0058] In some embodiments, phase noise analysis includes analyzing the noise sidebands of the signal spectrum in the frequency domain. Specifically, this includes performing a fast Fourier transform on the input clock data; observing the noise sidebands near the fundamental frequency; and calculating the phase noise, typically expressed in dBc / Hz as the noise power relative to the carrier power at a specific frequency offset.

[0059] In some embodiments, the duty cycle test includes measuring the ratio of the high-level time of a clock signal to its period. Specifically, this includes detecting the rising and falling edges of the clock signal, calculating the high-level time of each period and the total period, and calculating the duty cycle by dividing the high-level time by the total period.

[0060] Through the embodiments of the present invention, multiple target measurement data are calculated in parallel by the DSP chip of the digital signal processing module (time slice polling), and the results are packaged and transmitted to the adaptive calibration module as the input reference for deviation value calculation, ultimately achieving multi-dimensional closed-loop calibration (such as frequency deviation compensation, duty cycle fine-tuning, etc.).

[0061] According to a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present invention, the system further includes: The distributed detection module is in communication with the digital signal processing module and is used to collect and preprocess local signal data through multiple preset collection nodes to obtain multiple distributed signals, wherein the local signal data is a clock signal within the target physical coverage range.

[0062] In an embodiment of the present invention, a distributed detection module sets up multiple independent acquisition nodes in the system. Each acquisition node is responsible for the acquisition and preprocessing of local signal data, and transmits the data to the central processing module through a high-speed data bus to achieve data redundancy and fusion, thereby improving the reliability of the system.

[0063] In some embodiments, the acquisition nodes utilize multi-channel ADC acquisition boards, with multiple nodes deployed within the target physical coverage area (critical clock path areas) of the target device. For example, the master clock area monitors the frequency stability of the clock source output. Transmission path relay points detect jitter and phase noise in signal transmission. The terminal device area monitors duty cycle and clock skew.

[0064] Each region deploys a primary node and a backup node, and implements failover through hardware switches (such as analog multiplexers).

[0065] In some embodiments, local signal data acquisition includes: input signal conditioning and parameter extraction. For example, each acquisition node integrates front-end signal conditioning circuits (including impedance matching, anti-aliasing filtering, and programmable gain amplifiers) to ensure signal integrity; implements real-time Fast Fourier Transform (FFT) calculations through the local Field Programmable Gate Array (FPGA) of the acquisition node; uses a time interval analyzer core to measure period jitter; and executes a phase demodulation algorithm through a local digital signal processor.

[0066] Local signal data preprocessing includes: using node-built-in filters to eliminate high-frequency noise, extracting key parameters (such as frequency deviation and maximum jitter value) and generating structured data packets, achieving multi-node time synchronization through the IEEE 1588 protocol to ensure data alignment, and using lossless compression algorithms (such as LZW) to reduce transmission bandwidth usage.

[0067] In some embodiments, pre-processed data is transmitted via a CAN bus or Ethernet (EtherCAT) and aggregated to the PCIe interface of a central processing module (e.g., an industrial-grade industrial computer). Kalman filtering or a weighted averaging algorithm is used to fuse multi-node data to generate a global clock status assessment result.

[0068] In terms of data fusion, advanced algorithms such as Kalman filtering and weighted averaging can be used to further improve the accuracy and reliability of multi-node data fusion and optimize the system's data processing capabilities.

[0069] Through the embodiments of the present invention, redundant nodes and data fusion can reduce the risk of single point failure and improve the reliability of the system.

[0070] According to a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present invention, the system further includes: The data fusion and feedback control platform is connected to the distributed detection module and the adaptive calibration module respectively, and is used to fuse multiple distributed signals, multiple target measurement data and hardware layer signals to obtain feedback control signals; and drive the adaptive calibration module to perform real-time correction through the feedback control signals.

[0071] refer to Figure 4 , Figure 4This is an overall schematic diagram of the clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present invention, which includes: input clock signal, high-speed ADC acquisition module, digital signal processing module, multi-parameter data frequency, jitter, phase noise, duty cycle, distributed monitoring points, data fusion and feedback control platform, adaptive calibration module, PLL / DLL locking module and signal generator.

[0072] In an embodiment of the present invention, the data fusion and feedback control platform integrates data from hardware, digital processing modules and monitoring nodes at multiple levels to form a unified feedback signal, guiding the adaptive calibration module to perform real-time and accurate correction, thereby ensuring the improvement of the overall system performance.

[0073] In some embodiments, the data fusion and feedback control platform includes a central processing unit and a high-speed data interface.

[0074] Multi-level fusion can be achieved through Kalman filtering and weighted averaging algorithms. For example, a dynamic model of clock parameters (such as the relationship between frequency drift and temperature change) can be established to predict the parameter value at the next moment. By fusing measured data from multiple nodes with the predicted values, an optimal estimate is generated and output as a global clock state matrix (including fused values ​​such as frequency error and jitter tolerance).

[0075] Hardware-level signal fusion involves correlating data such as the phase error and lock status of the PLL / DLL module with the results of digital signal processing. For example, if the PLL fails to lock but the digital processing indicates a normal frequency, this is considered a hardware failure. If the PLL is locked but the jitter exceeds a certain limit, the adaptive calibration module is triggered to adjust the filter parameters.

[0076] In some embodiments, the global error after input fusion (such as frequency deviation Δf, jitter J) and environmental parameters (temperature T, voltage V) are input, and the data fusion and feedback control platform outputs a feedback control signal (such as DAC adjustment amount, signal generator frequency correction value), and the feedback control signal is encoded into a binary instruction (such as a 16-bit DAC control word) and transmitted to the adaptive calibration module via an Ethernet frame or a custom protocol packet.

[0077] According to a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present invention, the distributed detection module is further used to: The hardware status within the target physical coverage area is monitored through multiple preset collection nodes.

[0078] In some embodiments, multiple acquisition nodes are deployed in key areas of the device (such as clock sources, power modules, and signal transmission paths). Each acquisition node integrates sensors (for temperature, voltage, and clock parameter monitoring) and signal conditioning circuits.

[0079] Acquisition nodes collect data such as voltage, current, and power ripple in real time, detect frequency stability, jitter, and phase noise, and monitor the effects of temperature, humidity, and vibration on hardware. They transmit pre-processed data to a central platform via the CAN bus or Ethernet. Master and backup nodes collect data synchronously, ensuring that single-point failures do not affect monitoring continuity.

[0080] Add hardware status monitoring function to distributed monitoring nodes. When a node detects an abnormality, it can automatically report it and switch to the backup node by the central system, ensuring that the system can continue to operate stably in the event of a failure and improving the system's self-healing ability.

[0081] Through the embodiments of the present invention, multi-node redundancy avoids monitoring blind spots, automatically switches to a standby node in the event of a failure, and multi-dimensional data cross-verifies to reduce the false alarm rate.

[0082] According to a clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present invention, the hardware locking module is further used to: The input clock data is compared and locked with the internal reference signal at high speed through a digital phase-locked loop.

[0083] In some embodiments, a phase detector (PD) compares the phase difference between the input clock signal and an internal reference signal. It outputs a signal proportional to the phase difference (such as a pulse width or a digital error signal). A loop filter (LF) filters out high-frequency noise from the phase detector output, smoothes the error signal, and generates a control signal for adjusting the internal oscillator. A numerically controlled oscillator (NCO) adjusts the oscillation frequency based on the loop filter output, generating an internal reference signal synchronized with the input signal.

[0084] The following describes an example of a clock monitoring system based on multi-parameter integrated monitoring and adaptive calibration provided by the present invention in practical application, which specifically includes the following steps.

[0085] Step 1: Signal acquisition and processing.

[0086] The input clock signal is first sampled by a high-speed ADC, and the sampled data is sent to the digital signal processing module to extract key parameters such as frequency, jitter, phase noise and duty cycle in real time, providing basic data for subsequent calibration and monitoring.

[0087] Step 2: Adaptive calibration loop.

[0088] The adaptive calibration module compares the data output by the digital signal processing module with the preset reference value, calculates the error, and dynamically generates a control instruction according to the error, adjusts the output of the signal generator through closed-loop control, and simultaneously, the PLL / DLL module locks the signal at a high speed, thereby ensuring the stability and accuracy of the clock signal.

[0089] Reference Figure 5 , Figure 5 is a process schematic diagram of distributed data acquisition and fusion provided by the application, comprising: monitoring node 1, monitoring node 2, monitoring node 3, data uploading, central data fusion platform, unified state evaluation and feedback control signal.

[0090] Step 3, distributed data acquisition and fusion.

[0091] The multiple monitoring nodes acquire local data in real time, and transmit the data to the central processing platform (i.e., the central data fusion platform) through a high-speed data bus for redundancy check and data fusion, thereby ensuring the accuracy and reliability of the overall system state and reducing the risk of single-point failure.

[0092] Step 4, feedback control and dynamic adjustment.

[0093] The unified feedback signal formed after multi-level data fusion guides the adaptive calibration module to dynamically adjust the calibration parameters according to real-time data, forms a high-precision, real-time feedback closed-loop correction system, and improves the overall performance and stability of the system.

[0094] Reference Figure 6 , Figure 6 is a process schematic diagram of feedback control and dynamic adjustment provided by the application, comprising: input clock signal, reference signal / VCO, PLL / DLL circuit, locked state output and stable output signal.

[0095] Through the embodiment of the application, through multi-parameter real-time acquisition and comprehensive analysis, the system can comprehensively and accurately master the state of the clock signal, and significantly reduce the error through adaptive closed-loop calibration, thereby ensuring the accuracy and reliability of the test result of the error code instrument. The dynamically adjustable calibration strategy enables the system to automatically adjust the calibration parameters according to the dynamic changes of environmental factors such as temperature, voltage fluctuation and device aging, thereby ensuring the stability and consistency of the clock signal in long-term operation. Through the design of distributed monitoring and data fusion, the risk of single-point failure is eliminated, the stability and data accuracy of the entire test system are improved, and the reliability of the system in high-precision testing is ensured. The PLL / DLL locking technology at the hardware level is combined with the high-precision digital signal processing technology at the software level to form a precise clock management scheme, which is suitable for various application scenarios such as high-speed data communication and precise error code testing.

[0096] The clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present application is described below. The clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration described below can be correspondingly referred to the clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration described above.

[0097] Reference Figure 7 , Figure 7 is a flowchart of the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present application.

[0098] Step 701, calling the analog-to-digital converter to collect the clock signal in real time to obtain input clock data.

[0099] Step 702, filtering the input clock data to obtain a plurality of target measurement data.

[0100] Step 703, comparing the plurality of target measurement data with preset reference data to obtain a deviation value.

[0101] Step 704, dynamically generating a control instruction based on the deviation value, and driving the signal generator built-in the error code test equipment to automatically correct through the control instruction to obtain an internal reference signal output by the signal generator.

[0102] Step 705, comparing and locking the input clock data and the internal reference signal at high speed through the phase-locked loop and the delay-locked loop.

[0103] Specifically, the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration provided by the present application can realize all method steps of the clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration described above, and achieve the same technical effects. Therefore, the same parts and beneficial effects of the method embodiment will not be described in detail.

[0104] Figure 8 An example of an entity structure diagram of an electronic device is shown in FIG. 1. Figure 8As shown, the electronic device can include a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 complete mutual communication through the communications bus 840. The processor 810 can invoke the logic instructions in the memory 830 to execute the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration, which includes: invoking the analog-to-digital converter to collect the clock signal in real time to obtain input clock data; filtering the input clock data to obtain a plurality of target measurement data; comparing the plurality of target measurement data with the preset reference data to obtain a deviation value; dynamically generating a control instruction based on the deviation value, and driving the signal generator built-in the error code test equipment to automatically correct through the control instruction to obtain the internal reference signal output by the signal generator; and comparing and locking the input clock data and the internal reference signal at high speed through the phase-locked loop and the delay-locked loop.

[0105] In addition, the logic instructions in the memory 830 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0106] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration provided by the above methods. The method includes: calling an analog-to-digital converter to perform real-time acquisition of the clock signal to obtain input clock data; filtering the input clock data to obtain multiple target measurement data; comparing the multiple target measurement data with preset reference data to obtain deviation values; dynamically generating control instructions based on the deviation values, and driving the built-in signal generator of the error test equipment to perform automatic correction through the control instructions to obtain the internal reference signal output by the signal generator; and performing high-speed comparison and locking of the input clock data and the internal reference signal through a phase-locked loop and a delay phase-locked loop.

[0107] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration provided by the above-mentioned methods, the method comprising: calling an analog-to-digital converter to acquire the clock signal in real time to obtain input clock data; filtering the input clock data to obtain multiple target measurement data; comparing the multiple target measurement data with preset reference data to obtain deviation values; dynamically generating control instructions based on the deviation values, and driving the built-in signal generator of the error test equipment to perform automatic correction through the control instructions to obtain the internal reference signal output by the signal generator; and performing high-speed comparison and locking of the input clock data and the internal reference signal through a phase-locked loop and a delay phase-locked loop.

[0108] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. That is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0109] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in the various embodiments or some parts of the embodiments.

[0110] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A clock monitoring system based on multi-parameter integrated monitoring and adaptive calibration, applied to bit error test equipment, characterized in that: include: The signal sampling module is used to call the analog-to-digital converter to collect the clock signal in real time to obtain the input clock data; a digital signal processing module, communicatively connected to the signal sampling module, and configured to filter the input clock data to obtain a plurality of target measurement data; an adaptive calibration module, communicatively connected to the digital signal processing module, and configured to compare the plurality of target measurement data with preset reference data to obtain a deviation value; The adaptive calibration module is further configured to dynamically generate a control instruction based on the deviation value, and drive the built-in signal generator of the bit error test device to perform automatic correction through the control instruction, thereby obtaining an internal reference signal output by the signal generator; The hardware locking module is communicatively connected to the signal sampling module and the adaptive calibration module respectively, and is used for performing high-speed comparison and locking of the input clock data and the internal reference signal through a phase-locked loop and a delay-locked loop.

2. The clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration according to claim 1, characterized in that: The digital signal processing module is specifically used to: Performing frequency extraction on the input clock data to obtain a frequency; Performing jitter analysis on the input clock data to obtain jitter; Performing phase noise analysis on the input clock data to obtain phase noise; A duty cycle test is performed on the input clock data to obtain a duty cycle.

3. The clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration according to claim 1, characterized in that: The system further comprises: The distributed detection module is communicatively connected to the digital signal processing module and is used to collect and preprocess local signal data through multiple preset collection nodes to obtain multiple distributed signals, wherein the local signal data is a clock signal within the target physical coverage range.

4. The clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration according to claim 3, characterized in that: The system further comprises: The data fusion and feedback control platform is respectively connected to the distributed detection module and the adaptive calibration module for fusing the multiple distributed signals, the multiple target measurement data and the hardware layer signal to obtain a feedback control signal; and drives the adaptive calibration module to perform real-time correction through the feedback control signal.

5. The clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration according to claim 3, characterized in that: The distributed detection module is further configured to: The hardware status within the target physical coverage area is monitored through multiple preset collection nodes.

6. The clock monitoring system based on multi-parameter comprehensive monitoring and adaptive calibration according to claim 1, characterized in that: The hardware locking module is further configured to: The input clock data and the internal reference signal are compared and locked at high speed through a digital phase-locked loop.

7. A clock monitoring method based on multi-parameter integrated monitoring and adaptive calibration, characterized in that: include: Call the analog-to-digital converter to collect the clock signal in real time to obtain input clock data; Performing filtering on the input clock data to obtain a plurality of target measurement data; Comparing the plurality of target measurement data with preset reference data to obtain a deviation value; Dynamically generate a control instruction based on the deviation value, and drive a built-in signal generator of the error test device to perform automatic correction through the control instruction to obtain an internal reference signal output by the signal generator; The input clock data and the internal reference signal are compared and locked at high speed through a phase-locked loop and a delay-locked loop.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration as claimed in claim 7 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration as claimed in claim 7 is implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the clock monitoring method based on multi-parameter comprehensive monitoring and adaptive calibration as claimed in claim 7 is implemented.

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