Industrial control programming language implementation method based on text coding

Abstract

The invention discloses an industrial control programming language implementation method based on text coding, relates to an information processing technology, and is used for solving the problems of low manual code writing efficiency, high error rate and high threshold in traditional control logic development. Comprising the steps of pre-constructing an explanation text and a language prompt text; loading the description text and the language prompt into an AI dialogue model; inputting a demand and a purpose to the AI dialogue model; the AI dialogue model analyzes the demand and the purpose, carries out processing based on the description text and the language prompt text, generates a corresponding final code, and constructs the final code into a text document; and performing corresponding equipment control based on the text document. According to the method, automatic analysis and code generation are performed through the AI dialogue model, the manual coding time is shortened, and the response is faster.

Description

Technical Field

[0001] The present invention relates to the technical field of information processing, and in particular to a method for implementing an industrial control programming language based on text coding. Background Art

[0002] Industrial control programming is a core technology in the automation field. It focuses on designing, writing, debugging, and maintaining software programs used to control industrial equipment and processes. It directly interacts with the physical world, ensuring the safe, efficient, and reliable operation of production lines, robots, energy facilities, building systems, and more.

[0003] Currently, when using industrial control languages ​​for program development, developers rely on manual code writing. This process is error-prone and inefficient, especially for common problems such as syntax errors and logical loopholes. The cost of subsequent debugging is very high, and developers are required to have strong comprehensive programming skills, which has a high threshold. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems of low efficiency, easy errors and high threshold of manual code writing in traditional control logic development, and to propose an industrial control programming language implementation method based on text encoding.

[0005] The object of the present invention can be achieved by the following technical solution: a method for implementing an industrial control programming language based on text encoding, the method comprising:

[0006] Pre-built instructional text and language prompt text;

[0007] Loading the instruction text and language prompts into the AI ​​dialogue model;

[0008] Input requirements and objectives into the AI ​​dialogue model;

[0009] The AI ​​dialogue model analyzes the requirements and objectives, processes the instructions and the language prompt text, generates corresponding final codes, and constructs the final codes into a text document;

[0010] Based on the text document, corresponding device control is performed.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] This method pre-builds instructional text and voice prompt text within a computer. By inputting requirements and objectives, the AI ​​dialogue model parses these requirements and objectives, matches them with corresponding control logic, and decomposes the control logic into logical steps based on the grammatical rules in the instructional text. The method then processes the instructional text and voice prompt text, analyzes the logical steps, and generates a program structure. This program structure is then converted into a first code based on the BNF grammatical paradigm and the voice prompt text words. The first code is then verified against the voice prompt text words. Once verification is successful, the final code is generated. This automated analysis and code generation through the AI ​​dialogue model reduces manual coding time and provides faster response times. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To facilitate understanding by those skilled in the art, the present invention is further described below with reference to the accompanying drawings.

[0014] Figure 1 is a hardware block diagram of the present invention;

[0015] Figure 2 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0016] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0017] like Figure 1-Figure 2 As shown, a method for implementing an industrial control programming language based on text encoding is implemented based on a computer, a downloader and a chip, including:

[0018] Pre-built explanation text and voice prompt text in the computer, wherein the explanation text includes grammar rules and BNF grammar paradigm; the language prompt text includes structure mandatory verification rules, grammar rule constraint rules, complex logic checking rules, typical error prevention rules, verification mechanism rules, De Morgan's law quick reference table, automatic verification rules and mandatory verification list generation rules;

[0019] Loading the instruction text and language prompts into the AI ​​dialogue model installed in the computer;

[0020] Input requirements and objectives into the AI ​​dialogue model;

[0021] The AI ​​dialogue model analyzes the needs and objectives, matches the needs and objectives with corresponding control logic, and decomposes the control logic into logical steps based on the grammatical rules in the instruction text;

[0022] Based on the description text and the language prompt text, the logic steps are analyzed to generate a program structure, the program structure is generated into a first code according to the BNF grammar paradigm and the language prompt text words, and the first code is verified according to the language prompt text words. After successful verification, the final code is generated;

[0023] The computer converts the text document into the first data, connects the computer to the downloader via the 485 bus, writes the first data into the chip via the downloader, connects the chip to the control device after writing is completed, and downloads the first data into the control device, after downloading is completed, the control device executes the first data to perform corresponding control.

[0024] The specific process of converting the text document into the first data is: converting each line of characters in the text document into numbers according to the conversion rule, and obtaining the first data after all lines in the text document are converted.

[0025] It should be noted that the BNF grammar paradigm is specifically as follows:

[0026] / *Overall architecture* /

[0027] <Program>::=<File header><Fixed blank line>{3}<Repeat file header><Main text>+<Terminator>

[0028] <File header>::=[0-9A-Z]{4}".[0-9A-V][1-5][0-4]"C"<Line break>

[0029] <Fixed blank line>::="00000000"<line break>

[0030] <Repeat file header>::=<file header> / *Must be exactly the same as the first file header* /

[0031] <Main text>::=<line><newline>|<blank line>

[0032] <Terminator>::="END"<Line break>

[0033] <line>::=<first paragraph><last paragraph>|<first paragraph><new line>

[0034] / *When the lower character ↓ or upper character ↑ appears at the beginning of this line, it can be followed by <newline>* /

[0035] <front section>::=<front section with lower continuation>|<front section with upper continuation>|<normal front section>

[0036] <before the substring>::=<conditional field><substring>

[0037] <Preceding segment with preceding symbol>::=<Conditional field><Preceding symbol>

[0038] <Normal front section>::=<Conditional field>

[0039] <blank line>::=<new line>

[0040] / *The condition field is fixed to 4 characters* /

[0041] <Conditional field>::=<Control element><Connector>|<Through condition>|<Empty condition>

[0042] <Control Element>::=<Input Node>|<Output Node>|<Relay Node>|<Function Interface>|<Instrument Node>

[0043] <Input node>::="E""E"<hexadecimal number> / / Example: EE0

[0044] <Output Node>::="F""E"<Hexadecimal Number> / / Example: FE7

[0045] <Relay node>::=[HN]<Hexadecimal number>{2} / / Example: K1F (intermediate relay / functional element)

[0046] <Function interface>::=[HN]<Hexadecimal number>{2} / / Shares syntax with relay nodes and must be distinguished by ^ / *

[0047] <Instrument Node>::="F"[0-3][0-9A-F] / / Example: F0D (virtual instrument)

[0048] <Through condition>::=<Through character>{4}

[0049] <Empty condition>::=<space>{4}

[0050] / *When using a straight-through condition or an empty condition in the preceding section, you cannot add a <connector>. Error example: ----=FE0 (the correct value should be ----FE0)* /

[0051] <Later section>::=<node operation>|<function element declaration>|<function definition domain>|<parameter setting domain>|<function element operation>

[0052] <node operation>::=<positive node operation>|<negative node operation>

[0053] <positive node operation>::=<letter><hexadecimal number>{2}

[0054] <Inverse node operation>::=<letter><inverse symbol><hexadecimal number>{2}

[0055] <Function element declaration>::=<Positive function element declaration>|<Negative function element declaration>

[0056] <Positive function declaration>::=<function letter><hexadecimal number>{2}<encapsulation symbol>

[0057] <Negative function element declaration>::=<function element letter><negation symbol><hexadecimal number>{2}<encapsulation symbol>

[0058] <Function element operation>::=<Positive function element operation>|<Negative function element operation>

[0059] <Positive function element operation>::=<function element letter><hexadecimal number>{2}<operator>

[0060] <Negative function element operation>::=<function element letter><negation symbol><hexadecimal number>{2}<operator>

[0061] <Function definition domain>::=<Function definition domain without parameters>|<Function definition domain with parameters>|<Function definition domain with preset parameters>

[0062] <Non-parameter function definition domain>::=[AZ][0-9A-Z]

[0063] <Function definition domain with parameters>::=[AZ][0-9A-Z]<Addressing character>[0-3][0-9A-V]

[0064] <Preset parameter function definition domain>::=[AZ][0-9A-Z]<Addressing character>[0-3][0-9A-V]<Preset character>

[0065] <Parameter setting field>::=<number>{4} / / must appear in the last position

[0066] / *Lexical elements, all letters are allowed to be uppercase, no lowercase* /

[0067] <number>::=[0-9]

[0068] <Letter>::=[AZ]

[0069] <Function element letter>::=[HN]

[0070] <Hexadecimal number>::=[0-9A-F]

[0071] <Connector>::="="|"\"

[0072] <Through character>::="-"

[0073] <Space>::=""

[0074] <character>::=<number>|<letter>|<connector>|<straight character>|<space>

[0075] <Line break>::="\n"

[0076] <Following character>::="↓"

[0077] <Extension character>::="↑"

[0078] <Inverter>::="!"

[0079] <Addressing symbol>::="@"

[0080] <Encapsulation>::="^"

[0081] <Default symbol>::="$"

[0082] <Operator>::="*".

[0083] The grammar rules include:

[0084] Symbol judgment priority and contextual grammar rules;

[0085] Symbol judgment priority:

[0086] First, determine whether there is an <encapsulation character> in the <following section>. If so, the <following section> of this line is identified as a <functional element declaration>.

[0087] The <segment> of the line following the encapsulation character “^” must not be a space and must be a <function definition domain>;

[0088] Then determine whether there is a <preset symbol> in the <function definition domain>. If so, the <function definition domain> is identified as a <preset parameter function definition domain>.

[0089] The <last paragraph> of the next line of <preset parameter function definition field> must not be a space and must be <parameter setting field>.

[0090] Control elements:

[0091] symbol type scope Example EEx Input Node x:0-F EE0,EE9 FEx Output Node x:0-F FE0,FEF Hxx,Ixx,Jxx,Kxx,Lxx,Mxx,Nxx Relay Node xx:00-FF H01,H1A Hxx,Ixx,Jxx,Kxx,Lxx,Mxx,Nxx Functional elements xx:00-FF HEF,K2F,LFF,L28 Fxy Instrument Node x:0-3y:0-F F08,F3B

[0092] Note: The first letters of relay nodes and functional elements can be H, I, J, K, L, M, and N. When used as functional elements in the latter part, they must be used with the encapsulation character "^" or the operator "*". Each type of functional element can be classified by letter according to custom, such as Kxx for delay functional elements and Lxx for trigger functional elements. Users can adjust according to their own habits.

[0093] Single condition control:

[0094]

[0095] Note: When the negation symbol "!" is used for an output node or intermediate relay, it indicates reverse control of the node.

[0096] Cross-node negation is prohibited: F! E0 represents the negation operation of the FE0 node, rather than the negation of the previous condition.

[0097] Combinational logic:

[0098] Example 1 (parallel connection):

[0099] Parallel support up to 16 lines.

[0100] …

[0101] EE0=↓ / / Line 1: When EE0 is turned on, parallel connection is enabled, affecting the state of FE0;

[0102] EE1=↓ / / Line 2: When EE1 is turned on, it continues to be connected in parallel, affecting the state of FE0;

[0103] EE2=↑FE0 / / Row 3: When EE2 is turned on, the parallel connection is terminated, affecting the state of FE0;

[0104] …

[0105] Equivalent logic: EE0 OR EE1 OR EE2→FE0.

[0106] Example 2 (parallel connection):

[0107]

[0108] Equivalent logic: When EE0 is turned on, FE0 and FE1 output, and FE2 and FE3 output are turned off; when EE0 is turned off, FE0 and FE1 output are turned off, and FE2 and FE3 output.

[0109] Example 3 (parallel connection):

[0110]

[0111] Equivalent logic: (EE0 OR EE1 OR EE2→FE0) at the same time (EE0 OR EE1 OR EE2→FE1) at the same time (EE0 OR EE1 OR EE2→FE2).

[0112] Example 4 (concatenation):

[0113] Since the P language is limited to two segments, serial connection cannot be used directly. This example shows how to implement serial connection by parallel inverse logic.

[0114] …

[0115] EE0\↓ / / When EE0 is disconnected, FE0 turns off the output;

[0116] EE1\↑F! E0 / / When EE1 is disconnected, FE0 turns off the output;

[0117] …

[0118] The truth table is as follows:

[0119]

[0120] Implementation principle:

[0121] After negating the conditions of the series logic, combine them in parallel (parallel connection of NOT EE0 and NOT EE1);

[0122] The node operation is inverted, which is ultimately equivalent to EE0 AND EE1→FE0 being turned on.

[0123] Truth table verification:

[0124] NOT EE0 OR NOT EE1→NOT FE0 is equivalent to EE0 AND EE1→FE0.

[0125] Note: When multiple conditions are connected in parallel in the first part of the program and the negation symbol "!" appears in the second part, it can be regarded as the output result of multiple conditions (normally open or normally closed contacts are opposite to those in parallel) connected in series.

[0126] Concatenation logic grammar rules:

[0127] When using serial logic, the output result must contain the negation character "!";

[0128] The negation symbol "!" in the latter part is limited to the current node operation and does not affect the logical relationship of the previous condition.

[0129] Calculation order: (result of previous condition) → (node ​​operator);

[0130] Principle of serial logic implementation:

[0131] / / Realize EE0 AND EE1→H00;

[0132] EE0\↓ / / Condition 1: NOT EE0→H! 00;

[0133] EE1\↑H!00 / / Condition 2: NOT EE1→H!00;

[0134] Truth table:

[0135] EE0 EE1 Intermediate Logic H00 final state 0 0 1 OR 1→1 NOT(1)=0 0 1 1 OR 0→1 NOT(1)=0 1 0 0 OR 1→1 NOT(1)=0 1 1 0 OR 0→0 NOT(0)=1

[0136] The essence of serial transformation is the transformation through De Morgan's law: The negation operator only changes the node output behavior and does not participate in conditional operations.

[0137] / / Verification case: three conditions in series;

[0138] EE0\↓

[0139] EE1\↓

[0140] EE2\↑H!00 / / equivalent to H00=EE0 AND EE1 AND EE2.

[0141] / / Test case:

[0142] / / 1.EE0=1,EE1=1,EE2=1→H00=1

[0143] / / 2.EE0=0,EE1=1,EE2=1→H00=0

[0144] / / 3.EE0=1,EE1=0,EE2=1→H00=0

[0145] / / 4. All 0 input → H00 = 0.

[0146] Compound logic:

[0147] …

[0148] EE0=↓

[0149] EE1\↑H!01

[0150] H01=↓

[0151] EE2=↑FE0

[0152] …….

[0153] Parsing process:

[0154] 1. EE0 normally closed contact;

[0155] 2. Connect the normally open contact of EE1 in series;

[0156] 3. Activate intermediate relay H01;

[0157] 4. Parallel the normally open contact of EE2;

[0158] 5. Final drive FE0.

[0159] Mandatory specification: When parallel / series logic exists before a functional element (^), an intermediate relay aggregation condition must be used, and direct access to the functional element declaration line is prohibited.

[0160] Node operation restrictions:

[0161] 1. In the entire program, each node in the latter part can only appear once;

[0162] / / Error example (even if the operation direction is the same);

[0163] EE0=H!01 / / 1st operation H01;

[0164] EE1=H01 / / Second operation H01 → violation of rules;

[0165] EE2=H!01 / / The third operation H01→violation of the rules;

[0166] 2. The use of nodes in the front end is not restricted.

[0167] / / Allow: H01 to be used multiple times in the conditional field;

[0168] EE0=H01 / / Operation H01 (the only operation in the latter part);

[0169] H01=FE0 / / Allow: The conditional field uses H01 (the previous section can be reused);

[0170] H01=FE1 / / Allowed: The conditional field uses H01 (the previous section can be reused).

[0171] The principle of strengthening the uniqueness of the latter part:

[0172] 1. Each physical output node (FEx) in the entire program:

[0173] -Can only be operated once in a later stage;

[0174] - whether negated or not (!);

[0175] -When multiple conditions need to be applied to the same node at the same time, all conditions must be summarized (parallel / series / compound logic) before operating the node. Repeated operations cannot be performed multiple times.

[0176] 2. The same principle applies to intermediate relays (Hxx-Nxx):

[0177] / / ×Example of violation of principle;

[0178] EE0=H01 / / First operation H01;

[0179] EE1=H01 / / Secondary operation H01→error.

[0180] Basic usage rules for the following characters:

[0181] Core rules with ↓ lines:

[0182] Allows the preceding condition to be empty or the following operation to be empty;

[0183] The next line must contain valid logical content.

[0184] 3. Rules for adding the symbol ↑:

[0185] ↑ must appear in the last line of a parallel structure and cannot appear alone (the preceding or following paragraph must have content);

[0186] The content of the next line after ↑ has nothing to do with the parallel structure where ↑ is located;

[0187] Each parallel structure must have only one ↑.

[0188] Error example:

[0189] EE0=↑FE0

[0190] ↓FE1 / / Error: The next line after the ↓ character has no valid content and is not related to the previous line.

[0191] Correct example:

[0192] EE0=↓ / / Correct: No operation + there is a connection next;

[0193] EE1=↑FE0 / / Continue the conditions of the previous line and terminate in parallel;

[0194] Separate back row (continuing row):

[0195] Must be indented 4 spaces;

[0196] Must be followed by the line with ↓;

[0197] It can be continued with ↓ (needs to be followed by content) or terminated with ↑.

[0198] Correct example:

[0199] EE0=↓

[0200] ↓FE0 / / with ↓ continuation;

[0201] ↑FE1 / / Terminator alignment.

[0202] Hierarchical transfer rules:

[0203]

[0204] Complete example analysis:

[0205] Correct structure:

[0206]

[0207] Error structure:

[0208]

[0209]

[0210] Design specification:

[0211] Depth limit: maximum transfer depth 15 levels;

[0212] Acceptance conditions: acceptance line can be a single condition (empty after section), single operation (empty before section) or normal line;

[0213] When there are multiple conditions that need to operate functional elements, it is best to first summarize the conditions to intermediate relays and then operate.

[0214] Verification rules:

[0215] ↓ must be valid line (empty operation needs to be accepted);

[0216] The last stage of the acceptance line cannot be with ↓;

[0217] The function definition domain with empty before section cannot be used as an acceptance line;

[0218] Normal line is prohibited to be directly followed by an acceptance line;

[0219] ↑ forced rules:

[0220] All parallel structures must be explicitly terminated with ↑;

[0221] ↑ is prohibited to appear in the last line;

[0222] The last position of the acceptance line must be with ↑ (such as ↑FE0);

[0223] ↑ is prohibited to be used alone.

[0224] Quick reference table

[0225]

[0226] Language prompt text words include:

[0227] I. Structure forced verification:

[0228] 1. File header verification:

[0229] Must contain double file header and the content is exactly the same;

[0230] Format verification: ^ [0-9A-Z] {4}. [0-9A-V] [0-5] [0-4] C $.

[0231] Example: A001.010C;

[0232] Error interception:

[0233] A00a.01C / / contains lowercase letters;

[0234] A001.010D / / does not end in C.

[0235] 2. Paragraph structure:

[0236] File header → 3 blank lines → repeat file header → body → END;

[0237] Empty lines must be 00000000;

[0238] The end character must be a separate line END.

[0239] 2. Grammatical rule constraints:

[0240] 1. Node operation specifications:

[0241] Input node: ^E[E][0-9A-F]$ Example: EE0;

[0242] Output node: ^F[E][0-9A-F]$ Example: FE7;

[0243] Relay node: ^[HN][0-9A-F]{2}$ Example: K1F.

[0244] 2. The principle of strengthening the uniqueness of the latter part:

[0245] 2.1. Each physical output node (FEx) can only be operated (assigned a value) once in a subsequent step in the entire program;

[0246] Regardless of whether it is negated (!).

[0247] 2.2. The same principle applies to intermediate relays (Hxx-Nxx):

[0248] / / Example of violation of principle;

[0249] EE0=H01 / / First operation H01;

[0250] EE1=H01 / / Secondary operation H01→error.

[0251] 2.3 Principle of strengthening the uniqueness of the latter part:

[0252] Negation operation specifications:

[0253] The negation character ! is only allowed to appear after the last node letter;

[0254] Legal: F!E0,H!01;

[0255] Illegal: !FE0,F!0E;

[0256] Forward / reverse operations on the same node are considered repeated operations.

[0257] 3. Symbol Usage Standards (Newly Added↑Rules)

[0258]

[0259]

[0260] 4. Connector logic:

[0261] = indicates normally open contact connection;

[0262] \ indicates a normally closed contact connection;

[0263] Error interception: ----=FE0 (through condition with connector).

[0264] 3. Compound logic check (newly added ↑ rules)

[0265] 1. Serial logic implementation specifications (mandatory);

[0266] AND logic must be transformed using De Morgan's laws:

[0267] A AND B=NOT (NOT A OR NOT B).

[0268] Correctly implement the template:

[0269] <Condition 1>\↓ / / Condition 1 is negated

[0270] <Condition 2>\↑<node>! / / Condition 2 is negated and terminated.

[0271] 2. Parallel structure verification (enhancement):

[0272] The ↓ symbol must continue to the valid operation line;

[0273] Each parallel structure must be explicitly terminated with ↑;

[0274] The maximum connection depth is 15 layers;

[0275] Error interception:

[0276]

[0277]

[0278] 3. Functional component packaging process:

[0279] Declaration line (including ^) → definition domain → [parameter domain]

[0280] Formatting rules:

[0281] a. Function definition domain line:

[0282] Must appear immediately after the function declaration line containing ^;

[0283] Must be indented 4 spaces;

[0284] The first part must be empty (four spaces).

[0285] No other rows can be inserted in between.

[0286] b. Parameter setting field line:

[0287] Must be placed immediately after the function domain line;

[0288] Must be indented 4 spaces;

[0289] The first part must be empty (four spaces);

[0290] Must be 4 decimal digits.

[0291] Legal examples:

[0292]

[0293]

[0294] Error interception:

[0295]

[0296] Error interception:

[0297] EE0=K0F^

[0298] T0@00$ / / Four spaces are required before the function definition domain;

[0299] 1000 / / Four spaces are required before the parameter setting field.

[0300] 4. Functional element front-end parallel processing specifications (correct structure):

[0301]

[0302] 4. Error Prevention (New ↑ Rules)

[0303] 1. Parameter setting area;

[0304] Must be a 4-digit decimal number;

[0305] Error interception: 0A00 (including letters) / 123 (less than 4 digits);

[0306] 2. Conflict between functional components;

[0307] Package range check (e.g. T0 occupies 16-bit address).

[0308] Error interception:

[0309] K0F^→T0@00$ / / occupies K00-K0F.

[0310] K01^→RS / / Address conflict.

[0311] 3. Specifications for the use of upper continuation symbols;

[0312] Must appear in the last row of the parallel structure;

[0313] ↑The following line is prohibited;

[0314] ↑It is prohibited to appear alone.

[0315] Error interception:

[0316] EE0=↑ / / used alone↑;

[0317] EE0=↓FE0 / / unused↑terminated;

[0318] ↑ / / ↑ appears alone.

[0319] 4. Series logic missing inversion:

[0320] Phenomenon: When implementing serial logic, the parallel structure contains multiple conditions but does not use the "!" operator;

[0321] Hazard: Actually implements OR logic instead of AND;

[0322] Interception rule: When implementing series logic, an alarm is triggered when the parallel branch of the structure is greater than 1 and the subsequent operation is not inverted.

[0323] 5. Verification Mechanism Example (Updated↑Example)

[0324] Correct structure example

[0325]

[0326]

[0327] Error structure example

[0328]

[0329] Parallel structure termination verification:

[0330] IF (the current line is the last line of the parallel block) THEN

[0331] The ↑ symbol must be used

[0332] The ↓ symbol is prohibited

[0333] ENDIF.

[0334] 6. De Morgan's Law Quick Lookup Table (Updated to ↑ End)

[0335]

[0336] 7. Automatic verification rules (enhanced↑ inspection)

[0337] File structure integrity scan;

[0338] Symbol context validity check;

[0339] Global node operation record table maintenance;

[0340] Deduction of compound logic truth tables;

[0341] Automatic scanning of conflicting addresses;

[0342] ↑Symbol Validator:

[0343] 1. Check if each parallel block has one and only one ↑;

[0344] 2. Verify that ↑ appears in the last line;

[0345] 3. After confirmation, there is no accepting bank;

[0346] 4. It is prohibited to use ↑ alone (it must be used in conjunction with the conditional field).

[0347] Parameter setting field writing specifications:

[0348] 1. Must occupy a separate line;

[0349] 2. There must be only 4 spaces (U+0020) at the beginning of a line;

[0350] 3. The end of the line must be 4 decimal digits (if insufficient, fill with zeros);

[0351] 4. Any other characters are prohibited.

[0352] Correct example:

[0353] 0100 / / 4 spaces + 4 digits;

[0354] Error interception:

[0355] 0100 / / Missing space;

[0356] 0100 / / only 3 spaces;

[0357] A100 / / contains non-numeric characters;

[0358] 8. AI generates mandatory checklist (newly added ↑ rule); 1. Parallel termination check:

[0359] IF the current line is the end of the parallel block THEN;

[0360] You must use ↑;

[0361] ↓ is prohibited;

[0362] After checking, there is no taking over bank.

[0363] 2. Check the inversion operation:

[0364] The following operations of IF include ! THEN;

[0365] Verify whether the node has repeated operations;

[0366] Confirm! immediately after the node letter;

[0367] 3. Verify the position of the upper character:

[0368] IF ↑ THEN appears;

[0369] Confirm that there is ↓ to open parallel connection before;

[0370] Confirm that this is the last line of this parallel block;

[0371] There is no acceptance content after confirmation.

[0372] Example 1:

[0373] Needs and Purpose:

[0374] When button EE0 is turned on, it enters the automatic control state: FE0 is turned on to drive the cylinder forward;

[0375] When the cylinder moves forward to the front limit EE2 or FE0 is connected for more than 3 seconds, FE0 is disconnected and the cylinder moves backward;

[0376] When the cylinder moves back to EE3, FE0 is connected again to drive the cylinder forward, and the process repeats in sequence.

[0377] When EE1 is connected, the automatic control state is exited and FE0 is disconnected.

[0378] Decomposition of the control logic of the AI ​​dialogue model for needs and purposes:

[0379] 1. When the button EE0 is turned on, it enters the self-control state (maintained by a self-locking state, for example, using an RS trigger).

[0380] 2. In the automatic control state, FE0 is connected (the cylinder moves forward).

[0381] 3. When the cylinder moves forward to the front limit EE2 or FE0 is connected for more than 3 seconds, disconnect FE0 (cylinder moves backward).

[0382] Note: There are two conditions (EE2 or timeout) that can disconnect FE0. Therefore, we need a condition to reset FE0.

[0383] 4. When the cylinder retreats to the rear limit EE3, connect FE0 again (cylinder moves forward) to form a cycle.

[0384] 5. When EE1 is connected, it exits the automatic control state and FE0 is disconnected.

[0385] step:

[0386] 1. Use an RS flip-flop (functional element RS) to maintain the self-control state (set to L01). The start condition is EE0 and the stop condition is EE1.

[0387] 2. In the automatic control state, we need to control the on and off of FE0. The on and off logic of FE0 is:

[0388] - When the self-control state is started (L01=1) and the disconnection condition is not reached, FE0 is turned on.

[0389] - There are two disconnection conditions: EE2 (front limit) or a 3-second delay (starting from FE0 connection).

[0390] 3. When FE0 is disconnected, the cylinder moves backward until it hits the rear limit EE3. At this time, FE0 should be restarted (i.e., the conditions for resetting FE0).

[0391] Note: The disconnection and restart of FE0 here are cyclically controlled within the self-control state.

[0392] Program structure:

[0393] Step 1: File Header

[0394] Step 2: Blank Line

[0395] Step 3: Repeat the file header

[0396] Step 4: Program Body

[0397] 1) Automatic control state trigger (L01):

[0398] EE0=L00* / / Set terminal

[0399] EE1=L01^ / / Reset terminal

[0400] RS

[0401] L01=H00 / / Output the automatic control status to the intermediate relay H00.

[0402] Code:

[0403]

[0404]

[0405] The preferred embodiments of the application disclosed above are only to help explain the present application. The preferred embodiments do not describe all the details of the present application, and do not limit the present application to only the specific embodiments. Obviously, many modifications and variations can be made according to the content of the present description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well understand and utilize the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for implementing an industrial control programming language based on text encoding, characterized in that: The method includes: Pre-built instructional text and language prompt text; Loading the instruction text and language prompts into the AI ​​dialogue model; Input requirements and objectives into the AI ​​dialogue model; The AI ​​dialogue model analyzes the requirements and objectives, processes the instructions and the language prompt text, generates corresponding final codes, and constructs the final codes into a text document; Based on the text document, corresponding device control is performed.

2. The method for implementing an industrial control programming language based on text encoding according to claim 1, characterized in that: The description text includes grammar rules and BNF grammar paradigm; the language prompt text includes structure mandatory verification rules, grammar rule constraint rules, compound logic checking rules, typical error prevention rules, verification mechanism rules, De Morgan's law quick lookup table, automatic verification rules and mandatory verification list generation rules.

3. The method for implementing an industrial control programming language based on text encoding according to claim 2, characterized in that: The specific process of the AI ​​dialogue model parsing the requirements and objectives is as follows: For the control logic that matches the requirements and objectives, the control logic is decomposed into logical steps according to the grammatical rules in the description text.

4. The method for implementing an industrial control programming language based on text coding according to claim 3, characterized in that: The specific process of processing based on the description text and language prompt text is as follows: The logic steps are analyzed to generate a program structure, and the program structure is used to generate a first code based on the BNF grammar paradigm and language prompt text words. The first code is then verified based on the language prompt text words. After successful verification, the final code is generated.

5. The method for implementing an industrial control programming language based on text encoding according to claim 1, characterized in that: Based on the text document, the specific process of controlling the corresponding device is as follows: The text document is converted into first data, connected to the downloader via the 485 bus, and the first data is written into the chip via the downloader. After the writing is completed, the chip is connected to the control device, and the first data is downloaded to the control device. After the download is completed, the control device executes the first data for corresponding control.

6. The method for implementing an industrial control programming language based on text coding according to claim 1, characterized in that: The specific process of converting the text document into the first data is: Each line of characters in the text document is converted into numbers according to a conversion rule, and first data is obtained after all lines in the text document are converted.

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