Method for realizing PUF (Physical Unclonable Function) by using homomorphic write-in of FRAM (Frequency Random Access Memory) of 2T2C structure

Abstract

The invention discloses a method for realizing PUF (Physical Unclonable Function) by using homomorphic write-in of an FRAM (Frequency Random Access Memory) of a 2T2C structure, which comprises the following steps of: firstly, carrying out independent write-in operation on two ferroelectric capacitors and writing same data, and carrying out homomorphic storage; then, the two ferroelectric capacitors are recovered to different residual polarization states by using the manufacturing difference of the ferroelectric capacitors; then applying a reverse level to enable the two ferroelectric capacitors to reach a saturated polarization state from a residual polarization state; and finally, comparing a difference value delta I of the polarization current responses of the two ferroelectric capacitors, and outputting a corresponding binary numerical value according to the difference value delta I and a set judgment condition, thereby generating a random PUF response. According to the invention, the PUF response with high randomness and uniqueness is generated through homomorphic storage of the 2T2C FRAM and by using the polarization characteristic of the ferroelectric material.

Description

Technical Field

[0001] The present invention belongs to the field of information security and storage technology, and specifically is a method for realizing PUF (physical unclonable function) based on FRAM (Ferroelectric Random Access Memory) with a 2T2C (2Transistor / 2Capacitor, two transistors / two ferroelectric capacitors) structure. Background Art

[0002] The number of internet-connected devices is exploding, and traditional encryption methods based on digital keys are struggling to meet the growing security demands. Compared to traditional encryption methods, PUF technology leverages tiny random variations introduced during the hardware manufacturing process to generate unique, unclonable physical keys. Its inherent advantages in physical-layer encryption can, to a certain extent, effectively overcome side-channel attacks and machine learning modeling. Among the many silicon PUFs, memory PUFs, due to their high security, unclonability, and wide applicability, are becoming an ideal solution for future hardware security authentication and key management.

[0003] Traditional memories, such as dynamic random access memory (DRAM) and flash memory (Flash), have limitations in performance, energy consumption, and durability. DRAM relies on capacitors to store data, and charge leaks over time, requiring continuous refresh operations to prevent data loss. This not only increases power consumption but also reduces system energy efficiency. Furthermore, the DRAM write process involves charge and discharge operations, and in high-frequency read and write scenarios, its storage cells are susceptible to aging, resulting in insufficient durability.

[0004] In the demand scenarios of low power consumption, non-volatility and high write endurance, ferroelectric memory becomes an important research direction. Ferroelectric material has a unique crystal structure, which can produce spontaneous polarization under the action of an external electric field, and maintain this polarization state after the electric field is removed. The electric dipoles in the ferroelectric material will change direction under the action of an external electric field, forming a reversible polarization flipping process. This polarization flipping characteristic enables ferroelectric materials to be used for storing information, because it can maintain a stable polarization state without an electric field, thereby realizing non-volatile data storage. Ferroelectric materials represented by hafnium-zirconium oxide (HfZrO2, HZO) have become the preferred material for the next generation of ferroelectric memories because of their compatibility with CMOS processes, low power consumption, high switching speed and excellent scalability. In the process of growing ferroelectric materials, such as thin film deposition and annealing, there are subtle differences in the remanent polarization (Pr) values of different units due to nanoscale physical variations. These differences are random and unclonable, providing a unique physical identifier for PUF. By applying different electric fields or temperature treatments, the polarization state of the HZO unit can be partially or completely reset, and this type of PUF has the function of reconfigurability.

[0005] Compared with 1T1C FRAM, 2T2C structure FRAM can provide more storage units and better charge storage capability, and has important research value in the fields of information security such as hardware security, Internet of Things, embedded systems, intelligent hardware and physical attack resistance. However, although 2T2C FRAM has obvious advantages in storage density and charge stability, its potential as a PUF entropy source has not been fully explored. SUMMARY

[0006] In view of the deficiencies of the prior art, the technical problem to be solved by the present application is to provide a method for implementing PUF using homomorphic writing of FRAM with 2T2C structure.

[0007] The technical solution of the present application to solve the technical problem is to provide a method for implementing PUF using homomorphic writing of FRAM with 2T2C structure, characterized in that the method comprises the following steps:

[0008] Step 1, initialization and writing operation: first, initialize the storage unit of the FRAM with 2T2C structure to make the initial states of the two ferroelectric capacitors the same; then perform independent writing operations on the two ferroelectric capacitors and write the same data to perform homomorphic storage;

[0009] Step 2, use the manufacturing differences of ferroelectric capacitors to make the two ferroelectric capacitors return to different remanent polarization states;

[0010] Step 3: applying a reverse voltage to make the two ferroelectric capacitors reach a saturated polarization state opposite to the write timing of step 1 from the remanent polarization state of step 2;

[0011] Step 4: Compare the difference ΔI of the polarization current responses of the two ferroelectric capacitors from the remanent polarization state to the saturation polarization state with the opposite writing timing of step 1, and then output the corresponding binary value based on the difference ΔI and the set decision condition, thereby generating a random PUF response.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] (1) This invention proposes a PUF design based on a 2T2C memory cell. Through homomorphic storage in 2T2C FRAM, the polarization properties of ferroelectric materials are utilized to generate a highly random and unique PUF response. This design can simultaneously store 1 bit of data and generate a 1-bit encryption key using process variation. By reusing hardware resources, this design achieves the dual functions of data storage and key generation in a single cell without requiring additional area overhead. This design boasts high security, non-replicability, and low power consumption, making it suitable for hardware security authentication, encryption key generation, and IoT devices.

[0014] (2) In response to the problem that the traditional 2T2C architecture requires two storage units (four capacitors) to generate 1 bit of encrypted data in PUF generation, the present invention proposes a PUF generation method based on a single 2T2C unit. By optimizing the read and write timing, the same data is written into the two capacitors of a single unit, and the PUF response is extracted using process variation. Compared with heterogeneous writing, the present invention simplifies timing control and significantly reduces the unit area required for PUF generation, thereby improving hardware efficiency while ensuring PUF performance.

[0015] (3) The 2T2C structure, with its mature commercial background and highly scalable manufacturing process, provides a more ideal technical platform for PUF research than the 1T1C structure. By extracting the inherent process variation characteristics of 2T2C, this invention can efficiently achieve PUF response generation while significantly reducing the technical risks and costs of physical implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is the overall flow chart of the present invention;

[0017] Figure 2 Schematic diagram of the electric hysteresis characteristics of the ferroelectric material of the present invention;

[0018] Figure 3 A structural diagram of a single memory cell of a 2T2C FRAM of the present invention;

[0019] Figure 4 A PV curve diagram of the ferroelectric capacitor used in Example 1 of the present invention;

[0020] Figure 5 This is an IV curve diagram of the ferroelectric capacitor used in Example 1 of the present invention. DETAILED DESCRIPTION

[0021] The specific embodiments of the present invention are given below. The specific embodiments are only used to further illustrate the present invention and do not limit the scope of protection of the present invention.

[0022] The present invention provides a method for implementing PUF by homomorphic writing of FRAM with a 2T2C structure (hereinafter referred to as the method), characterized in that the method comprises the following steps:

[0023] Step 1: Initialization and write operation: First, initialize the memory cell of the 2T2C structure FRAM so that the initial states of the two ferroelectric capacitors are the same; then apply write timing to the memory cell, and simultaneously perform independent write operations on the two ferroelectric capacitors with the same data, thus performing homomorphic storage;

[0024] Preferably, in step 1, homomorphic storage is specifically: when both ferroelectric capacitors need to store 1, a high level is applied to the bit line (BL) and a low level is applied to the plate line (PL). At this time, the state of the ferroelectric material in the ferroelectric capacitor is at the vertex of the hysteresis loop in the first quadrant; when both ferroelectric capacitors need to store 0, a low level is applied to the bit line (BL) and a high level is applied to the plate line (PL). At this time, the state of the ferroelectric material in the ferroelectric capacitor is at the vertex of the hysteresis loop in the third quadrant.

[0025] Preferably, in step 1, the memory cell of the 2T2C structure FRAM is composed of two transistors and two ferroelectric capacitors, such as Figure 3 As shown; each memory cell can store 1 bit of data, and through specific write timing and read mechanisms, manufacturing differences are used to generate encryption keys; two ferroelectric capacitors store the same information.

[0026] Preferably, in step 1, the ferroelectric material of the memory cell of the 2T2C structure FRAM is a hafnium oxide ferroelectric material doped with zirconium, lanthanum, aluminum, and strontium.

[0027] Preferably, in step 1, Figure 3 The two transistors are MOS1 and MOS2, and the two ferroelectric capacitors are Fecap1 and Fecap2.

[0028] Step 2: utilizing manufacturing differences of ferroelectric capacitors to restore the two ferroelectric capacitors to different remanent polarization states;

[0029] Preferably, step 2 is specifically: the manufacturing difference of ferroelectric capacitors will cause the remanent polarization (Pr) of the two capacitors to deviate, so when the two ferroelectric capacitors of step 1 are both written with data 1, and the two ferroelectric capacitors are restored to the remanent polarization state, the state of the ferroelectric material in the ferroelectric capacitor is at the intersection of the hysteresis loop and the Y-axis of the hysteresis loop plane rectangular coordinate system; when the two ferroelectric capacitors of step 1 are both written with data 0, and the two ferroelectric capacitors are restored to the remanent polarization state, the state of the ferroelectric material in the ferroelectric capacitor is at the intersection of the hysteresis loop and the Y-axis of the hysteresis loop plane rectangular coordinate system.

[0030] Step 3, apply a reverse level to make the two ferroelectric capacitors from the remanent polarization state of step 2 to the saturation polarization state opposite to the write timing sequence of step 1;

[0031] Preferably, in step 3, when the two ferroelectric capacitors of step 1 are both written with data 1, the two ferroelectric capacitors are made to reach the saturation polarization state opposite to the write timing sequence of step 1, which requires applying a low level to the bit line (BL) and a high level to the plate line (PL), at this time the state of the ferroelectric material in the ferroelectric capacitor is at the top of the hysteresis loop in the third quadrant; when the two ferroelectric capacitors of step 1 are both written with data 0, the two ferroelectric capacitors are made to reach the saturation polarization state opposite to the write timing sequence of step 1, which requires applying a high level to the bit line (BL) and a low level to the plate line (PL), at this time the state of the ferroelectric material in the ferroelectric capacitor is at the top of the hysteresis loop in the first quadrant.

[0032] Step 4, the manufacturing difference of the two ferroelectric capacitors will cause different polarization current responses when they are from the remanent polarization state to the saturation polarization state opposite to the write timing sequence of step 1; by comparing the difference ΔI of the current responses of the two ferroelectric capacitors with the set decision condition, the corresponding binary value 0 or 1 is output, thereby generating a random PUF response.

[0033] Preferably, in steps 1, 2, and 3, the excitation is a level signal applied to the storage unit, and in step 4, the response is a digital signal obtained by comparison.

[0034] Preferably, in step 4, the polarization current of the ferroelectric capacitor is in the order of μA.

[0035] Preferably, in step 4, the generation of the PUF response is based on the manufacturing difference of the two capacitors.

[0036] Preferably, in step 4, the judgment condition is: according to the size relationship between the difference ΔI and 0, the output binary value 0 or 1 is set; for example, it is stipulated that when ΔI>0, the binary value 1 is output, and when ΔI<0, the binary value 0 is output, or it is stipulated that when ΔI>0, the binary value 0 is output, and when ΔI<0, the binary value 1 is output.

[0037] Example 1:

[0038] In step 1, write 1, and the ferroelectric material is in Figure 2 Point A (the hysteresis loop is located at the vertex of the first quadrant); Figure 4 This is a set of hysteresis loop data of ferroelectric materials actually tested;

[0039] In step 2, the two ferroelectric capacitors are restored to the remanent polarization state, where the ferroelectric material is in Figure 2 Point B (the point where the hysteresis loop intersects the Y axis); Figure 4 As shown, even devices prepared under the same process will have a unique slight deviation, and the remnant polarization states of the two ferroelectric capacitors will have deviations;

[0040] In step 3, a reverse voltage is applied, and the ferroelectric material is in Figure 2 Point C (the hysteresis loop is located at the vertex of the third quadrant);

[0041] In step 4, the two ferroelectric capacitors are obtained from the +Pr state ( Figure 2 Point B) to the saturated negative polarization state ( Figure 2 The polarization current generated by each of the two polarization currents (point C) is obtained, and the difference between the two polarization currents ΔI is obtained; it is defined that when ΔI>0, the output is 1, and when ΔI<0, the output is 0. Therefore, if Figure 5 As shown, ΔI<0, and binary data 0 is output.

[0042] Example 2:

[0043] In step 1, write 0, and the ferroelectric material is in Figure 2 Point C (the hysteresis loop is located at the vertex of the third quadrant);

[0044] In step 2, the two capacitors are restored to the remanent polarization state, where the ferroelectric material is in Figure 2 Point D (the negative intersection of the hysteresis loop and the Y axis);

[0045] In step 3, a reverse voltage is applied, and the ferroelectric material is in Figure 2 Point A (the hysteresis loop is located at the vertex of the first quadrant);

[0046] In step 4, the two ferroelectric capacitors are obtained from the -Pr state ( Figure 2 Point D) to the saturated forward polarization state ( Figure 2The polarization current generated by each of the two polarization currents (at point A) is then calculated, and the difference ΔI between the two polarization currents is obtained; then, according to the judgment conditions, the corresponding binary data 0 or 1 is output.

[0047] Any matters not described in the present invention are applicable to the prior art.

Claims

1. A method for implementing PUF using homomorphic writing of FRAM with a 2T2C structure, characterized in that: The method comprises the following steps: Step 1: Initialization and write operation: First, initialize the storage unit of the 2T2C structure FRAM so that the initial states of the two ferroelectric capacitors are the same; then, perform independent write operations on the two ferroelectric capacitors and write the same data to perform homomorphic storage; Step 2: utilizing manufacturing differences of ferroelectric capacitors to restore the two ferroelectric capacitors to different remanent polarization states; Step 3: applying a reverse voltage to make the two ferroelectric capacitors reach a saturated polarization state opposite to the write timing of step 1 from the residual polarization state of step 2; Step 4: Compare the difference ΔI of the polarization current responses of the two ferroelectric capacitors from the remanent polarization state to the saturation polarization state with the opposite writing timing of step 1, and then output the corresponding binary value based on the difference ΔI and the set decision condition, thereby generating a random PUF response.

2. The method for implementing PUF using homomorphic writing of 2T2C structured FRAM according to claim 1, characterized in that: In step 1, homomorphic storage is specifically: when both ferroelectric capacitors need to store 1, a high level is applied to the bit line and a low level is applied to the plate line. At this time, the state of the ferroelectric material in the ferroelectric capacitor is at the vertex of the hysteresis loop in the first quadrant; when both ferroelectric capacitors need to store 0, a low level is applied to the bit line and a high level is applied to the plate line. At this time, the state of the ferroelectric material in the ferroelectric capacitor is at the vertex of the hysteresis loop in the third quadrant.

3. The method for implementing PUF using homomorphic writing of 2T2C structured FRAM according to claim 1, characterized in that: In step 1, a memory cell of a 2T2C structured FRAM is composed of two transistors and two ferroelectric capacitors; the two ferroelectric capacitors store the same information.

4. The method for implementing PUF using homomorphic writing of 2T2C structured FRAM according to claim 1, characterized in that: In step 1, the ferroelectric material of the memory cell of the 2T2C structure FRAM is a hafnium oxide ferroelectric material doped with zirconium, lanthanum, aluminum, and strontium.

5. The method for implementing PUF using homomorphic writing of 2T2C structured FRAM according to claim 1, characterized in that: Step 2 is specifically: taking advantage of the manufacturing differences of ferroelectric capacitors, when data 1 is written into both ferroelectric capacitors in step 1, the two ferroelectric capacitors are restored to the residual polarization state, and the state of the ferroelectric material in the ferroelectric capacitor is at the orthogonal intersection of the hysteresis loop and the Y axis of the rectangular coordinate system of the plane where the hysteresis loop is located; when data 0 is written into both ferroelectric capacitors in step 1, the two ferroelectric capacitors are restored to the residual polarization state, and the state of the ferroelectric material in the ferroelectric capacitor is at the negative intersection of the hysteresis loop and the Y axis of the rectangular coordinate system of the plane where the hysteresis loop is located.

6. The method for implementing PUF by homomorphic writing of 2T2C structure FRAM according to claim 1, characterized in that: In step 3, when data 1 is written into both ferroelectric capacitors in step 1, the two ferroelectric capacitors reach a saturated polarization state opposite to the write timing of step 1, and a low level needs to be applied to the bit line and a high level needs to be applied to the plate line. At this time, the state of the ferroelectric material in the ferroelectric capacitor is at the vertex of the hysteresis loop in the third quadrant; when data 0 is written into both ferroelectric capacitors in step 1, the two ferroelectric capacitors reach a saturated polarization state opposite to the write timing of step 1, and a high level needs to be applied to the bit line and a low level needs to be applied to the plate line. At this time, the state of the ferroelectric material in the ferroelectric capacitor is at the vertex of the hysteresis loop in the first quadrant.

7. The method for implementing PUF by homomorphic writing of 2T2C structure FRAM according to claim 1, characterized in that: In step 4, the decision condition is: according to the magnitude relationship between the difference ΔI and 0, the output binary value is set to 0 or 1.

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