Test circuit, display substrate and display device

Abstract

A test circuit, a display substrate and a display device relate to the technical field of display. The test circuit is located on one side of the display substrate and comprises a plurality of control lines extending in the first direction; the test lines extend along a second direction, and the second direction and the first direction intersect with each other; grid electrodes of the switch transistors are connected with the control lines, first poles of the switch transistors are connected with the test lines, and second poles of the switch transistors are connected with data lines in the display substrate; wherein the plurality of test lines comprise first test lines and second test lines which are arranged at intervals along a first direction, the plurality of switch transistors comprise first switch transistors and second switch transistors, the first switch transistors are connected with the first test lines, the second switch transistors are connected with the second test lines, and the first test lines and the second test lines are arranged along a second direction. The first switch transistor and the second switch transistor are staggered from each other.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a test circuit, a display substrate, and a display device. Background Art

[0002] Before a display panel leaves the factory, a test device is usually used to perform a lighting test on the display panel to check whether the display panel can display normally. In related art, the test device is generally connected to the pixels through a test circuit to perform the lighting test on the pixels. Summary of the Invention

[0003] The present disclosure provides a test circuit located on one side of a display substrate, comprising:

[0004] a plurality of control lines extending along a first direction;

[0005] a plurality of test lines, the test lines extending along a second direction, the second direction intersecting the first direction; and

[0006] a plurality of switch transistors, wherein a gate of each switch transistor is connected to the control line, a first electrode of each switch transistor is connected to the test line, and a second electrode of each switch transistor is connected to a data line in the display substrate;

[0007] Among them, the multiple test lines include a first test line and a second test line arranged at intervals along the first direction, the multiple switching transistors include a first switching transistor and a second switching transistor, the first switching transistor is connected to the first test line, and the second switching transistor is connected to the second test line. Along the second direction, the first switching transistor and the second switching transistor are staggered with each other.

[0008] In some embodiments, orthographic projections of the first switching transistor and the second switching transistor on a first reference plane do not overlap, and the first reference plane is a plane perpendicular to the first direction.

[0009] In some embodiments, orthographic projections of the first switching transistor and the second switching transistor on a second reference plane have an overlapping region, and the second reference plane is a plane perpendicular to the second direction.

[0010] In some embodiments, a ratio of a size of the overlapping region along the first direction to a size of the switch transistor along the first direction is greater than or equal to one-fifth and less than or equal to four-fifths.

[0011] In some embodiments, the first test lines and the second test lines are alternately arranged in sequence in the first direction, a plurality of the first switching transistors connected to different first test lines are roughly aligned in the second direction, and a plurality of the second switching transistors connected to different second test lines are roughly aligned in the second direction.

[0012] In some embodiments, the plurality of control lines include a first control line and a second control line arranged at intervals along the second direction, the first control line is connected to the gate of the first switch transistor, and the second control line is connected to the gate of the second switch transistor;

[0013] The second control line is located on a side of the first control line away from the first test line. The orthographic projections of the first control line and the second test line on the display substrate intersect each other, and the first control line and the second test line are arranged in different layers.

[0014] In some embodiments, the test circuit further includes a lead, one end of the lead is connected to the first control line, and the other end of the lead is connected to the second control line.

[0015] In some embodiments, the first control line and the second control line are insulated from each other.

[0016] In some embodiments, the active layer of the switching transistor includes a channel portion, and one or more slits are provided on the active layer. The extension direction of the slits is parallel to the length direction of the channel portion, and the multiple slits are arranged along the width direction of the channel portion.

[0017] In some embodiments, the active layer further includes a first connecting portion and a second connecting portion located on both sides of the channel portion, the first connecting portion being connected to the first electrode of the switching transistor, and the second connecting portion being connected to the second electrode of the switching transistor;

[0018] Along the length direction of the channel portion, the slit completely penetrates the channel portion and ends at a junction between the first connecting portion and the channel portion, and at a junction between the second connecting portion and the channel portion.

[0019] In some embodiments, along a length direction of the channel portion, the slit completely penetrates the active layer.

[0020] In some embodiments, a length direction of the channel portion is parallel to the first direction or the second direction.

[0021] In some embodiments, the gate and active layer of the switching transistor are stacked in a direction perpendicular to the display substrate, and the switching transistor further includes a blocking gate located on a side of the active layer facing away from the gate;

[0022] The test circuit further includes a plurality of shielding lines extending along the first direction, the shielding lines and the shielding gate are arranged in the same layer and are interconnected, the control lines and the gate are arranged in the same layer, and the shielding lines and the control lines are interconnected.

[0023] In some embodiments, in the length direction of the channel portion, the size of the shielding gate is larger than the size of the gate, and the gate is centered relative to the shielding gate, and the shielding gate is used to shield light incident on the channel portion.

[0024] The present disclosure provides a display substrate, comprising a base substrate, and a display area and a non-display area arranged on one side of the base substrate;

[0025] The display area includes a plurality of scan lines extending along the first direction and a plurality of data lines extending along the second direction, wherein the orthographic projections of the scan lines and the data lines on the base substrate intersect with each other to form a plurality of sub-pixels;

[0026] The non-display area includes the test circuit as described in any one of the items, the test line is connected to the data line through the switch transistor, and the second electrode of the switch transistor is connected to the data line.

[0027] In some embodiments, the plurality of data lines are divided into a plurality of data line groups, each data line group including a plurality of data lines, and different data lines in the same data line group are connected to sub-pixels in the same pixel unit but with different colors;

[0028] The test lines connected to different data lines in the same data line group include a first test line and / or a second test line that are adjacently arranged.

[0029] In some embodiments, the plurality of data line groups include a first data line group and a second data line group that are adjacently disposed, the test lines connected to different data lines in the first data line group are a plurality of first test lines that are adjacently disposed, and the test lines connected to different data lines in the second data line group are a plurality of second test lines that are adjacently disposed;

[0030] The data lines in the first data line group are connected to the switching transistor via a first adapter line, and the data lines in the second data line group are connected to the switching transistor via a second adapter line. The orthographic projections of at least one of the first adapter lines and at least one of the second adapter lines on the base substrate intersect with each other, and the intersecting first adapter lines and second adapter lines are arranged in different layers.

[0031] In some embodiments, in the first patch cord and the second patch cord that cross each other, the first patch cord is provided on the same layer as the test line and the data line, and the second patch cord is provided on the same layer as the control line; or

[0032] In the first adapter wire and the second adapter wire that cross each other, the first adapter wire and the control wire are arranged on the same layer, and the second adapter wire and the test wire and the data wire are arranged on the same layer.

[0033] In some embodiments, the non-display area includes a test area and a binding area disposed opposite to each other along the second direction, the test circuit is located in the test area, and the binding area includes a plurality of pins;

[0034] Multiple test lines are divided into multiple test units, different test units include the same number of test lines, and multiple test lines in the same test unit are sorted along the first direction. Test lines located in the same test unit with different serial numbers are connected to different pins, and test lines located in different test units with the same serial number are connected to the same pin.

[0035] The present disclosure provides a display device, comprising:

[0036] The display substrate according to any one of the preceding claims; and

[0037] The driving circuit is connected to the display substrate and is used to drive the display substrate to perform display.

[0038] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0040] Figure 1 A schematic diagram of a planar structure of a test circuit in the related art is shown;

[0041] Figure 2 The schematic diagram of the planar structure of the first test circuit provided by the present disclosure is exemplarily shown;

[0042] Figure 3 exemplarily shows a planar structural diagram of a second test circuit provided by the present disclosure;

[0043] Figure 4 Schematically shows a planar structural diagram of a third test circuit provided by the present disclosure;

[0044] Figure 5 exemplarily shows a planar structural diagram of a fourth test circuit provided by the present disclosure;

[0045] Figure 6 The characteristic curve of a switching transistor using a bulk active layer is exemplarily shown;

[0046] Figure 7 The characteristic curve of a switching transistor using a slit active layer is shown as an example;

[0047] Figure 8 The cross-sectional structure diagram of a switching transistor provided by the present disclosure is exemplarily shown;

[0048] Figure 9 A schematic diagram of a planar structure of a display substrate is exemplarily shown;

[0049] Figure 10 The following is a schematic diagram showing a connection structure between a first test circuit and a data line;

[0050] Figure 11 The following is a schematic diagram showing a connection structure between a second test circuit and a data line;

[0051] Figure 12 The following is a schematic diagram showing a connection structure between a third test circuit and a data line;

[0052] Figure 13a The schematic diagram of the planar structure of the display substrate after the shielding layer is prepared is shown as an example;

[0053] Figure 13b The schematic diagram of the planar structure of the display substrate after the active layer preparation is shown as an example;

[0054] Figure 13c The schematic diagram of the planar structure of the display substrate after the first metal layer is prepared is shown as an example;

[0055] Figure 13d The schematic diagram of the planar structure of the display substrate after the first through hole is prepared is shown as an example;

[0056] Figure 13e The schematic diagram of the planar structure of the display substrate after the second metal layer is prepared is shown as an example;

[0057] Figure 13f The schematic diagram of the planar structure of the display substrate after the second through hole and the third through hole are prepared is exemplarily shown. DETAILED DESCRIPTION

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0059] Reference Figure 1 A schematic diagram of a test circuit in a traditional display substrate is shown. The test circuit includes multiple thin-film transistors, and the multiple thin-film transistors are arranged in a straight line in the row direction. For high-resolution display substrates or specially designed thin-film transistors, there is a problem of insufficient space in the row direction for the test circuit.

[0060] In order to solve the above problems, the present disclosure provides a test circuit located on one side of the display substrate. Figures 2 to 5 As shown in any one of the figures, the test circuit includes: a plurality of control lines CL, which extend along a first direction f1; a plurality of test lines TL, which extend along a second direction f2, and the second direction f2 intersects with the first direction f1; and a plurality of switching transistors SW, wherein the gate G of the switching transistor SW is connected to the control line CL, the first electrode S of the switching transistor SW is connected to the test line TL, and the second electrode D of the switching transistor SW is connected to the data line DL in the display substrate.

[0061] Among them, the multiple test lines TL include a first test line TL1 and a second test line TL2 arranged at intervals along the first direction f1, and the multiple switching transistors SW include a first switching transistor SW1 and a second switching transistor SW2. The first switching transistor SW1 is connected to the first test line TL1, and the second switching transistor SW2 is connected to the second test line TL2. Along the second direction f2, the first switching transistor SW1 and the second switching transistor SW2 are staggered with each other.

[0062] In the test circuit provided by the present disclosure, since the first switching transistor SW1 and the second switching transistor SW2 are staggered in the second direction f2, the lateral space in the first direction f1 can be fully utilized, thereby increasing the lateral layout space of the switching transistor SW, thereby increasing the number or size of the lateral layout of the switching transistor SW, which is beneficial to improving the resolution of the screen or improving the characteristics of the switching transistor SW.

[0063] Exemplarily, the second direction f2 is perpendicular to the first direction f1 .

[0064] In some embodiments, as Figures 2 to 5 As shown in any one of the figures, the orthographic projections of the first switching transistor SW1 and the second switching transistor SW2 on the first reference plane do not overlap, and the first reference plane is a plane perpendicular to the first direction f1.

[0065] In some embodiments, as Figures 2 to 5 As shown in any one of the figures, there is an overlapping area between the orthographic projections of the first switching transistor SW1 and the second switching transistor SW2 on the second reference plane, and the second reference plane is a plane perpendicular to the second direction f2.

[0066] Since the orthographic projections of the first switching transistor SW1 and the second switching transistor SW2 on the second reference plane overlap with each other, full utilization of the space in the first direction f1 is achieved.

[0067] In some embodiments, a ratio of a size of the overlapping region along the first direction f1 to a size of the switch transistor SW along the first direction f1 is greater than or equal to one-fifth and less than or equal to four-fifths.

[0068] In some embodiments, as Figures 2 to 5 As shown in any one of the figures, the first test lines TL1 and the second test lines TL2 are alternately arranged in sequence in the first direction f1, and the multiple first switching transistors SW1 connected to different first test lines TL1 are roughly aligned in the second direction f2, and the multiple second switching transistors SW2 connected to different second test lines TL2 are roughly aligned in the second direction f2.

[0069] like Figures 2 to 5 As shown in any one of the figures, the first test lines TL1 and the second test lines TL2 are alternately arranged one by one in the first direction f1.

[0070] The plurality of first switching transistors SW1 being substantially aligned in the second direction f2 means that the positions of the plurality of first switching transistors SW1 in the second direction f2 are consistent or consistent within an acceptable deviation range. The plurality of second switching transistors SW2 being substantially aligned in the second direction f2 means that the positions of the plurality of second switching transistors SW2 in the second direction f2 are consistent or consistent within an acceptable deviation range. The acceptable deviation range is determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

[0071] For example, Figures 2 to 5 As shown in any one of the figures, a plurality of first switch transistors SW1 connected to different first test lines TL1 are arranged along a straight line in a first direction f1 , and a plurality of second switch transistors SW2 connected to different second test lines TL2 are arranged along a straight line in the first direction f1 .

[0072] In some embodiments, as Figures 2 to 5 As shown in any one of the figures, the multiple control lines CL include a first control line CL1 and a second control line CL2 arranged at intervals along a second direction f2. The first control line CL1 is connected to the gate G of the first switching transistor SW1, and the second control line CL2 is connected to the gate G of the second switching transistor SW2. The second control line CL2 is located on a side of the first control line CL1 away from the first test line TL1. The orthographic projections of the first control line CL1 and the second test line TL2 on the display substrate intersect each other. The first control line CL1 and the second test line TL2 are arranged on different layers to prevent a short circuit between the first control line CL1 and the second test line TL2.

[0073] like Figures 2 to 4 As shown in any one of the figures, the gate G of the first switch transistor SW1 is the region where the first control line CL1 overlaps with the active layer ACT of the first switch transistor SW1 , and the gate G of the second switch transistor SW2 is the region where the second control line CL2 overlaps with the active layer ACT of the second switch transistor SW2 .

[0074] like Figure 5 As shown, the gate G of the first switching transistor SW1 is connected to the first control line CL1 and is located on the side of the first control line CL1 close to the second control line CL2. The gate G of the second switching transistor SW2 is connected to the second control line CL2 and is located on the side of the second control line CL2 close to the first control line CL1. The gate G of the first switching transistor SW1 overlaps with the active layer ACT of the first switching transistor SW1, and the gate G of the second switching transistor SW2 overlaps with the active layer ACT of the second switching transistor SW2.

[0075] In some embodiments, as Figure 2As shown, the test circuit further includes a lead wire YL, one end of the lead wire YL is connected to the first control wire CL1, and the other end is connected to the second control wire CL2. That is, the first control wire CL1 and the second control wire CL2 are connected via the lead wire YL.

[0076] For example, Figure 2 As shown, the lead YL extends along the second direction f2, which is not limited in the present disclosure.

[0077] In some embodiments, as Figures 3 to 5 As shown, the first control line CL1 and the second control line CL2 are insulated from each other. Thus, by separating the first control line CL1 and the second control line CL2, the problem of excessive load caused by the control line CL being too long can be avoided.

[0078] Exemplarily, the first control line CL1 and the second control line CL2 may be connected to the same signal input pin PIN, or may be connected to different signal input pins PIN.

[0079] Exemplarily, the first control line CL1 and the second control line CL2 transmit the same signal at the same time.

[0080] For example, the active layer ACT in the switch transistor SW may be formed as follows: Figure 1 The block design shown, i.e., the orthographic projection of the entire active layer ACT on the display substrate is a continuous surface, can reduce the width of the switching transistor SW in the first direction f1, increase the number of switching transistors SW within a limited space, and improve the resolution of the display substrate.

[0081] The inventors have found that the block active layer ACT design easily causes the problem of negative drift of transistor characteristics. Figure 6 As shown, when the channel width W of the block active layer ACT is greater than or equal to 20 microns, a serious negative drift problem already occurs. This negative drift in transistor characteristics prevents the switching transistor SW from turning off during the display substrate's display process, leading to display anomalies and also interfering with the display substrate's lighting test.

[0082] In order to solve the above problems, in some embodiments, as Figures 2 to 5 As shown, the active layer ACT of the switching transistor SW includes a channel portion CH, and one or more slits XF are provided on the active layer ACT. The extending direction of the slit XF is parallel to the length direction fL of the channel portion CH, and the multiple slits XF are arranged along the width direction fW of the channel portion CH.

[0083] The channel portion CH is an area where the active layer ACT of the switching transistor SW overlaps with the gate G of the switching transistor SW. In a direction f3 perpendicular to the display substrate, the slit XF is a through hole that completely penetrates the active layer ACT.

[0084] like Figures 2 to 5 As shown, the channel portion CH is divided into a plurality of channel strips CHT by slits XF. In the width direction fW of the channel portion CH, the width of the channel strips CHT is, for example, 5 micrometers.

[0085] like Figure 7 As shown, the active layer ACT employs a slit XF design, maintaining normal characteristics even when the channel width W of the active layer ACT is 50 microns. This demonstrates that the slit XF design of the active layer ACT can effectively alleviate negative drift in transistor characteristics and enhance the stability of the switching transistor SW, thereby improving the display quality and lighting test results of the display substrate. Because the slit XF design may increase the space occupied by the switching transistor SW in the channel width direction, combining it with a staggered design of the switching transistors SW in the second direction f2 can maintain or even increase the number of switching transistors SW that can be accommodated in the first direction f1.

[0086] For example, Figures 2 to 5 As shown, the number of slits XF on the active layer ACT is greater than or equal to 1 and less than 5, for example, 3 or 4.

[0087] In some embodiments, as Figures 2 to 5 As shown in any one of the figures, the active layer ACT further includes a first connection portion LJ1 and a second connection portion LJ2 located on both sides of the channel portion CH. The first connection portion LJ1 is connected to the first electrode S of the switching transistor SW, and the second connection portion LJ2 is connected to the second electrode D of the switching transistor SW.

[0088] like Figure 2 or Figure 3 As shown, along the length direction fL of the channel portion CH, the slit XF completely penetrates the channel portion CH and ends at the junction between the first connection portion LJ1 and the channel portion CH, and at the junction between the second connection portion LJ2 and the channel portion CH.

[0089] like Figure 2 or Figure 3 As shown, a plurality of channel bars CHT are connected to the same first connection portion LJ1 and the same second connection portion LJ2.

[0090] For example, Figure 2 or Figure 3 As shown, in the length direction fL of the channel portion CH, the length of the slit XF is greater than or equal to the length of the channel portion CH and smaller than the size of the active layer ACT.

[0091] In some embodiments, as Figure 4 or Figure 5 As shown, along the length direction fL of the channel portion CH, the slit XF completely penetrates the active layer ACT. For example, in the length direction fL of the channel portion CH, the length of the slit XF is equal to the size of the active layer ACT.

[0092] For example, Figures 2 to 4 As shown in either figure, the length direction fL of the channel portion CH is parallel to the second direction f2.

[0093] For example, Figure 5 As shown, the length direction fL of the channel portion CH is parallel to the first direction f1.

[0094] When the length of the channel portion CH is greater than its width, setting the length direction fL of the channel portion CH parallel to the second direction f2 facilitates disposing a greater number of switching transistors SW in the first direction f1, thereby achieving high resolution. When the length of the channel portion CH is less than its width, setting the length direction fL of the channel portion CH parallel to the first direction f1 facilitates disposing a greater number of switching transistors SW in the first direction f1, thereby achieving high resolution.

[0095] It should be noted that the length direction of the channel is the direction from the first connection portion LJ1 to the second connection portion LJ2, and the width direction of the channel is perpendicular to the length direction of the channel.

[0096] For example, the active layer ACT of the switching transistor SW includes an oxide semiconductor material such as IGZO, and may also include materials such as amorphous silicon or low-temperature polycrystalline silicon. The use of an oxide semiconductor material in the active layer ACTACT reduces the off-state current of the switching transistor SW, further improving the stability of the switching transistor SW and enhancing the display quality and lighting test results of the display substrate.

[0097] In some embodiments, as Figure 8 As shown, the gate G of the switching transistor SW and the active layer ACT are stacked along a direction f3 perpendicular to the display substrate. The switching transistor SW further includes a blocking gate LSG located on a side of the active layer ACT away from the gate G.

[0098] In this embodiment, the switch transistor SW is a dual-gate transistor, which can further improve transistor characteristics.

[0099] For example, Figures 2 to 5 As shown, the test circuit further includes a plurality of shielding lines ZL extending along the first direction f1. The shielding lines ZL and the shielding gate LSG are arranged in the same layer and are interconnected. The control lines CL and the gate G are arranged in the same layer and are interconnected.

[0100] For example, Figures 2 to 5 As shown, the orthographic projections of the blocking line ZL and the control line CL on the display substrate overlap. For example, in the second direction f2, the orthographic projection of the control line CL on the display substrate is within the orthographic projection of the blocking line ZL on the display substrate, and the control line CL is centered relative to the blocking line ZL.

[0101] like Figures 2 to 5 As shown in any one, the shielding line ZL includes a first shielding line ZL1 and a second shielding line ZL2. For example, in the second direction f2, the first control line CL1 is centered relative to the first shielding line ZL1, and the second control line CL2 is centered relative to the second shielding line ZL2.

[0102] like Figures 2 to 4 As shown in any one of the figures, the blocking gate LSG of the first switching transistor SW1 is the region where the first blocking line ZL1 overlaps with the active layer ACT of the first switching transistor SW1, and the blocking gate LSG of the second switching transistor SW2 is the region where the second blocking line ZL2 overlaps with the active layer ACT of the second switching transistor SW2.

[0103] like Figure 5 As shown, the blocking gate LSG of the first switching transistor SW1 is connected to the first blocking line ZL1 and is located on the side of the first blocking line ZL1 close to the second blocking line ZL2, and the blocking gate LSG of the second switching transistor SW2 is connected to the second blocking line ZL2 and is located on the side of the second blocking line ZL2 close to the first blocking line ZL1.

[0104] like Figure 2 As shown, the first shielding line ZL1 and the second shielding line ZL2 are connected via an auxiliary lead FYL. The lead YL, the first control line CL1, and the second control line CL2 are arranged on the same layer. The auxiliary lead FYL, the first shielding line ZL1, and the second shielding line ZL2 are also arranged on the same layer. The lead YL and the auxiliary lead FYL are each connected to the first transfer pattern ZP1 through vias, thereby interconnecting the shielding line ZL and the control line CL. In the first direction f1, the lead YL is centered relative to the auxiliary lead FYL.

[0105] For example, Figures 3 to 5 As shown in any one of the diagrams, the first shielding line ZL1 and the second shielding line ZL2 are insulated from each other. The first control line CL1 and the second control line CL2 are provided on the same layer, and the first shielding line ZL1 and the second shielding line ZL2 are provided on the same layer. The first shielding line ZL1 and the first control line CL1 are respectively connected to the second transfer pattern ZP2 through vias, and the second shielding line ZL2 and the second control line CL2 are respectively connected to the second transfer pattern ZP2 through vias, thereby achieving mutual connection between the shielding line ZL and the control line CL.

[0106] For example, Figure 8 As shown, the shielding gate LSG is used to shield the light incident on the channel portion CH. The orthographic projection of the shielding gate LSG on the display substrate completely covers the orthographic projection of the gate G on the display substrate.

[0107] For example, Figure 8 As shown in FIG. a or FIG. b , in the length direction fL of the channel portion CH, the size of the blocking gate LSG is larger than the size of the gate G, and the gate G is centered relative to the blocking gate LSG.

[0108] For example, Figure 8 As shown in FIG. 5( b ), the orthographic projection of the shielding gate LSG on the display substrate completely covers the orthographic projection of the active layer ACT on the display substrate, thereby better protecting the active layer ACT.

[0109] The present disclosure provides a display substrate, such as Figure 9 As shown, the display substrate includes a base substrate 10 ( Figure 9 (not shown), and a display area AA and a non-display area NA arranged on one side of the base substrate 10.

[0110] like Figure 9 As shown, the display area AA includes a plurality of scan lines GL extending along a first direction f1 and a plurality of data lines DL extending along a second direction f2. The orthographic projections of the scan lines GL and the data lines DL on the base substrate 10 intersect to form a plurality of sub-pixels. The non-display area NA includes the test circuit 90 provided in any embodiment. The test lines TL are connected to the data lines DL via a switching transistor SW, and the second electrode D of the switching transistor SW is connected to the data line DL.

[0111] During the lighting test, the switch transistor SW in the test circuit 90 is turned on, and the test line TL provides a test signal to the data line DL; during the display process, the switch transistor SW in the test circuit 90 is turned off, and the driver IC provides a data signal to the data line DL.

[0112] In some embodiments, as Figures 10 to 12 As shown in any of the figures, the plurality of data lines DL are divided into a plurality of data line groups XZ. Each data line group XZ includes a plurality of data lines DL. Different data lines DL in the same data line group XZ are connected to sub-pixels of different colors in the same pixel unit. The test lines TL connected to different data lines DL in the same data line group XZ include adjacently arranged first test lines TL1 and / or second test lines TL2.

[0113] exist Figures 10 to 12Figure 1 shows two data line groups XZ: a first data line group XZ1 and a second data line group XZ2. The first data line group XZ1 includes three data lines DL, namely R / o, G / o, and B / o, which are sequentially connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel. The second data line group XZ2 includes three data lines DL, namely R / e, G / e, and B / e, which are sequentially connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

[0114] like Figure 10 or Figure 11 As shown, the test lines TL connected to the data lines R / o, G / o and B / o in the first data line group XZ1 are three adjacent first test lines TL1, and the test lines TL connected to the data lines R / e, G / e and B / e in the second data line group XZ2 are three adjacent second test lines TL2.

[0115] like Figure 12 As shown, the test lines TL connected to the data lines R / o, G / o and B / o in the first data line group XZ1 are, in sequence, the first test line TL1, the second test line TL2 and the first test line TL1 set adjacent to each other, and the test lines TL connected to the data lines R / e, G / e and B / e in the second data line group XZ2 are, in sequence, the second test line TL2, the first test line TL1 and the second test line TL2 set adjacent to each other.

[0116] In some embodiments, as Figure 10 or Figure 11 As shown, the multiple data line groups XZ include a first data line group XZ1 and a second data line group XZ2 that are adjacently arranged, the test lines TL connected to different data lines DL in the first data line group XZ1 are multiple first test lines TL1 that are adjacently arranged, and the test lines TL connected to different data lines DL in the second data line group XZ2 are multiple second test lines TL2 that are adjacently arranged.

[0117] like Figure 10 or Figure 11 As shown, the data lines DL in the first data line group XZ1 are connected to the switching transistor SW via a first adapter line ZJ1, and the data lines DL in the second data line group XZ2 are connected to the switching transistor SW via a second adapter line ZJ2. The orthographic projections of at least one first adapter line ZJ1 and at least one second adapter line ZJ2 on the base substrate 10 intersect with each other, and the intersecting first adapter lines ZJ1 and second adapter lines ZJ2 are arranged in different layers.

[0118] like Figure 10 and Figure 11As shown, the second adapter wire ZJ2 connected to the data line R / e intersects the orthographic projections of the first adapter wire ZJ1 connected to the data line G / o and the first adapter wire ZJ1 connected to the data line B / o on the base substrate 10. The second adapter wire ZJ2 connected to the data line G / e intersects the orthographic projections of the first adapter wire ZJ1 connected to the data line B / o on the base substrate 10.

[0119] For example, Figures 2 to 5 As shown, in the first and second adapter cables ZJ1 and ZJ2 that cross each other, the first adapter cable ZJ1 is provided on the same layer as the test line TL and the data line DL, and the second adapter cable ZJ2 is provided on the same layer as the control line CL. Alternatively, in the first and second adapter cables ZJ1 and ZJ2 that cross each other, the first adapter cable ZJ1 is provided on the same layer as the control line CL, and the second adapter cable ZJ2 is provided on the same layer as the test line TL and the data line DL.

[0120] like Figure 12 As shown, the switching lines connected between the data line DL and the switch transistor SW extend along the second direction f2 and do not cross each other.

[0121] Figure 10 and Figure 11 The connection shown can improve the display effect. Figure 12 The connections shown can simplify the design.

[0122] In some embodiments, as Figure 9 As shown, the non-display area NA includes a test area TA and a binding area BA, which are arranged opposite each other along the second direction f2. The test circuit 90 is located in the test area TA, and the binding area BA includes multiple pins PIN. The multiple test lines TL are divided into multiple test units U. Different test units U include the same number of test lines TL. The multiple test lines TL within the same test unit U are sorted along the first direction f1. Test lines TL with different sequence numbers in the same test unit U are connected to different pins PIN, while test lines TL with the same sequence number in different test units U are connected to the same pin PIN.

[0123] For example, Figure 9 As shown, each test unit U includes six test lines TL. The test lines TL in each test unit U are sorted along the first direction f1 and numbered 1, 2, 3, 4, 5, and 6. Test lines TL with different numbers are connected to different pins PIN through different transmission lines CL, and test lines TL with the same number are connected to the same pin PIN through the same transmission line CL.

[0124] Illustratively, the display substrate provided by the present disclosure can be prepared according to the following steps:

[0125] Step 1: Provide a base substrate 10, and perform coating and etching of a shielding layer LS on one side of the base substrate 10. The shielding layer LS includes two shielding lines ZL, and the following is obtained: Figure 13a The pattern shown.

[0126] Step 2: forming a buffer layer (buffer) on the side of the shielding layer LS away from the base substrate 10 Figure 13b (not shown), the active layer ACT is formed and etched on the side of the buffer layer away from the base substrate 10, and the following is obtained: Figure 13b The pattern shown.

[0127] Step 3: Form a gate insulating layer GI on the side of the active layer ACT away from the substrate 10 ( Figure 13c (not shown), the first metal layer M1 is formed and etched on the side of the gate insulating layer GI away from the base substrate 10 to form the gate G and the control line CL of the switching transistor SW, forming two control lines CL in total. Figure 13c The first metal layer M1 may further include a scanning line GL and a second connecting line ZJ2.

[0128] Step 4: Dry-etch the gate insulating layer GI to expose part of the active layer ACT, and then conduct the exposed active layer ACT to form a first connection portion LJ1 and a second connection portion LJ2. Then, an interlayer dielectric layer ILD is formed on the side of the gate insulating layer GI away from the substrate 10. Figure 13d (not shown), and the interlayer dielectric layer ILD is etched to form a first through hole H1, and the Figure 13d The pattern shown.

[0129] Step 5: Form and etch the second metal layer M2 on the side of the interlayer dielectric layer ILD away from the substrate 10 to obtain Figure 13e In the pattern shown, the second metal layer M2 includes a test line TL, a first electrode S, and a second electrode D of the switching transistor SW. The first electrode S is connected to the first connection portion LJ1 via a first through-hole H1, and the second electrode D is connected to the second connection portion LJ2 via a first through-hole H1. The first metal layer M1 may also include a data line DL. The first electrode S is also connected to the test line TL, and the second electrode D is also connected to the data line DL. The second adapter line ZJ2 is connected to the second electrode D and the data line DL respectively via a first through-hole H1.

[0130] Step 6: Form a first passivation layer PVX1 on the side of the second metal layer M2 away from the base substrate 10, then form and etch the first electrode layer ITO1 on the first passivation layer PVX1, then form a second passivation layer PVX2 on the first electrode layer ITO1, and then use an etching process to form a second through hole H2 and a third through hole H3, etch away all the insulating materials above the corresponding position shielding line ZL to form the second through hole H2, and etch away all the insulating materials above the corresponding position control line CL to form the third through hole H3, and obtain the following: Figure 13f The pattern shown.

[0131] Step 7: Form and etch the second electrode layer ITO2 on the side of the second passivation layer PVX2 away from the base substrate 10. The second electrode layer ITO2 includes a second transfer pattern ZP2. The second transfer pattern ZP2 is connected to the shielding line ZL through the second through hole H2. The second transfer pattern ZP2 is connected to the control line CL through the third through hole H3 to obtain the following: Figure 4 The test circuit 90 is shown.

[0132] The present disclosure provides a display device, comprising: a display substrate as provided in any embodiment; and a driving circuit connected to the display substrate, for driving the display substrate to perform display.

[0133] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the display substrate of any of the above embodiments.

[0134] The display device provided by the present disclosure can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0135] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0136] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0137] In this disclosure, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0138] References in this disclosure to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0139] In this disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0140] In this specification, the terms "electrically connected" and "coupled" include components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0141] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0142] The polygons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, rounded corners, arc edges and deformations.

[0143] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0144] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0145] The use of "for" or "configured to" in this disclosure is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0146] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0147] As used in this disclosure, "parallel," "perpendicular," "equal," and "level" include the stated conditions and conditions similar to the stated conditions, with the range of the similar conditions being within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism may be, for example, a deviation within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity may also be, for example, a deviation within 10° or 5°.

[0148] "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality is, for example, that the difference between the two equals is less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein the acceptable deviation range of approximate flush is, for example, that the distance between the two flushes is less than or equal to 5% of either one's size.

[0149] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0150] The present disclosure describes exemplary embodiments with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this disclosure, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A test circuit, located on one side of a display substrate, comprising: a plurality of control lines extending along a first direction; a plurality of test lines, wherein the test lines extend along a second direction, and the second direction intersects the first direction; as well as a plurality of switch transistors, wherein a gate of each switch transistor is connected to the control line, a first electrode of each switch transistor is connected to the test line, and a second electrode of each switch transistor is connected to a data line in the display substrate; Among them, the multiple test lines include a first test line and a second test line arranged at intervals along the first direction, the multiple switching transistors include a first switching transistor and a second switching transistor, the first switching transistor is connected to the first test line, and the second switching transistor is connected to the second test line. Along the second direction, the first switching transistor and the second switching transistor are staggered with each other.

2. The test circuit according to claim 1, wherein: The orthographic projections of the first switching transistor and the second switching transistor on a first reference plane do not overlap, and the first reference plane is a plane perpendicular to the first direction.

3. The test circuit according to claim 1, wherein: There is an overlapping area between the orthographic projections of the first switching transistor and the second switching transistor on a second reference plane, and the second reference plane is a plane perpendicular to the second direction.

4. The test circuit according to claim 3, wherein: A ratio of a size of the overlapping region along the first direction to a size of the switching transistor along the first direction is greater than or equal to one-fifth and less than or equal to four-fifths.

5. The test circuit according to claim 1, wherein: The first test lines and the second test lines are alternately arranged in sequence in the first direction, the multiple first switching transistors connected to different first test lines are roughly aligned in the second direction, and the multiple second switching transistors connected to different second test lines are roughly aligned in the second direction. The test circuit according to claim 1 , wherein: The plurality of control lines include a first control line and a second control line arranged at intervals along the second direction, the first control line is connected to the gate of the first switch transistor, and the second control line is connected to the gate of the second switch transistor; The second control line is located on a side of the first control line away from the first test line. The orthographic projections of the first control line and the second test line on the display substrate intersect each other, and the first control line and the second test line are arranged in different layers.

7. The test circuit according to claim 6, wherein: The test circuit further includes a lead, one end of which is connected to the first control line, and the other end of which is connected to the second control line.

8. The test circuit according to claim 6, wherein: The first control line and the second control line are insulated from each other.

9. The test circuit according to claim 1, wherein: The active layer of the switching transistor includes a channel portion. One or more slits are provided on the active layer. The extending direction of the slits is parallel to the length direction of the channel portion. The multiple slits are arranged along the width direction of the channel portion.

10. The test circuit according to claim 9, wherein: The active layer further includes a first connecting portion and a second connecting portion located on both sides of the channel portion, the first connecting portion being connected to the first electrode of the switching transistor, and the second connecting portion being connected to the second electrode of the switching transistor; Along the length direction of the channel portion, the slit completely penetrates the channel portion and ends at a junction between the first connecting portion and the channel portion, and at a junction between the second connecting portion and the channel portion.

11. The test circuit according to claim 9, wherein: Along the length direction of the channel portion, the slit completely penetrates the active layer.

12. The test circuit according to claim 9, wherein: The length direction of the channel portion is parallel to the first direction or the second direction.

13. The test circuit according to any one of claims 1 to 12, wherein: The gate and active layer of the switching transistor are stacked in a direction perpendicular to the display substrate, and the switching transistor further comprises a blocking gate, which is located on a side of the active layer away from the gate; The test circuit further includes a plurality of shielding lines extending along the first direction, the shielding lines and the shielding gate are arranged in the same layer and are interconnected, the control lines and the gate are arranged in the same layer, and the shielding lines and the control lines are interconnected.

14. The test circuit according to claim 13, wherein: In the length direction of the channel portion, the size of the shielding gate is larger than the size of the gate, and the gate is centrally arranged relative to the shielding gate. The shielding gate is used to shield light incident on the channel portion.

15. A display substrate comprising a base substrate, and a display area and a non-display area arranged on one side of the base substrate; The display area includes a plurality of scan lines extending along the first direction and a plurality of data lines extending along the second direction, wherein the orthographic projections of the scan lines and the data lines on the base substrate intersect with each other to form a plurality of sub-pixels; The non-display area includes the test circuit according to any one of claims 1 to 14, the test line is connected to the data line through the switch transistor, and the second electrode of the switch transistor is connected to the data line.

16. The display substrate according to claim 15, wherein: The plurality of data lines are divided into a plurality of data line groups, each data line group including a plurality of the data lines, and different data lines in the same data line group are connected to sub-pixels in the same pixel unit but with different colors; The test lines connected to different data lines in the same data line group include a first test line and / or a second test line that are adjacently arranged.

17. The display substrate according to claim 16, wherein: The plurality of data line groups include a first data line group and a second data line group that are adjacently arranged, the test lines connected to different data lines in the first data line group are a plurality of first test lines that are adjacently arranged, and the test lines connected to different data lines in the second data line group are a plurality of second test lines that are adjacently arranged; The data lines in the first data line group are connected to the switching transistor via a first adapter line, and the data lines in the second data line group are connected to the switching transistor via a second adapter line. The orthographic projections of at least one of the first adapter lines and at least one of the second adapter lines on the base substrate intersect with each other, and the intersecting first adapter lines and second adapter lines are arranged in different layers.

18. The display substrate according to claim 17, wherein: In the first adapter line and the second adapter line that cross each other, the first adapter line is provided on the same layer as the test line and the data line, and the second adapter line is provided on the same layer as the control line; or In the first adapter wire and the second adapter wire that cross each other, the first adapter wire and the control wire are arranged on the same layer, and the second adapter wire and the test wire and the data wire are arranged on the same layer.

19. The display substrate according to any one of claims 15 to 18, wherein: The non-display area includes a test area and a binding area that are oppositely arranged along the second direction, the test circuit is located in the test area, and the binding area includes a plurality of pins; Multiple test lines are divided into multiple test units, different test units include the same number of test lines, and multiple test lines in the same test unit are sorted along the first direction. Test lines located in the same test unit with different serial numbers are connected to different pins, and test lines located in different test units with the same serial number are connected to the same pin.

20. A display device comprising: The display substrate according to any one of claims 15 to 19; as well as The driving circuit is connected to the display substrate and is used to drive the display substrate to perform display.

Images