Prediction search type SAR ADC circuit and SAR ADC method suitable for focal plane detector

Abstract

The invention belongs to the technical field of focal plane detector readout circuits, and discloses a predictive search type SARADC circuit design method suitable for a focal plane detector, which comprises a sampling switch, a DAC array, a comparator, a predictive search module and a digital output module. Compared with a traditional SARADC circuit architecture, the SARADC circuit architecture has the advantages that a predictive search algorithm is used, the correlation of amplitude values between adjacent pixels is utilized, the number of ADC comparison times needed when the amplitude information of the current pixel is digitally quantized is greatly reduced, the requirements of an ADC circuit module for designing a high-speed DAC and a high-speed comparator are avoided, and the area and power consumption are reduced. By using the amplitude value conversion result of the adjacent pixels, the comparison frequency of the current pixel comparator is reduced, and the ADC conversion period of a single pixel is reduced, so that the output frame frequency of the whole focal plane detector reading circuit is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of focal plane detector readout circuits and relates to a predictive search type SAR ADC circuit and a SAR ADC method suitable for a focal plane detector. Background Art

[0002] Traditional ammunition is inexpensive to manufacture, but suffers from poor accuracy and a low cost-effectiveness. Precision-guided weapons, on the other hand, are gaining increasing attention in the weaponry community due to their high precision and cost-effectiveness. Focal plane detectors have been successfully incorporated into modern precision-guided weapons and hold broad application prospects in fire control systems, target identification, and ballistic interception. Focal plane detectors, with their long detection range, rapid target acquisition, and high frame rates, can rapidly track a variety of high-speed moving military targets, providing reliable imaging data for defense systems. Focal plane detectors can calculate not only distance information through the time-determined coordinate (TDC) but also intensity information through the analog-to-digital converter (ADC), generating grayscale images that can be used to identify decoys, obstructions, and high-speed moving targets, possessing significant military applications.

[0003] As precision-guided weapons place increasing demands on ranging accuracy and speed, focal plane detectors are gradually evolving toward larger sizes and higher frame rates. However, conventional focal plane detector readout circuits typically use ramp ADCs or traditional SAR ADC circuits to digitize pixel amplitude information. Ramp ADCs are slow and struggle to meet high frame rate requirements. Traditional SAR ADCs, to accommodate large arrays and high frame rates, often require high-speed DACs and comparators. This often comes at the expense of performance metrics like area and power consumption, increasing design complexity and cost while reducing circuit reliability.

[0004] The DAC area size in a SAR ADC depends on the accuracy and speed requirements. To implement an N-bit SAR ADC, using the upper-board sampling method and the binary CDAC capacitor array arrangement, the number of unit capacitors Cu required is 2N-1. To ensure a certain matching accuracy, the unit capacitor size cannot be too small. However, if the capacitance value is too large, the DAC output requires a longer settling time when switching at high bits, which will affect the ADC conversion speed.

[0005] On the other hand, comparator design requires a compromise between noise, speed, and power consumption. Comparators need to quickly compare weak differential input signals within a short period of time. This typically uses a static cascaded dynamic comparator architecture, but this suffers from high power consumption, making it unsuitable for use in large-scale focal plane detector readout circuits.

[0006] Traditional SAR ADC circuits require a binary search from the beginning each time they digitize an analog signal. Large-array focal plane detectors have small pixel sizes (e.g., 50μm × 50μm). The target's reflected echo typically strikes multiple adjacent pixels, leaving a large number of remaining pixels receiving only background light. Consequently, the amplitude values ​​of these adjacent pixels exhibit significant correlation. Therefore, by leveraging the correlation between the quantized amplitude values ​​required by the ADC for adjacent pixels, a predictive search algorithm can be used to optimize the SAR ADC architecture and simplify the design of the DAC and comparator. This paper proposes a high-speed, high-precision, low-power SAR ADC architecture with a predictive search algorithm suitable for focal plane detector circuits. Summary of the Invention

[0007] (1) Purpose of the invention

[0008] The purpose of the present invention is to provide a predictive search SAR ADC circuit and SAR ADC method suitable for focal plane detectors, which are used to solve the problem that the speed of DAC and comparator needs to be increased proportionally as the size and frame rate of large-array focal plane detectors increase.

[0009] (2) Technical solution

[0010] In order to solve the above technical problems, the present invention provides a predictive search type SARADC circuit suitable for a focal plane detector, which includes: a first sampling switch, a second sampling switch, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, a comparator and a predictive search module;

[0011] The first sampling switch is used to receive the positive input of the differential signal;

[0012] The second sampling switch is used to receive the negative end input of the differential signal;

[0013] The first analog-to-digital conversion unit is connected to the first sampling switch and is used for digital-to-analog conversion;

[0014] The second analog-to-digital conversion unit is connected to the second sampling switch and is used for digital-to-analog conversion;

[0015] The comparator has a first input terminal connected to the output terminal of the first analog-to-digital conversion unit, and a second input terminal connected to the output terminal of the second analog-to-digital conversion unit, for comparing the output signals of the first analog-to-digital unit and the second analog-to-digital conversion unit, and outputting a comparison result;

[0016] The prediction search unit is connected to the output of the comparator and the output of the digital output unit, and generates a switching control signal for the first analog-to-digital conversion unit and the second digital-to-analog conversion unit based on the digital signal output by the comparator and the digital code output by the last ADC conversion.

[0017] Furthermore, the prediction search module includes: prediction logic, N-stage cascaded asynchronous SAR logic units, and a selection switch; L is the number of prediction bits of the prediction logic module; the output of the prediction logic is connected to the input of the selection switch SW_1 and the input of the selection switch SW_2; the output of the prediction logic is connected to the control ends of the selection switches SW_3, ..., SW_L+3; the output of the N-th asynchronous SAR logic unit is connected to the input of the N-1th asynchronous SAR logic unit; the output of the N-1th asynchronous SAR logic unit is connected to the input of the N-2th asynchronous SAR logic unit; the output of the N-L+2th asynchronous SAR logic unit is connected to the input of the N-L+1th asynchronous SAR logic unit; the output of the N-L+1th asynchronous SAR logic unit is connected to the input of the selection switch SW_2; the output of the selection switch SW_2 is connected to the input of the NLth asynchronous SAR logic unit; the output of the NLth asynchronous SAR logic unit is connected to the input of the NL-1th asynchronous SAR logic unit; and the output of the 1st asynchronous SAR logic unit is connected to the input of the 0th asynchronous SAR logic unit.

[0018] Furthermore, the prediction search type SAR ADC has a prediction bit number of L.

[0019] Furthermore, the control signals of the SW_1, SW_2, SW_3, ..., SW_L+3 selection switches are pulled high, the asynchronous SAR logic units of the Nth, ..., N-L+1th bits do not work, the asynchronous SAR logic units of the NLth, ..., 0th bits work in sequence, and the SW_3, ..., SW_L+3 selection switches output the high-bit conversion results of adjacent pixels.

[0020] Furthermore, the control signals of the SW_1, SW_2, SW_3, ..., SW_L+3 selection switches are pulled low, and the Nth, ..., 0th asynchronous SAR logic units work in sequence, and the SW_3, ..., SW_L+3 selection switches output the switching control signals of the analog-to-digital conversion unit according to the traditional binary search algorithm.

[0021] Furthermore, the output digital code of the predictive search SAR ADC circuit=the upper L bits of the digital code output by the adjacent pixel ADC+the lower NL bits of the digital code output by the current pixel ADC.

[0022] The present invention also provides a predictive search SAR ADC method applicable to a focal plane detector, comprising the following steps:

[0023] Step 1: sampling the differential signal to the first digital-to-analog conversion unit and the second digital-to-analog conversion unit based on the first sampling switch and the second sampling switch;

[0024] Step 2: Based on the prediction search module, the high-order L bits of the ADC output digital codes of adjacent pixels are used to output a set of control signals for the digital-to-analog converters. The comparator compares the outputs of the first analog-to-digital converter and the second analog-to-digital converter, and the comparison result is fed back to the prediction search module.

[0025] Step 3: Based on the signal fed back to the prediction search module by the comparator, determine whether the prediction search logic is correct; if the prediction is correct, reuse the high L bits and low NL bits of adjacent pixels for conventional binary search; if the prediction is wrong, discard the high L bits of adjacent pixels and perform conventional binary search on all N bits.

[0026] Furthermore, before executing the first step, a process of resetting the analog-to-digital conversion unit is also included, that is, the first sampling switch is turned on and the second sampling switch is turned off, and the first analog-to-digital conversion unit and the second analog-to-digital conversion unit are reset.

[0027] (3) Beneficial effects

[0028] The predictive search SAR ADC circuit and SAR ADC method applicable to a focal plane detector provided by the above technical solution have the following beneficial effects:

[0029] (1) Compared with the traditional SAR ADC architecture, the present invention uses a predictive search algorithm, exploits the correlation between the amplitude values ​​of adjacent pixels, and uses the high L bits of the digital code of the adjacent pixel amplitude values ​​to predict the amplitude value of the current pixel, thus avoiding the design difficulty of high-precision, high-speed, and low-power ADC required for large-array, high-frame-rate focal plane detector readout.

[0030] (2) By using the high L bits of the digital code of the amplitude value of the adjacent pixel to predict the amplitude value of the current pixel, the number of comparisons of the comparator in the single conversion process of the ADC is reduced, the complexity of the DAC and comparator design is reduced, and the readout frame rate of the entire large-size focal plane detector is improved. Compared with the traditional SAR ADC circuit architecture, the required circuit overhead is less, the area is smaller, and the power consumption is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is the predictive search type SAR ADC circuit provided in the first embodiment of the present application.

[0032] Figure 2 This is a submodule circuit of the predictive search type SAR ADC circuit provided in the first embodiment of the present application.

[0033] Figure 3 This is a timing logic diagram of the predictive search type SAR ADC circuit provided in the second embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below with reference to the accompanying drawings and examples.

[0035] See also Figures 1 to 3 . It should be noted that the circuits, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any modification of the circuit, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0036] Example 1:

[0037] like Figure 1 As shown, this embodiment provides a predictive search SAR ADC circuit suitable for a focal plane detector, comprising: a first sampling switch 110, a second sampling switch 120, a first digital-to-analog conversion unit 130, a second digital-to-analog conversion unit 140, a comparator 150, a predictive search module 160, and a digital output module 170, wherein:

[0038] The first sampling switch 110 is used to receive the positive input of the differential signal;

[0039] The second sampling switch 120 is used to receive the negative terminal input of the differential signal;

[0040] The first analog-to-digital conversion unit 130 is connected to the first sampling switch 110 and is used for digital-to-analog conversion;

[0041] The second analog-to-digital conversion unit 140 is connected to the second sampling switch 120 and is used for digital-to-analog conversion;

[0042] The comparator 150 has a first input connected to the output of the first analog-to-digital conversion unit 130 and a second input connected to the output of the second analog-to-digital conversion unit 140, and is configured to compare the output signals of the first analog-to-digital conversion unit and the second analog-to-digital conversion unit and output a comparison result.

[0043] The prediction search module 160 is connected to the output of the comparator 150 and the output of the digital output module 170, and generates a switching control signal for the first analog-to-digital conversion unit 130 and the second digital-to-analog conversion unit 140 based on the digital signal output by the comparator and the digital code output by the last ADC conversion;

[0044] Specifically, in this embodiment, the prediction search module 160 includes: a prediction logic 210, N-stage cascaded asynchronous SAR logic units 250, 251, ..., 25_N, and selection switches 220, 230, 24_N-L+1, ..., 24_N; the output of the prediction logic 210 is connected to the input of the selection switch 220 and the input of the selection switch 230; the output of the prediction logic 210 is connected to the control end of the selection switches 24_N-L+1, ..., 24_N; the output of the N-th asynchronous SAR logic unit 25_N is connected to the input of the N-1-th asynchronous SAR logic unit 25_N-1; the output of the N-1-th asynchronous SAR logic unit 25_N-1 is connected to the N-2-th asynchronous SAR logic unit 25_N-1. The output of the N-L+2th asynchronous SAR logic unit 25_N-L+2 is connected to the input of the N-L+1th asynchronous SAR logic unit 25_N-L+1; the output of the N-L+1th asynchronous SAR logic unit 25_N-L+1 is connected to the input of the selection switch 230; the output of the selection switch 230 is connected to the input of the NLth asynchronous SAR logic unit 25_N-L; the output of the NLth asynchronous SAR logic unit 25_N-L is connected to the input of the NL-1th asynchronous SAR logic unit 25_N-L-1; the output of the 1st asynchronous SAR logic unit 251 is connected to the input of the 0th asynchronous SAR logic unit 250.

[0045] It should be noted that the first sampling switch 110 and the second sampling switch 120 include but are not limited to diodes, transistors, field effect transistors, thyristors, and any device that can function as a switch is applicable, and they are not described in detail here.

[0046] More specifically, the number of prediction bits of the prediction module is L, where L is the number of prediction bits of the predictive search-type SAR ADC; the setting method of the prediction bit number of the prediction module includes but is not limited to configuration and adaptation. Any implementation method that can set the prediction bit number of the prediction module is applicable and will not be described in detail here.

[0047] Specifically, the control signals of the selection switches 24_N-L+1, ..., 24_N of the prediction logic are pulled high, the asynchronous SAR logic units 25_N-L+1, ..., 25_N at the N, ..., N-L+1th bits do not work, the asynchronous SAR logic units 25_N-L, ..., 250 at the NL, ..., 0th bits work sequentially, and the selection switches 24_N-L+1, ..., 24_N output high-bit conversion results of adjacent pixels; the control signals of the selection switches 24_N-L+1, ..., 24_N are pulled low, the asynchronous SAR logic units 25_N, ..., 250 at the N, ..., 0th bits work sequentially, and the selection switches 24_N-L+1, ..., 24_N output switching control signals of the analog-to-digital conversion units according to a traditional binary search algorithm.

[0048] Specifically, the output digital code of the predictive search SAR ADC circuit = the upper L bits of the adjacent pixel ADC output digital code + the lower NL bits of the current pixel ADC output digital code;

[0049] The predictive search type SAR ADC of the present invention has a small area, low power consumption and high conversion speed, and can improve the frame rate of a large array focal plane detector.

[0050] Example 2

[0051] This embodiment provides a predictive search SAR ADC method applicable to a focal plane detector. The predictive search SAR ADC method is implemented based on the predictive search SAR ADC circuit provided in the first embodiment and includes the following steps:

[0052] Step S1: Figure 1 and Figure 3 As shown, the first sampling switch 110 and the second sampling switch 120 are disconnected, and the first analog-to-digital conversion unit 130 and the second analog-to-digital conversion unit 140 are reset. Figure 3 The process 301 of resetting the analog-to-digital conversion unit.

[0053] Step S2: Figure 1 and Figure 3 As shown, based on the first sampling switch 110 and the second sampling switch 120, the differential signal is sampled to the first analog-to-digital conversion unit 130 and the second analog-to-digital conversion unit 140, that is, Figure 3 The process 302 of sampling the differential signal.

[0054] Step S3: Figure 2 and Figure 3As shown, based on the output of the control signal Pre_correct by the prediction logic 210 to the control terminals of the selection switches 24_N-L+1, ..., 24_N, the switching control signals of the first analog-to-digital conversion unit 130 and the second digital-to-analog conversion unit 140 are generated. The comparator performs a first comparison and determines whether the prediction is correct based on the comparison result. Figure 3 The process of prediction comparison 303.

[0055] Step S4: Figure 2 and Figure 3 As shown, the output signal of the comparator 150 is output to the prediction logic 210. If the comparator output is high, it means the prediction is correct. Then the high L bits of the last converted digital code of the ADC are reused and the low NL bits are subjected to traditional binary search, i.e. Figure 3 The process of successive approximation 304.

[0056] Step S5: Figure 2 and Figure 3 As shown, the output signal of the comparator 150 is output to the prediction logic 210. If the comparator output is low, it means that the prediction fails. Then the high L bits of the last converted digital code of the ADC are not reused, and the traditional binary search is used for all N bits, that is, Figure 3 The process of successive approximation 312.

[0057] It should be noted that, as an example, Figure 3 As shown, if the prediction bit number L of the prediction search SAR ADC is 5 and the precision N is 10, the digital code output by the ADC = the predicted digital code <9:5> + the traditional binary search digital code <4:0>.

[0058] In summary, the present embodiment is applicable to a predictive search SAR ADC circuit and a SAR ADC method for a focal plane detector, comprising: the predictive search SAR ADC circuit comprising at least: a first sampling switch, a second sampling switch, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, a comparator, and a predictive search module, wherein: the first sampling switch is used to receive a positive input of a differential signal; the second sampling switch is used to receive a negative input of a differential signal; the first analog-to-digital conversion unit is connected to the first sampling switch for digital-to-analog conversion; the second analog-to-digital conversion unit is connected to the second sampling switch for digital-to-analog conversion; the first input terminal of the comparator is connected to the output terminal of the first analog-to-digital conversion unit, and the second input terminal is connected to the output terminal of the second analog-to-digital conversion unit, for comparing the output signals of the first analog-to-digital conversion unit and the second analog-to-digital conversion unit and outputting a comparison result; the predictive search module is connected to the output terminal of the comparator and the output of the digital output module, and generates a switching control signal for the first analog-to-digital conversion unit and the second digital-to-analog conversion unit based on the digital signal output by the comparator and the digital code output by the previous ADC conversion; compared with the traditional SAR Compared to existing ADC circuit architectures, the present invention uses a predictive search algorithm and leverages the correlation between adjacent pixel amplitude values ​​to reduce the number of ADC comparisons during digitization of the current pixel amplitude information. This circumvents the design challenge of requiring a high-precision, high-speed, and low-power ADC for large-array, high-frame-rate focal plane detector readout circuits. By utilizing the amplitude conversion results of adjacent pixels, the number of comparisons performed by the current pixel comparator is reduced, shortening the ADC conversion cycle for a single pixel and thereby increasing the frame rate of the entire focal plane detector. Therefore, the present invention effectively overcomes the shortcomings of existing focal plane detector technology, achieving high frame rates while reducing area and power consumption, and possesses significant application value.

[0059] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A predictive search SARADC circuit suitable for a focal plane detector, characterized in that: include: A first sampling switch, a second sampling switch, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, a comparator, and a prediction search module; The first sampling switch is used to receive the positive input of the differential signal; The second sampling switch is used to receive the negative end input of the differential signal; The first analog-to-digital conversion unit is connected to the first sampling switch and is used for digital-to-analog conversion; The second analog-to-digital conversion unit is connected to the second sampling switch and is used for digital-to-analog conversion; The comparator has a first input terminal connected to the output terminal of the first analog-to-digital conversion unit, and a second input terminal connected to the output terminal of the second analog-to-digital conversion unit, for comparing the output signals of the first analog-to-digital unit and the second analog-to-digital conversion unit, and outputting a comparison result; The prediction search unit is connected to the output of the comparator and the output of the digital output unit, and generates a switching control signal for the first analog-to-digital conversion unit and the second digital-to-analog conversion unit based on the digital signal output by the comparator and the digital code output by the last ADC conversion.

2. The predictive search SAR ADC circuit suitable for a focal plane detector according to claim 1, wherein: The prediction search module includes: prediction logic, N-stage cascaded asynchronous SAR logic units and a selection switch; L is the number of prediction bits of the prediction logic module; the output of the prediction logic is connected to the input of the selection switch SW_1 and the input of the selection switch SW_2; the output of the prediction logic is connected to the control ends of the selection switches SW_3, ..., SW_L+3; the output of the N-th asynchronous SAR logic unit is connected to the input of the N-1th asynchronous SAR logic unit; the output of the N-1th asynchronous SAR logic unit is connected to the input of the N-2th asynchronous SAR logic unit; the output of the N-L+2th asynchronous SAR logic unit is connected to the input of the N-L+1th asynchronous SAR logic unit; the output of the N-L+1th asynchronous SAR logic unit is connected to the input of the selection switch SW_2; the output of the selection switch SW_2 is connected to the input of the NLth asynchronous SAR logic unit; the output of the NLth asynchronous SAR logic unit is connected to the input of the NL-1th asynchronous SAR logic unit; and the output of the 1st asynchronous SAR logic unit is connected to the input of the 0th asynchronous SAR logic unit.

3. The predictive search SAR ADC circuit suitable for a focal plane detector according to claim 2, wherein: The number of prediction bits of the prediction search type SARADC is L.

4. The predictive search SAR ADC circuit suitable for a focal plane detector according to claim 3, wherein: The control signals of the SW_1, SW_2, SW_3, ..., SW_L+3 selection switches are pulled high, the asynchronous SAR logic units of the N, ..., N-L+1th bits do not work, the asynchronous SAR logic units of the NL, ..., 0th bits work in sequence, and the SW_3, ..., SW_L+3 selection switches output the high-bit conversion results of adjacent pixels.

5. The predictive search SAR ADC circuit suitable for a focal plane detector according to claim 4, wherein: The control signals of the SW_1, SW_2, SW_3, ..., SW_L+3 selection switches are pulled low, and the Nth, ..., 0th asynchronous SAR logic units work in sequence. The SW_3, ..., SW_L+3 selection switches output the switching control signals of the analog-to-digital conversion unit according to the traditional binary search algorithm.

6. The predictive search SAR ADC circuit suitable for a focal plane detector according to claim 5, wherein: The output digital code of the predictive search type SARADC circuit = the upper L bits of the adjacent pixel ADC output digital code + the lower NL bits of the current pixel ADC output digital code.

7. A predictive search SAR ADC method suitable for a focal plane detector, characterized in that: The invention is realized based on the predictive search type SARADC circuit applicable to the focal plane detector described in claim 6.

8. The predictive search SAR ADC method applicable to a focal plane detector according to claim 7, wherein: The following processes are included: Step 1: sampling the differential signal to the first digital-to-analog conversion unit and the second digital-to-analog conversion unit based on the first sampling switch and the second sampling switch; Step 2: Based on the prediction search module, the high-order L bits of the ADC output digital codes of adjacent pixels are used to output a set of control signals for the digital-to-analog converters. The comparator compares the outputs of the first analog-to-digital converter and the second analog-to-digital converter, and the comparison result is fed back to the prediction search module. Step 3: Based on the signal fed back to the prediction search module by the comparator, determine whether the prediction search logic is correct; if the prediction is correct, reuse the high L bits and low NL bits of adjacent pixels for conventional binary search; if the prediction is wrong, discard the high L bits of adjacent pixels and perform conventional binary search on all N bits.

9. The predictive search SAR ADC method applicable to a focal plane detector according to claim 8, wherein: Before executing the first step, a process of resetting the analog-to-digital conversion unit is also included, that is, the first sampling switch is turned on and the second sampling switch is turned off, and the first analog-to-digital conversion unit and the second analog-to-digital conversion unit are reset.

10. Application of a predictive search SAR ADC method suitable for a focal plane detector according to any one of claims 7 to 9 in a focal plane detector readout circuit technology.

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