One-time programmable memory device in monolithic GaN technology

Abstract

The invention relates to a one-time programmable memory device in monolithic GaN technology. A one time programmable (OTP) memory device includes a semiconductor die and an OTP memory cell integrated into the die. The die includes a channel layer and a barrier layer forming a heterostructure and a plurality of metallization levels over the heterostructure. The OTP memory cell includes a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, where the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to flow a write current to change the fuse element from an unprogrammed state to a programmed state in an irreversible manner. A fuse element is formed in one of the metallization levels of the die. The selector includes a high electron mobility transistor (HEMT) formed at least partially in a heterostructure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a one-time programmable memory device in monolithic GaN technology. BACKGROUND

[0002] As known, many integrated circuits comprise a functional block for trimming, whose purpose is to compensate for process dispersion or parameter drifts that can affect, for example, reference voltages, oscillators and operational amplifiers. The functional block generally comprises a plurality of sets of components, such as capacitors or resistors, which can be connected in various configurations to obtain a desired compensation value. This type of functional block is particularly useful in devices in GaN (gallium nitride) technology, which is extremely promising in terms of performance, but is still not mature.

[0003] In many cases, the configuration of the components forming the trimming functional block is determined using an array of one-time programmable read-only memories, also known as OTP (one-time programmable) memories. In practice, each memory cell is associated with a specific component of the trimming block, and the state of the cell determines the connection or disconnection of the corresponding component.

[0004] While the integration of various types of memories, including OTP memories, is no longer a major problem in traditional silicon semiconductor devices, for devices in GaN technology it is still necessary to resort to external OTP memories, which are packaged together with the main device in the same package. However, the use of external OTP memories can be limited in terms of performance, size and cost. SUMMARY

[0005] The present disclosure relates to providing a one-time programmable memory device that allows overcoming or at least mitigating said limitations.

[0006] The present disclosure relates to a one-time programmable (OTP) memory device comprising a semiconductor die including: a channel layer and a barrier layer forming a heterostructure with a heterojunction at an interface between the channel layer and the barrier layer, and a plurality of metallization levels above the heterostructure. A one-time programmable (OTP) memory cell integrated into the semiconductor die, the OTP memory cell including: a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, wherein the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to cause a write current to flow and irreversibly change the fuse element from the unprogrammed state to the programmed state. The fuse element is formed in one of the metallization levels of the semiconductor die, and the selector includes a high electron mobility transistor (HEMT) formed at least partially in the heterostructure. BRIEF DESCRIPTION OF DRAWINGS

[0007] For a better understanding of the present disclosure, preferred embodiments are provided by way of non-limiting examples with reference to the drawings, in which:

[0008] Figure 1 is a simplified circuit diagram of an OTP memory device according to an embodiment of the present disclosure;

[0009] Figure 2 is a cross-section through Figure 1 an OTP memory device;

[0010] Figure 3 is a simplified plan view of a portion of Figure 1 an OTP memory device;

[0011] Figure 4 is a cross-section through an OTP memory device according to different embodiments of the present disclosure;

[0012] Figure 5 is a simplified plan view of a portion of Figure 4 an OTP memory device;

[0013] Figure 6 is a simplified block diagram of an OTP memory according to an embodiment of the present disclosure;

[0014] Figure 7 is a more detailed block diagram of a first component of Figure 6 an OTP memory;

[0015] Figure 8 is a more detailed block diagram of a portion of Figure 7 a component;

[0016] Figure 9 is a more detailed block diagram of a second component of Figure 6 an OTP memory; and Figures 10-12 is an example of a circuit diagram related to a component of Figure 6 an OTP memory. DETAILED DESCRIPTION

[0017] The following description refers to the arrangement shown in the drawings; therefore, expressions such as "above", "below", "top", "bottom", "side", "end", "right", "left", and the like should not be interpreted as limiting expressions but as expressions referring to the drawings.

[0018] Reference is made to Figure 1A one-time programmable memory device or OTP (one-time programmable) memory device, in particular an OTP memory cell, indicated as a whole with the number 1 and comprising a fuse element 2 and a selector 3, both integrated into a semiconductor die 10. The fuse element 2 and the selector 3 are connected in series between a first line at a constant potential, for example a write line 5 at a write voltage VW, and a second line at a constant potential, for example a ground line 6 or a supply line at a negative voltage.

[0019] The fuse element 2 is of the type having a first impedance value in the unwritten or natively unprogrammed state and a second impedance value in the written or programmed state, wherein the first impedance value is lower than the second impedance value. For example, the first impedance value has a value at least two orders of magnitude, such as three orders of magnitude, lower than the second impedance value.

[0020] The selector 3 is defined by an enhanced high electron mobility transistor or HEMT (enhanced HEMT), i.e. normally-off. The selector 3 can be of the type Figure 1 operated by a drive circuit, not shown in the figure, to make the write current IW flow and to cause the fuse element to change from the unprogrammed state to the programmed state in an irreversible manner, for example by electromigration.

[0021] An intermediate node between the fuse element 2 and the selector 3 defines an output terminal la of the OTP memory cell 1.

[0022] Figure 2 and Figure 3 A portion of the semiconductor die 10 in which the OTP memory cell 1 is integrated is shown. The die 10 comprises a substrate 11 having mechanical support functions and / or electrical functions, for example made of silicon or silicon carbide, a channel layer 12 and a barrier layer 13. The channel layer 12 and the barrier layer 13 are made of respective semiconductor materials having different bandgaps and form a heterostructure 15 with a heterojunction 15a at a common interface. For example, the channel layer 12 is made of intrinsic gallium nitride (GaN), while the barrier layer 13 is made of aluminum gallium nitride (AlGaN) and has N-type conductivity. A two-dimensional electron gas (2DEG) 14 is formed in a channel region of the channel layer 12 at the heterojunction 15a. The die 10 further comprises a plurality of metallization levels, in each of which a respective conductive structure is formed, as detailed below.

[0023] The selector 3 is formed in the first portion of the die 10 and comprises a source contact 16, a drain contact 17, a gate region 18, a gate metallization structure 20 and a source field plate 21. The gate region 18 is made of gallium nitride (pGaN) doped to have a P-type conductivity. The gate region 18 modulates the thickness of a conductive channel formed at the interface between the channel layer 12 and the barrier layer 13 based on a voltage applied thereto and ensures that the HEMT device forming the selector 3 operates in a "normally-off" mode. The gate metallization structure 20 is obtained in a first one of the metallization levels, which is also referred to as gate metallization level and is indicated here with Ml.

[0024] The source field plate 21 is formed in a second one of the metallization levels, which is also referred to as field plate metallization level and is indicated here with M2, and partially extends over the gate metallization structure 20 and partially extends on the barrier layer 13 between the gate region 18 and the drain contact 17.

[0025] A dielectric structure comprising a first dielectric layer 22 and a second dielectric layer 23 covers the heterostructure 15, the gate region 18 and the gate metallization structure 20 and provides insulation from the source field plate 21. More specifically, the first dielectric layer 22 is formed on the heterostructure 15 and covers the side faces of the gate region 18, while leaving the gate metallization structure 20 exposed. The second dielectric layer 23 is formed on the first dielectric layer 22 and further covers the gate metallization structure 20 and separates the source field plate 21 from the gate metallization structure 20. Thus, the entire dielectric structure defined by the first dielectric layer 22 and the second dielectric layer 23 covers the gate region 18 and the gate metallization structure 20 (except for a portion of the top surface of the gate metallization structure 20, which will be contacted by a metal contact or plug, not shown in the figure) and insulates the gate region 18 and the gate metallization structure 20 from the source field plate 21.

[0026] The fuse element 2 is formed in the second portion of the die 10 and, in particular, in one embodiment, it is formed in the gate metallization level Ml, like the gate metallization structure 20. The fuse element 2 is in contact with a portion of the first dielectric layer 22 and covered by the second dielectric layer 23. Thus, the fuse element 2 is separated from the heterostructure 15 by the first dielectric layer 22 and completely encapsulated in dielectric material, except for the intermetallic via for providing the electrical coupling. Moreover, the fuse element 2 is distanced from and not in contact with the doped gallium nitride (pGaN) forming the gate region 18. Advantageously, there is dielectric all around the fuse element 2 and the distance from the doped gallium nitride region reduces heat dissipation and favors a fast temperature rise. In fact, dielectric material provides a better thermal insulation than doped gallium nitride. As a result, the fuse element 2 can be broken at a lower current and / or in a shorter time. From another perspective, the programming operation is made more reliable at a given same programming current.

[0027] The third dielectric layer 24 covers the first dielectric layer 22, the second dielectric layer 23, the gate region 18, the gate metallization structure 20 and the source field plate 21.

[0028] The metallization levels of the die 10 further comprise a plurality of wiring metallization levels at respective distances from the surface of the barrier layer above the source contact 16 and the drain contact 17 of the selector 3. In the described embodiment, in particular, the die 10 has three wiring metallization levels indicated by M3, M4 and M5, respectively. Wiring structures are formed in the wiring metallization levels M3-M5, in particular for high voltages and currents. The number of the shown wiring metallization levels is purely exemplary and does not limit the present disclosure.

[0029] Reference Figure 3 For example, for the OTP memory cell 1, the die 10 comprises a source pad 25 connected to the ground line 6 and arranged at the reference voltage, a drain pad 26 arranged at the supply voltage VDD, a gate pad 27 receiving a control voltage VG from a control unit external to the die 10 and not shown here, and a write pad 28 connected to the write line 5 and arranged at the write voltage VW. The source pad 25 and the drain pad 26 are connected to the source contact 16 and the drain contact 17, respectively, by portions of the wiring metallization levels M3-M5. The gate pad 27 is connected to the gate region 18 by the metallization structure 20 in the gate metallization level Ml. The write pad 28 is connected to the drain contact 17 by a portion of the wiring metallization levels M3-M5 and the fuse element 2, as already mentioned, in the embodiment of Figure 2 and Figure 3 The fuse element 2 is formed in the gate metallization level Ml. In particular, as Figure 3As better visible in the enlarged detail, the fuse element 2 comprises a narrowing of the conductive track 30 along the gate metallization level Ml, which connects the write line 5 (not shown here for simplicity) to the selector 3. In Figure 3 In the example shown, the fuse element 2 extends along a serpentine path and generally has a length and a width chosen to break at a desired time in response to a given write current flow. To improve control of the break location and timing, the conductive track 30 can have a further narrowing 30a having a minimum width in the conductive track 30. The further narrowing 30a can be located in a middle portion of the conductive track 30, for example at the center. The number, width and length of the straight portions and turns of the serpentine path can be chosen according to design preferences.

[0030] According to design preferences, connections between the metallization levels of the die 10 are formed by intermetallic vias 32.

[0031] In the embodiment of Figure 4 and Figure 5 wherein parts identical to those already shown are indicated with the same reference numerals, the fuse element (here indicated by 40) is formed in the field plate metallization level M2, in which the source field plate 21 is also formed. In this case, the fuse element 40 comprises a narrowing along a conductive track 41, which connects the write pad 28 and the drain contact 17 together with parts of the wiring metallization levels M3-M5. In Figure 4 and Figure 5 In the embodiment of

[0032] As shown in Figure 4 , the fuse element 40 is formed on the second dielectric layer 23 and embedded in the third dielectric layer 24, which also encloses the gate region 18, the gate metallization structure 20 and the source field plate 21. Thus, in this case, the fuse element 40 also benefits from the high thermal insulation of the entire dielectric material surrounding the doped gallium nitride and is not in contact with the doped gallium nitride, which is advantageous for heat dissipation. Moreover, the field plate metallization level M2 is generally thinner and has a greater resistivity than the gate metallization level Ml and the wiring metallization levels M3-M5, thus proving easier to break the fuse element 40. For example, the thickness of the field plate metallization level M2 can be 85 nm, while the thickness of the gate metallization level Ml can be 270 nm. Thus, the fuse element 40 has further advantages in terms of power consumption, programming time and reliability.

[0033] In principle, fuse elements can also be formed in the upper metallization levels M3-M5 (or generally M3-MN). However, the gate metallization level Ml and the field plate metallization level M2 have the advantage of being much thinner and thus have a greater resistivity, allowing the formation of fuse elements programmable with lower write currents or having a smaller size at the same write current.

[0034] It is also to be understood that the shape of the fuse elements, in particular the shape of the narrowing, can be chosen arbitrarily depending on design preferences.

[0035] The described OTP memory cells can advantageously be included in a system of monolithic GaN technology, i.e. in a system of GaN-HEMT devices and auxiliary components integrated monolithically in the same die. Thus, the present disclosure allows the transition from so-called system-in-package, in which components are assembled in the same package separately or in any case not monolithically, to system-on-chip, in which components are integrated in the same semiconductor support and have advantages in terms of performance, size and cost.

[0036] In the field of system-on-chip of monolithic GaN technology, the OTP memory cells can be used for different purposes.

[0037] For example, a group of OTP memory cells can be used for permanently storing a unique code for identification and tracking purposes.

[0038] The OTP memory cells can also be used for permanently configuring integrated devices. In particular, some series of integrated devices sharing a basic architecture and differing in a limited number of functions can be produced using the same manufacturing process. The functional blocks integrated in all devices of a series can be configured by the OTP memory cells downstream of the manufacturing to specialize their functions depending on the use. In this way, it is not necessary to diversify the manufacturing process due to the final marginal variations between the devices of a series. For example, it is not necessary to design different masks only for a few details.

[0039] Another extremely advantageous use involves the integration of an array of OTP memories for trimming integrated circuits to compensate for process dispersion or parameter drifts that can affect, for example, reference voltages and currents, oscillator frequencies and operational amplifier offsets.

[0040] Reference Figure 6 In one embodiment, a one-time programmable read-only memory or OTP memory 100 is integrated into a die 101 having the same structure as the die 10 of the Figure 2 and Figure 3 and in particular comprising a gallium nitride (GaN) channel layer, a barrier layer of aluminum gallium nitride (AlGaN) having N-type conductivity and a plurality of metallization levels, not shown here for simplicity.

[0041] The OTP memory 100 comprises a memory array 102, a row decoder 103, a command decoder 104, a shift register 105, a pull-up circuit 107 and a local bus 108. All components are made by using a monolithic GaN technology and are based on either enhancement or depletion mode HEMTs depending on design preferences.

[0042] The memory array 102 contains a plurality of bit cells 110 arranged in rows R0,..., Rm-1 which are selectively addressable by the row decoder 103 via row selection signals S0,..., Sm-1. Each row R0,..., Rm-1 comprises n bit cells 110. Each bit cell 110 comprises a respective OTP memory cell, e.g. as Figure 2 and Figure 3 OTP memory cell 1 as explained in more detail below.

[0043] The row decoder 103 (optional in case there is only one row of bit cells 110) selectively activates one of the rows R0,..., Rm-1 for a write, read or write-emulation operation in response to an address RADD received from an external processing unit (not shown).

[0044] The command decoder 104 (optional) receives commands CMD from the external processing unit and provides global enable signals W_EN, R_EN, S_EN via the local bus 108 for write, read and write-emulation operations. The global enable signals can comprise a global write signal W_EN, a global read signal R_EN and optionally a global write-emulation signal S_EN.

[0045] The local bus 108 is also used to distribute auxiliary signals Saux useful for managing write, read and write-emulation operations and are not described in detail herein.

[0046] The shift register 105, whose length n equals the number of bit cells 110 in each of the rows R0,..., Rm-1, allows for a serial loading of write data W0,..., Wn-1 to be written into the memory array 102 and a parallel loading of data read from the memory array 102. More precisely, when the command decoder 104 sets one of the global write signal W_EN and the global write-emulation signal S_EN to an active level for a write or write-emulation operation, data serially pre-loaded into the shift register 105 are transferred to the row R0,..., Rm-1 selected by the row decoder 103. Instead, when the command decoder 104 sets the global read signal R_EN to an active level and performs a read operation of the row R0,..., Rm-1 selected by the row decoder 103, read data are loaded into the shift register 105 in a parallel fashion and temporarily stored for external availability.

[0047] Figure 7 One of the rows R0,..., Rm-1, for example a generic row Ri, is shown in more detail and comprises the enable circuit 111 and the n bit cells 110. Each bit cell 110 comprises an OTP memory cell 1 and a read / write circuit 112 configured to perform read, write and optionally write emulation operations on the respective OTP memory cell 1.

[0048] The enable circuit 111 comprises a logic module 113 and a read bias circuit 115. The logic module 113 receives from the row decoder 103 the respective row selection signal Sj, from the command decoder 104 the enable signals W_EN, R_EN, S_EN and optionally one or more of the auxiliary signals Saux over the local bus 108. The logic module 113 is configured to determine the operating conditions of the bit cells 110, in particular of the read / write circuits 112, according to the local read signal R_ENL, the local write signal W_ENL and the local write emulation signal S_ENL generated according to one or more of the enable signals W_EN, R_EN, S_EN and possibly the auxiliary signals Saux, according to design preferences. The read bias circuit 115 provides a reference read current IWREF during read operations of the row Ri.

[0049] Figure 8 One of the read bias circuit 115 and the read / write circuit 112 of the row Ri is shown in more detail.

[0050] The read bias circuit 115 comprises a reference current generator 116 and forms a read current mirror 117 with the read / write circuit 112 of each bit cell 110 of the row Ri. More precisely, the read bias circuit 115 comprises a reference branch 117a of the current mirror 117 receiving a read reference current IRW from the reference current generator 116. The read / write circuit 112 comprises a mirror branch 117b of the current mirror 117 connected to the output terminal la of the OTP memory cell 1. The branches 117a, 117b each comprise a high- enhancement HEMT 118a, 118b and a depletion-mode HEMT 120a, 120b in series with each other and a read enable switch 121a, 121b defined for example by another high- enhancement HEMT and connected between the respective high-enhancement HEMT 118a, 118b and the respective depletion-mode HEMT 120a, 120b. The high-enhancement HEMTs 118a, 118b form a proper current mirror and have a gate terminal in common and connected to the drain terminal of the depletion-mode HEMT 120a of the reference branch 117a. The read enable switches 121a, 121b are controlled by the local read signal R_ENL provided by the logic module 113.

[0051] The read / write circuit 112 further comprises a pull-up switch 122, a write enable port 123, a multiplexer 124 and a latch circuit 125.

[0052] The pull-up switch 122 is controlled by the negated local read signal R_ENL in an opposite phase with respect to the read enable switches 121a, 121b, to connect the output terminal 1a of the OTP memory cell 1 to the pull-up circuit 107 when the read is not enabled.

[0053] The write enable port 123 controls the selector 3 as a function of the local write signal W_ENL and of the write data Wi received from the shift register 105 during the write step. When the local write signal W_ENL enables the write and the write data Wi is 1 (in the described example), the write enable port 123 turns on the selector 3 and allows the flow of the write current IW, which brings the fuse element 2 in the programmed state. Depending on the design preferences, the type of gate (AND, NAND, OR, NOR) is chosen based on the signal level used.

[0054] The multiplexer 124 has inputs connected to the output terminal 1a of the OTP memory cell 1 to receive the read signal indicative of the state of the OTP memory cell 1 during the read step, and to the respective outputs of the shift register 105 to receive the write data Wi during the write emulation step. The output of the multiplexer 124 is connected to the latch circuit 125. The data passed from the multiplexer 124 to the latch circuit 125 is selected, for example, on the basis of the local write emulation signal S_ENL. In particular, the multiplexer 124 is controlled to pass the write data Wi during the write emulation step, and otherwise to pass the data present on the output terminal 1a of the OTP memory cell 1.

[0055] The latch circuit 125, for example a D-type flip-flop, provides the output data Bi to the shift register 105. During the read step, the output data Bi is representative of the state of the OTP memory cell 1, while during the write emulation step the output data Bi is the write data Wi.

[0056] According to Figure 9By way of non-limiting example, the shift register 105 comprises n register units 105a connected in series, each register unit 105a comprising a bistable element, for example a D master / slave flip-flop 130, and a multiplexer 131. In detail, all multiplexers 131 have parallel inputs 131a connected to the respective bit cell 110 to receive the respective output data B0,..., Bn-1, a serial input 131b and an output connected to the data input of the respective flip-flop 130. The multiplexers 131 are controlled by a selection signal SEL provided directly by an external processing unit, not shown. In the first register unit 105a, i.e. the one most upstream in the sequence, the serial input 131b of the multiplexer 131 receives in turn the write data W0,..., Wn-1 to be loaded into the shift register 105 and written into one of the rows R0,..., Rm-1 of the memory array 102. In the subsequent register units 105a, the serial input 131b of the multiplexer 131 is connected to the data output of the flip-flop 130 of the immediately upstream register unit 105a. The data outputs of the flip-flops 130 define the n-bit parallel output of the shift register 105, while the data outputs of the flip-flops 130 of the register units 105a more downstream in the sequence define the serial output.

[0057] The OTP memory 100 advantageously described can be manufactured entirely by using monolithic GaN technology in a single die, in particular since the fuse element of each OTP memory cell is integrated in one of the metallization lines present in the same die.

[0058] The remaining components can be designed by using a single type of HEMT device, in particular N-channel HEMT devices, which can be integrated into a single die. For example, the circuits and logic gates can be implemented in resistive ratio logic.

[0059] The multiplexer 124 and the latch circuit 125 can be formed by way of example in Figure 10 .

[0060] In each register unit 105a of the shift register 105, the flip-flop 130 and the multiplexer 131 can be formed by way of non-limiting example as shown in Figure 11 .

[0061] The current reference can instead be provided as shown in the example of Figure 12 , using two series resistors, one with a negative temperature coefficient and one with a positive temperature coefficient, to obtain better stability with respect to temperature and to the supply voltage variation.

[0062] Finally, it is clear that modifications and variations can be made to the OTP memory device described and illustrated herein, without departing from the scope of the present disclosure as defined in the appended claims.

[0063] In one embodiment, the memory device comprises a plurality of OTP memory cells 1 identical to each other integrated into the die 101.

[0064] In one embodiment, the OTP memory cells 1 are arranged in rows R0,..., Rm-1, each row comprising a plurality of bit cells 110 and an enabling circuit 111, wherein each bit cell 110 comprises a respective one of the OTP memory cells 1 and a respective read / write circuit 112 configured to perform read and write operations on the respective OTP memory cell 1 and selectively operable by the enabling circuit 111.

[0065] In one embodiment, in each row R0,..., Rm-1, the enabling circuit 111 comprises a read bias circuit 115 forming a read current mirror circuit 117 with the read / write circuit 112 of each bit cell 10.

[0066] In one embodiment, the enabling circuit 111 defines a reference branch 117a of the read current mirror circuit 117 comprising a first enhancement-mode HEMT 118a and a first depletion-mode HEMT 120a in series with each other, wherein the read / write circuit 112 of each bit cell 110 defines a respective mirror branch 117b of the read current mirror circuit 117 coupled to the output la of the respective OTP memory cell 1 and comprising a second enhancement-mode HEMT 118b and a second depletion-mode HEMT 120b in series with each other, and wherein the first and second enhancement-mode HEMTs 118a, 118b have respective gate terminals in common and connected to a drain terminal of the first depletion-mode HEMT 120a.

[0067] In one embodiment, the read current mirror circuit 117 comprises a first read enable switch 121a defined by another HEMT and connected between the first enhancement-mode HEMT 118a and the first depletion-mode HEMT 120a, and, for each bit cell 110 of a respective row R0,..., Rm-1, a second read enable switch 121b defined by another HEMT and connected between the second enhancement-mode HEMT 118b and the second depletion-mode HEMT 120b of the respective mirror branch 117b.

[0068] In one embodiment, the memory device comprises a row decoder 103, a command decoder 104 and a shift register 105, all made by using GaN technology.

[0069] In one embodiment, in each row R0,..., Rm-1, the enable circuit 111 comprises a logic module 113 configured to generate local enable signals W_ENL, R_ENL, S_ENL from the row select signals S0,..., Sm-1 provided by the row decoder 103 and the global enable signals W_EN, R_EN, S_EN provided by the command decoder 104 and to determine the operation mode of the respective bit cell 110 from the local enable signals W_ENL, R_ENL, S_ENL.

[0070] In one embodiment, each read / write circuit 112 comprises a respective write enable port 123 configured to control the selector 3 of the respective OTP memory cell 1 from the local enable signals W_ENL, R_ENL, S_ENL and the write data Wi provided by the shift register 105.

[0071] In one embodiment, the shift register 105 is coupled to each of the rows R0,..., Rm-1 and configured for serial loading of write data W0,..., Wn-1 to be selectively written in the addressed row of the rows R0,..., Rm-1 during a write operation and for parallel loading of output data B0,..., Bn-1 read from the addressed row of the rows R0,..., Rm-1 during a read operation.

[0072] A one-time programmable (OTP) memory device can be summarized as comprising: a semiconductor die (10; 101); a one-time programmable (OTP) memory cell (1) integrated into the die (10; 101); wherein the die (10; 101) comprises: a channel layer (12) and a barrier layer (13) forming a heterostructure (15), wherein a heterojunction (15a) is located at an interface between the channel layer (12) and the barrier layer (13); and a plurality of metallization levels (M1-M5) above the heterostructure (15); wherein the OTP memory cell (1) comprises: a fuse element (2; 40) having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, wherein the first impedance value is lower than the second impedance value; and a selector (3) coupled in series to the fuse element (2; 40) and operable to flow a write current (IW) and to irreversibly bring the fuse element (2; 40) from the unprogrammed state into the programmed state; wherein the fuse element (2; 40) is formed in one of the metallization levels (M1-M5) of the die (10; 101); and wherein the selector (3) comprises a high electron mobility transistor (HEMT) formed at least partially in the heterostructure (15).

[0073] The selector (3) can comprise a normally-off enhancement-mode HEMT having a gate region (18) on a barrier layer (13).

[0074] The channel layer (12) can be made of intrinsic gallium nitride, the barrier layer (13) can be made of aluminum gallium nitride (AlGaN) and can have N-type conductivity, and the gate region (18) can be made of gallium nitride having P-type conductivity.

[0075] The selector (3) can comprise a gate metallization structure (20) on the gate region (18), wherein the metallization levels (M1-M5) can comprise a gate metallization level (M1), a source field plate (21), wherein the metallization levels (M1-M5) can comprise a field plate metallization level (M2).

[0076] The gate metallization structure (20) and the fuse element (2) can be formed in the gate metallization level (M1).

[0077] The source field plate (21) and the fuse element (40) can be formed in the field plate metallization level (M2).

[0078] The device can comprise a write power source (5), wherein the fuse element (2; 40) can comprise a narrowing along a conductive track (30, 41) connecting the write power source (5) to the selector (3).

[0079] The device can comprise a plurality of identical OTP memory cells (1) integrated into a die (101), wherein the OTP memory cells (1) can be arranged in rows (R0,..., Rm-1), each row can comprise a plurality of bit cells (110) and an enable circuit (111), wherein each bit cell (110) can comprise a respective one of the OTP memory cells (1) and a respective read / write circuit (112) configured to perform read and write operations on the respective OTP memory cell (1) and selectively operable by the enable circuit (111).

[0080] In each row (R0,..., Rm-1), the enable circuit (111) can comprise a read bias circuit (115) forming a read current mirror circuit (117) with the read / write circuit (112) of each bit cell (110), wherein the enable circuit (111) can define a reference branch (117a) of the read current mirror circuit (117) which can comprise a first enhancement-mode HEMT (118a) and a first depletion-mode HEMT (120a) in series with each other, wherein the read / write circuit (112) of each bit cell (110) can define a respective mirror branch (117b) of the read current mirror circuit (117) coupled to the output (1a) of the respective OTP memory cell (1) and can comprise a second enhancement-mode HEMT (118b) and a second depletion-mode HEMT (120b) in series with each other, and wherein the first enhancement-mode HEMT (118a) and the second enhancement-mode HEMT (118b) can have respective gate terminals which are common and connected to a drain terminal of the first depletion-mode HEMT (120a), wherein the read current mirror circuit (117) can comprise a first read enable switch (121a) defined by another HEMT and connected between the first enhancement-mode HEMT (118a) and the first depletion-mode HEMT (120a), and, for each bit cell (110) of the respective row (R0,..., Rm-1), a second read enable switch (121b) defined by another HEMT and connected between the second enhancement-mode HEMT (118b) and the second depletion-mode HEMT (120b) of the respective mirror branch (117b).

[0081] The device can comprise a row decoder (103), a command decoder (104) and a shift register (105), all of which are made by using GaN technology, wherein in each row (R0,..., Rm-1) the enable circuit (111) can comprise a logic module (113) configured to generate a local enable signal (W_ENL, R_ENL, S_ENL) from a row select signal (S0,..., Sm-1) provided by the row decoder (103) and a global enable signal (W_EN, R_EN, S_EN) provided by the command decoder (104) and to determine an operation mode of the respective bit cell (110) from the local enable signal (W_ENL, R_ENL, S_ENL), wherein each read / write circuit (112) can comprise a respective write enable port (123) configured to control a selector (3) of the respective OTP memory cell (1) from the local enable signal (W_ENL, R_ENL, S_ENL) and a write data (Wi) provided by the shift register (105), wherein the shift register (105) can be coupled to each of the rows (R0,..., Rm-1) and can be configured for serial loading of write data (W0,..., Wn-1) to be selectively written in a row addressed in the rows (R0,..., Rm-1) during a write operation and for parallel loading of output data (B0,..., Bn-1) read by a row addressed in the rows (R0,..., Rm-1) during a read operation.

[0082] The various embodiments described above can be combined to provide further embodiments. Aspects of an embodiment can be modified, if necessary to employ concepts of various patents, applications, and publications to provide yet further embodiments.

[0083] These and other changes can be made to the embodiments in light of the above- detailed description. The disclosed elements can be implemented in a variety of manners. In general, the terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the claims should be construed more broadly, in accordance with the principles of patent law. Accordingly, the claims are not limited to the embodiments described herein.

Claims

1. A one-time programmable, OTP, memory device, comprising: a semiconductor die, comprising: a heterostructure of a channel layer and a barrier layer having a heterojunction at an interface between the channel layer and the barrier layer; and a plurality of metallization levels over the heterostructure; a one-time programmable, OTP, memory cell integrated into the semiconductor die, the OTP memory cell comprising: a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, wherein the first impedance value is lower than the second impedance value; and a selector coupled in series to the fuse element and operable to cause a write current to flow and irreversibly change the fuse element from an unprogrammed state to a programmed state; wherein the fuse element is formed in one of the metallization levels of the semiconductor die; and wherein the selector comprises a high electron mobility transistor, HEMT, formed at least partially in the heterostructure.

2. The apparatus of claim 1, wherein, The selector comprises a normally-off enhancement-mode HEMT having a gate region located on the barrier layer.

3. The apparatus of claim 2, wherein, The channel layer is made of intrinsic gallium nitride, the barrier layer is made of aluminum gallium nitride and has N-type conductivity, and the gate region is made of gallium nitride having P-type conductivity.

4. The apparatus of claim 2, wherein, The selector comprises: a gate metallization structure on the gate region, wherein the metallization levels comprise a gate metallization level, and a source field plate, wherein the metallization levels comprise a field plate metallization level.

5. The apparatus of claim 4, wherein, The gate metallization structure and the fuse element are formed in the gate metallization level.

6. The apparatus of claim 4, wherein, The source field plate and the fuse element are formed in the field plate metallization level.

7. The device of claim 5, comprising a dielectric structure on the heterostructure, the gate region, and the gate metallization structure, wherein the dielectric structure separates the heterostructure from the fuse element, wherein the dielectric structure separates the source field plate from the gate region and the gate metallization structure, wherein the fuse element is in contact with the dielectric structure.

8. The apparatus of claim 7, wherein, The dielectric structure comprises a first dielectric layer on the heterostructure and a second dielectric layer on the first dielectric layer, and the fuse element is in contact with at least one of the first and second dielectric layers.

9. The apparatus of claim 8, wherein, The fuse element is formed on and in contact with a portion of the first dielectric layer, and is covered by the second dielectric layer.

10. The device of claim 8, comprising a third dielectric layer on the second dielectric layer, wherein the fuse element is formed on and in contact with a portion of the second dielectric layer, and is embedded in the third dielectric layer.

11. The device of claim 1, comprising a write power source, wherein the fuse element comprises a narrowed portion along a conductive track connecting the write power source to the selector.

12. The apparatus of claim 11, wherein, The fuse element extends along a serpentine path and the conductive track has a further narrowing having a minimum width in the conductive track and located at an intermediate portion of the conductive track.

13. The device of claim 1, comprising a plurality of identical OTP memory cell banks integrated into the semiconductor die, wherein the OTP memory cell banks are arranged in rows, each row comprising an enable circuit and a plurality of bit cells, wherein each bit cell comprises a respective one of the OTP memory cell banks and a respective read / write circuit configured to perform read and write operations on the respective OTP memory cell bank and selectively operable by the enable circuit.

14. The apparatus of claim 13, wherein, In each row, the enable circuit comprises a read bias circuit forming a read current mirror circuit with the read / write circuit of each bit cell, wherein the enable circuit defines a reference branch of the read current mirror circuit comprising a first enhancement-mode HEMT and a first depletion-mode HEMT in series with each other, wherein the read / write circuit of each bit cell defines a respective mirror branch of the read current mirror circuit coupled to an output of the respective OTP memory cell bank and comprising a second enhancement-mode HEMT and a second depletion-mode HEMT in series with each other, and wherein the first and second enhancement-mode HEMTs have respective gate terminals in common and connected to a drain terminal of the first depletion-mode HEMT, wherein the read current mirror circuit comprises a first read enable switch defined by another HEMT and connected between the first enhancement-mode HEMT and the first depletion-mode HEMT, and, for each bit cell of a respective row, a second read enable switch defined by another HEMT and connected between the second enhancement-mode HEMT and the second depletion-mode HEMT of the respective mirror branch.

15. The apparatus of claim 13, comprising a row decoder, a command decoder, and a shift register, all fabricated using GaN technology, wherein, In each row, the enable circuit comprises a logic module configured to generate a local enable signal from a row select signal provided by the row decoder and a global enable signal provided by the command decoder and to determine an operation mode of a respective bit cell from the local enable signal, wherein each read / write circuit comprises a respective write enable port configured to control a selector of the respective OTP memory cell bank from the local enable signal and write data provided by the shift register, wherein the shift register is coupled to each of the rows and configured for serial loading of write data to be selectively written to a row addressed in a write operation and for parallel loading of output data to be read by a row addressed in a read operation.

16. A system comprising: at least one one-time programmable, OTP, memory device, an OTP memory device of the at least one OTP memory device comprising: a semiconductor die comprising: a heterostructure comprising a channel layer and a barrier layer; a first enhancement-mode HEMT and a first depletion-mode HEMT in series with each other, wherein the first and second enhancement-mode HEMTs have respective gate terminals in common and connected to a drain terminal of the first depletion-mode HEMT, wherein the read current mirror circuit comprises a first read enable switch defined by another HEMT and connected between the first enhancement-mode HEMT and the first depletion-mode HEMT, and, for each bit cell of a respective row, a second read enable switch defined by another HEMT and connected between the second enhancement-mode HEMT and the second depletion-mode HEMT of the respective mirror branch. In each row, the enable circuit comprises a logic module configured to generate a local enable signal from a row select signal provided by the row decoder and a global enable signal provided by the command decoder and to determine an operation mode of a respective bit cell from the local enable signal, wherein each read / write circuit comprises a respective write enable port configured to control a selector of the respective OTP memory cell bank from the local enable signal and write data provided by the shift register, wherein the shift register is coupled to each of the rows and configured for serial loading of write data to be selectively written to a row addressed in a write operation and for parallel loading of output data to be read by a row addressed in a read operation.

16. A system comprising: at least one one-time programmable, OTP, memory device, an OTP memory device of the at least one OTP memory device comprising: a semiconductor die comprising: a heterostructure comprising a channel layer and a barrier layer; a heterojunction at an interface between the channel layer and the barrier layer; and a plurality of metallization levels over the heterostructure; an OTP memory cell integrated into the semiconductor die, the OTP memory cell including: a fuse element having a first impedance value in a native unprogrammed state and a second impedance value in a programmed state, wherein the first impedance value is lower than the second impedance value; and a selector coupled to the fuse element and operable to cause a write current to flow and cause the fuse element to change from an unprogrammed state to a programmed state.

17. The system of claim 16, wherein, the fuse element is included in one of the metallization levels of the semiconductor die; and wherein the selector includes a normally-off enhancement mode HEMT having a gate region located on the barrier layer.

18. The system of claim 16, wherein, the selector includes: a gate metallization structure on the gate region, wherein the metallization levels include a gate metallization level.

19. The system of claim 16, wherein, the selector includes: a source field plate, wherein the metallization levels include a field plate metallization level.

20. The system of claim 16, including a write power source, wherein the fuse element includes a narrowing along a conductive track connecting the write power source to the selector.

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