Built-in self-test system and method for MTP memory
By designing a built-in self-test system for MTP memory and using the mode state machine and signal state machine to generate flexible test operation signals, the problem of single function in the existing technology is solved, and flexible testing and function expansion of multiple areas of MTP memory are achieved.
Patent Information
- Application Number
- CN202410496368.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-24
- Publication Date
- 2025-10-24
AI Technical Summary
The built-in self-test function of existing MTP memories is single and cannot be applied to different storage areas at the same time. Test vectors cannot be generated flexibly, resulting in fixed read and write methods and single functions.
A built-in self-test (BIST) system for MTP memory is designed. It includes an address generator, a pattern generator, a signal generator, and a comparator. Through the combination of a pattern state machine and a signal state machine, flexible test operation signals are generated. The system supports multiple test modes and timing waveforms, enabling flexible testing of different storage areas.
It enables flexible testing of multiple areas of MTP memory, simplifies the test control process, expands chip functions, provides more flexible test options, and is easy to maintain and modify.
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Figure CN120833836A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip testing technical field, and particularly relates to a built-in self-test system and method for MTP memory. BACKGROUND
[0002] With the development of modern integrated circuit design technology and the improvement of digital chip manufacturing level, the functions that can be realized by chips are more and more rich, and the chips play more and more important roles in the society. The storage in the chip is divided into MTP (multi-time programmable), FTP (Few-Time Programmable) and OTP (One-Time Programmable), wherein the MTP can be programmed multiple times, which allows the stored information to be configured or modified by programming after the chip is manufactured, so as to realize different working modes or adapt to different application scenarios.
[0003] Built-in self-test (BIST) is an important technology in integrated circuit design, which establishes test generation, application, analysis and test control structure in the circuit, so that the circuit can test itself. The built-in self-test reduces the test cost, discovers potential faults as early as possible, improves the test efficiency, and improves the testability and reliability of the chip by integrating the self-test function in the chip.
[0004] The existing MTP memory uses a built-in self-test interface to receive signals when performing built-in self-test, generates a test mode through a built-in self-test controller, and interacts with the memory module through test mode handshake, erase handshake, program handshake, read handshake and the like. However, it cannot be applied to different storage areas of the MTP memory at the same time, cannot generate test vectors flexibly, and cannot change the read-write mode, so the function is single. SUMMARY
[0005] In view of the above analysis, the embodiments of the present application aim to provide a built-in self-test system for MTP memory to solve the problem that the existing built-in self-test function is single and cannot be applied to different storage areas of the MTP memory at the same time.
[0006] In one aspect, the embodiments of the present application provide a built-in self-test system for MTP memory, comprising:
[0007] An address generator for generating an address signal and sending the address signal to the MTP memory, the mode generator, the signal generator and the comparator;
[0008] a mode generator for generating a test operation signal according to the input region selection signal, mode selection signal and test sequence selection signal, starting a mode state machine and entering a test state corresponding to the test operation signal, sending a test state signal to the signal generator, comparator and MTP memory, and outputting a test result signal according to a comparison result of the comparator;
[0009] a signal generator for starting a signal state machine and entering a corresponding signal state according to the test state signal and preset time of the time sequence counter after receiving the address signal of the address generator and the test state signal of the mode generator, and sending the signal state to the MTP memory;
[0010] an MTP memory for starting a test according to the received address signal, test operation signal and signal state, and returning test data of each address signal to the comparator;
[0011] a comparator for comparing the test data of each address signal received with the address signal and test operation signal received, and feeding back a comparison result to the mode generator.
[0012] Further improvements based on the above system, the region selection signal is used to select a main storage area, EEPROM area and Information area of the MTP memory; the mode selection signal is used to select a test mode, including a read-write mode and a data retention read-write mode, and both are completed in a round of operation according to the operation order of writing first and reading later; and the test sequence selection signal is used to select test sequence data, including all zero, all 1, all 5A, all A5, chessboard mode data and diagonal mode data.
[0013] Further improvements based on the above system, the mode state machine includes an idle state, a plurality of region preparation states and a plurality of test states, the idle state is a default state after the mode state machine is started or a round of test operation is completed; each region preparation state is a state of each region selection signal, and each test state is a state combined according to the mode selection signal and test sequence selection signal in each region preparation state.
[0014] Further improvements based on the above system, after the mode generator enters the test state corresponding to the test operation signal, if an address end signal sent by the address generator is received, the next test state of the test state is entered, and a new test state signal is sent to the signal generator.
[0015] Further improvements based on the above system, the mode state machine further includes an error state and a correct state; when the comparison result received by the mode generator is an error, the error state is entered to output a test result error signal and then return to the idle state; when the comparison result received by the mode generator is a correct signal, the correct state is entered and then return to the idle state.
[0016] Based on further improvements of the above system, the signal states of the signal state machine include: multiple operation signal states, busy signal states and cooling signal states, where the operation signal states correspond to the operations in the received test status signal, including: write operation signal state, read operation signal state, retain write operation signal and retain read operation signal.
[0017] Based on a further improvement of the above system, after the MTP memory receives the address signal, test operation signal and signal status, it performs the operation corresponding to the signal status on each address signal in the area corresponding to the test operation signal according to the test sequence in the test operation signal; when the MTP memory performs a write operation or reserves a write operation on each address in turn, it returns a busy signal to the signal generator.
[0018] Based on the further improvement of the above system, the signal state machine in the signal generator enters the corresponding signal state according to the test status signal and the preset time of the timing counter. When the busy signal returned by the MTP memory is received, it enters the busy signal state until an address is written, and then enters the cooling signal state until the preset cooling time is reached. If the address end signal sent by the address generator is not received, a take next address signal is sent to the address generator, and the signal state corresponding to the test signal is returned; if the address end signal is received, it returns to the idle state and waits to enter the corresponding signal state according to the new test status signal.
[0019] Based on the further improvement of the above system, the signal generator includes multiple timing counters, which count multiple timings and generate and output timing waveforms corresponding to the signal states.
[0020] On the other hand, an embodiment of the present invention provides a built-in self-test method for an MTP memory, comprising the following steps:
[0021] When the enable signal and the address signal are received, the test operation signal is obtained according to the input area selection signal, the mode selection signal and the test sequence selection signal, the mode state machine is started and the test state corresponding to the test operation signal is entered, and the signal state machine is started;
[0022] Enter the signal state corresponding to the signal state machine according to the test state signal and the preset time of the timing counter, and start testing the MTP memory according to the address signal, the test operation signal and the signal state;
[0023] The test data of each address signal returned by the MTP memory is obtained, and compared with the address signal and the test operation signal in sequence. According to the comparison result, the test state corresponding to the mode state machine is entered and the test result signal is output.
[0024] Compared with the prior art, the present application can achieve at least one of the following beneficial effects:
[0025] 1. Through the mode state machine, different test operation signals are generated by flexible combination in three dimensions of area, mode and test sequence, and multiple areas of the MTP memory are tested in multiple functions, so that the test control flow is simplified; in the test process, the waveforms meeting the timing requirements in various states are generated through the state change of the signal state machine and multiple timing counters, so that the MTP chip function is facilitated to be expanded.
[0026] 2. The address generator, the mode generator, the signal generator and the comparator are realized through modular design, so that the maintenance and modification are facilitated; through the state change of the state machine, different test operations are dynamically added or reduced, and the output waveform is changed, so that the self-defined test scheme and the output waveform are realized, and more flexible test options are provided for users.
[0027] In the present application, the above technical solutions can be combined with each other to realize more preferred combination schemes. Other features and advantages of the present application will be described in the subsequent specification, and some advantages will become apparent from the specification, or will be understood by implementing the present application. The purposes and other advantages of the present application can be realized and obtained through the contents specifically indicated in the specification and the drawings. BRIEF DESCRIPTION OF DRAWINGS
[0028] The accompanying drawings are included to provide a further understanding of the present application and are incorporated herein and constitute a part of the application. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.
[0029] Figure 1 It is a structure schematic diagram of a built-in self-test system for MTP memory in the embodiment 1 of the present application.
[0030] Figure 2 It is a mode state machine schematic diagram of the mode generator in the embodiment 1 of the present application.
[0031] Figure 3 It is a signal state machine schematic diagram of the signal generator in the embodiment 1 of the present application.
[0032] Figure 4 It is a flow chart of a built-in self-test method for MTP memory in the embodiment 2 of the present application. DETAILED DESCRIPTION
[0033] The preferred embodiments of the present application will be specifically described below in combination with the drawings, wherein the drawings constitute a part of the present application, and are used to explain the principles of the embodiments of the present application, and are not used to limit the scope of the present application.
[0034] Embodiment 1
[0035] A specific embodiment of the present invention discloses a built-in self-test system for MTP memory, such as Figure 1 As shown, including:
[0036] An address generator, used to generate an address signal and send it to the MTP memory, the pattern generator, the signal generator and the comparator;
[0037] A pattern generator is configured to obtain a test operation signal based on an input region selection signal, a mode selection signal, and a test sequence selection signal, start a mode state machine and enter a test state corresponding to the test operation signal, send a test state signal to the signal generator, a comparator, and an MTP memory; and output a test result signal based on a comparison result of the comparator;
[0038] A signal generator is configured to, upon receiving an address signal from the address generator and a test state signal from the pattern generator, start a signal state machine and enter a corresponding signal state according to the test state signal and a preset time of a timing counter, and send the signal state to the MTP memory;
[0039] The MTP memory is used to start the test according to the received address signal, test operation signal and signal status, and obtain the test data of each address signal and return it to the comparator;
[0040] The comparator is used to compare the test data of each received address signal with the received address signal and the test operation signal, and feed back the comparison result to the pattern generator.
[0041] During implementation, the MTP memory's built-in self-test begins upon receiving an enable signal. Based on the region selection, mode selection, and test sequence selection signals sent to the system via the control bus, different test operation signals are flexibly combined to perform various functional tests on multiple regions of the chip. Furthermore, waveforms that meet timing requirements in various states can be generated, facilitating the expansion of MTP chip functionality.
[0042] The following is a detailed description of each component:
[0043] (1) Address Generator
[0044] The address generator accesses the addresses in the address space of the memory according to a set address generation mode, and generates corresponding address signals. The address generation mode includes a normal pattern, a diagonal pattern and a checkerboard pattern. In the normal pattern, the address generator generates addresses in a continuously increasing order, which is widely used in various data transmission, memory access and cache management scenarios. In the diagonal pattern, the address generator accesses the addresses of the memory in a diagonal line order. This mode can be used to test a specific area of the memory, or for a specific data distribution strategy, in which data is stored and accessed in a diagonal pattern. In the checkerboard pattern, the address generator alternately accesses odd and even addresses of the memory, forming a pattern similar to a checkerboard. This mode is often used to test the even-odd bit independence of the memory, or when alternating data distribution is required.
[0045] When the address generator receives the next address signal begin_next_addr generated by the signal generator, it sends the next address to the MTP memory, the pattern generator, the signal generator and the comparator, jumps to the next address of the test area and continues the test. When the address generator has taken all the addresses, it sends an address end signal to the MTP memory, the pattern generator, the signal generator and the comparator, indicating the end of the test.
[0046] (2) Pattern generator
[0047] It should be noted that the AHB control bus outputs the region selection signal, the mode selection signal and the test sequence selection signal to the pattern generator. The region selection signal is used to select the main storage area, the EEPROM area and the Information area of the MTP memory. The mode selection signal is used to select the test mode, including the read-write mode and the data retention read-write mode, both of which are completed in the operation order of writing first and then reading. That is, the read-write mode includes a write operation WR and a read operation RD in sequence, and the data retention read-write mode includes a data retention write operation MRGNWR and a data retention read operation MRGNRD in sequence. The test sequence selection signal is used to select the test sequence data, including all zeros, all ones, all 5As, all A5s, checkerboard pattern data and diagonal pattern data. All 5As means writing 01011010, and all A5s means writing 10100101.
[0048] The mode generator receives and identifies the corresponding signals and starts the mode state machine, which includes an idle state, a plurality of region preparation states and a plurality of test states. The idle state is the default state after the mode state machine is started or after a round of test operation is completed. Each region preparation state is the state of each region selection signal. Each test state is the state formed according to the combination of the mode selection signal and the test sequence selection signal in each region preparation state.
[0049] Specifically, as shown in Figure 2 The mode state machine enters the idle state IDLE by default, jumps to the corresponding region preparation state according to the region selection signal bist_block, and enters the specific test state according to the mode selection signal bist_mode and the test sequence selection signal bist_code. If the address end signal sent by the address generator is received, the next test state of the test state is entered, and a new test state signal is sent to the signal generator.
[0050] For example, when the region selection signal bist_block = 0, the region preparation state MEM1_IDLE of the main storage region is entered. The mode selection signal bist_mode = 0 corresponds to the read-write mode, which includes the write operation WR and the read operation RD in turn. The test sequence selection signal bist_code = 1 corresponds to the all-1 test sequence, which is identified as 11. Therefore, according to the sequence of the read-write operation, the test state MEM1_WR_11 corresponding to the write operation of the main storage region is entered. If the address end signal sent by the address generator is received, the test state MEM1_RD_11 corresponding to the read operation of the main storage region is entered.
[0051] Further, the mode state machine further includes an error state ERROR and a correct state CORRECT. When the mode generator receives the comparison result sent by the comparator, which is an error, the error state is entered to output the test result error signal test_error and then return to the idle state IDLE. When the mode generator receives the comparison result, which is a correct signal, the correct state is entered and then returns to the idle state IDLE. Returning to the idle state indicates that a round of test operation is completed. When the mode generator receives new region selection signals, mode selection signals and test sequence selection signals, a new round of test operation is started.
[0052] (3) Signal generator
[0053] It should be noted that when receiving the address signal of the address generator and the test state signal of the pattern generator, the start signal state machine enters the idle state IDLE by default. Since the embodiment can meet the timing requirements while self-testing, the signal generator further comprises a plurality of timing counters. When the preset time of the timing counter is reached, the signal state is entered according to the test state signal, and the waveform meeting the timing requirements can be recognized by the MTP memory, and the MTP memory can further perform corresponding test operations.
[0054] As shown in Figure 3 , the signal state of the signal state machine comprises a plurality of operation signal states, a busy signal state MTP_BUSY and a cooling signal state WR_WAIT, wherein the operation signal state corresponds to the operation in the received test state signal, and comprises a write operation signal state WRITE, a read operation signal state READ, a reserved write operation signal MRGNWRITE and a reserved read operation signal MRGNREAD.
[0055] Exemplarily, the preset time of the timing counter comprises the waiting time of the enable signal to the read / write operation, and the waiting time of the address signal to the read / write operation is preset to 100 ns. After the preset time is reached, the write operation WR in MEM1_WR_11 is entered according to the test state signal, and the corresponding write operation signal state WRITE is entered.
[0056] Specifically, after the signal state machine enters the write operation signal state WRITE or the reserved write operation signal state MRGNWRITE, the busy signal busy returned by the MTP memory is received, and the busy signal state MTP_BUSY is entered until a write operation is completed, and then the cooling signal state WR_WAIT is entered until the preset cooling time is reached. If the address end signal sent by the address generator is not received, the next address signal begin_next_addr is sent to the address generator, and the write operation signal state WRITE or the reserved write operation signal state MRGNWRITE is returned; if the address end signal is received, the step end signal test_step_done is sent, and the idle state is returned, and then the corresponding signal state is entered according to the new test state signal.
[0057] Further, when the signal state machine enters the read operation signal state READ and the reserved read operation signal state MRGNREAD according to the new test state, each address is read one by one, and when all the addresses are read, the operation end signal test_done is sent, and the idle state is returned, and then the corresponding signal state is entered according to the new test state signal.
[0058] It should be noted that the multiple time sequences are counted by the multiple time sequence counters, and the time sequence waveforms required by the MTP chip are generated and output, wherein the multiple time sequences include but are not limited to: the time from the rising edge of the enable signal to the rising edge of the current signal state (i.e. the waiting time of the enable signal to the current operation), the time from the address signal change time to the rising edge of the current signal state (i.e. the waiting time of the address signal to the current operation), the high level duration of the current signal state (i.e. the pulse width of the current operation), the time from the rising edge of the current signal state to the rising edge of the busy signal state (i.e. the time from the write / retained write operation to the busy signal), the time from the rising edge of the current signal state to the address signal change time (i.e. the time of one address of the write / retained write), and the time from the falling edge of the busy signal state to the rising edge of the next signal state (i.e. the cooling time).
[0059] (4) MTP memory
[0060] After the MTP memory receives the address signal, the test operation signal and the signal state, the signal state corresponding operation in the test sequence in the test operation signal is performed on each address signal in the corresponding area of the test operation signal in turn.
[0061] Specifically, when the signal state corresponds to the write operation signal state or the retained write operation signal state, the MTP memory writes the test sequence in one address in the corresponding area, returns the busy signal to the signal generator until one address is written, and then writes the test sequence to the next address received until all addresses are written, completing a step of testing; when the signal state corresponds to the read operation signal state or the retained read operation signal state, the data DOUT written in each address is read out and returned to the comparator, completing a round of test operation.
[0062] (5) Comparator
[0063] It should be noted that the test data of each address signal received by the comparator is the actual written data, and the data to be written in each address signal is obtained according to the received address signal and test operation signal. The actual written data and the data to be written are compared one by one according to the address signal. Once there is a discrepancy, it indicates that the comparison result is incorrect. If they are consistent, it indicates that the comparison result is correct. The comparison result is fed back to the pattern generator to promote the state transition of the pattern state machine in the pattern generator.
[0064] It should be noted that the address generator in the embodiment can customize the address generation mode to achieve different test requirements. If new area test or new test mode and test sequence is added / modified in the control signal, i.e. the test scheme is extended / adjusted, the mode generator can generate customized test operation signals by combining the selection signals, and the area preparation state and test state of the mode state machine are added / modified to correspond to the extended / adjusted test operation signals. The signal generator adds / modifies the corresponding signal state by using the signal state machine and adjusts the preset time of the timing counter to achieve the addition / change of the output waveform, thereby providing more flexible test options for users.
[0065] For example, the AHB control bus adds a memory cell current test mode in the mode selection signal to perform current test on each storage area of the MTP memory. Therefore, a current test state is added to each area preparation state in the mode state machine, such as a test state MEM1_CLEN in the main storage area. A corresponding current test operation signal state CLEN is added in the signal state machine, and a timing counter is added to count the timing and output the timing waveform.
[0066] Compared with the prior art, the built-in self-test system for the MTP memory provided by the embodiment can generate different test operation signals by flexibly combining the area, mode and test sequence through the mode state machine, perform multiple function tests on multiple areas of the MTP memory, and simplify the test control process. In the test process, the state change of the signal state machine and multiple timing counters are used to generate waveforms that meet the timing requirements in various states, which facilitates the expansion of the MTP chip function. The address generator, mode generator, signal generator and comparator are realized by modular design, which is easy to maintain and modify. By expanding the state of the state machine, different test operations and output waveforms are dynamically added / removed and changed, thereby realizing the customization of the test scheme and the output waveform and providing more flexible test options for users.
[0067] Embodiment 2
[0068] Another embodiment of the application is based on the built-in self-test system for the MTP memory in embodiment 1, and discloses a built-in self-test method for the MTP memory. The specific implementation of each step is described with reference to the corresponding description in embodiment 1. As shown in the figure, the method comprises the following steps: Figure 4
[0069] S1, when receiving the enable signal and the address signal, obtaining the test operation signal according to the input area selection signal, mode selection signal and test sequence selection signal, starting the mode state machine and entering the test state corresponding to the test operation signal, and starting the signal state machine;
[0070] S2, entering the corresponding signal state of the signal state machine according to the test state signal and the preset time of the time sequence counter, starting the test of the MTP memory according to the address signal, the test operation signal and the signal state;
[0071] S3, obtaining the test data of each address signal returned by the MTP memory, comparing the test data with the address signal and the test operation signal in sequence, entering the corresponding test state of the mode state machine according to the comparison result and outputting the test result signal.
[0072] Since the present embodiment is related to the aforementioned built-in self-test system for MTP memory, the two can be used as reference to each other, and thus the description is not repeated here. Since the method embodiment has the same principle as the system embodiment, the method embodiment also has the corresponding technical effects of the system embodiment.
[0073] Those skilled in the art can understand that all or part of the processes of the above-mentioned embodiments can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium. The computer readable storage medium includes a magnetic disk, an optical disk, a read-only memory, a random access memory, etc.
[0074] The above is only the preferred embodiment of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.
Claims
1. A built-in self-test system for MTP memory, characterized by, The application comprises: an address generator for generating address signals to the MTP memory, the mode generator, the signal generator and the comparator; a mode generator for obtaining test operation signals according to input area selection signals, mode selection signals and test sequence selection signals, starting a mode state machine and entering a test state corresponding to the test operation signals, sending test state signals to the signal generator, the comparator and the MTP memory; and outputting test result signals according to the comparison results of the comparator; a signal generator for starting a signal state machine and entering a corresponding signal state according to the test state signals and preset time of a timing counter after receiving the address signals of the address generator and the test state signals of the mode generator, and sending the signal state to the MTP memory; an MTP memory for starting a test according to the received address signals, test operation signals and signal states, and obtaining test data of each address signal and returning the test data to the comparator; a comparator for comparing the test data of each address signal received with the address signals and test operation signals received, and feeding back the comparison results to the mode generator.
2. The built-in self-test system for MTP memory of claim 1, wherein, The area selection signals are used for selecting the main storage area, EEPROM area and Information area of the MTP memory; the mode selection signals are used for selecting test modes, including read-write mode and data retention read-write mode, and each mode is completed in the operation order of writing first and reading later; and the test sequence selection signals are used for selecting test sequence data, including all zero, all 1, all 5A, all A5, chessboard mode data and diagonal mode data.
3. The built-in self-test system for MTP memory of claim 2, wherein, The mode state machine comprises an idle state, a plurality of area preparation states and a plurality of test states; the idle state is the default state after the mode state machine is started or a round of test operation is completed; each area preparation state is the state of each area selection signal; and each test state is a state combined according to the mode selection signals and test sequence selection signals in each area preparation state.
4. The built-in self-test system for MTP memory of claim 2, wherein, After the mode generator enters the test state corresponding to the test operation signals, if an address end signal is received from the address generator, the next test state of the test state is entered, and a new test state signal is sent to the signal generator.
5. The built-in self-test system for MTP memory of claim 3, wherein, The mode state machine further comprises an error state and a correct state; when the comparison results received by the mode generator are errors, the error state is entered, a test result error signal is output, and then the idle state is returned; when the comparison results received by the mode generator are correct signals, the correct state is entered, and then the idle state is returned.
6. The built-in self-test system for MTP memory of claim 2, wherein, The signal state of the signal state machine comprises a plurality of operation signal states, a busy signal state and a cooling signal state; the operation signal states correspond to the operations in the test state signals received, and comprise write operation signal state, read operation signal state, retention write operation signal and retention read operation signal.
7. The built-in self-test system for MTP memory of claim 6, wherein, The MTP memory receives address signals, test operation signals and signal states, and sequentially performs signal state corresponding operations on each address signal in the test operation signal corresponding area according to the test sequence in the test operation signal; when the MTP memory sequentially performs write operation or reserved write operation on each address, a busy signal is returned to the signal generator.
8. The built-in self-test system for MTP memory of claim 7, wherein, The signal state machine in the signal generator enters the corresponding signal state according to the test state signal and the preset time of the time sequence counter; when the busy signal returned by the MTP memory is received, the busy signal state is entered until the write of one address is completed, and then the cooling signal state is entered until the preset cooling time is reached; if the address end signal sent by the address generator is not received, the next address signal is sent to the address generator, and the signal state corresponding to the test signal is returned; if the address end signal is received, the idle state is returned, and the corresponding signal state is entered according to the new test state signal.
9. The built-in self-test system for MTP memory of claim 1, wherein, The signal generator includes a plurality of time sequence counters, which count a plurality of time sequences to generate and output the time sequence waveforms corresponding to the signal states.
10. A method for built-in self-test of MTP memory, characterized by, The method comprises the following steps: When the enable signal and the address signal are received, the test operation signal is obtained according to the input area selection signal, mode selection signal and test sequence selection signal, the mode state machine is started and the test state corresponding to the test operation signal is entered, and the signal state machine is started; The signal state machine enters the corresponding signal state according to the test state signal and the preset time of the time sequence counter, and the MTP memory starts testing according to the address signal, the test operation signal and the signal state; The test data of each address signal returned by the MTP memory is obtained, and is sequentially compared with the address signal and the test operation signal, and the test result signal is output according to the comparison result and the test state corresponding to the mode state machine is entered.