Image sensor and operating method thereof

Abstract

Provided are an image sensor and a method of operating the same, the image sensor including: a readout circuit configured to convert an electrical signal received from a pixel array into image data; and an image signal processor configured to process the image data. The image signal processor includes: a clock user configured to generate a first clock request signal and receive a first clock signal; a block clock management unit configured to receive the first clock request signal from the clock user, generate a second clock request signal corresponding to the first clock request signal, and receive a clock response signal and a second clock signal corresponding to the second clock request signal; and a top clock management unit configured to receive the second clock request signal from the block clock management unit, generate the clock response signal and the second clock signal, and transmit the clock response signal and the second clock signal to the block clock management unit.

Description

TECHNICAL FIELD

[0001] The present inventive concepts relate to image processing, and more particularly, to an image sensor providing a clock required for image processing through a clock management unit and an operating method thereof. BACKGROUND

[0002] Recently, as the performance of image sensors improves, image sensors have been widely applied to various home appliances in addition to portable devices such as smartphones and digital cameras. In the mobile device field, research has been actively conducted to reduce the power consumption of image sensors.

[0003] Image data provided from an image sensor is configured in units of frames, and can have a signal indicating the start of a frame. SUMMARY

[0004] Some example embodiments of the present inventive concepts provide an image sensor and an operating method thereof capable of reducing power and reducing or minimizing a delay in clock supply when a clock is supplied to the image sensor. The image sensor according to some example embodiments can be configured to ensure that no image data is input during a period between processing last image data of a current frame and processing first image data of a next frame. The image sensor can be configured to control a clock in a manner suitable for the image sensor (e.g., to implement an image processing operation of the image sensor) while reducing or minimizing power consumption based on utilizing characteristics of the image sensor.

[0005] According to some example embodiments of the inventive concepts, an image sensor can include a pixel array including a plurality of sensing pixels, a readout circuit configured to convert electrical signals received from the pixel array into image data, and an image signal processor configured to process the image data output from the readout circuit. The image signal processor can include a clock consumer, a block clock management unit, and a top clock management unit. The clock consumer can be configured to generate a first clock request signal and receive a first clock signal corresponding to the first clock request signal. The block clock management unit can be configured to receive the first clock request signal from the clock consumer, generate a second clock request signal corresponding to the first clock request signal, and receive a clock response signal and a second clock signal corresponding to the second clock request signal. The top clock management unit can be configured to receive the second clock request signal from the block clock management unit, generate the clock response signal and the second clock signal corresponding to the second clock request signal, and send the clock response signal and the second clock signal to the block clock management unit. The block clock management unit can be configured to generate the first clock signal corresponding to the first clock request signal based on the second clock signal and send the first clock signal to the clock consumer.

[0006] According to some example embodiments of the inventive concepts, an image sensor can include a plurality of clock users, a block clock management unit, and a top clock management unit. Each of the plurality of clock users can be configured to generate a first clock request signal and receive a first clock signal corresponding to the first clock request signal. The block clock management unit can be configured to receive the first clock request signal from each of the plurality of clock users, generate a second clock request signal corresponding to the first clock request signal, and receive a clock response signal and a second clock signal corresponding to the second clock request signal. The top clock management unit can be configured to receive the second clock request signal from the block clock management unit, generate the clock response signal and the second clock signal corresponding to the second clock request signal, and transmit the clock response signal and the second clock signal to the block clock management unit. The block clock management unit can be configured to generate the first clock signal corresponding to the first clock request signal based on the second clock signal and transmit the first clock signal to each of the plurality of clock users. The block clock management unit can be configured to generate the second clock request signal in response to receiving the first clock request signal from at least one of the plurality of clock users and stop generating the second clock request signal in response to stopping transmission of the first clock request signal from all of the plurality of clock users.

[0007] According to some example embodiments of the inventive concepts, an image sensor can include a plurality of clock users, a block clock management unit, and a top clock management unit. Each of the plurality of clock users can be configured to generate a first clock request signal and receive a first clock signal corresponding to the first clock request signal. The block clock management unit can be configured to receive the first clock request signal from each of the plurality of clock users, generate a second clock request signal corresponding to the first clock request signal, and receive a clock response signal and a second clock signal corresponding to the second clock request signal. The top clock management unit can be configured to receive the second clock request signal from the block clock management unit, generate the clock response signal and the second clock signal corresponding to the second clock request signal, and transmit the clock response signal and the second clock signal to the block clock management unit. The block clock management unit can be configured to generate the first clock signal corresponding to the first clock request signal based on the second clock signal and transmit the first clock signal to each of the plurality of clock users. The block clock management unit can be configured to generate the second clock request signal in response to receiving the first clock request signal from at least one of the plurality of clock users and stop generating the second clock request signal in response to stopping transmission of the first clock request signal from all of the plurality of clock users. BRIEF DESCRIPTION OF DRAWINGS

[0008] The example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and by comparison with the examples set forth in the prior art, of which: The example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and by comparison with the examples set forth in the prior art, of which:Figure 1 is a block diagram illustrating an image sensor according to some example embodiments; Figure 2 is a block diagram illustrating an image signal processor according to some example embodiments; Figure 3 is a block diagram illustrating an image signal processor according to some example embodiments; Figure 4 is a block diagram illustrating a block of an image signal processor according to some example embodiments; Figure 5A and Figure 5B is a timing diagram illustrating an operation of a block of an image signal processor and a transmission / reception signal according to some example embodiments; Figure 6 is a block diagram illustrating a block of an image signal processor according to some example embodiments; Figure 7A and Figure 7B is a timing diagram illustrating a signal according to an operation of a block of an image signal processor according to some example embodiments; Figure 8 is a block diagram illustrating a block of an image signal processor according to some example embodiments; Figure 9 is a timing diagram illustrating a signal according to an operation of a block of an image signal processor according to some example embodiments; Figure 10 is a timing diagram illustrating a signal according to an operation of a block of an image signal processor according to some example embodiments; Figure 11 is a block diagram illustrating a block of an image signal processor according to some example embodiments; Figure 12 is a timing diagram illustrating a signal according to an operation of a block of an image signal processor according to some example embodiments; Figure 13 is a flowchart illustrating an operation method of an image sensor according to some example embodiments; and Figure 14 is a block diagram illustrating an image sensor according to some example embodiments. DETAILED DESCRIPTION

[0009] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings.

[0010] It will be understood that elements and / or attributes recited in this specification as “same as,” “identical to,” or “equivalent to” other elements and / or attributes can be “same as,” “identical to,” or “equivalent to” other elements and / or attributes, and it will be further understood that elements and / or attributes recited in this specification as “same as,” “identical to,” or “equivalent to” other elements and / or attributes can be “same as,” “identical to,” or “equivalent to” or “substantially same as,” “substantially identical to,” or “substantially equivalent to” other elements and / or attributes. Elements and / or attributes that are “substantially same as,” “substantially identical to,” or “substantially equivalent to” other elements and / or attributes will be understood to include elements and / or attributes that are the same as, identical to, or equivalent to other elements and / or attributes within manufacturing tolerances and / or material tolerances. Elements and / or attributes that are the same as or substantially the same as, equivalent to or substantially equivalent to, or identical to or substantially identical to other elements and / or attributes can be structurally identical or substantially identical, functionally identical or substantially identical, and / or compositionally identical or substantially identical. Although the terms “same as,” “identical to,” or “equivalent to” can be used in the description of some example embodiments, it will be understood that there can be some inaccuracy. Thus, when an element or attribute is referred to as being the same as, identical to, or equivalent to another element or attribute, it will be understood that the element or attribute is the same as the other element or attribute within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0011] It will be understood that elements and / or attributes described herein as “substantially” the same, equivalent, and / or identical encompass elements and / or attributes that have a relative difference in magnitude equal to or less than 10%. Furthermore, whether an element and / or attribute is modified as “substantially” or not, it will be understood that such elements and / or attributes should be interpreted to include manufacturing tolerances or operational tolerances (e.g., ±10%) around the recited element and / or attribute.

[0012] When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operational tolerances (e.g., ±10%) around the stated value. Furthermore, when the words “about” and “substantially” are used in connection with a geometric shape, it is intended that precision of the geometric shape is not required, but that the degrees of freedom of the shape are within the scope of the present disclosure. Furthermore, whether a numerical value or a shape is modified as “about” or “substantially,” it will be understood that such values and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated value or shape. When a range is specified, the range includes all values therein such as in increments of 0.1%.

[0013] As described herein, when operations are described as being performed, or effects of structures are described as being established “by” or “through” performance of additional operations, it should be understood that the operations and / or effects / structures can be performed “based on” the additional operations, which can include performing the additional operations alone or in combination with other further additional operations.

[0014] Figure 1 is a block diagram illustrating an image sensor 100 according to some example embodiments.

[0015] The image sensor 100 can convert a light signal of an object (Object) incident through an optical lens LS into image data. The image sensor 100 can be mounted on an electronic device having an image or light sensing function. For example, the image sensor 100 can be mounted on an electronic device such as a digital still camera, a digital video camera, a smart phone, a wearable device, an Internet of Things (IoT) device, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation device, etc. Also, the image sensor 100 can be mounted on an electronic device provided as a component in a vehicle, furniture, manufacturing equipment, a door, various measuring devices, etc.

[0016] Referring to Figure 1 , the image sensor 100 can include a pixel array 1100, a readout circuit 1200, a control logic circuit 1300, an image signal processor 1400, and an output circuit 1500.

[0017] The pixel array 1100 can be implemented as a photoelectric conversion device such as a charge-coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS), and also as various types of photoelectric conversion devices. The pixel array 1100 can include a plurality of sensing pixels PX that convert a received light signal (light) into an electrical signal, and the sensing pixels PX can be arranged in rows and columns. Each sensing pixel PX can include a light sensing device. For example, the light sensing device can include a photodiode, an organic photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0018] The readout circuit 1200 can receive an electrical signal from the pixel array 1100, and convert the received electrical signal into image data. The readout circuit 1200 can amplify the electrical signal and perform analog-to-digital conversion on the amplified electrical signal. The image data generated by the readout circuit 1200 can include a plurality of pixels corresponding to the plurality of sensing pixels PX of the pixel array 1100. Here, the sensing pixels PX of the pixel array 1100 can be a physical structure that generates a signal according to a received light, and the pixels provided in the image data can represent data corresponding to the sensing pixels PX. The readout circuit 1200 can form a sensing core together with the pixel array 1100.

[0019] The control logic circuit 1300 can control the overall operation of the image sensor 100. In some example embodiments, the control logic circuit 1300 can control the readout circuit 1200, the image signal processor 1400, and the output circuit 1500 to generate image data IDT.

[0020] The image signal processor 1400 can perform image processing on the image data output from the readout circuit 1200. For example, the image signal processor 1400 can perform image processing, such as bad pixel correction, re-mosaicking, and noise removal, on the image data.

[0021] The output circuit 1500 can communicate with an external processor based on one of various high-speed interface methods. For example, the output circuit 1500 can communicate with the external processor based on a Mobile Industry Processor Interface (MIPI) method. The output circuit 1500 can convert the image data output from the image signal processor 1400 into image data IDT having a data format according to a set interface method, and can transmit the image data IDT to the external processor. The external processor can include a main processor, an application processor, or a graphic processor of an electronic device in which the image sensor 100 is mounted.

[0022] The control logic circuit 1300, the image signal processor 1400, and the output circuit 1500 can be implemented as digital circuits, and a clock signal can be provided to each digital circuit. When each digital circuit transmits a clock request signal to a clock management unit, the clock management unit can provide (e.g., transmit) a clock signal corresponding to the clock request signal to each digital circuit (e.g., in response to such transmission). Accordingly, the clock signal can be independently provided to the digital circuits in response to the clock request signal, and the clock management unit can refrain from providing the clock signal to one or more digital circuits without transmission of the clock request signal from the one or more digital circuits (e.g., can prevent the clock signal from being provided). In some example embodiments, the clock signal can be independently provided to the digital circuits only when the digital circuits need to operate (e.g., the clock signal can be provided to the digital circuits only in response to the clock request signal transmitted from the digital circuits). Accordingly, unnecessary power consumption of the image sensor 100 can be reduced or minimized (e.g., power efficiency of the image sensor 100 can be improved) without compromising operational performance of the image sensor 100 (e.g., without degradation in image processing operations performed by the image sensor 100, without reduction, minimization, or prevention of data loss in such image processing operations, etc.). Accordingly, functionality of the image sensor 100 can be improved.

[0023] Figure 2 is a block diagram illustrating the image signal processor 1400 according to some example embodiments.

[0024] Referring to Figure 2 , the image signal processor 1400 can include a plurality of intellectual property (IP) blocks 1410. In Figure 2 , the IP blocks 1410 are illustrated as including first to third IP blocks 1411, 1412, and 1413, but are not limited thereto, and the IP blocks 1410 can include two or more IP blocks.

[0025] Each of the IP blocks 1410 (i.e., the first to third IP blocks 1411, 1412, and 1413) can perform an image processing set as a function block for image processing, and the first to third IP blocks 1411, 1412, and 1413 can perform different image processing (e.g., different image processing operations). In some example embodiments, the first IP block 1411 can correct bad pixels of image data, the second IP block 1412 can perform re-stitching, and the third IP block 1413 can remove noise. The first to third IP blocks 1411, 1412, and 1413 can sequentially perform image processing on an image frame, but are not limited thereto. The IP blocks 1410 can perform image processing with a clock signal (e.g., can operate based on utilizing a received clock signal). Each of the IP blocks 1410 can be referred to herein as a clock consumer.

[0026] In the above, the IP blocks 1410 included in the image signal processor 1400 have been described as an example, but each of the IP blocks included in the digital circuit (such as the control logic circuit 1300 and the output circuit 1500) can also be a clock consumer.

[0027] Figure 3 is a block diagram illustrating an image signal processor 1400 according to some example embodiments. Figure 3 A clock architecture of the image signal processor 1400 is illustrated.

[0028] Referring to Figure 3 , the image signal processor 1400 can include a top clock management unit (or top CMU) 110, a plurality of blocks 120, and analog control logic 140.

[0029] Figure 3 The clock consumers included in each of the blocks 120 of Figure 2 may correspond to the IP blocks 1410 of Figure 2 , and the following clock signal management can correspond to the clock signal management provided to the IP blocks 1410 of

[0030] A top clock management unit 110 can provide n clock signals CLK1 to CLKn to n blocks BLK1 to BLKn through n channels CH1 to CHn. n can be 1 or more. In Figure 3 n can be any positive integer.

[0031] The n channels CH1 to CHn can be formed by transmitting and receiving n clock request signals REQ1 to REQn and n clock response signals ACK1 to ACKn corresponding to each other. The n clock request signals REQ1 to REQn can be transmitted from the n blocks BLK1 to BLKn to the top clock management unit 110, and the n clock response signals ACK1 to ACKn can be transmitted from the top clock management unit 110 to the n blocks BLK1 to BLKn. The top clock management unit 110 can simultaneously provide the n clock response signals ACK1 to ACKn and the n clock signals CLK1 to CLKn to the n blocks BLK1 to BLKn.

[0032] The time at which the top clock management unit 110 starts or stops providing the n clock signals CLK1 to CLKn to the n blocks BLK1 to BLKn can be the time at which the top clock management unit 110 starts or stops receiving the n clock request signals REQ1 to REQn from the n blocks BLK1 to BLKn. The n blocks BLK1 to BLKn can independently start or stop transmission of the n clock request signals REQ1 to REQn, respectively, and independently start or stop reception of the n clock response signals ACK1 to ACKn and the n clock signals CLK1 to CLKn, respectively.

[0033] The time at which the n blocks BLK1 to BLKn start to transmit the n clock request signals REQ1 to REQn to the top clock management unit 110 can be the same. Accordingly, the time at which the top clock management unit 110 starts to provide the n clock response signals ACK1 to ACKn and the n clock signals CLK1 to CLKn to the n blocks BLK1 to BLKn can be the same.

[0034] The time at which the n blocks BLK1 to BLKn start to transmit the n clock request signals REQ1 to REQn to the top clock management unit 110 can be different from each other. Accordingly, the time at which the top clock management unit 110 starts to provide the n clock response signals ACK1 to ACKn and the n clock signals CLK1 to CLKn to the n blocks BLK1 to BLKn can be different from each other.

[0035] The time when the n blocks BLK1 to BLKn stop sending the n clock request signals REQ1 to REQn to the top clock management unit 110 can be the same. Accordingly, the time when the top clock management unit 110 stops providing the n clock response signals ACK1 to ACKn and the n clock signals CLK1 to CLKn to the n blocks BLK1 to BLKn can be the same.

[0036] The time when the n blocks BLK1 to BLKn stop sending the n clock request signals REQ1 to REQn to the top clock management unit 110 can be different from each other. Accordingly, the time when the top clock management unit 110 stops providing the n clock response signals ACK1 to ACKn and the n clock signals CLK1 to CLKn to the n blocks BLK1 to BLKn can be different from each other.

[0037] Each of the n blocks BLK1 to BLKn can include a block clock management unit and a plurality of clock users. The number (quantity) of clock users included in the n blocks BLK1 to BLKn can be the same or different. For example, the first block BLK1 can include a first block clock management unit 130-1 and m clock users 1201-1 to 1201-m. For the following n blocks BLK1 to BLKn, the same configuration and operation as the first block BLK1 will be omitted or briefly described, and other configurations and operations will be described in more detail.

[0038] The first block clock management unit 130-1 can provide m clock signals CLK1-1 to CLK1-m to the m clock users 1201-1 to 1201-m. m can be 1 or more. In some example embodiments, m can be any positive integer. The first block clock management unit 130-1 can receive m clock request signals REQ1-1 to REQ1-m from the m clock users 1201-1 to 1201-m, and can send m clock signals CLK1-1 to CLK1-m corresponding to the m clock request signals REQ1-1 to REQ1-m to the m clock users 1201-1 to 1201-m. The first block clock management unit 130-1 can provide m clock signals CLK1-1 to CLK1-m in response to the m clock request signals REQ1-1 to REQ1-m without m clock response signals, i.e., without a channel. That is, the first block clock management unit 130-1 can provide m clock signals CLK1-1 to CLK1-m according to a method other than a handshake method.

[0039] The time when the m clock consumers 1201-1 to 1201-m start or stop receiving the m clock signals CLK1-1 to CLK1-m from the first block clock management unit 130-1 can be the time when the m clock consumers 1201-1 to 1201-m start or stop transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1.

[0040] The time when the m clock consumers 1201-1 to 1201-m start transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 can be the same. Accordingly, the time when the first block clock management unit 130-1 starts providing the m clock signals CLK1-1 to CLK1-m to the m clock consumers 1201-1 to 1201-m can be the same.

[0041] The time when the m clock consumers 1201-1 to 1201-m start transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 can be different from each other. Accordingly, the time when the first block clock management unit 130-1 starts providing the m clock signals CLK1-1 to CLK1-m to the m clock consumers 1201-1 to 1201-m can be different from each other.

[0042] The time when the m clock consumers 1201-1 to 1201-m stop transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 can be the same. Accordingly, the time when the first block clock management unit 130-1 stops providing the m clock signals CLK1-1 to CLK1-m to the m clock consumers 1201-1 to 1201-m can be the same.

[0043] The time when the m clock consumers 1201-1 to 1201-m stop transmitting the m clock request signals REQ1-1 to REQ1-m to the first block clock management unit 130-1 can be different from each other. Accordingly, the time when the first block clock management unit 130-1 stops providing the m clock signals CLK1-1 to CLK1-m to the m clock consumers 1201-1 to 1201-m can be different from each other.

[0044] Since the image sensor (100) is configured to receive the m clock signals CLK1-1 to CLK1-m from the first block clock management unit (130-1) and the m clock request signals REQ1-1 to REQ1-m from the second block clock management unit (130-2), the image sensor (100) can be configured to receive the m clock signals CLK1-1 to CLK1-m from the first block clock management unit (130-1) and the m clock request signals REQ1-1 to REQ1-m from the second block clock management unit (130-2) at the same time. Figure 1The image sensor 100 (which can be included in the image sensor 100, for example, as a part of the control logic circuit 1300 and / or a device implementing the same, which can be included in the image processing device 2000 illustrated in FIG. 1, for example, as a part of the application processor (AP) or a device implementing the same, any combination thereof, etc.) can have the following characteristics: image data can be processed frame by frame, image data can be transmitted in only one direction, and limited applications with a function of stopping processing, so the image sensor 100 can be configured to reduce or prevent subsequent image data loss. According to some example embodiments, the top clock management unit 110 can stably supply a clock signal to the block clock management unit through a channel formed by a handshaking method, and the block clock management unit can immediately supply a clock signal to a clock user in response to a clock request signal (for example, transmitted from the clock user) of the clock user, thereby reducing or minimizing a delay in clock supply to the clock user, and reducing, minimizing, or preventing data loss.

[0045] The analog control logic 140 (which can be included in the image sensor 100, for example, as a part of the control logic circuit 1300 and / or a device implementing the same, which can be included in the image processing device 2000 illustrated in FIG. 1, for example, as a part of the application processor (AP) or a device implementing the same, any combination thereof, etc.) can transmit a start signal to each clock user. The start signal can be a signal indicating an end time of a vertical blanking period of an image frame. That is, the start signal can be a signal indicating a start time of an active period of an image frame. The vertical blanking period can refer to a period between a time at which the operation of all clock users in the current image frame ends and a time at which the start signal is generated in the next image frame. Figure 14

[0046] Each clock user can generate a clock request signal in response to the start signal received from the analog control logic 140, but example embodiments are not limited thereto.

[0047] Hereinafter, the operation of the blocks of the image signal processor 1400 according to some example embodiments is described in detail with reference to Figure 4 , Figure 5A and Figure 5B .

[0048] Figure 4 is a block diagram illustrating the blocks of the image signal processor 1400 according to some example embodiments.

[0049] Figure 5A and Figure 5B are timing diagrams illustrating the operation of the blocks of the image signal processor 1400 according to some example embodiments and the transmission / reception of signals.

[0050] Reference is made to Figure 4 and Figure 5A ​The 1-1 clock consumer 1201-1 can generate a 1-1 clock request signal REQ1-1 and transmit the generated 1-1 clock request signal REQ1-1 to the first block clock management unit 130-1, and can receive a 1-1 clock signal CLK1-1 corresponding to the 1-1 clock request signal REQ1-1 from the first block clock management unit 130-1.

[0051] The 1-1 clock consumer 1201-1 can generate the 1-1 clock request signal REQ1-1 in response to a start signal received from the analog control logic 140. That is, the 1-1 clock consumer 1201-1 can generate the 1-1 clock request signal REQ1-1 at the end of the vertical blanking period Vblank of the image frame. For example, the 1-1 clock consumer 1201-1 can generate the 1-1 clock request signal REQ1-1 at a first time t1 at which the start signal is received (e.g., in response to receiving the start signal).

[0052] The first block clock management unit 130-1 can generate a second clock request signal REQ1 corresponding to the 1-1 clock request signal REQ1-1 and transmit the generated second clock request signal REQ1 to the top clock management unit 110, and can receive a clock response signal ACK1 and a second clock signal CLK1 corresponding to the second clock request signal REQ1 from the top clock management unit 110.

[0053] The first block clock management unit 130-1 can generate the second clock request signal REQ1 upon receiving (e.g., in response to receiving) any (e.g., at least one) of the m clock request signals REQ1-1 to REQ1-m. For example, the first block clock management unit 130-1 can generate the second clock request signal REQ1 at the first time t1 at which the 1-1 clock request signal REQ1-1 is received (e.g., in response to receiving the 1-1 clock request signal REQ1-1).

[0054] The top clock management unit 110 can generate the clock response signal ACK1 and the second clock signal CLK1 corresponding to the second clock request signal REQ1 received from the first block clock management unit 130-1 (e.g., the top clock management unit 110 can generate the clock response signal ACK1 and the second clock signal CLK1 in response to receiving the second clock request signal REQ1), and the top clock management unit 110 can transmit the generated clock response signal ACK1 and the second clock signal CLK1 to the first block clock management unit 130-1.

[0055] For example, the top clock management unit 110 can generate the clock response signal ACK1 and the second clock signal CLK1 at a first time t1 at which the second clock request signal REQ1 is received (e.g., in response to receiving the second clock request signal REQ1), the clock response signal ACK1 can remain high during a period from the first time t1 to a second time t2 at which the second clock request signal REQ1 remains high, and the second clock signal CLK1 can toggle during the period from the first time t1 to the second time t2 at which the second clock request signal REQ1 remains high.

[0056] The first block clock management unit 130-1 can transmit a 1-1 clock signal CLK1-1 corresponding to the 1-1 clock request signal REQ1-1 based on the second clock signal CLK1 received from the top clock management unit 110 (e.g., in response to receiving the second clock signal CLK1).

[0057] The first block clock management unit 130-1 can include a plurality of adapters 1301-1 to 1301-m and a plurality of clock gate units 1302-1 to 1302-m. The 1-1 adapter 1301-1 can control the 1-1 clock gate unit 1302-1. The 1-1 clock gate unit 1302-1 can transmit the 1-1 clock signal CLK1-1.

[0058] The 1-1 clock gate unit 1302-1 is a unit that performs clock gating, and can be disposed within the first block clock management unit 130-1. The 1-1 clock gate unit 1302-1 can be implemented in various ways, and can include logic elements such as flip-flops and AND gates. The 1-1 clock gate unit 1302-1 can transmit the 1-1 clock signal CLK1-1 or block transmission of the 1-1 clock signal CLK1-1 under the control of the 1-1 adapter 1301-1.

[0059] When the 1-1 clock request signal REQ1-1 is transmitted from the 1-1 clock user 1201-1 (e.g., in response to the 1-1 clock request signal REQ1-1 being transmitted from the 1-1 clock user 1201-1 and thus being received at the 1-1 adapter 1301), the 1-1 adapter 1301-1 can control the 1-1 clock gate unit 1302-1 to transmit the 1-1 clock signal CLK1-1, and when the transmission of the 1-1 clock request signal REQ1-1 from the 1-1 clock user 1201-1 is stopped (e.g., in response to the transmission of the 1-1 clock request signal REQ1-1 from the 1-1 clock user 120-1 being stopped), the 1-1 adapter 1301-1 can control the 1-1 clock gate unit 1302-1 to block the transmission of the 1-1 clock signal CLK1-1.

[0060] For example, when the 1-1 adapter 1301-1 receives the 1-1 clock request signal REQ1-1 (e.g., in response to the reception), the 1-1 adapter 1301-1 can generate the second clock request signal REQ1 corresponding to the 1-1 clock request signal REQ1-1, and transmit the generated second clock request signal REQ1 to the top clock management unit 110, and control the 1-1 clock gate unit 1302-1 to transmit the second clock signal CLK1 as the 1-1 clock signal CLK1-1 to the 1-1 clock user 1201-1. When the reception of the 1-1 clock request signal REQ1-1 is stopped (e.g., in response to the transmission of the 1-1 clock request signal REQ1-1 from the 1-1 clock user 120-1 being stopped), the 1-1 adapter 1301-1 can control the 1-1 clock gate unit 1302-1 to block the transmission of the 1-1 clock signal CLK1-1 to the 1-1 clock user 1201-1. That is, the first block clock management unit 130-1 can transmit the 1-1 clock signal CLK1-1 corresponding to the 1-1 clock request signal REQ1-1 to the 1-1 clock user 1201-1 during a period from a first time t1 at which the 1-1 clock request signal REQ1-1 is received, to a 1-1 time t1-1 at which the reception of the 1-1 clock request signal REQ1-1 is stopped.

[0061] Meanwhile, the first block clock management unit 130-1 can transmit the 1-2 clock signal CLK1-2 corresponding to the 1-2 clock request signal REQ1-2 to the 1-2 clock user 1201-2 during a period from a first time t1 at which the reception of the 1-2 clock request signal REQ1-2 is started, to a second time t2 at which the reception of the 1-2 clock request signal REQ1-2 is stopped.

[0062] The first block clock management unit 130-1 can stop generating the second clock request signal REQ1 when the reception of all the m clock request signals REQ1-1 to REQ1-m is stopped (e.g., in response to the transmission of all the m clock request signals REQ1-1 to REQ1-m being stopped). For example, if the 1-1 time t1-1 at which the 1-1 clock user 1201-1 stops generating the 1-1 clock request signal REQ1-1 is different from the second time t2 at which the 1-2 clock user 1201-2 stops generating the 1-2 clock request signal REQ1-2, the first block clock management unit 130-1 can stop generating the second clock request signal REQ1 at the later second time t2, and the top clock management unit 110 can stop transmitting the clock response signal ACK1 and the second clock signal CLK1 at the second time t2.

[0063] According to some example embodiments, a clock (e.g., a clock signal) can be selectively supplied to a clock user for a limited time period during which the clock is used to perform image processing (e.g., in response to a clock request signal sent by the clock user), and the clock (e.g., the clock signal) can be prevented from being supplied (e.g., provided, sent, etc.) to the clock user during a time period in which the clock user does not perform an image processing operation that utilizes the clock signal (e.g., in response to the clock request signal from the clock user being stopped from being sent). For example, the clock can be selectively supplied to the clock user only for a time period in which the clock user utilizes the clock to perform image processing for each of a plurality of IP blocks included in the image sensor 100 (as can be indicated by the sending of the clock request signal from the clock user), such that power (e.g., power consumption of the image sensor 100) due to unnecessary clock supply (e.g., supplying the clock during a time period in which the clock user does not utilize the clock to perform image processing) can be reduced or minimized. Thus, power consumption of the image sensor 100 can be reduced or minimized without compromising image processing performance of the image sensor 100 (e.g., without degradation in image processing operations performed by the image sensor 100, without reducing, minimizing, or preventing data loss in such image processing operations, etc.). Thus, functionality of the image sensor 100 can be improved.

[0064] Referring to Figure 4 and Figure 5B For example, when the 1-1 clock user 1201-1 and the 1-2 clock user 1201-2 generate and send the 1-1 clock request signal REQ1-1 and the 1-2 clock request signal REQ1-2, respectively, to the first block clock management unit 130-1 at a first time t1, in response, the first block clock management unit 130-1 can generate and send the second clock request signal REQ1 to the top clock management unit 110 at the first time t1 at which at least one of the 1-1 clock request signal REQ1-1 or the 1-2 clock request signal REQ1-2 is received.

[0065] The first block clock management unit 130-1 can generate and send the second clock request signal REQ1 during a time period, e.g., from the first time t1 to a second time t2, at which at least one of the 1-1 clock request signal REQ1-1 or the 1-2 clock request signal REQ1-2 is received (e.g., based on the receiving).

[0066] The top clock management unit 110 can generate (e.g., in response to the transmission of the second clock request signal REQ1) the clock response signal ACK1 during the period from the first time tl to the second time t2, and transmit the generated clock response signal ACK1 to the first block clock management unit 130-1, and can form the first channel CH1 during the period from the first time tl to the second time t2. During the period from the first time tl to the second time t2 in which the first channel CH1 is formed, the top clock management unit 110 can generate and transmit the second clock signal CLK1 to the first block clock management unit 130-1.

[0067] The 1-1 clock consumer 1201-1 can generate and transmit the 1-1 clock request signal REQ1-1 to the first block clock management unit 130-1 during the period from the first time tl to the 1-1 time t1-1, stop generating (and thus transmitting) the 1-1 clock request signal REQ1-1 during the period from the 1-1 time t1-1 to the 1-2 time t1-2, generate and transmit the 1-1 clock request signal REQ1-1 to the first block clock management unit 130-1 during the period from the 1-2 time t1-2 to the 1-3 time t1-3, and stop generating (and thus transmitting) the 1-1 clock request signal REQ1-1 at the 1-3 time t1-3. In response thereto, the 1-1 clock consumer 1201-1 can receive the 1-1 clock signal CLK1-1 during the period from the first time tl to the 1-1 time t1-1, stop receiving the 1-1 clock signal CLK1-1 during the period from the 1-1 time t1-1 to the 1-2 time t1-2, receive the 1-1 clock signal CLK1-1 during the period from the 1-2 time t1-2 to the 1-3 time t1-3, and stop receiving the 1-1 clock signal CLK1-1 at the 1-3 time t1-3.

[0068] Here, since the first block clock management unit 130-1 receives the second clock signal CLK1 from the top clock management unit 110 through the first channel CH1 during a period from the first time t1 to the second time t2, the 1-1 clock signal CLK1-1 corresponding to the 1-1 clock request signal REQ1-1 can be provided based on the second clock signal CLK1 immediately at a 1-2 time t1-2 at which the reception of the 1-1 clock request signal REQ1-1 is restarted after a 1-1 time t1-1 at which the reception of the 1-1 clock request signal REQ1-1 is stopped, and thus a delay for clock supply for the 1-1 clock user 1201-1 can be reduced or minimized, thereby enabling to selectively transmit a clock signal to the 1-1 clock user 1201-1 to reduce power consumption of the image sensor 100 while reducing, minimizing, or preventing a reduction in image processing performance of the image sensor 100 without impairing an image processing operation, thereby improving a function of the image sensor 100.

[0069] According to some example embodiments, a clock (e.g., a clock signal) can be supplied (e.g., transmitted, provided, etc.) to a clock user included in the image sensor 100 with a reduced or minimized delay, thereby performing a clock control suitable for the image sensor 100.

[0070] Figure 6 is a block diagram illustrating blocks of the image signal processor 1400 according to some example embodiments.

[0071] Figure 7A and Figure 7B is a timing diagram illustrating signals according to operations of the blocks of the image signal processor 1400 according to some example embodiments.

[0072] Referring to Figure 6 , the 1-3 clock user 1201-3 can generate the 1-3 clock request signal REQ1-3 based on the start signal transmitted from the analog control logic 140 and the enable signal generated by the 1-3 enable register 150-3.

[0073] The analog control logic 140 can transmit the start signal to a plurality of clock users. For example, the analog control logic 140 can transmit the start signal to the 1-1 clock user 1201-1, the 1-2 clock user 1201-2, and the 1-3 clock user 1201-3.

[0074] The 1-1 clock user 1201-1, the 1-2 clock user 1201-2, and the 1-3 clock user 1201-3 can include a 1-1 enable register 150-1, a 1-2 enable register 150-2, and a 1-3 enable register 150-3, respectively. The 1-1 enable register 150-1, the 1-2 enable register 150-2, and the 1-3 enable register 150-3 can each receive an enable control signal from the external CPU 200 (which can be included in the image sensor 100, for example, as part of the control logic circuit 1300 and / or a device implementing the same, which can be included in the image processing device 2000 shown in FIG. 1, for example, as part of an application processor (AP) or a device implementing the same, any combination thereof, etc.), and the like. The enable control signal can be a signal that changes the enable signal of the enable register to an active signal or a deactive signal. Figure 14

[0075] Referring to Figure 7A and Figure 7B If the enable signal is the active signal (e.g., in response to determining that the enable signal is the active signal while the start signal is received), the 1-3 clock user 1201-3 can generate the 1-1 clock request signal REQ1-1 in response to the start signal, and if (e.g., in response to determining that) the enable signal is the deactive signal (e.g., in response to determining that the enable signal is the deactive signal while the start signal is received), the 1-3 clock user 1201-3 can not respond to the start signal (e.g., can refrain from generating and / or transmitting the 1-1 clock request signal REQ1-1).

[0076] For example, as shown in Figure 7A When the 1-3 enable register 150-3 generates the high-level active signal in response to the enable control signal received from the CPU 200, in response, the 1-3 clock user 1201-3 can generate the 1-3 clock request signal REQ1-3 at a first time t1 at which the start signal becomes a high level (e.g., in response to the start signal becoming a high level), and transmit the generated 1-3 clock request signal REQ1-3 to the first block clock management unit 130-1, and can receive the 1-3 clock signal CLK1-3 corresponding to the 1-3 clock request signal REQ1-3 at the first time t1.

[0077] For example, as shown in Figure 7B ​As shown, if the 1-3 enable register 150-3 generates a low-level deactivation signal in response to the enable control signal received from the CPU 200, in response, the 1-3 clock user 1201-3 can not generate (e.g., can refrain from generating) the 1-3 clock request signal REQ1-3, and can not receive the 1-3 clock signal CLK1-3 at the first time t1 at which the start signal becomes a high level. At this time (e.g., at the first time t1), the 1-3 clock user 1201-3 can perform a bypass operation of outputting (e.g., transmitting) input image data as is without image processing. The bypass operation can be performed without a clock (e.g., without any clock).

[0078] According to some example embodiments, the supply of a clock (e.g., the supply of one or more clock signals) to at least one IP block of a plurality of IP blocks included in an image sensor configured to perform image processing for a particular (or, alternatively, predetermined) image frame, which can be a limited image frame (e.g., the clock can be controlled to be supplied to the at least one IP block only for the particular image frame for which the at least one IP block is performing an image processing operation, and not during image frames for which the at least one IP block is not performing an image processing operation, as indicated by no clock request signal being transmitted from the at least one IP block), or for a particular (or, alternatively, predetermined) time period, which can be a limited time period (e.g., the clock can be controlled to be supplied to the at least one IP block only for the particular time period for which the at least one IP block is performing an image processing operation, and not during separate particular time periods for which the at least one IP block is not performing an image processing operation, as indicated by no clock request signal being transmitted from the at least one IP block), can be controlled, thereby reducing or minimizing power (e.g., power consumption of the image sensor 100) due to unnecessary clock supply. Thus, the image sensor 100 can be configured to operate with reduced or minimized power consumption without compromising operational performance (e.g., without degrading in image processing operations performed by the image sensor 100, without reducing, minimizing, or preventing data loss in such image processing operations, etc.). Thus, functionality of the image sensor 100 can be improved.

[0079] Figure 8 is a block diagram illustrating blocks of the image signal processor 1400 according to some example embodiments.

[0080] Figure 9 is a timing diagram illustrating signals according to operations of the blocks of the image signal processor 1400 according to some example embodiments.

[0081] Reference is made to Figure 8 and Figure 9The analog control logic 140 can send a start signal to the 1-1 clock consumer 1201-1 and the 1-2 clock consumer 1201-2.

[0082] Meanwhile, the register 160 can generate a 1-3 clock request signal REQ1-3, and the 1-3 clock consumer 1201-3 can receive a 1-3 clock signal CLK1-3 corresponding to the 1-3 clock request signal REQ1-3 generated by the register 160. In some example embodiments, the register 160 can send the 1-3 clock request signal REQ1-3 to the 1-3 clock consumer 1201-3, and the 1-3 clock consumer 1201-3 can send the 1-3 clock request signal REQ1-3 to the block clock management unit 130-1 (e.g., to the 1-3 adapter 1301-3) based on receiving the 1-3 clock request signal REQ1-3 from the register 160, such that generating the 1-3 clock request signal REQ1-3 by the 1-3 clock consumer 1201-3 can include receiving the 1-3 clock request signal REQ1-3 from the register 160.

[0083] The 1-3 clock consumer 1201-3 can not receive a start signal from the analog control logic 140 (e.g., can not receive any start signal). Thus, the 1-3 clock consumer 1201-3 can receive the 1-3 clock signal CLK1-3 regardless of the start signal.

[0084] When the 1-3 clock request signal REQ1-3 is sent from the register 160 (e.g., in response to such sending), the 1-3 adapter 1301-3 can control the 1-3 clock gate unit 1302-3 to send the second clock signal CLK1 as the 1-3 clock signal CLK1-3 to the 1-3 clock consumer 1201-3. For example, the register 160 can generate the 1-3 clock request signal REQ1-3 at a second time t2 instead of the first time t1 at which the start signal is provided, and send the generated 1-3 clock request signal REQ1-3 to the 1-3 adapter 1301-3, and the 1-3 adapter 1301-3 can control the 1-3 clock gate unit 1302-3 to send the 1-3 clock signal CLK1-3 to the 1-3 clock consumer 1201-3 at the second time t2.

[0085] That is, the 1-1 clock user 1201-1 and the 1-2 clock user 1201-2 can generate the 1-1 clock signal CLK1-1 and the 1-2 clock signal CLK1-2 at the first time t1 when receiving the start signal, and send them to the first block clock management unit 130-1, and the register 160 can generate the 1-3 clock request signal REQ1-3 at the second time t2 different from the first time t1, and send the 1-3 clock request signal REQ1-3 to the first block clock management unit 130-1.

[0086] When sending of the 1-3 clock request signal REQ1-3 from the register 160 is stopped at the third time t3 (e.g., in response to stopping sending of the 1-3 clock request signal REQ1-3 from the register 160 at the third time t3), the 1-3 adapter 1301-3 may control the 1-3 clock gate unit 1302-3 to block sending of the 1-3 clock signal CLK1-3 to the 1-3 clock user 1201-3 at the third time t3.

[0087] According to some example embodiments, since the clock supply to at least one IP block configured to independently perform image processing among the IP blocks included in the image sensor 100 can be controlled regardless of the start signal, the power (e.g., power consumption) of the image sensor 100 caused by unnecessary clock supply can be reduced or minimized. Consequently, the image sensor 100 can be configured to operate with reduced or minimized power consumption without compromising operational performance (e.g., without degrading image processing operations performed by the image sensor 100, reducing, minimizing, or preventing data loss in such image processing operations, etc.). Consequently, the functionality of the image sensor 100 can be improved.

[0088] Figure 10 is a timing diagram illustrating signals according to operations of blocks of the image signal processor 1400 according to some example embodiments.

[0089] refer to Figure 10 The first block clock management unit 130-1 may transmit the 1-1 clock signal CLK1-1 corresponding to the 1-1 clock request signal REQ1-1 to the 1-1 clock user 1201-1 during a period from the first time t1 (i.e., the time when the 1-1 clock request signal REQ1-1 starts to be received) to the time t4-1 (i.e., the 4-1 time by which the first margin value (margin value 1) has elapsed since the fourth time t4 when the 1-1 clock signal CLK1-1 stops to be received). This may be done via the controller ( Figure 1 1300 in the preset and change the margin value.

[0090] The first-block clock management unit 130-1 can transmit the 1-2 clock signal CLK1-2 corresponding to the 1-2 clock request signal REQ1-2 to the 1-2 clock user 1201-2 during a period from a second time t2 (i.e., a time at which the reception of the 1-2 clock request signal REQ1-2 is started) to a time t5-1 (i.e., a 5-1 time has passed from the fifth time t5 at which the reception of the 1-2 clock request signal REQ1-2 is stopped by the second margin value (margin 2)). The first-block clock management unit 130-1 can transmit the 1-3 clock signal CLK1-3 corresponding to the 1-3 clock request signal REQ1-3 to the 1-3 clock user 1201-3 during a period from a third time t3 (i.e., a time at which the reception of the 1-3 clock request signal REQ1-3 is started) to a time t6-1 (i.e., a 6-1 time has passed from the sixth time t6 at which the reception of the 1-3 clock request signal REQ1-3 is stopped by the third margin value (margin value 3)).

[0091] The first margin value (margin value 1) can be 3 cycles, the second margin value (margin value 2) can be 4 cycles, and the third margin value (margin value 3) can be 2 cycles. That is, the margin values of the 1-1 clock user 1201-1, the 1-2 clock user 1201-2, and the 1-3 clock user 1201-3 can be different from each other, but are not limited thereto.

[0092] According to some example embodiments, based on the clock user retransmitting the clock request signal within the time margin value after the clock user stops transmitting the clock request signal of the clock user, it is possible to reduce or minimize the delay of the clock supply to the clock user, thereby enhancing the stability of the image processing operation of the image sensor 100, and thereby improving the operation performance (e.g., image processing performance) and / or operation reliability of the image sensor 100.

[0093] Figure 11 is a block diagram illustrating blocks of an image signal processor 1400 according to some example embodiments.

[0094] Figure 12 is a timing diagram of signals illustrating operations of blocks of the image signal processor 1400 according to some example embodiments.

[0095] Referring to Figure 11 and Figure 12 The first block BLK1 can include the first-block clock management unit 130-1 and the 1-1 clock user 1201-1 to the 1-5 clock user 1201-5.

[0096] The first block clock management unit 130-1 can include a 1-2 adapter 1301-2, a 1-4 adapter 1301-4, a 1-5 adapter 1301-5, a 1-2 clock gate unit 1302-2, a 1-4 clock gate unit 1302-4, a 1-5 clock gate unit 1302-5, and an OR gate unit 170.

[0097] The 1-1 clock consumer 1201-1 can not receive a start signal from the analog control logic 140 (e.g., can not receive any start signal), and there can be no corresponding clock gate unit and adapter.

[0098] The 1-2 clock consumer 1201-2 and the 1-3 clock consumer 1201-3 can receive a 1-2 clock signal CLK1-2 that corresponds to the 1-2 clock request signal REQ1-2 generated by the 1-2 clock consumer 1201-2 and sent to the first block clock management unit 130-1. The 1-3 clock consumer 1201-3 can not receive a start signal from the analog control logic 140, and there can be no corresponding clock gate unit and adapter. The 1-3 clock consumer 1201-3 can share the 1-2 adapter 1301-2 and the 1-2 clock gate unit 1302-2 with the 1-2 clock consumer 1201-2. For example, when (e.g., in response to) the 1-2 clock request signal REQ1-2 is sent from the 1-2 clock consumer 1201-2, the 1-2 adapter 1301-2 can control the 1-2 clock gate unit 1302-2 to send the second clock signal CLK1 as the 1-2 clock signal CLK1-2 and the 1-3 clock signal CLK1-3 to the 1-2 clock consumer 1201-2 and the 1-3 clock consumer 1201-3. That is, the 1-2 clock signal CLK1-2 and the 1-3 clock signal CLK1-3 can be the same clock signal.

[0099] When the transmission of the 1-2 clock request signal REQ1-2 from the 1-2 clock user 1201-2 is stopped (e.g., in response to such transmission being stopped), the 1-2 adapter 1301-2 can control the 1-2 clock gate unit 1302-2 to block transmission of the 1-2 clock signal CLK1-2 and the 1-3 clock signal CLK1-3 to the 1-2 clock user 1201-2 and the 1-3 clock user 1201-3. Thus, during a period from a first time tl at which the transmission of the 1-2 clock request signal REQ1-2 is started to a fifth time t5 at which the transmission of the 1-2 clock request signal REQ1-2 is stopped, the 1-2 clock user 1201-2 and the 1-3 clock user 1201-3 can receive the 1-2 clock signal CLK1-2 corresponding to the 1-2 clock request signal REQ1-2 (e.g., can receive the 1-2 clock signal CLK1-2 and the 1-3 clock signal CLK1-3, respectively). That is, the 1-3 clock user 1201-3 can operate during the same period as the 1-2 clock user 1201-2.

[0100] According to some example embodiments, the number of adapters and clock gate units included in the image sensor 100 can be reduced, thereby reducing power (e.g., power consumption) of the image sensor 100. Thus, the image sensor 100 can be configured to operate with reduced or minimized power consumption without compromising operational performance (e.g., without degrading in image processing operations performed by the image sensor 100, without reducing, minimizing, or preventing data loss in such image processing operations, etc.). Thus, functionality of the image sensor 100 can be improved.

[0101] The 1-4 clock user 1201-4 can receive the 1-4 clock signal CLK1-4 corresponding to the 1-4 clock request signal REQ1-4 generated by the 1-4 clock user 1201-4 and transmitted to the first block clock management unit 130-1, and the 1-5 clock user 1201-5 can receive the 1-5 clock signal CLK1-5 corresponding to at least one of the 1-4 clock request signal REQ1-4 or the 1-5 clock request signal REQ1-5 generated by the 1-5 clock user 1201-5 and transmitted to the first block clock management unit 130-1.

[0102] The OR unit 170 can receive at least one of the 1-4 clock request signal REQ1-4 or the 1-5 clock request signal REQ1-5 from the 1-4 clock user 1201-4 and the 1-5 clock user 1201-5, and can transmit the at least one of the 1-4 clock request signal REQ1-4 or the 1-5 clock request signal REQ1-5 to the 1-5 adapter 1301-5.

[0103] Accordingly, when at least one of the 1-4 clock request signal REQ1-4 or the 1-5 clock request signal REQ1-5 is received (e.g., in response to such reception at the 1-5 adapter 1301-5), the 1-5 adapter 1301-5 can control the 1-5 clock gate cell 1302-5 to transmit the 1-5 clock signal CLK1-5 corresponding to at least one of the 1-4 clock request signal REQ1-4 or the 1-5 clock request signal REQ1-5 to the 1-5 clock user 1201-5, and when both of the 1-4 clock request signal REQ1-4 and the 1-5 clock request signal REQ1-5 are stopped being received (e.g., in response to such reception stopping, transmission of both of the 1-4 clock request signal REQ1-4 and the 1-5 clock request signal REQ1-5 is stopped), the 1-5 adapter 1301-5 can control the 1-5 clock gate cell 1302-5 to block transmission of the 1-5 clock signal CLK1-5 to the 1-5 clock user 1201-5. The 1-5 clock user 1201-5 can receive the 1-5 clock signal CLK1-5 corresponding to at least one of the 1-4 clock request signal REQ1-4 or the 1-5 clock request signal REQ1-5. Accordingly, even during a period in which the 1-5 clock request signal REQ1-5 is stopped being transmitted from the second time t2 to the third time t3, the 1-5 clock user 1201-5 can receive the 1-5 clock signal CLK1-5 in response to transmission of the 1-4 clock request signal REQ1-4. That is, the 1-5 clock user 1201-5 can operate during the same period as the 1-4 clock user 1201-4. Meanwhile, the 1-5 clock user 1201-5 can even operate during a period independent of operation of the 1-4 clock user 1201-4.

[0104] The 1-1 clock user 1201-1 can not receive a start signal from the analog control logic 140 (e.g., can not receive any start signal), and there can be no corresponding clock gate cell and adapter. The 1-1 clock user 1201-1 can receive the second clock signal CLK1 as the 1-1 clock signal CLK1-1. For example, the first block clock management unit 130-1 can generate and send the second clock request signal REQ1 to the top clock management unit 110 during a period from a first time t1 at which it receives at least one of the 1-2 clock request signal REQ1-2, the 1-4 clock request signal REQ1-4, or the 1-5 clock request signal REQ1-5 to a sixth time t6 at which it stops receiving all of the 1-2 clock request signal REQ1-2, the 1-4 clock request signal REQ1-4, and the 1-5 clock request signal REQ1-5, and receive the second clock signal CLK1 corresponding to the second clock request signal REQ1. Accordingly, the 1-1 clock user 1201-1 can receive the second clock signal CLK1 as the 1-1 clock signal CLK1-1 during a period from the first time t1 at which it receives the second clock signal CLK1 to the sixth time t6.

[0105] According to some example embodiments, clock control suitable for the image sensor 100 can be performed based on relationships between clock users.

[0106] Figure 13 is a flowchart illustrating an operation method of an image sensor according to some example embodiments. The operation method can be implemented by an image sensor according to some example embodiments, including the image sensor 100 according to some example embodiments.

[0107] Hereinafter, n can refer to the number (e.g., the quantity) of blocks, m can refer to the number (e.g., the quantity) of clock users, and n and m can each be 1 or more. That is, one top clock management unit can manage n blocks, and one block clock management unit can manage m clock users. The number of clock users managed by each block clock management unit can be the same or different.

[0108] Referring to Figure 13 , the n-mth clock user 120n-m generates and sends a first clock request signal to the nth block clock management unit 130-n (S110) (S120).

[0109] The clock user or register (160) in Figure 8 may determine when to generate a clock request signal. For example, the clock user can generate a clock request signal when it receives a start signal from the analog control logic (140) in Figure 3the clock request signal generated in 160 of FIG. 1 can be a signal generated only for a certain clock user. The start signal can be maintained for a plurality of periods, and the time at which the start signal changes from a low level to a high level, the number of periods for which the start signal is maintained, and the time at which the start signal changes from a high level to a low level can be predetermined and changed by the controller (not shown) in 1300 of FIG. 1. Figure 8 The clock request signal generated in 160 of FIG. 1 can be a signal generated only for a certain clock user. The start signal can be maintained for a plurality of periods, and the time at which the start signal changes from a low level to a high level, the number of periods for which the start signal is maintained, and the time at which the start signal changes from a high level to a low level can be predetermined and changed by the controller (not shown) in 1300 of FIG. 1. Figure 1 The n-block clock management unit 130-n generates a second clock request signal corresponding to the first clock request signal (S130), and transmits the second clock request signal to the top clock management unit 110 (S140).

[0110] The n-block clock management unit 130-n can generate the second clock request signal when (e.g., in response to receiving) the first clock request signal is received from one of the m clock users, and can stop generating the second clock request signal when (e.g., in response to stopping) the first clock request signal is transmitted from all of the m clock users.

[0111] Operations S110 to S140 can be operations that can be performed without a clock.

[0112] The top clock management unit 110 generates a clock response signal and a second clock signal in response to the second clock request signal (S150), and transmits the clock response signal and the second clock signal to the n-block clock management unit 130-n (S160). Operations S140 and S150 can indicate that a handshake method is applied to a communication method between the top clock management unit 110 and the n-block clock management unit 130-n.

[0113] The n-block clock management unit 130-n generates a first clock signal corresponding to the first clock request signal based on the second clock signal (S170), and transmits the first clock signal to the n-m clock users 120n-m (S180).

[0114] In operation S170, the n-block clock management unit 130-n can transmit the first clock signal to the n-m clock users 120n-m without generating and transmitting a clock response signal corresponding to the first clock signal to the n-m clock users 120n-m, which can indicate that a communication method between the n-block clock management unit 130-n and the n-m clock users 120n-m is irrelevant to a handshake method.

[0115] The first clock signal transmitted by the n-th clock management unit 130-n to the n-m clock consumer 120n-m can be maintained until the first clock request signal of the n-m clock consumer 120n-m is stopped being transmitted, but example embodiments are not limited thereto. The first clock signal transmitted by the n-th clock management unit 130-n to the n-m clock consumer 120n-m can be maintained until a margin value of time elapses after the time at which the first clock request signal of the n-m clock consumer 120n-m is stopped being transmitted.

[0116] That is, according to some example embodiments, the top clock management unit and the block clock management unit can provide a clock signal based only on a clock request signal of a clock consumer, and can not provide a clock signal without considering a clock request signal of a clock consumer.

[0117] Figure 14 is a block diagram illustrating an image processing apparatus 2000 according to some example embodiments.

[0118] Figure 14 The image processing apparatus 2000 of

[0119] Referring to Figure 14 The image processing apparatus 2000 according to some example embodiments can include an application processor (AP) 2100, an image sensor 2200, a display apparatus 2400, a working memory 2500, a storage 2600, a user interface 2700, and a wireless transceiver 2800.

[0120] The AP 2100 can control overall operations of the image processing apparatus 2000, and can be provided as a system on chip (SoC) that runs an application program, an operating system, etc.

[0121] The AP 2100 can provide image data received from the image sensor 2200 to the display apparatus 2400 or store the image data in the storage 2600. In some example embodiments, the AP 2100 can further include an image signal processor that performs image processing on image data received from the image sensor 2200. The image signal processor provided in the AP 2100 can perform various image processing such as noise removal, demosaicing, sharpening, and high dynamic range (HDR) processing on the image data.

[0122] The image sensor 2200 can generate image data (e.g., raw image data) based on a received light signal, and provide the image data to the image signal processor 2300.

[0123] The image sensor 2200 can be an image sensor 100 according to some example embodiments, including as described above with reference to Figures 1 to 12the image sensor 100 of any one or more of the above. As above with reference to the image sensor 100 and Figures 1 to Figure 12 As described above with reference to any one or more of the image sensor 100, the image sensor 2200 can include a plurality of clock users, a plurality of block clock management units, and a top clock management unit, and each block clock management unit can transmit a second clock request signal to the top clock management unit in response to a first clock request signal received from at least one clock user of the plurality of clock users, the top clock management unit can transmit each clock response signal corresponding to each second clock request signal, and the top clock management unit can transmit a second clock signal to each block clock management unit through a channel formed by transmitting and receiving the second clock request signal and the clock response signal. When the second clock signal is transmitted through the channel (e.g., in response to such transmission), each block clock management unit can transmit a first clock signal corresponding to the first clock request signal to the clock user that has transmitted the first clock request signal among the clock users based on the second clock signal. Accordingly, the image sensor 2200 can supply a clock only when necessary for performing image processing for each clock user, thereby reducing power consumption due to unnecessary clock supply. Accordingly, the image sensor 2200, and thus the image processing apparatus 2000 including the image sensor 2200, can be configured to operate with reduced or minimized power consumption without compromising operational performance (e.g., no degradation in image processing operations performed by the image sensor 100, reduction, minimization, or prevention of data loss in such image processing operations, etc.). Accordingly, the functionality of the image sensor 2200, and thus the image processing apparatus 2000, can be improved.

[0124] The working memory 2500 can be implemented as a volatile memory (e.g., DRAM, SRAM, etc.) or a non-volatile resistive memory (e.g., FeRAM, RRAM, or PRAM). The working memory 2500 can store programs and / or data processed or executed by the AP 2100.

[0125] The storage 2600 can be implemented as a non-volatile memory device, such as a NAND flash, a resistive memory, etc., and for example, the storage 2600 can be provided as a memory card (MMC, eMMC, SD, microSD), etc. The storage 2600 can store data and / or programs for an execution algorithm for controlling image processing operations of the image signal processor 2300, and when the image processing operations are performed, the data and / or programs can be loaded into the working memory 2500.

[0126] In some example embodiments, the storage 2600 can store image data generated by the image signal processor 2300, such as transformed image data or post-processed image data.

[0127] The user interface 2700 can be implemented as various means for receiving user input, such as a keypad, a curtain key panel, a touch panel, a fingerprint sensor, and a microphone. The user interface 2700 can receive a user input and provide a signal corresponding to the received user input to the AP 2100.

[0128] The wireless transceiver 2800 can include a transceiver 2810, a modem 2820, and an antenna 2830.

[0129] As described herein, any apparatus, system, module, component, unit, block, controller, circuit, and / or and / or any part thereof (including but not limited to the image sensor 100, the pixel array 1100, the readout circuit 1200, the control logic circuit 1300, the image signal processor 1400, the output circuit 1500, the plurality of IP blocks 1410, the first IP block 1411, the second IP block 1412, the third IP block 1413, the top clock management unit 110, the plurality of blocks 120, the block clock management unit 130-1 to 130-n, the analog control logic 140, the OR gate unit 170, the plurality of clock users 1201-1 to 120n-m, the plurality of adapters 1301-1 to 1301-m, the plurality of clock gate units 1302-1 to 1302-m, the plurality of enable registers 150-1 to 150-3, the register 160, the CPU 200, the image processing apparatus 2000, the AP 2100, the image sensor 2200, the image signal processor 2300, the display apparatus 2400, the working memory 2500, the storage apparatus 2600, the user interface 2700, the wireless transceiver 2800, any part thereof, etc.) according to any example embodiment can include, can be included in, and / or can be implemented by one or more example processing circuitry (e.g., hardware including logic circuitry, hardware / software combination such as a processor executing software, or a combination thereof). For example, the processing circuitry can include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry can include a non-transitory computer-readable storage device (e.g., a memory such as a solid state drive (SSD)) storing a program of instructions and a processor (e.g., a CPU) configured to run the program of instructions to implement functions and / or methods performed by some or all of any apparatus, system, module, component, unit, block, controller, circuit, and / or part thereof according to any example embodiment.

[0130] While the inventive concept has been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor comprising: a pixel array comprising a plurality of sensing pixels; a readout circuit configured to convert electrical signals received from the pixel array into image data; an image signal processor configured to process image data output from the readout circuit, wherein the image signal processor comprises: a clock user configured to generate a first clock request signal and receive a first clock signal corresponding to the first clock request signal, a block clock management unit configured to receive the first clock request signal from the clock user, generate a second clock request signal corresponding to the first clock request signal, and receive a clock response signal and a second clock signal corresponding to the second clock request signal, and a top clock management unit configured to receive the second clock request signal from the block clock management unit, generate the clock response signal and the second clock signal corresponding to the second clock request signal, and send the clock response signal and the second clock signal to the block clock management unit, and wherein the block clock management unit is configured to generate the first clock signal corresponding to the first clock request signal based on the second clock signal and send the first clock signal to the clock user.

2. The image sensor of claim 1, wherein the block clock management unit is configured to send the first clock signal corresponding to the first clock request signal from a time when the first clock request signal is started to be received to a time when the first clock request signal is stopped to be received.

3. The image sensor of claim 1, wherein the block clock management unit comprises: a clock gate unit configured to send the first clock signal; and an adapter configured to control the clock gate unit, and the adapter is configured to send the first clock signal through the clock gate unit in response to the first clock request signal being sent from the clock user and to prevent the clock gate unit from sending the first clock signal in response to the first clock request signal being stopped to be sent from the clock user.

4. The image sensor of claim 1, further comprising: an analog control logic configured to send a start signal to the clock user indicating an end point of a vertical blanking period of an image frame, wherein the clock user is configured to generate the first clock request signal in response to the start signal.

5. The image sensor of claim 1, further comprising: an analog control logic configured to send a start signal to the clock user indicating an end point of a vertical blanking period of an image frame; and an analog control logic configured to send a start signal to the clock user indicating an end point of a vertical blanking period of an image frame; and an enable register configured to generate an enable signal for controlling activation of operation of the clock user, wherein the clock user is configured to generate the first clock request signal in response to the start signal based on the enable signal being an active signal; and not respond to the start signal based on the enable signal being an inactive signal.

6. The image sensor of claim 1, further comprising: a register configured to control activation of operation of the clock user, wherein the register is configured to generate the first clock request signal.

7. The image sensor of claim 1, wherein the block clock management unit is configured to transmit the first clock signal corresponding to the first clock request signal from a time at which the first clock request signal is first received to a time at which a margin value elapses from when the first clock request signal is stopped being received.

8. An image sensor, comprising: a plurality of clock users, each of the plurality of clock users configured to generate a first clock request signal and receive a first clock signal corresponding to the first clock request signal; a block clock management unit configured to receive the first clock request signal from each of the plurality of clock users, generate a second clock request signal corresponding to the first clock request signal, and receive a clock response signal and a second clock signal corresponding to the second clock request signal; and a top clock management unit configured to receive the second clock request signal from the block clock management unit, generate the clock response signal and the second clock signal corresponding to the second clock request signal, and transmit the clock response signal and the second clock signal to the block clock management unit, wherein the block clock management unit is configured to generate a first clock signal corresponding to the first clock request signal based on the second clock signal and transmit the first clock signal to each of the plurality of clock users, and wherein the block clock management unit is configured to generate the second clock request signal in response to receiving the first clock request signal from at least one of the plurality of clock users and stop generating the second clock request signal in response to stopping transmission of the first clock request signal from all of the plurality of clock users.

9. The image sensor of claim 8, wherein the top clock management unit is configured to transmit the second clock request signal, the clock response signal, and the second clock signal to each of a plurality of block clock management units, including the block clock management unit, and receive the second clock request signal, the clock response signal, and the second clock signal from each of the plurality of block clock management units.

10. The image sensor of claim 8, wherein ​ The plurality of clock users includes a first clock user and a second clock user, wherein the image sensor further includes: an analog control logic configured to send a start signal indicating an end point of a vertical blanking period of an image frame to the first clock user; and a register configured to control activation of operation of the second clock user, and the first clock user is configured to generate a first clock request signal in response to the start signal, and the first clock request signal of the second clock user is generated by the register.

11. The image sensor of claim 10, wherein the first clock user is configured to generate a first clock request signal at a time different from a time at which the register generates a first clock request signal.

12. The image sensor of claim 8, wherein the block clock management unit is configured to send the first clock signal corresponding to the first clock request signal from a time at which the first clock request signal is first received to a time at which a margin value elapses from when the first clock request signal is stopped being received, and the plurality of clock users includes a first clock user and a second clock user, and a first margin value of the first clock user is different from a second margin value of the second clock user.

13. The image sensor of claim 8, wherein the plurality of clock users includes a first clock user and a second clock user, and each of the first clock user and the second clock user is configured to receive a first clock signal corresponding to a first clock request signal generated by the first clock user.

14. The image sensor of claim 8, wherein the plurality of clock users includes a first clock user and a second clock user, the first clock user is configured to receive a first clock signal corresponding to a first clock request signal generated by the first clock user, and the second clock user is configured to receive a first clock signal corresponding to at least one of the first clock request signal generated by the first clock user or the first clock request signal generated by the second clock user.

15. An operating method of an image sensor including a clock user, a block clock management unit, and a top clock management unit, the operating method comprising: generating, by the clock user, a first clock request signal; sending, by the clock user, the first clock request signal to the block clock management unit; generating, by the block clock management unit, a second clock request signal corresponding to the first clock request signal; sending, by the block clock management unit, the second clock request signal to the top clock management unit; generating, by the top clock management unit, a clock response signal and a second clock signal corresponding to the second clock request signal; sending, by the top clock management unit, the clock response signal and the second clock signal to the block clock management unit; and ​ based on the second clock signal, sending, by the block clock management unit, a first clock signal corresponding to the first clock request signal to the clock user.

16. The operating method of claim 15, further comprising: in response to the clock user stopping sending the first clock request signal, stopping, by the block clock management unit, sending the first clock signal to the clock user.

17. The operating method of claim 15, wherein: the image sensor further comprises analog control logic, and generating, by the clock user, the first clock request signal comprises: in response to a start signal received from the analog control logic indicating an end point of a vertical blanking period of an image frame, generating, by the clock user, the first clock request signal.

18. The operating method of claim 15, wherein: the image sensor further comprises analog control logic and an enable register, and generating, by the clock user, the first clock request signal comprises: in response to a start signal received from the analog control logic indicating an end point of a vertical blanking period of an image frame, and an enable signal generated by the enable register being an active signal for controlling activation of operation of the clock user, generating, by the clock user, the first clock request signal.

19. The operating method of claim 15, wherein: the image sensor further comprises a register, and generating, by the clock user, the first clock request signal comprises: receiving, by the clock user, the first clock request signal from the register.

20. The operating method of claim 16, wherein: the in response to the clock user stopping sending the first clock request signal, stopping, by the block clock management unit, sending the first clock signal to the clock user, comprises: stopping, by the block clock management unit, sending the first clock signal to the clock user after a certain period of time has elapsed from the clock user stopping receiving the first clock request signal.

Images