On-satellite important data backup and recovery method, system and equipment

Abstract

The invention relates to a method, a system and equipment for backing up and recovering important data on a satellite. The method comprises the following steps: packaging important data on a satellite, and sending the data to a monitoring processor and a nonvolatile memory for backup; the important data is backed up online through the monitoring processor, the code block information is backed up passively through the first nonvolatile memory, and the important data is backed up actively through the second nonvolatile memory; when important data recovery is carried out, important data recovery is firstly carried out through the monitoring processor under the soft reset condition, if recovery fails, code block information recovery is carried out through the first nonvolatile memory, and then important data recovery is carried out through the second nonvolatile memory; and under the condition of re-electrification, code block information recovery is performed through the first nonvolatile memory, and then important data recovery is performed through the second nonvolatile memory. According to the method, the real-time performance and the recovery reliability of important data backup on the satellite can be improved.

Description

Technical Field

[0001] This invention relates to the field of onboard data management technology, and in particular to a method, system, and device for backing up and restoring important onboard data. Background Technology

[0002] Satellites operate in an extremely complex space environment. Under interference from high-energy particles, space rays, geomagnetic storms, etc., the satellite's telemetry, tracking, and command (TT&C) transponders may trigger single-event upsets, resets, or abnormal power outages. When the TT&C transponder resets and restarts after a power outage, restoring it to its pre-abnormal working state not only ensures data continuity but also allows for analysis of the state before and after the anomalous event, aiding in fault location.

[0003] Traditional satellite tracking and control (TT&C) equipment relies on the status information recorded by the onboard computer to restore the transponder's operational status after a reset or power failure. This method requires the onboard computer to specifically record and extract the operational status of the satellite TT&C equipment, and to specifically identify and control the reset and power-on / off events. This increases the design difficulty and complexity of the onboard computer, and it cannot solve the problems of data loss due to power failure and the excessively long recovery time of existing technologies. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, system, and device for backing up and restoring important onboard data that can improve the real-time performance and recovery reliability of important onboard data backup, in response to the above-mentioned technical problems.

[0005] A method for backing up and restoring critical data on satellite, the method comprising: Important data on the satellite is packaged and sent to a monitoring processor and a non-volatile memory for backup. The non-volatile memory includes a first non-volatile memory and a second non-volatile memory. The monitoring processor performs online backup of important data, the first non-volatile memory performs passive backup of code group information, and the second non-volatile memory performs active backup of important data. When performing important data recovery, in the case of a soft reset, the important data is first recovered through the monitoring processor. If the recovery fails, the code group information is recovered through the first non-volatile memory, and then the important data is recovered through the second non-volatile memory. When power is restored, the code group information is first recovered through the first non-volatile memory, and then the important data is recovered through the second non-volatile memory.

[0006] On the other hand, an on-board important data backup and recovery system is also provided, including: a processing FPGA, and a monitoring processor, a first non-volatile memory and a second non-volatile memory respectively connected to the processing FPGA; The processing FPGA is used to package important on-board data and send it to the monitoring processor, the first non-volatile memory, and the second non-volatile memory for backup operations; and when important data recovery is performed, it reads the corresponding data from the monitoring processor, the first non-volatile memory, and the second non-volatile memory and performs the recovery operation. During data backup, the monitoring processor and the second non-volatile memory are used to store important data; the first non-volatile memory is used to store code group information.

[0007] On another front, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-mentioned method for backing up and restoring important onboard data.

[0008] Compared with existing technologies, the method, system, and equipment for backing up and restoring critical onboard data provided by this invention have the following advantages: 1. Employing a dual backup mechanism of monitoring processor and non-volatile memory avoids data loss due to the failure of a single storage medium, improving system fault tolerance. Simultaneously, splitting backup tasks according to data type enables categorized storage and precise data backup, enhancing the real-time performance, comprehensiveness, and reliability of data backup.

[0009] 2. Different recovery strategies are adopted according to different recovery scenarios, which reduces recovery time and resource consumption, and improves the flexibility and efficiency of data recovery.

[0010] 3. The on-board environment poses risks such as high-energy particle radiation and drastic temperature changes. Non-volatile memory itself has anti-interference capabilities. Through the backup mechanism of the first and second non-volatile memory, it can further resist transient failures such as single-event upsets and ensure the stability of data in extreme environments. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention, and those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating the method for backing up and restoring critical onboard data provided in Example 1. Figure 2A flowchart illustrating the onboard critical data backup and recovery method provided in Example 1; Figure 3 This is a flowchart illustrating the data recovery process under a soft reset as provided in Example 1. Figure 4 This is a flowchart illustrating the data recovery process upon power-on, as provided in Example 1. Figure 5 A schematic diagram illustrating the important data recovery time provided in Example 1; Figure 6 This is a schematic diagram of the candidate blocks for the traversal search mechanism provided in Example 1; Figure 7 This is a structural block diagram of the on-board important data backup and recovery system provided in Example 1.

[0013] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0015] It is understood that the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] Example 1 like Figure 1 As shown, a method for backing up and restoring important data on satellite is provided, including the following steps: Step 201: Package the important data on the satellite and send it to the monitoring processor and non-volatile memory for backup. The non-volatile memory includes a first non-volatile memory and a second non-volatile memory.

[0018] It is understandable that the monitoring processor has real-time processing and caching capabilities, while the non-volatile memory has the ability to retain data even when power is lost. Through this dual backup mechanism, data loss caused by the failure of a single storage medium can be effectively avoided, reducing the risk of single point of failure and improving system fault tolerance.

[0019] Step 202: The important data is backed up online by monitoring the processor, the code group information is passively backed up by the first non-volatile memory, and the important data is actively backed up by the second non-volatile memory.

[0020] Step 203: When performing important data recovery, in the case of a soft reset, the important data is first recovered through the monitoring processor. If the recovery fails, the code group information is recovered through the first non-volatile memory, and then the important data is recovered through the second non-volatile memory.

[0021] Understandably, in the event of a soft reset, data is recovered first through the monitoring processor, enabling rapid recovery of critical data. If recovery fails, data is recovered from non-volatile memory in the order of "code group information → all important data," ensuring that the critical code group information for satellite link establishment can be successfully recovered under triple backup, and that other important data remains valid under dual backup. Step 204: When power is restored, the code group information is first recovered through the first non-volatile memory, and then the important data is recovered through the second non-volatile memory.

[0022] It is understandable that upon power-on, the backup data is lost due to the power-down initialization of the monitoring processor. Recovery begins directly from the non-volatile memory, first restoring the code group information, and then restoring all important data. It can be seen that this invention selects the recovery path based on scenario priority, reducing recovery time and resource consumption.

[0023] The onboard critical data backup and recovery method provided by this invention enables efficient data backup and recovery, reduces system downtime due to data loss, and improves system continuous operation capability. Furthermore, this media- and type-based backup mechanism helps locate the source of the fault, facilitating rapid troubleshooting during maintenance.

[0024] In one embodiment, passive backup of code group information is performed through a first non-volatile memory, including: dividing the first non-volatile memory into three or more address segments; when a code group backup instruction is received, the first non-volatile memory adopts a serial writing mechanism to perform multi-mode backup of the code group information in the address segments.

[0025] In one embodiment, active backup of important data is performed using a second non-volatile memory, including: The second non-volatile memory is divided into three or more storage spaces, and then a serial write mechanism is used to perform multi-mode backup of important data.

[0026] During backup, if it is the first backup, important data is written starting from the beginning address of each storage space; if it is not the first backup, important data is written starting from the address where the backup ended before each storage space was reset or powered off.

[0027] When performing subsequent backup operations, write to the next consecutive address in sequence until the maximum address value of the storage space is reached, and then return to the starting address to write in a loop.

[0028] Specifically, when the FPGA initiates a backup operation, a counter register is established for the second non-volatile memory (Flash1), which increments by 1 according to the rising edge of the clock. When the count reaches 100ms, a pulse signal is generated and the counter is cleared and continues to increment. The backup operation is initiated when the pulse signal is detected. For the first non-volatile memory (Flash0), the backup operation is initiated after the FPGA receives the code group backup instruction sent by the space service.

[0029] During backup, important data is first packaged into a 1024-byte frame according to the protocol, as shown in Table 1.

[0030] Table 1 Important Data Formats

[0031] Then, the FPGA sends the packaged data to the monitoring processor (A3P), the first non-volatile memory, and the second non-volatile memory for backup operations. Important data is written to the second non-volatile memory, and data is simultaneously sent to the monitoring processor via serial port for online backup. When a code group backup command is received, the code group information is written to the first non-volatile memory. It's worth noting that the monitoring processor's online backup refers to caching data in internal registers; if the monitoring processor loses power, the data will not be saved. The passive backup of the first non-volatile memory is performed only after receiving a command. The active backup of the second non-volatile memory is performed upon detecting a pulse signal. Data in both the first and second non-volatile memories is preserved.

[0032] In this embodiment, both the first non-volatile memory and the second non-volatile memory have a space size of 16G. The first non-volatile memory is divided into three address segments to store code group information, that is, the data addresses for storing code group information are the 1st, 2nd, and 3rd addresses. Serial tri-mode backup is performed through the three address segments, that is, the same data is stored three times.

[0033] Three 4GB storage spaces were allocated on the second non-volatile memory for serial tri-mode backup of important data. The storage spaces are 0~4GB, 4~8GB, and 8~12GB respectively. During the first write operation, important data is written to the starting address sequentially, i.e., addresses 0G, 4G, and 8G. After each backup, the write address is incremented by 1 until the maximum address of the storage space is reached, and then the process returns to the initial address and writes in a loop.

[0034] If it is not the first operation, important data will be written starting from the address where the backup ended before each storage space was reset or powered off. After each backup, the write address will be incremented by 1 until the maximum address of the storage space is reached, and then the process will return to the initial address and write in a loop.

[0035] The reason why 4GB of space is allocated to each storage space in the second non-volatile memory is that writing to Flash requires erasing before writing data, and the number of erase cycles for Flash is limited. After a certain number of erase cycles, Flash may become bad blocks and unable to store data. This method can extend the lifespan of the second non-volatile memory. Since the frequency of code group backup instructions issued by the space agency is about once a month, the number of erase cycles does not need to be considered when writing to the same address in the first non-volatile memory.

[0036] It is worth noting that, based on the satellite's 10-year lifespan, the number of erase / write operations required to write data at the end of its 10-year lifespan can be roughly estimated as follows: ; The Flash chip used in this invention is model MT29F128G08AMCABH2, and its datasheet indicates that its nominal erase / write cycle life is 60,000 times. The erase / write cycles calculated above are far below the limit and can meet normal requirements.

[0037] In addition, the number of address ranges and storage space divisions can be determined according to requirements. The division method mentioned in this embodiment is only an example for illustration and does not constitute a limitation on this embodiment.

[0038] It's understandable that larger storage space leads to a longer lifespan, so the size of the storage space can be determined based on actual circumstances and is not limited to the 4GB size mentioned in this implementation. However, larger storage space means longer recovery times for important data after power-on, so the recovery time for important data should be taken into account when allocating storage space size.

[0039] In one embodiment, the recovery of critical data via a monitoring processor includes: The monitoring processor sends the latest important data to the processing FPGA; the processing FPGA parses the received important data and assigns it to the corresponding signal. During the parsing process, the frame header, important data identifiers, and checksum are checked. If any of these conditions are not met, the frame data is discarded, and the next frame of important data is received.

[0040] In one embodiment, after recovering important data by monitoring the processor, the method further includes: A flag indicating successful recovery of important data is generated and fed back to the monitoring processor via a GPIO port. The monitoring processor then stops sending important data.

[0041] Specifically, such as Figure 3 As shown, the satellite sends an FPGA reset command. After receiving the command, the FPGA stops working and sends a reset command to the monitoring processor. The monitoring processor executes the command to reload the FPGA program. After the FPGA program is successfully loaded, it performs important data recovery operations.

[0042] First, after a soft reset, the monitoring processor continuously sends the latest important data to the processing FPGA every 0.1 seconds via the serial port. After receiving the important data, the processing FPGA parses the important data according to the format in Table 1 and assigns it to the corresponding backup signal. During the parsing process, the frame header, important data identifier, and checksum are checked. If any one of them is not satisfied, the frame data is discarded and the next frame is received.

[0043] After the monitoring processor successfully recovers within 0.5 seconds, it sets the important data validity flag to A and feeds back the generated important data recovery success flag to the monitoring processor through the GPIO port. The monitoring processor then stops sending frame data.

[0044] In one embodiment, code group information recovery via a first non-volatile memory includes: The FPGA reads address data from each address segment in the first non-volatile memory, performs voting on each address data during the reading process, and outputs the voting results.

[0045] The FPGA processes frame data based on the voting results and recovers code group information from the corresponding address segment; and generates a code group information recovery success flag after successful code group information recovery.

[0046] In one embodiment, critical data recovery via a second non-volatile memory includes: The FPGA process reads data from each memory space through a traversal search mechanism and determines the latest backup data based on the index number; then, it uses the latest backup data to restore important data.

[0047] In one embodiment, the FPGA reads data from each memory space through a traversal search mechanism, including: Traverse the frame data at the 1KB address of every MB in all memory spaces and parse out the index number; calculate the difference between adjacent index numbers and select the MB block with the largest index number as the initial candidate block.

[0048] Based on the initial candidate block, data for each subsequent KB address is read sequentially starting from KB 1; and the index number difference between adjacent KB addresses is calculated until the KB block corresponding to the largest index number is found as the first candidate block.

[0049] The first candidate block is voted on, and the voting result is output. The FPGA then assigns important data to the corresponding signals based on the voting result.

[0050] Specifically, such as Figure 4 As shown, if the monitoring processor fails to recover within 0.5 seconds during a soft reset or upon power-up, the code group information is recovered from a fixed address segment of the first non-volatile memory within 0.5 to 0.7 seconds. The processing FPGA reads data from addresses 1, 2, and 3M of the first non-volatile memory respectively. During the data reading process, a 2-out-of-3 vote is performed on the three data sets in real time to prevent single-event errors and improve data reliability. Based on the voting results, the processing FPGA parses the frame data and recovers the code group information from the corresponding address segment. After successful code group information recovery, the valid code group information flag is set to A, a code group information recovery success flag is generated for feedback, and then the next step of important data recovery in the second non-volatile memory is performed.

[0051] Between 0.7 and 2.2 seconds, the processing FPGA begins recovering data from the second non-volatile memory. The FPGA reads data from the second non-volatile memory and uses the index number to determine the latest backup data, then uses this latest backup data to recover important data. However, reading all the data from the entire 12GB (three 4GB blocks) space is time-consuming; therefore, this invention employs a traversal search mechanism, such as... Figure 6 As shown. First, a big-endian search is performed: traverse and read the frame data at the 1KB address of the whole MB in the three storage spaces and parse out the index number; calculate the difference between adjacent index numbers (less than 3600). After all three storage spaces have been searched, select the MB block with the largest index number in each storage space as the initial candidate block, and the big-endian search is completed.

[0052] Then, a little-endian search is performed: In each memory space, based on the initial candidate block, data is read sequentially from the 1st KB address to each subsequent KB address; the index difference between adjacent KB addresses is calculated until the KB block corresponding to the largest index number is found as the first candidate block. The data corresponding to the first candidate block is the latest backup data before the power failure. A voting process is performed on the first candidate block, and the voting result is output; the FPGA then processes the signal to assign important data to the corresponding backup based on the voting result. This traversal search mechanism significantly shortens the Flash recovery time for important data; according to actual tests, each Flash recovery takes approximately 1 second.

[0053] Furthermore, assuming that both the monitoring processor and the second non-volatile memory fail to recover within 5 seconds, a forced recovery measure is taken, assigning the important data to the default value. Then, the monitoring processor recovers, the second non-volatile memory recovers, or a forced recovery is performed. Then, the FPGA sets the important data validity flag to A, and a new important data backup begins from step 201.

[0054] This invention employs a dual backup method using a monitoring processor and non-volatile memory. Every 100ms, the processing FPGA packages important data into 1KB blocks according to the protocol format in Table 1 and writes them to a 16GB second non-volatile memory (the second non-volatile memory is divided into three 4GB storage spaces, backing up three identical copies of the data each time). Simultaneously, the frame data of the important data is sent to the monitoring processor for online storage via an asynchronous 422 serial port. In addition, the processing FPGA also receives code injection commands from the satellite and writes the current code information to a 16GB first non-volatile memory (the first non-volatile memory has a 3MB space allocated for code information backup).

[0055] After a soft reset of the processing FPGA or a power-on re-energization of the telemetry and control transponder, critical data recovery begins. In the case of a soft reset, critical data is recovered by the monitoring processor 0.5 seconds after the processing FPGA completes loading; if the monitoring processor fails to recover the data, recovery from non-volatile memory takes another 1.5 seconds. In the case of a power-on re-energization, recovery from non-volatile memory takes 2.2 seconds after the processing FPGA completes loading. The processing FPGA parses frame data and assigns critical data to the corresponding backup signals. If both monitoring processor and non-volatile memory recovery fail, the processing FPGA restores the critical data to its default values.

[0056] The present invention provides important data backup at a frequency of 0.1s / time, improving the real-time performance of onboard important data backup; it divides the second non-volatile memory into three 4GB spaces, and the data backup address is continuously accumulated, extending the system's lifespan; and it performs triple redundancy processing for important data backup and recovery in the non-volatile memory, improving the system's reliability; the index number traversal search mechanism adopted greatly shortens the important data recovery time, solving the problem of excessively long recovery time in existing technologies.

[0057] It should be understood that, although this embodiment Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0058] Example 2 Based on the onboard important data backup and recovery method in Embodiment 1, this embodiment discloses an onboard important data backup and recovery system, such as... Figure 7 As shown, the onboard critical data backup and recovery system includes: a processing FPGA, and a monitoring processor, a first non-volatile memory, and a second non-volatile memory, all connected to the processing FPGA.

[0059] The FPGA is used to package important on-board data and send it to the monitoring processor, the first non-volatile memory, and the second non-volatile memory for backup operations; and when important data recovery is performed, the corresponding data is read from the monitoring processor, the first non-volatile memory, and the second non-volatile memory and the recovery operation is performed. During data backup, the monitoring processor and the second non-volatile memory are used to store important data; the first non-volatile memory is used to store code group information.

[0060] In this embodiment, the specific working process and working principle of the FPGA processing, as well as the monitoring processor, the first non-volatile memory, and the second non-volatile memory connected to the FPGA, are the same as those in Embodiment 1, and therefore will not be described again in this embodiment. Each unit module can be implemented entirely or partially through software, hardware, or a combination thereof. Each unit module can be embedded in the processor of the computer device in hardware form or independent of it, or it can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above unit modules.

[0061] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0062] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A method for backing up and restoring critical data on satellite, characterized in that, The method includes: Important data on the satellite is packaged and sent to a monitoring processor and a non-volatile memory for backup. The non-volatile memory includes a first non-volatile memory and a second non-volatile memory. The monitoring processor performs online backup of important data, the first non-volatile memory performs passive backup of code group information, and the second non-volatile memory performs active backup of important data. When performing important data recovery, in the case of a soft reset, the important data is first recovered through the monitoring processor. If the recovery fails, the code group information is recovered through the first non-volatile memory, and then the important data is recovered through the second non-volatile memory. When power is restored, the code group information is first recovered through the first non-volatile memory, and then the important data is recovered through the second non-volatile memory.

2. The method for backing up and restoring important onboard data according to claim 1, characterized in that, Passive backup of code group information is performed through the first non-volatile memory, including: The first non-volatile memory is divided into three or more address segments. When a code group backup instruction is received, the first non-volatile memory adopts a serial writing mechanism to perform multi-mode backup of the code group information on the address segments.

3. The method for backing up and restoring important onboard data according to claim 1, characterized in that, Active backup of important data is performed using the second non-volatile memory, including: The second non-volatile memory is divided into three or more storage spaces, and then a serial write mechanism is used to perform multi-mode backup of the important data; During backup, if it is the first backup, important data is written starting from the beginning address of each storage space; if it is not the first backup, important data is written starting from the address where the backup ended before each storage space was reset or powered off. When performing subsequent backup operations, write to the next consecutive address in sequence until the maximum address value of the storage space is reached, and then return to the starting address to write in a loop.

4. The method for backing up and restoring critical onboard data according to any one of claims 1 to 3, characterized in that, The recovery of critical data via the monitoring processor includes: The monitoring processor sends the latest important data to the processing FPGA; the processing FPGA parses the received important data and assigns it to the corresponding signal. During the parsing process, the frame header, important data identifiers, and checksum are checked. If any of these conditions are not met, the frame data is discarded, and the next frame of important data is received.

5. The method for backing up and restoring important onboard data according to claim 4, characterized in that, After recovering important data through the monitoring processor, the process also includes: A flag indicating successful recovery of important data is generated and fed back to the monitoring processor via a GPIO port. The monitoring processor then stops sending important data.

6. The method for backing up and restoring important onboard data according to claim 2, characterized in that, Recovering code group information through the first non-volatile memory includes: The FPGA reads address data from each address segment in the first non-volatile memory, performs voting on each address data during the reading process, and outputs the voting results. The processing FPGA parses the frame data based on the voting result and recovers the code group information from the corresponding address segment; and generates a code group information recovery success flag after the code group information is successfully recovered.

7. The method for backing up and restoring important onboard data according to claim 3, characterized in that, Important data recovery via the second non-volatile memory includes: The FPGA process reads data from each memory space through a traversal search mechanism and determines the latest backup data based on the index number; then, it uses the latest backup data to restore important data.

8. The method for backing up and restoring important onboard data according to claim 7, characterized in that, The FPGA processes data by reading it from various memory spaces through a traversal search mechanism, including: Traverse all memory spaces for frames at the 1KB address of every MB and parse out the index number; calculate the difference between adjacent index numbers and select the MB block with the largest index number as the initial candidate block; Based on the initial candidate block, data for each subsequent KB address is read sequentially starting from the 1st KB; and the index number difference between adjacent KB addresses is calculated until the KB block corresponding to the largest index number is found as the first candidate block; The first candidate block is voted on, and the voting result is output. The FPGA then assigns important data to the corresponding signals based on the voting result.

9. An on-board critical data backup and recovery system, characterized in that, The system includes: a processing FPGA, and a monitoring processor, a first non-volatile memory, and a second non-volatile memory respectively connected to the processing FPGA; The processing FPGA is used to package important on-board data and send it to the monitoring processor, the first non-volatile memory, and the second non-volatile memory for backup operations; and when important data recovery is performed, it reads the corresponding data from the monitoring processor, the first non-volatile memory, and the second non-volatile memory and performs the recovery operation. During data backup, the monitoring processor and the second non-volatile memory are used to store important data; the first non-volatile memory is used to store code group information.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the on-board important data backup and recovery method according to any one of claims 1 to 8.

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