Data sorting apparatus, method, chip, electronic device and storage medium

Abstract

The application discloses a data sorting device, method, chip, electronic equipment and storage medium. The device comprises a controller configured to acquire a plurality of first data groups; a parity sorting network configured to sort the first data groups into second data groups; a data selector configured to acquire a target data group; the controller is configured to compare the target data group with an i-th second data group at intervals of N bits to obtain an i-1-th third data group; when TopN sorting is performed, a double-adjusted merging network is configured to sort the i-1-th third data group into an i-1-th fourth data group; when i is equal to the number of the plurality of first data groups, the i-1-th fourth data group is taken as a TopN sorting result; when full sorting is performed, the double-adjusted merging network is configured to iteratively merge the sorted fourth data groups to obtain a full sorting result. The application can be compatible with TopN and double-adjusted full sorting algorithms and save computing resources.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a data sorting device, method, chip, electronic device and storage medium. Background Technology

[0002] In the data processing technology system, sorting is a core fundamental operation. TopN and bitonic full sorting are two targeted sorting technologies whose development is closely related to the expansion of data scale, the increase in real-time requirements, and the evolution of hardware environment. TopN technology only needs to obtain the core top N data items, without needing to sort the entire dataset. Bitonic full sorting, on the other hand, is adapted to parallel hardware, which can distribute the sorting task to thousands of threads of a graphics processing unit (GPU) or hardware logic units of a field-programmable gate array (FPGA) for parallel execution, significantly improving sorting efficiency.

[0003] In related technologies, if the same hardware device wants to implement TopN and bitone full sort, it is necessary to deploy the corresponding TopN module and bitone full sort module independently. This results in the duplication of core computing units such as sorting network and merge network, which increases the occupation of computing resources and circuit area, leading to hardware resource redundancy. Summary of the Invention

[0004] This application proposes a data sorting device, data sorting method, chip, electronic device, and computer storage medium that are compatible with TopN and bitonic full sorting algorithms and save computational resources.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0006] A data sorting device includes: a controller, a buffer, a data selector, an even / odd sorting network, and a bitonetic merge network, wherein...

[0007] The controller is used to divide the data to be sorted into multiple first data groups, wherein each first data group includes N values;

[0008] The odd-even sorting network is used to sort the plurality of first data groups within each group to obtain a plurality of second data groups, and to input each second data group into the data selector in sequence.

[0009] The data selector is used to obtain the target data group of the i-th second data group for the i-th second data group;

[0010] The controller is configured to compare the target data group with the i-th second data group at intervals of N bits, and combine the results of each comparison into the (i-1)-th third data group, where i is an integer greater than or equal to 2, and the target data group is the data group obtained in the previous round of sorting;

[0011] When the sorting method indicated by the controller is TopN sorting, the bitone merging network is used to sort the (i-1)th third data group to obtain the (i-1)th fourth data group; when i is less than the number of the plurality of first data groups, the (i-1)th fourth data group is used as the data group obtained in the i-th round of sorting; when i is equal to the number of the plurality of first data groups, the (i-1)th fourth data group is used as the TopN sorting result of the plurality of first data groups.

[0012] When the sorting method indicated by the controller is full sorting, the bitone merging network is used to sort the (i-1)th third data group to obtain the (i-1)th fourth data group, and to iteratively merge the sorted fourth data group to obtain the full sorting result of the multiple first data groups.

[0013] In some embodiments, this application also provides a data sorting method, the method comprising:

[0014] The data to be sorted is divided into multiple first data groups, wherein each first data group includes N values, where N is a positive integer greater than or equal to 2;

[0015] The plurality of first data groups are sorted within each group to obtain a plurality of second data groups, and each second data group is sequentially input into the data selector.

[0016] For the i-th second data group, obtain the target data group of the i-th second data group;

[0017] The target data group is compared with the i-th second data group at intervals of N, and the results of each comparison are combined into the (i-1)-th third data group, where i is an integer greater than or equal to 2, and the target data group is the data group obtained in the previous round of sorting.

[0018] When the sorting method is TopN sorting, the (i-1)th third data group is sorted to obtain the (i-1)th fourth data group; when i is less than the number of the plurality of first data groups, the (i-1)th fourth data group is taken as the data group obtained in the i-th round of sorting; when i is equal to the number of the plurality of first data groups, the (i-1)th fourth data group is taken as the TopN sorting result of the plurality of first data groups.

[0019] When the sorting method is full sorting, the (i-1)th third data group is sorted to obtain the (i-1)th fourth data group, and the sorted fourth data group is iteratively merged to obtain the full sorting result of the multiple first data groups.

[0020] In some embodiments, this application also provides a chip, the chip including: a data sorting device as described in the embodiments of this application.

[0021] In some embodiments, this application also provides an electronic device, the electronic device including a processor, wherein the processor includes: a data sorting device as described in the embodiments of this application;

[0022] Alternatively, a memory may be used to store computer-executable instructions or computer programs; a processor may be used to execute the computer-executable instructions or computer programs stored in the memory to implement the data sorting method described in the embodiments of this application.

[0023] In some embodiments, this application also provides a computer-readable storage medium storing computer-executable instructions or a computer program, which, when executed by a processor, implements the data sorting method described in this application.

[0024] The embodiments of this application have the following beneficial effects:

[0025] The system uses an even-odd sorting network to sort each input data group within its group. A data selector selects the input dataset and already sorted data groups, performing N-bit comparisons between them. The results of each comparison are combined into the (i-1)th third data group. When the controller indicates TopN sorting, a bitone merging network sorts the data groups. The output of the bitone merging network after all inputs are complete serves as the TopN sorting result. When the controller indicates full sorting, the bitone merging network merges the data groups, expanding the range of ordered data groups from the results of the current round of sorting to the results of multiple rounds, achieving full data sorting. Using the same hardware architecture, both TopN sorting and full sorting are implemented, reusing the even-odd sorting network and the bitone merging network, improving hardware utilization, significantly saving chip area, and reducing the power consumption of the sorting device. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 1 ;

[0027] Figure 2 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 2 ;

[0028] Figure 3 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 3 ;

[0029] Figure 4 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 4 ;

[0030] Figure 5 This is a flowchart illustrating the method provided in the embodiments of this application.

[0031] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0032] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0034] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0035] It should also be noted that the terms "first," "second," and "third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first," "second," and "third" can be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program with a predetermined function, which works together with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of a larger module or unit that includes the functionality of that module or unit.

[0036] It should be noted that the data collection and processing in this application should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0037] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant terms and technologies of the embodiments of this application are described below. The following related technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0038] 1) Field Programmable Gate Array (FPGA): A novel programmable logic device fabricated using Complementary Metal Oxide Semiconductor (CMOS)-Static Random-Access Memory (SRAM) technology. Its core architecture consists of programmable logic blocks (CLBs), input / output modules (IOBs), programmable interconnect resources (IRs), and SRAM. FPGAs enable circuit reconfiguration through hardware description languages, possess reprogrammable characteristics, and support top-down system design methodologies.

[0039] 2) Application Specific Integrated Circuit (ASIC): An ASIC is an integrated circuit designed specifically for a particular application, used in fields such as computers and embedded control systems. The core advantages of ASICs include extremely small size, low power consumption, high reliability, security, computing power, and energy efficiency, especially excelling in scenarios such as artificial intelligence (AI) inference, high-speed search, and visual processing.

[0040] 3) Bitonic Sort is a parallel sorting algorithm based on the properties of bitonic sequences. It is suitable for parallel processing systems, such as graphics processing units (GPUs) and FPGAs, and other hardware acceleration scenarios. A bitonic sequence is a sequence that is first monotonically increasing and then monotonically decreasing (or first decreasing and then increasing). A completely monotonic sequence (such as either increasing or decreasing) is also considered a bitonic sequence.

[0041] 4) TopN statistics: This is an operation that selects the top N elements from a dataset. It is often used to quickly extract the best or worst data to support decision-making or optimize efficiency.

[0042] 5) Merge Sort: This is an efficient and stable sorting algorithm based on the merge operation. It is a very typical application of the divide-and-conquer method. It merges already sorted subsequences to obtain a completely sorted sequence; that is, first sorting each subsequence, then sorting the subsequences relative to each other. The bitonic merge sort network, proposed by Batcher, is a parallel sorting network that achieves efficient sorting based on the properties of bitonic sequences. Its core idea is to decompose the input sequence into bitonic sequences and complete the sorting through recursive decomposition and merging. Batcher's theorem states that any bitonic sequence A of length 2n is divided into two equal halves X and Y. The elements in X are compared one by one with the elements in Y in their original order, i.e., the i-th element a... i With the (i+n)th element a i+n The comparison is performed, with the larger element placed in the MAX sequence and the smaller element placed in the MIN sequence. The resulting MAX and MIN sequences are still bitonic sequences, and any element in the MAX sequence is no less than any element in the MIN sequence. Based on this principle, an input n-element bitonic sequence can first be shuffled and compared to obtain a MAX sequence and a MIN sequence. Then, two n / 2-order bitonic mergers can be used to process this sequence to obtain an ordered sequence. The n-order bitonic merger consists of a shuffled comparison network and two n / 2-order bitonic mergers.

[0043] 6) Data Selector: A data selector is a combinational logic circuit that selects a specific signal from a set of input signals based on the input address code and sends it to the output. Sometimes, a data selector is also called a multiplexer or multiplexer. The core function of a data selector is to converge data from multiple channels onto a single common data channel according to selection logic, thus achieving data selection and transmission. In this embodiment, the 3-to-2 data selector selects and outputs two valid signals from three parallel input data signals (usually denoted as D0, D1, and D2) according to preset logic or control signals. Essentially, it is a logic device for "filtering and parallel output" of multiple input data, and can be used for data routing and signal gating scenarios in digital systems.

[0044] 7) Comparator: A comparator is a circuit that compares an analog voltage signal with a reference voltage. The two inputs of a comparator are analog signals, and the output is a binary signal of 0 or 1. When the difference between the input voltages increases or decreases while the sign remains unchanged, the output remains constant. Comparing two or more data items to determine whether they are equal, or to determine their magnitude relationship and order, is called comparison. A circuit or device that can perform this comparison function is called a comparator.

[0045] In the data processing technology system, sorting is a core fundamental operation. TopN and bitonic full sort, as two targeted sorting technologies, are closely related to the expansion of data scale, the increase in real-time requirements, and the evolution of hardware environments. TopN technology only needs to obtain the core top N data items, without needing to sort the entire dataset. Bitonic full sort, on the other hand, is adapted to parallel hardware, allowing the sorting task to be distributed to thousands of threads on a GPU or the hardware logic units of an FPGA for parallel execution, significantly improving sorting efficiency. The TopN algorithm only requires address generation and backpressure control, while bitonic sort requires additional management of iteration signals, polarity switching, etc., and the control logic cannot be reused when implemented independently. This is because the control logic of bitonic sort is closely related to the specific sorting stage and the characteristics of the sequence. Different iteration stages and sequences of different lengths may require different control logic, and operations such as polarity switching also depend on the specific sorting context. Therefore, the control logic of bitonic sort is relatively complex and specific to its sorting process, making it difficult to directly reuse in other different algorithms or scenarios. In contrast, the address generation and backpressure control of the TopN algorithm are relatively independent, not dependent on a specific sorting process, and have better versatility and reusability.

[0046] In related technologies, implementing TopN and bitonic full sorting on the same hardware requires independently deploying corresponding TopN and bitonic full sorting modules. The dynamic merge network of TopN differs significantly in topology from the fixed sorting network of bitonic sorting. The heap-based TopN algorithm requires a heap sort computation unit, but the control logic of the heap sort computation unit is incompatible with that of the bitonic sequence comparator. Repeated deployment doubles the number of comparators in the hardware, increases the circuit area occupied by the sorting network, wastes computing resources, and reduces the overall hardware utilization.

[0047] Based on this, embodiments of this application provide a data sorting device, a data sorting method, a chip, an electronic device, and a computer storage medium, which integrates the common computing units (odd-even sorting network and merge network) involved in both TopN and bitonic full sorting, reducing logical resource consumption, saving computing resources, and improving hardware utilization.

[0048] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0049] The following description, in conjunction with the accompanying drawings, illustrates the data sorting apparatus provided in embodiments of this application. Figure 1 , Figure 1 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 1 The data sorting device 100 includes: a controller 101, a buffer, a data selector 103, an odd-even sorting network 102, and a bitone merging network 104, wherein...

[0050] The controller 101 is used to divide the data to be sorted into multiple first data groups, wherein each first data group includes N values.

[0051] To facilitate understanding of the principle of the data sorting device in this application embodiment, the commonalities of TopN sorting and full sorting are described below. Both TopN sorting and full sorting rely on element comparison to establish order. TopN sorting is used to obtain the top N largest / smallest elements, while full sorting is used to completely sort all elements. For large amounts of data, grouping the data before sorting is suitable for both TopN sorting and full sorting. Each first data group has the same amount of data. For example, if there are 64 values ​​to be sorted, the values ​​can be divided into 8 data groups, each containing 8 values. Array 1: [5, 12, 8, 19, 3, 15, 0, 11]

[0052] Array 2: [17, 4, 9, 20, 7, 1, 13, 6]

[0053] Array 3: [18, 2, 16, 10, 5, 14, 8, 3]

[0054] Array 4: [0, 19, 7, 12, 15, 4, 11, 9]

[0055] Array 5: [13, 6, 20, 1, 17, 10, 5, 14]

[0056] Array 6: [9, 18, 3, 16, 2, 8, 19, 7]

[0057] Array 7: [12, 4, 15, 0, 11, 6, 20, 13]

[0058] Array 8: [5, 17, 10, 1, 8, 14, 3, 19].

[0059] The odd-even sorting network 102 is used to sort the multiple first data groups within each group to obtain multiple second data groups, and then input each second data group into the data selector 103 in sequence.

[0060] For example, within-group sorting refers to sorting the N data points within a first data group to obtain an ordered second data group. Here, "first" and "second" are used to distinguish the order of the data groups before and after sorting, and do not indicate the actual order of the data groups. Multiple ordered data groups can be compared pairwise to extend the partially ordered nature of the data within a group to an ordered nature across all data groups. Assuming the sorting process is ascending (with the largest value at the end), based on the first data group in the example above, we can obtain the following second data group: Array 1 after ascending sorting: [0, 3, 5, 8, 11, 12, 15, 19]

[0061] Array 2, after ascending sort: [1, 4, 6, 7, 9, 13, 17, 20]

[0062] Array 3, after ascending sorting: [2, 3, 5, 8, 10, 14, 16, 18]

[0063] Array 4, after ascending sorting: [0, 4, 7, 9, 11, 12, 15, 19]

[0064] Array 5, after being sorted in ascending order, becomes: [1, 5, 6, 10, 13, 14, 17, 20]

[0065] Array 6, after being sorted in ascending order, becomes: [2, 3, 7, 8, 9, 16, 18, 19]

[0066] Array 7, after ascending sorting: [0, 4, 6, 11, 12, 13, 15, 20]

[0067] Array 8, after ascending sort: [1, 3, 5, 8, 10, 14, 17, 19]

[0068] The data selector 103 is used to obtain the target data group of the i-th second data group for the i-th second data group.

[0069] In this embodiment, the data selector can be a 3-to-2 data selector, meaning it has three input terminals and selects the input content from two of them as the selected data. The input data of the data selector includes: an odd-even sorting network, a bitonic merge network, and a buffer. When the buffer is completely empty, it stores the input of the odd-even sorting network, such as the first second data group among multiple second data groups. The buffer can also store the results generated by each round of sorting by the bitonic merge network; for example, it can store the sorting result generated in the (i-1)th round and update the stored content of the i-th round based on the sorting result of the i-th round. The input terminals selected by the data selector include the second data group input by the odd-even sorting network (i.e., the i-th second data group), the bitonic merge network, or the buffer (i.e., the target data group of the i-th second data group). When the i-th second data group is input, if the buffer contains the sorting result obtained in the (i-1)-th round, the content in the buffer is used as the selected target data group. When the i-th second data group is input, if there is no data in the buffer and the bitonic merge network outputs the sorting result obtained in the (i-1)-th round, then the output of the bitonic merge network is used as the selected data.

[0070] The controller 101 is used to compare the target data group with the i-th second data group at intervals of N bits, and combine the results of each comparison into the (i-1)-th third data group, where i is an integer greater than or equal to 2, and the target data group is the data group obtained in the previous round of sorting.

[0071] For example, performing an N-bit interval comparison involves concatenating the target data group with the i-th second data group end-to-end to form a single data group, and then comparing the values ​​at an interval of N within the merged data group. For instance, if the merged data group contains 16 data points, numbered 0 to 15, then perform an 8-bit interval comparison on the 16 data points in the merged data group: D[0] vs D[8], D[1] vs D[9]...D[7] vs D

[15] . Assuming that the larger value is obtained as the result of each comparison, a third data group is obtained.

[0072] In some embodiments, the controller is further configured to perform the following processing on the target data group and the i-th second data group: merging the i-th second data group and the target data group to obtain a merged data group, wherein the i-th second data group is sorted in ascending order and the target data group is sorted in descending order; comparing the j-th value in the merged data group with the (j+N)-th value to obtain the larger value between the j-th value and the (j+N)-th value, wherein j is a positive integer less than or equal to N; and combining the larger value obtained from each comparison into the (i-1)-th third data group.

[0073] For example, taking the array above as an example, according to the input order, the first second data group is sorted in descending order, and the second second data group is sorted in ascending order, resulting in the merged data group [1, 4, 6, 7, 9, 13, 17, 20, 19, 15, 12, 11, 8, 5, 3, 0]. Based on the position interval of each value of 8, we get [20, 17, 13, 9, 11, 12, 15, 19].

[0074] In some embodiments, when the sorting method indicated by the controller is TopN sorting, before dividing the data to be sorted into multiple first data groups, the controller is further configured to generate multiple consecutive addresses according to a bitonic sequence, wherein the consecutive addresses are used to store the data to be sorted; the device further includes a bus interface, which is configured to read a preset amount of the data to be sorted and divide the data to be sorted into multiple first data groups.

[0075] For example, contiguous addresses can be AXI4 addresses. AXI4 is the Advanced Dextensible Interface 4 (AD 4). AXI4 requires addresses to be aligned to the data width; that is, for 128-bit (16-byte) data, the address must be a multiple of 16 (i.e., the lowest 4 bits are 0). The bus interface can be an AXI4 interface. Assuming the data width is 64 bits, and 64 bits of data are input per cycle, the bus interface will split the input data into eight 8-bit streams.

[0076] When the sorting method indicated by the controller is TopN sorting, the bitone merge network 104 is used to sort the (i-1)th third data group to obtain the (i-1)th fourth data group. The bitone merge network is used to sort each value in the (i-1)th third data group in descending order to obtain the (i-1)th fourth data group.

[0077] For example, the controller indicates the sorting method of the bimodal merge network through an output signal.

[0078] For example, since the third data group is the result of comparisons at interval N, it may be unordered. For instance, the third data group [20, 17, 13, 9, 11, 12, 15, 19] obtained from comparisons at interval 8 in the example above is composed of the 8 largest values ​​from the merged data group [1, 4, 6, 7, 9, 13, 17, 20, 19, 15, 12, 11, 8, 5, 3, 0]. However, the values ​​are unordered. A bitonemic merge network is used to sort the third data group, resulting in an ordered fourth data group. When i is not the number of multiple first data groups, the bitonemic merge network is also used to store the (i-1)th fourth data group in a cache for processing the (i+1)th second data group.

[0079] When i is less than the number of the plurality of first data groups, the (i-1)th fourth data group is taken as the data group obtained by the i-th round of sorting, so that the data selector continues to perform the processing after the input of the i+1th second data group based on the data group obtained by the i-th round of sorting, and the process of "data selector selects data, performs interval N comparison based on the selected data, and bitone merging network sorts the data group obtained by interval N comparison" is repeated.

[0080] For example: the first fourth data group is the target data group of the third second data group. The third second data group is sorted in ascending order and the first fourth data group is sorted in descending order. The two are compared at intervals of N. The larger value combination in each comparison is selected as the second third data group. The second third data group is sorted in descending order to obtain the second fourth data group, which is used as the target data group of the fourth second data group, and so on.

[0081] When i equals the number of the plurality of first data groups, the (i-1)th fourth data group is taken as the TopN sorting result of the plurality of first data groups.

[0082] For example, when i equals the number of the multiple first data groups, it means that all the multiple second data groups have been input into the data selector, and the results of the comparisons at intervals of N have also been input into the bitonemic merge network. The (i-1)th fourth data group output by the bitonemic merge network is used as the final TopN sorting result. In practical applications, the output result of each round of the bitonemic merge network is input into a buffer. When the last round of processing is completed, the (i-1)th fourth data group can be read from the buffer as the TopN sorting result.

[0083] In some embodiments, when the sorting method indicated by the controller is full sort, before dividing the data to be sorted into multiple first data groups, the controller is further configured to generate multiple non-contiguous addresses according to a bitonic sequence form, wherein the non-contiguous addresses are used to store the data to be sorted.

[0084] For example, during the full sorting process, each output of the bitone merge network is stored in the corresponding memory address. After the last round of sorting, the data group that has been stored in the memory address is used as the full sorting result.

[0085] In some embodiments, when the sorting method indicated by the controller is full sorting, the bitone merging network is used to sort the (i-1)th third data group to obtain the (i-1)th fourth data group, and to iteratively merge the sorted fourth data group to obtain the full sorting result of the plurality of first data groups.

[0086] For example, when i is 2, the bitone merge network is used to sort the first third data group in descending order to obtain the first fourth data group.

[0087] When i is greater than 2, the controller is further configured to perform the following processing for the target data group and the i-th second data group:

[0088] The (i+1)th second data group and the (i-1)th fourth data group are merged to obtain a merged data group. When the polarity signal indicates descending order, the (i-1)th fourth data group is sorted in descending order and the (i+1)th second data group is sorted in ascending order; when the polarity signal indicates ascending order, the (i-1)th fourth data group is sorted in ascending order and the (i+1)th second data group is sorted in descending order.

[0089] In practical applications, during the full sorting process, before each comparison at interval N, the controller sends a polarity signal. This polarity signal controls the sorting order of the merged data groups to be the reverse of the previous sorting order. For example, if the first merged data group is sorted in descending order then ascending order, then the second merged data group will be sorted in ascending order then descending order.

[0090] The j-th value in the merged data group is compared with the (j+N)-th value, and the result of each comparison is combined into the i-th third data group, where j is a positive integer less than or equal to N; assuming the goal of the full sort is to obtain a descending order, the j-th value is compared with the (j+N)-th value to select the larger value.

[0091] The bitone merge network is further configured to sort the (i-1)th third data group according to the polarity signal sent by the controller to obtain the (i-1)th fourth data group, generate a storage address according to the number of iterations, and store the i-th fourth data group in the storage address. The bitone merge network is also configured to, after the last round of sorting, use the data groups already stored in the storage address as the full sort result.

[0092] The data sorting method provided in the embodiments of this application is described below with reference to the accompanying drawings. Figure 5 , Figure 5 This is a flowchart illustrating the method provided in the embodiments of this application.

[0093] In step 501, the data to be sorted is divided into multiple first data groups.

[0094] Each first data group includes N values, where N is a positive integer greater than or equal to 2;

[0095] In step 502, the multiple first data groups are sorted within each group to obtain multiple second data groups, and each second data group is sequentially input into the data selector;

[0096] In step 503, for the i-th second data group, the target data group of the i-th second data group is obtained;

[0097] In step 504, the target data group is compared with the i-th second data group at intervals of N bits, and the results of each comparison are combined into the (i-1)-th third data group.

[0098] Here, i is an integer greater than or equal to 2, and the target data set is the data set obtained from the previous round of sorting;

[0099] In step 505, when the sorting method is TopN sorting, the (i-1)th third data group is sorted to obtain the (i-1)th fourth data group; when i is less than the number of multiple first data groups, the (i-1)th fourth data group is taken as the data group obtained in the i-th round of sorting; when i is equal to the number of multiple first data groups, the (i-1)th fourth data group is taken as the TopN sorting result of multiple first data groups.

[0100] In step 506, when the sorting method is full sort, the (i-1)th third data group is sorted to obtain the (i-1)th fourth data group, and the sorted fourth data group is iteratively merged to obtain the full sorting results of multiple first data groups.

[0101] In this embodiment, an even-odd sorting network is used to sort each input data group within the group. A data selector selects the input dataset and the already sorted data groups, and performs N-bit comparisons between them. The results of each comparison are combined into the (i-1)th third data group. When the controller indicates that the sorting method is TopN sorting, a bitone merging network is used to sort the data groups. When all inputs are complete, the output of the bitone merging network can be used as the TopN sorting result. When the controller indicates that the sorting method is full sorting, the bitone merging network merges the data groups, expanding the range of ordered data groups from the results of the current round of sorting to the results of multiple rounds of sorting, thus achieving full data sorting. Using the same hardware structure, both TopN sorting and full sorting are achieved, reusing the even-odd sorting network and the bitone merging network, improving hardware utilization, significantly saving chip area, and reducing the power consumption of the sorting device.

[0102] The following will describe an exemplary application of the data sorting device according to the embodiments of this application in a practical application scenario.

[0103] In integrated circuits of related technologies, TopN sorting and full sorting require independent deployment of TopN modules and bitone full sorting modules, resulting in core computing units such as sorting networks and merge networks repeatedly occupying circuit area. In related technologies, full sorting, if implemented using bitone sorting, employs pairwise comparisons, leading to low performance. While the TopN algorithm only requires address generation and backpressure control, bitone sorting requires additional management of iteration signals and polarity switching, making the control logic unreusable when implemented independently. Step-by-step processing necessitates multiple memory reads and writes, increasing data transmission latency (e.g., caching intermediate results multiple times for 1024 8-bit data points). Furthermore, the microarchitecture used in implementing full sorting in related technologies is non-pipelined, making back-to-back data transmission difficult in most cases (back-to-back transmission means that there are no gaps between data transfers on the bus during execution, and all data is valid).

[0104] This application addresses the aforementioned problems in related technologies by providing a data sorting device. It reduces hardware redundancy and logic resource consumption by integrating a common computing unit (odd-even sorting network + bitonetic merge network) from two algorithms. A controller sends a polarity signal to switch between TopN / full sorting modes. Data selectors and streaming processing reduce the number of intermediate data buffering operations, and pipelined design improves data processing throughput. By utilizing the existing odd-even sorting network and bitonetic merge network in TopN, the bitonetic full sorting process can perform multiple traditional cycles (the minimum time step where only one pair of comparisons or swaps can be performed at a time) of comparison.

[0105] refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 2 ; Figure 2 The system includes a configurable controller 201, an Axi4 bus protocol unit 202, an odd-even sorting network 204, a buffer 203, a data flow management unit 205 (including a 3-to-2 data selector 206), and a bi-tone merging network 207. The configurable controller 201 dynamically generates Axi4 addresses, outputs a reverse voltage signal (to indicate that the current sorting mode is TopN mode), and a polarity / iteration signal (to indicate that the current sorting mode is full sorting mode). The odd-even sorting network 204 and the bi-tone merging network 207 are multiplexed calculation units for TopN mode and full sorting mode. The buffer 203 and the 3-to-2 data selector 206 are the data flow management units of the sorting device.

[0106] In TopN mode, the configurable controller 201 generates contiguous addresses and a backpressure signal, which indicates that sorting should be performed in TopN mode. In full sort mode, the configurable controller 201 generates non-contiguous addresses and a polarity signal, which indicates that sorting should be performed in full sort mode, in which the sorting direction is swapped during each iteration. A 3-to-2 selector implements streaming iterative processing and a pipelined buffer, which can be used to cache intermediate results, significantly reducing memory accesses.

[0107] Odd-even sorting networks can be parallel sorting networks composed of Batcher comparators. They employ the Batcher odd-even sorting algorithm, using a divide-and-conquer strategy to achieve sequence sorting through recursive decomposition and merging. They mainly include two types: odd-even merge networks and bitone merge networks. Odd-even merge networks use an inverse shuffle operation to split the input sequence into odd and even sequences, and then complete the sorting through recursive merging combined with shuffling comparisons. Their correctness is verified by the 0-1 principle. Bitone merge networks, based on the characteristics of bitone sequences, decompose the sequence into maximum and minimum (MAX and MIN) sequences through cyclic shifting and comparison exchange operations, and then generate ordered subsequences through recursive processing. In this embodiment, the example of an odd-even sorting network completing a local sorting of N (e.g., 8) data points per cycle is used. The hardware implementation of the odd-even sorting network can be a 5-level comparator (19 comparison units), supporting data pass-through in bitone sorting mode.

[0108] The bimodal merge network supports ascending / descending order switching (controlled by a polarity signal). In each merged data group processing, the first N elements of the merged data group are arranged in ascending order, and the last N elements are arranged in descending order.

[0109] The 3-to-2 data selector supports validity checks on the output of the bitone merging network; it supports buffering the output of the bitone merging network or re-inputting the bitone merging network with either (merged output, buffered) or (merged output, input data); it supports injecting input data into the buffer or inputting it into the bitone merging network with either (input data, buffered data).

[0110] The control signal pipeline, also known as the data flow management unit, is used to transmit data streams and signals issued by the controller. It supports the propagation of backpressure signals for topN and bitone sorting, the propagation of iterative control signals and polarity signals for bitone sorting, and the generation of comparison flag signals related to merge sorting.

[0111] refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 3 ; Figure 3 yes Figure 2 The data sorting device is applied in TopN sorting mode. The controller outputs a reverse voltage signal to indicate the TOP8 sorting. The controller generates consecutive AXI4 addresses: from address baseAddr to address baseAddr+1016. Taking Top 8 and 1024 8-bit data as an example, the data bit width is 64 bits (8 8-bit data), the address step size is 8 bits, and the AXI4 interface inputs 64 bits of data per cycle, which is split into 8 8-bit data streams. The odd-even sorting network performs a local full sort on each group of 8 data, that is, the data output by the odd-even sorting network is the sorted data of each group of 8 data in ascending order.

[0112] The 3-to-2 selector has three input terminals, and each processing selects the input content of two input terminals for processing. When there is no calculation data of the previous Topn8 in the buffer and no intermediate result of the current Topn8 merge (there is no historical data or current intermediate data in the buffer), the input group is injected into the buffer. For example, if the input group is the first sorted data group output by the odd-even sorting network and there is no data in the buffer, the input group is stored in the buffer. If there is calculation data of the previous Topn8 in the buffer, wait for the previous Topn8 to be calculated. For example, if the previous round of Topn8 calculation used the data in the buffer and the odd-even sorting network has already output the next local sorted group, wait for the previous processing to be completed. If there is calculation data of the current Topn8 in the buffer, select the input group and the buffer group to form 16 data and perform 8 comparisons: D[0] vs D[8], D[1] vs D[9]... D[7] vs D

[15] . If the buffer is empty but there are intermediate results from this Topn8 merge, the input group and the merged output are selected to form a merged data group of 16 data points. An interval 8 comparison is performed on each of the 16 merged data points. The first 8 bits of the merged data group are arranged in ascending order, and the last 8 bits are arranged in descending order. After performing the interval 8 comparison, 8 numbers are output. The bitonic merge network sorts these 8 numbers, using this as the sorting result for the current round. If the current round is not the final round, the sorting result for the current round is fed into a 3-to-2 selector to update the buffer. Based on the updated buffer and the (i+1)th sorted data group output by the odd-even sorting network, the loop continues until all data has been input. When all 1024 8-bit data points have been input, the 8×8 bits in the buffer represent the Top 8.

[0113] refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the data sorting device provided in the embodiments of this application. Figure 4 ; Figure 4 yes Figure 2 In the application of the data sorting device in full sorting mode, the controller outputs a polarity signal to control the reversal of the sorting order of the bitone sequences in each round of iteration. That is, the sorting order of the bitone sequences in adjacent rounds is reversed.

[0114] The controller generates non-contiguous addresses according to the bitone sequence construction rule. In the first round of the iteration, the odd-even sorting network sorts every 8 data points (a total of 1024 data points). If the buffer is not empty, the result is passed through to the merge network (selecting two out of three input groups + merge group). If the buffer is empty, the result is passed through and sent to the buffer. The passed-through result of the full sort and the data in the buffer are combined to form 16 data points. The 16 numbers are compared pairwise at intervals of 8 and output serially as 8 numbers. The 8 data points are then subjected to a bitone merge sort. The result of the merge sort is output.

[0115] Starting from the second iteration, the following processing is performed: The controller outputs a polarity signal to control the comparison direction (alternating ascending / descending order) in the merged data group of 16 data points in the form of a bitonic sequence, and controls the polarity signal to reverse according to the iteration number so that the comparison direction alternates in adjacent rounds. Pairwise comparisons of the 16 numbers are performed at intervals of 8, and the results are output serially as 8 numbers. The bitonic merge network processes the 8 data points → obtaining the merge result, or passing through these 8 data points. The merge result is an 8×8b ordered group, which is output sequentially, and intermediate results are written back to memory via AXI4 (the address is generated by the iteration counter). When the iterative processing can cover all 1024 input data points, the final round result is stored according to the iteration address, and the data written back to memory is used as the globally ordered fully sorted data.

[0116] In this embodiment, by studying the hardware design architecture of TopN and bitonic sorting and rationally selecting the computing units used in different computation stages, TopN and bitonic sorting can share a set of computing units, ultimately reducing hardware area overhead. By rationally designing the control flow of TopN and bitonic sorting, they can reuse a single control path. By rewriting the iterative control method of bitonic sorting, the overall sorting performance is significantly improved by effectively utilizing the sorting network in TopN. Hardware reuse is improved by sharing the odd-even sorting network and the bitonic merge network, avoiding redundant deployment of computing units. Through the configuration of polarity signals and iterative control signals, the same hardware supports two algorithms (such as Top8 filtering or full sorting of 1024 data). TopN results are directly output, and intermediate results of full sorting are written back according to iteration rounds. Streaming processing reduces memory access frequency. The fused controller uniformly generates AXI4 addresses, backpressure signals, and bitonic polarity signals, reducing design complexity. Multiple cycles of comparisons are performed in parallel during the full sorting process, significantly improving sorting performance with only a small increase in hardware overhead.

[0117] In another embodiment of this application, a chip is provided, which may include: the data sorting device as described in any of the foregoing embodiments, or the data sorting method as described in any of the foregoing embodiments.

[0118] In another embodiment of this application, an electronic device is provided, which includes a processor. The processor includes: the data sorting device described in any of the foregoing embodiments, or the processor includes a memory storing computer-executable instructions or computer programs; the processor is configured to execute the computer-executable instructions or computer programs stored in the memory to implement the data sorting method described in the embodiments of this application.

[0119] In summary, the above embodiments have provided a detailed explanation of the specific implementation of the aforementioned embodiments. It can be seen that the technical solution of the aforementioned embodiments uses an even-odd sorting network to sort each input data group within its group. A data selector selects the input dataset and the already sorted data groups, and performs N-bit comparisons between them. The results of each comparison are combined into the (i-1)th third data group. When the controller indicates that the sorting method is TopN sorting, a bitonemic merge network is used to sort the data groups. When all inputs are complete, the output of the bitonemic merge network can be used as the TopN sorting result. When the controller indicates that the sorting method is full sorting, the bitonemic merge network merges the data groups, expanding the range of ordered data groups from the results of the current round of sorting to the results of multiple rounds of sorting, thus achieving full data sorting. Using the same hardware structure, both TopN sorting and full sorting are achieved, reusing the even-odd sorting network and the bitonemic merge network, improving hardware utilization, significantly saving chip area, and reducing the power consumption of the sorting device.

[0120] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0121] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0123] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0124] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0125] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0126] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0127] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0128] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0129] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0130] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A data sorting device, characterized in that, The data sorting device includes: a controller, a buffer, a data selector, an odd-even sorting network, and a bitonic merge network, wherein... The controller is used to divide the data to be sorted into multiple first data groups, wherein each first data group includes N values; The odd-even sorting network is used to sort the plurality of first data groups within each group to obtain a plurality of second data groups, and to input each second data group into the data selector in sequence. The data selector is used to obtain the target data group of the i-th second data group for the i-th second data group; The controller is configured to compare the target data group with the i-th second data group at intervals of N bits, and combine the results of each comparison into the (i-1)-th third data group, where i is an integer greater than or equal to 2, and the target data group is the data group obtained in the previous round of sorting; When the sorting method indicated by the controller is TopN sorting, the bitone merging network is used to sort the (i-1)th third data group to obtain the (i-1)th fourth data group; when i is less than the number of the plurality of first data groups, the (i-1)th fourth data group is used as the data group obtained in the i-th round of sorting; when i is equal to the number of the plurality of first data groups, the (i-1)th fourth data group is used as the TopN sorting result of the plurality of first data groups. When the sorting method indicated by the controller is full sorting, the bitone merging network is used to sort the (i-1)th third data group to obtain the (i-1)th fourth data group, and to iteratively merge the sorted fourth data group to obtain the full sorting result of the multiple first data groups.

2. The data sorting device according to claim 1, characterized in that, The data selector is also configured to store the first second data group in a cache and use the first second data group as the data group obtained from the first round of sorting for the first second data group. The data selector is also used to determine, for the i-th second data group, whether there is a data group in the buffer; When a data group exists in the cache, the data group in the cache is used as the target data group; If no data group exists in the cache, the data group obtained from the previous round of sorting is used as the target data group.

3. The data sorting device according to claim 1, characterized in that, The controller is also configured to perform the following processing for the target data group and the i-th second data group: The i-th second data group and the target data group are merged to obtain a merged data group, wherein the i-th second data group is sorted in ascending order and the target data group is sorted in descending order; The j-th value in the merged data group is compared with the (j+N)-th value to obtain the larger value between the j-th value and the (j+N)-th value, where j is a positive integer less than or equal to N; The larger values ​​obtained from each comparison are combined into the (i-1)th third data group.

4. The data sorting device according to claim 1, characterized in that, When the sorting method indicated by the controller is full sort, before dividing the data to be sorted into multiple first data groups, the controller is also used to generate multiple non-contiguous addresses according to the bitone sequence form, wherein the non-contiguous addresses are used to store the data to be sorted.

5. The data sorting device according to claim 4, characterized in that, When i is 2, the bitone merge network is used to sort the first third data group in descending order to obtain the first fourth data group; When i is greater than 2, the controller is further configured to perform the following processing for the target data group and the i-th second data group: The (i+1)th second data group and the (i-1)th fourth data group are merged to obtain a merged data group. When the polarity signal sent by the controller indicates descending order, the (i-1)th fourth data group is sorted in descending order, and the (i+1)th second data group is sorted in ascending order; when the polarity signal indicates ascending order, the (i-1)th fourth data group is sorted in ascending order, and the (i+1)th second data group is sorted in descending order. The j-th value in the merged data group is compared with the (j+N)-th value, and the results of each comparison are combined into the i-th third data group, where j is a positive integer less than or equal to N; The bimodal merging network is further configured to sort the (i-1)th third data group according to the polarity signal sent by the controller to obtain the (i-1)th fourth data group, generate a storage address according to the number of iterations, and store the i-th fourth data group in the storage address.

6. The data sorting device according to claim 5, characterized in that, The bitone merge network is also used to use the data groups that have been stored in the storage address as the full sort result after the last round of sorting.

7. The data sorting device according to claim 1, characterized in that, When the sorting method indicated by the controller is TopN sorting, before dividing the data to be sorted into multiple first data groups, the controller is also used to generate multiple consecutive addresses according to the bitonic sequence form, wherein the consecutive addresses are used to store the data to be sorted; The device further includes a bus interface, which is used to read a preset amount of data to be sorted and divide the data to be sorted into multiple first data groups.

8. The data sorting device according to claim 1, characterized in that, When the sorting method indicated by the controller is TopN sorting, the bitone merge network is used to sort each value in the (i-1)th third data group in descending order to obtain the (i-1)th fourth data group.

9. A data sorting method, characterized in that, The method includes: The data to be sorted is divided into multiple first data groups, wherein each first data group includes N values, where N is a positive integer greater than or equal to 2; The plurality of first data groups are sorted within each group to obtain a plurality of second data groups; For the i-th second data group, obtain the target data group of the i-th second data group; The target data group is compared with the i-th second data group at intervals of N, and the results of each comparison are combined into the (i-1)-th third data group, where i is an integer greater than or equal to 2, and the target data group is the data group obtained in the previous round of sorting. When the sorting method is TopN sorting, the (i-1)th third data group is sorted to obtain the (i-1)th fourth data group; when i is less than the number of the multiple first data groups, the (i-1)th fourth data group is taken as the data group obtained in the i-th round of sorting; when i is equal to the number of the multiple first data groups, the (i-1)th fourth data group is taken as the TopN sorting result of the multiple first data groups. When the sorting method is full sorting, the (i-1)th third data group is sorted to obtain the (i-1)th fourth data group, and the sorted fourth data group is iteratively merged to obtain the full sorting result of the multiple first data groups.

10. A chip, characterized in that, The chip includes: a data sorting device as described in any one of claims 1 to 8.

11. An electronic device, characterized in that, The electronic device includes a processor, wherein the processor includes: a data sorting device as described in any one of claims 1 to 8; Alternatively, a memory may be used to store computer-executable instructions or computer programs; a processor may be used to implement the data sorting method of claim 9 when executing the computer-executable instructions or computer programs stored in the memory.

12. A computer-readable storage medium storing computer-executable instructions or a computer program, characterized in that, When the computer-executable instructions or computer program are executed by a processor, the data sorting method of claim 9 is implemented.

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